LTC2493

FeaTures ■ ■ LTC2493 24-Bit 2-/4-Channel DS ADC with Easy Drive Input Current Cancellation and I2C Interface DescripTion The LTC®2493 is a 4-channel (2-channel differential), 24-bit, No Latency DSTM ADC with Easy Drive technology and a 2-wire, I2C interface. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2493 includes a high accuracy temperature sensor and an integrated oscillator. This device can be configured to measure an external signal (from combinations of 4 analog input channels operating in singleended or differential modes) or its internal temperature sensor. The integrated temperature sensor offers 1/30th °C resolution and 2°C absolute accuracy. The LTC2493 allows a wide common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion, after a new channel is selected, is valid. Access to the multiplexer output enables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No Latency DS and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Up to 2 Differential or 4 Single-Ended Inputs Easy DriveTM Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 2-Wire I2C Interface with 9 Addresses Plus One Global Address for Synchronization 600nV RMS Noise Integrated High Accuracy Temperature Sensor GND to VCC Input/Reference Common Mode Range Programmable 50Hz, 60Hz or Simultaneous 50Hz/ 60Hz Rejection Mode 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error 2x Speed/Reduced Power Mode (15Hz Using Internal Oscillator and 80µA at 7.5Hz Output) No Latency: Digital Filter Settles in a Single Cycle, Even After a New Channel Is Selected Single Supply 2.7V to 5.5V Operation (0.8mW) Internal Oscillator Tiny 4mm × 3mm DFN Package applicaTions ■ ■ ■ ■ Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control Typical applicaTion Data Acquisition System with Temperature Compensation 2.7V TO 5.5V VCC 0.1µF 10µF ABSOLUTE ERROR (°C) Integrated High Performance Temperature Sensor 5 4 CH0 CH1 IN+ REF + 3 2 1 0 –1 –2 –3 –4 –5 –55 –30 –5 20 45 70 TEMPERATURE (°C) 95 120 2493 TA02 1.7k SDA SCL CA1 CA0 FO OSC 2493 vTA01a CH2 CH3 COM 4-CHANNEL MUX 24-BIT ∆Σ ADC WITH EASY-DRIVE IN– REF – 2-WIRE I2C INTERFACE 9-PIN SELECTABLE ADDRESSES TEMPERATURE SENSOR 2493fa  LTC2493 absoluTe MaxiMuM raTings (Notes 1, 2) pin conFiguraTion FO CA0 CA1 SCL SDA GND COM 1 2 3 4 5 6 7 15 14 REF– 13 REF+ 12 VCC 11 CH3 10 CH2 9 CH1 8 CH0 Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (CH0 to CH3, COM) .................. –0.3V to (VCC + 0.3V) REF+, REF– .................................... –0.3V to (VCC + 0.3V) Digital Input Voltage...................... –0.3V to (VCC + 0.3V) Digital Output Voltage ................... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2493C ................................................ 0°C to 70°C LTC2493I ............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C DE PACKAGE 14-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH LTC2493CDE#PBF LTC2493IDE#PBF TAPE AND REEL LTC2493CDE#TRPBF LTC2493IDE#TRPBF PART MARKING* 2493 2493 PACKAGE DESCRIPTION 14-Lead (4mm × 3mm) Plastic DFN 14-Lead (4mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. *For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2493fa  LTC2493 elecTrical characTerisTics (norMal speeD) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 12) TA = 27°C (Note 13) 27.8 ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 24 2 1 0.5 10 25 0.1 25 0.1 15 15 15 0.6 28.0 93.5 28.2 10 2.5 TYP MAX UNITS Bits ppm of VREF ppm of VREF µV nV/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF µVRMS mV µV/°C Output Noise Internal PTAT Signal Internal PTAT Temperature Coefficient elecTrical characTerisTics (2x speeD) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Output Noise CONDITIONS 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 24 ● ● TYP 2 1 0.2 100 MAX 10 2 25 UNITS Bits ppm of VREF ppm of VREF mV nV/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C µVRMS 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC ● 0.1 ● 25 0.1 0.85 converTer characTerisTics PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 50Hz ±2% Input Common Mode Rejection 60Hz ±2% Input Normal Mode Rejection 50Hz ±2% Input Normal Mode Rejection 60Hz ±2% Input Normal Mode Rejection 50Hz/60Hz ±2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ±2%, 60Hz ±2% CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN ● ● ● ● ● ● ● TYP MAX UNITS dB dB dB 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC 2.5V ≤ VREF ≤ VCC 2.5V ≤ VREF ≤ VCC VREF , GND ≤ IN+ = IN– ≤ V , GND ≤ IN+ = IN– ≤ V , GND ≤ IN+ = IN– ≤ V CC (Notes 5, 7) CC (Notes 5, 7) CC (Notes 5, 9) 140 140 140 110 110 87 120 140 120 120 120 120 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) = 2.5V, IN+ = IN– = GND VREF = 2.5V, IN+ = IN– = GND (Notes 7, 8, 9) dB dB dB dB dB dB 2493fa  LTC2493 analog inpuT anD reFerence SYMBOL IN+ IN– VIN FS LSB REF+ REF– VREF CS(IN+) CS(IN–) CS(VREF) IDC_LEAK(IN+) IDC_LEAK(IN–) IDC_LEAK(REF+) IDC_LEAK(REF–) tOPEN QIRR PARAMETER Absolute/Common Mode IN+ Voltage (IN+ Corresponds to the Selected Positive Input Channel) Absolute/Common Mode IN– Voltage (IN– Corresponds to the Selected Negative Input Channel) Input Differential Voltage Range (IN+ – IN–) Full Scale of the Differential Input (IN+ – IN–) Least Significant Bit of the Output Code Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Voltage Range (REF+ – REF–) IN+ Sampling Capacitance IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current REF+ DC Leakage Current REF– DC Leakage Current MUX Break-Before-Make MUX Off Isolation VIN = 2VP-P DC to 1.8MHz Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, REF+ = V CC The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN GND – 0.3V GND – 0.3V ● ● ● ● ● ● TYP MAX VCC + 0.3V VCC + 0.3V +FS UNITS V V V V –FS 0.5VREF FS/224 0.1 GND 0.1 11 11 11 VCC REF+ – 0.1V VCC V V V pF pF pF ● ● ● ● –10 –10 –100 –100 1 1 1 1 50 120 10 10 100 100 nA nA nA nA ns dB Sleep Mode, REF– = GND i2c inpuTs anD DigiTal ouTpuTs SYMBOL VIH VIL VIHA VILA RINH RINL RINF II VHYS VOL tOF IIN CCAX PARAMETER High Level Input Voltage Low Level Input Voltage Low Level Input Voltage for Address Pins CA0, CA1 High Level Input Voltage for Address Pins CA0, CA1 Resistance from CA0, CA1 to VCC to Set Chip Address Bit to 1 Resistance from CA0, CA1 to GND to Set Chip Address Bit to 0 Resistance from CA0, CA1 to GND or VCC to Set Chip Address Bit to Float Digital Input Current (fO) Hysteresis of Schmitt Trigger Inputs Low Level Output Voltage (SDA) Output Fall Time VIH(MIN) to VIL(MAX) Input Leakage (SDA, SCL) External Capacitative Load on Chip Address Pins (CA0, CA1) for Valid Float The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● ● ● ● ● ● ● ● MIN 0.7VCC TYP MAX 0.3VCC 0.05VCC UNITS V V V V kW kW MW 0.95VCC 10 10 2 –10 0.05VCC 0.4 20 + 0.1CB 250 1 10 10 µA V V ns µA pF (Note 5) I = 3mA Bus Load CB 10pF to 400pF (Note 14) 0.1VCC ≤ VIN ≤ 0.9VCC ● ● ● ● ● 2493fa  LTC2493 power requireMenTs SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Current (Note 11) Temperature Measurement (Note 11) Sleep Mode (Note 11) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● ● ● ● MIN 2.7 TYP 160 200 1 MAX 5.5 275 300 2 UNITS V µA µA µA DigiTal inpuTs anD DigiTal ouTpuTs SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time for 1x Speed Mode CONDITIONS (Note 16) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN ● ● ● TYP MAX 4000 50 50 UNITS kHz µs µs ms ms ms ms ms ms ms ms 10 0.125 0.125 157.2 131 144.1 78.7 65.6 72.2 160.3 133.6 146.9 41036/fEOSC (in kHz) 80.3 66.9 73.6 50Hz Mode 60Hz Mode Simultaneous 50Hz/60Hz Mode External Oscillator (Note 10) 50Hz Mode 60Hz Mode Simultaneous 50Hz/60Hz Mode External Oscillator (Note 10) ● ● ● ● ● ● 163.5 136.3 149.9 81.9 68.2 75.1 tCONV_2 Conversion Time for 2x Speed Mode 20556/fEOSC (in kHz) i2c TiMing characTerisTics SYMBOL fSCL tHD(STA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Pin High Period of the SCL Pin Set-Up Time for a Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time for SDA Signals Fall Time for SDA Signals Set-Up Time for Stop Condition The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15) CONDITIONS ● ● ● ● ● ● ● MIN 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 TYP MAX 400 UNITS kHz µs µs µs µs 0.9 300 300 µs ns ns ns µs (Note 14) (Note 14) ● ● ● Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V VREFCM = VREF/2, FS = 0.5VREF VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the selected input channels. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator). Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses its internal oscillator. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation. Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF). Note 15: All values refer to VIH(MIN) and VIL(MAX) levels. Note 16: Refer to Applications Information section for Performance vs Data Rate graphs. 2493fa  LTC2493 Typical perForMance characTerisTics Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm of VREF) 1 0 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND –45°C INL (ppm of VREF) 25°C 3 2 1 0 –1 –2 –3 –1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 85°C INL (ppm of VREF) 3 2 1 0 –1 –2 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 85°C 2 2.5 – 0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2493 G02 –3 –1.25 – 0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2493 G03 2493 G01 12 8 TUE (ppm of VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 5V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 12 8 TUE (ppm of VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND 85°C 25°C TUE (ppm of VREF) 12 8 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 25°C 85°C 25°C 85°C –45°C –45°C –45°C –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 2.5 –12 –1.25 – 0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2493 G05 –12 –1.25 – 0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2493 G06 2493 G04 Noise Histogram (6.8sps) 14 12 NUMBER OF READINGS (%) 10,000 CONSECUTIVE READINGS RMS = 0.60µV VCC = 5V AVERAGE = – 0.69µV VREF = 5V 10 VIN = 0V TA = 25°C 8 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (µV) 1.2 1.8 14 12 NUMBER OF READINGS (%) Noise Histogram (7.5sps) 10,000 CONSECUTIVE READINGS RMS = 0.59µV VCC = 2.7V AVERAGE = – 0.19µV VREF = 2.5V 10 VIN = 0V TA = 25°C 8 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (µV) 1.2 1.8 5 4 3 ADC READING (µV) 2 1 0 –1 –2 –3 –4 –5 Long-Term ADC Readings VCC = 5V TA = 25°C VREF = 5V RMS NOISE = 0.60µV VIN = 0V VIN(CM) = 2.5V 0 10 30 40 20 TIME (HOURS) 50 60 2493 G09 2493 G07 2493 G08 2493fa  LTC2493 Typical perForMance characTerisTics RMS Noise vs Input Differential Voltage 1.0 0.9 RMS NOISE (µV) 0.8 0.7 0.6 0.5 0.4 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C FO = GND 1.0 0.9 RMS NOISE (µV) 0.8 0.7 0.6 0.5 0.4 RMS Noise vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25°C FO = GND 1.0 0.9 RMS NOISE (µV) 0.8 0.7 0.6 0.5 RMS Noise vs Temperature (TA) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 2.5 –1 0 1 2 3 4 5 6 2493 G11 0.4 –45 –30 –15 VIN(CM) (V) 0 15 30 45 60 TEMPERATURE (°C) 75 90 2493 G10 2493 G12 1.0 0.9 RMS NOISE (µV) 0.8 0.7 0.6 0.5 RMS Noise vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND TA = 25°C FO = GND 1.0 0.9 RMS NOISE (µV) 0.8 0.7 0.6 0.5 0.4 RMS Noise vs VREF VCC = 5V VIN = 0V VIN(CM) = GND TA = 25°C FO = GND 0.3 0.2 0.1 0 – 0.1 – 0.2 Offset Error vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25°C FO = GND 0.4 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 OFFSET ERROR (ppm of VREF) 0 1 2 3 VREF (V) 4 5 2493 G14 – 0.3 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2493 G15 2493 G13 Offset Error vs Temperature 0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.3 0.2 0.1 0 – 0.1 – 0.2 Offset Error vs VCC REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C FO = GND 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF – = GND VIN = 0V VIN(CM) = GND TA = 25°C FO = GND OFFSET ERROR (ppm of VREF) OFFSET ERROR (ppm of VREF) – 0.1 – 0.2 – 0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 – 0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 OFFSET ERROR (ppm of VREF) – 0.1 – 0.2 – 0.3 0 1 2 3 VREF (V) 4 5 2493 G18 2493 G16 2493 G17 2493fa  LTC2493 Typical perForMance characTerisTics On-Chip Oscillator Frequency vs Temperature 310 310 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 308 FREQUENCY (kHz) FREQUENCY (kHz) 308 306 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (°C) 75 90 304 302 302 300 –120 –140 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 300 –45 –30 –15 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2493 G20 2493 G19 2493 G21 PSRR vs Frequency at VCC 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2493 G22 CONVERSION CURRENT (µA) REJECTION (dB) VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 FO = GND TA = 25°C –60 –80 –100 0 PSRR vs Frequency at VCC 200 180 Conversion Current vs Temperature FO = GND VCC = 5V 160 VCC = 2.7V 140 120 100 –45 –30 –15 –120 –140 30600 30650 30750 FREQUENCY AT VCC (Hz) 30700 30800 2493 G23 0 15 30 45 60 TEMPERATURE (°C) 75 90 2493 G24 Sleep Mode Current vs Temperature 2.0 1.8 SLEEP MODE CURRENT (µA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 VCC = 2.7V VCC = 5V SUPPLY CURRENT (µA) FO = GND 500 450 400 350 300 250 200 150 100 Conversion Current vs Output Data Rate VREF = VCC IN+ = GND IN– = GND FO = EXT OSC TA = 25°C 3 2 VCC = 5V INL (µV) 1 0 –1 –2 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 5V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 25°C, 85°C VCC = 3V –45°C 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 G26 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 2.5 2493 G25 2493 G27 2493fa  LTC2493 Typical perForMance characTerisTics Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 2.5V) 3 2 INL (ppm OF VREF) 1 0 –1 –2 –3 –1.25 –45°C, 25°C VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) 85°C 3 2 1 0 –1 –2 –3 –1.25 –45°C, 25°C Integral Nonlinearity (2x Speed Mode; VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 85°C 16 Noise Histogram (2x Speed Mode) RMS = 0.85µV 10,000 CONSECUTIVE AVERAGE = 0.184mV 14 READINGS VCC = 5V 12 VREF = 5V VIN = 0V T = 25°C 10 A 8 6 4 2 NUMBER OF READINGS (%) 1.25 2493 G29 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2493 G28 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 0 179 181.4 183.8 186.2 OUTPUT READING (µV) 188.6 2493 G30 RMS Noise vs VREF (2x Speed Mode) 1.0 200 198 0.8 OFFSET ERROR (µV) RMS NOISE (µV) 196 194 192 190 188 186 184 182 3 2 VREF (V) 4 5 2493 G31 Offset Error vs VIN(CM) (2x Speed Mode) VCC = 5V VREF = 5V VIN = 0V FO = GND TA = 25°C 240 230 OFFSET ERROR (µV) 220 210 200 190 180 170 –1 0 1 3 VIN(CM) (V) 2 4 5 6 2493 G32 Offset Error vs Temperature (2x Speed Mode) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.6 0.4 0.2 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 0 1 0 180 160 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2493 G33 2493fa  LTC2493 Typical perForMance characTerisTics Offset Error vs VCC (2x Speed Mode) 250 VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 240 230 OFFSET ERROR (µV) 220 210 200 190 180 170 0 2 2.5 3 4 3.5 VCC (V) 4.5 5 5.5 2493 G34 Offset Error vs VREF (2x Speed Mode) VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 0 1 2 3 VREF (V) 4 5 2493 G35 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC ±0.7V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C 200 OFFSET ERROR (µV) 150 100 50 160 –140 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2493 G36 PSRR vs Frequency at VCC (2x Speed Mode) 0 –20 –40 –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2493 G37 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC ±0.7V REF+ = 2.5V REF– = GND IN+ = GND –40 IN– = GND FO = GND –60 TA = 25°C –20 –80 –100 –120 –140 30600 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2493 G38 RREJECTION (dB) REJECTION (dB) VCC = 4.1V DC ±1.4V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C 0 2493fa 0 LTC2493 pin FuncTions FO (Pin 1): Frequency Control Pin. Digital input that controls the internal conversion clock rate. When FO is connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate and the digital filter rejection null. CA0, CA1 (Pins 2, 3): Chip Address Control Pins. These pins are configured as a three-state (LOW, HIGH, Floating) address control bits for the device’s I2C address. SCL (Pin 4): Serial Clock Pin of the I2C Interface. The LTC2493 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. SDA (Pin 5): Bidirectional Serial Data Line of the I2C Interface. In the transmitter mode (Read), the conversion result is output through the SDA pin, while in the receiver mode (Write), the device channel select and configuration bits are input through the SDA pin. The pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to VCC) during the data output mode. GND (Pin 6): Ground. Connect this pin to a common ground plane through a low impedance connection. COM (Pin 7): The Common Negative Input (IN –) for All Single-Ended Multiplexer Configurations. The voltage on CH0-CH3 and COM pins can have any value between GND – 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN– ) provide a bipolar input range (VIN = IN+ – IN– ) from –0.5 • VREF to 0.5 • VREF . Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH3 (Pin 8-Pin 11): Analog Inputs. May be programmed for single-ended or differential mode. VCC (Pin 12): Positive Supply Voltage. Bypass to GND with a 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible. REF+, REF – (Pin 13, Pin 14): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF–, by at least 0.1V. The differential voltage (VREF = REF+ – REF –) sets the full-scale range for all input channels. Exposed Pad (Pin 15): Ground. This pin is ground and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating. 2493fa  LTC2493 FuncTional block DiagraM VCC GND REF + REF – CH0 CH1 CH2 CH3 COM IN+ MUX IN– TEMP SENSOR AUTOCALIBRATION AND CONTROL INTERNAL OSCILLATOR FO (INT/EXT) – + I2C INTERFACE DECIMATING FIR ADDRESS 2493 BD 1.7k SDA SCL CA0 CA1 DIFFERENTIAL 3RD ORDER ∆Σ MODULATOR 2493fa  LTC2493 applicaTions inForMaTion CONVERTER OPERATION Converter Operation Cycle The LTC2493 is a multichannel, low power, delta-sigma analog-to-digital converter with a 2-wire, I2C interface. Its operation is made up of four states (see Figure 1). The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/output cycle . Initially, at power-up, the LTC2493 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in the sleep state, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long it is not addressed for a read/write operation. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. The device will not acknowledge an external request during the conversion state. After a conversion is finished, the device is ready to accept a read/write request. Once the LTC2493 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. The data output is 32 bits long and contains a 24-bit plus sign conversion result. Data is updated on the falling edges of SCL allowing the user to reliably latch data on the rising edge of SCL. A new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation. The conversion automatically begins at the conclusion of a complete read cycle (all 32 bits read out of the device). Ease of Use The LTC2493 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input or mode, is valid and accurate to the full specifications of the device. POWER-ON RESET DEFAULT CONFIGURATION: IN+ = CH0, IN– = CH1 50Hz/60Hz REJECTION 1X OUTPUT CONVERSION SLEEP NO ACKNOWLEDGE YES DATA OUTPUT/INPUT NO STOP OR READ 32 BITS YES 2493 F01 Figure 1. State Transition Table The LTC2493 automatically performs offset and full-scale calibration every conversion cycle independent of the input channel selected. This calibration is transparent to the user and has no effect on the operation cycle described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. Easy Drive Input Current Cancellation The LTC2493 combines a high precision, delta-sigma ADC with an automatic, differential, input current cancellation front end. A proprietary front end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2493 without external 2493fa  LTC2493 applicaTions inForMaTion amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see the Automatic Differential Input Current Cancellation section). This unique architecture does not require on-chip buffers, thereby enabling signals to swing beyond ground and VCC. Moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external RC networks. Power-Up Sequence The LTC2493 automatically enters an internal reset state when the power supply voltage, VCC, drops below approximately 2.0V. This feature guarantees the integrity of the conversion result and input channel selection. When VCC rises above this threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. The conversion immediately following a POR cycle is performed on the input channel IN+ = CH0, IN – = CH1 with simultaneous 50Hz/60Hz rejection and 1x output rate. The first conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7V to 5.5V) before the end of the POR interval. A new input channel, rejection mode, speed mode, or temperature selection can be programmed into the device during this first data input/output cycle. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage range for the REF+ and REF – pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF must be positive (REF+ > REF –). The LTC2493 differential reference input range is 0.1V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF – can be shorted to GND. The converter output noise is determined by the thermal noise of the front end circuits and, as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a decreased reference will improve the converter’s overall INL performance. Input Voltage Range The analog inputs are truly differential with an absolute, common mode range for the CH0-CH3 and COM input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2493 converts the bipolar differential input signal VIN = IN+ – IN– (where IN+ and IN – are the selected input channels), from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ - REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see Table 1). In order to limit any fault current, resistors of up to 5kW may be added in series with the input. The effect of series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent error due to input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. I2C INTERFACE The LTC2493 communicates through an I2C interface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. The connected devices can only pull the data line (SDA) low and can never drive it high. SDA is required to be externally 2493fa  LTC2493 applicaTions inForMaTion connected to the supply through a pull-up resistor. When the data line is not being driven, it is high. Data on the I2C bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. Each device on the I2C bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Devices addressed by the master are considered a slave. The LTC2493 can only be addressed as a slave. Once addressed, it can receive configuration bits (channel selection, rejection mode, speed mode) or transmit the last conversion result. The serial clock line, SCL, is always an input to the LTC2493 and the serial data line SDA is bidirectional. The device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. Figure 2 shows the definition of the I2C timing. The Start and Stop Conditions A Start (S) condition is generated by transitioning SDA from high to low while SCL is high. The bus is considered to be busy after the Start condition. When the data transfer is finished, a Stop (P) condition is generated by transitioning SDA from low to high while SCL is high. The bus is free after a Stop is generated. Start and Stop conditions are always generated by the master. When the bus is in use, it stays busy if a Repeated Start (Sr) is generated instead of a Stop condition. The repeated Start timing is functionally identical to the Start and is used for writing and reading from the device before the initiation of a new conversion. Data Transferring After the Start condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA low or issue a Not Acknowledge (NAK) by leaving the SDA line high impedance (the external pull-up resistor will hold the line high). Change of data only occurs while the clock line (SCL) is low. DATA FORMAT After a Start condition, the master sends a 7-bit address followed by a read/write (R/W) bit. The R/W bit is 1 for a read request and 0 for a write request. If the 7-bit address matches the hard wired LTC2493’s address (one of 9 pin-selectable addresses) the device is selected. When the device is addressed during the conversion state, it will not acknowledge R/W requests and will issue a NAK by leaving the SDA line high. If the conversion is complete, the LTC2493 issues an ACK by pulling the SDA line low. The LTC2493 has two registers. The output register (32 bits long) contains the last conversion result. The input register (16 bits long) sets the input channel, selects the temperature sensor, rejection mode, and speed mode. SDA tf SCL S tHD(SDA) tHD(DAT) tHIGH tSU(STA) Sr tSU(STO) P S 2493 F02 tLOW tr tSU(DAT) tf tHD(SDA) tSP tr tBUF Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus 2493fa  LTC2493 applicaTions inForMaTion DATA OUTPUT FORMAT The output register contains the last conversion result. After each conversion is completed, the device automatically enters the sleep state where the supply current is reduced to 1µA. When the LTC2493 is addressed for a read operation, it acknowledges (by pulling SDA low) and acts as a transmitter. The master/receiver can read up to four bytes from the LTC2493. After a complete read operation (4 bytes), a new conversion is initiated. The device will NAK subsequent read operations while a conversion is being performed. The data output stream is 32 bits long and is shifted out on the falling edges of SCL (see Figure 3a). The first bit is the conversion result sign bit (SIG) (see Tables 1 and 2). This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN corresponds to the selected input signal IN+ – IN–). The second bit is the most significant bit (MSB) of the result. The first two bits (SIG and MSB) can be used to indicate over and under range conditions (see Table 2). If both bits are HIGH, the differential input voltage is equal to or above +FS. If both bits are set low, the input voltage is below –FS. The function of these bits is summarized in Table 2. The 24 bits following the MSB bit are the conversion result in binary two’s, complement format. The remaining six bits are sub LSBs below the 24-bit level. As long as the voltage on the selected input channels (IN+ and IN–) remains between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 • VREF . For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to +FS. For differential input voltages below –FS, the conversion result is clamped to the value –FS – 1LSB. Table 2. LTC2493 Status Bits Input Range VIN ≥ FS 0V ≤ VIN < FS –FS ≤ VIN < 0V VIN < –FS Bit 31 SIG 1 1 0 0 Bit 30 MSB 1 0 1 0 INPUT DATA FORMAT The serial input word to the LTC2493 is 13 bits long and is written into the device input register in two 8-bit words. Table 1. Output Data Format Differential Input Voltage VIN* VIN* ≥ FS** FS** – 1LSB 0.5 • FS** 0.5 • FS** – 1LSB 0 –1LSB –0.5 • FS** –0.5 • FS** – 1LSB –FS** VIN* < –FS** Bit 31 SIG 1 1 1 1 1 0 0 0 0 0 Bit 30 MSB 1 0 0 0 0 1 1 1 1 0 Bit 29 0 1 1 0 0 1 1 0 0 1 Bit 28 0 1 0 1 0 1 0 1 0 1 Bit 27 0 1 0 1 0 1 0 1 0 1 … … … … … … … … … … … Bit 6 LSB 0 1 0 1 0 1 0 1 0 1 Bits 5-0 Sub LSBs*** 00000 XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX 11111 *The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF . *** Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution. 2493fa  LTC2493 applicaTions inForMaTion The first word (SGL, ODD, A2, A1, A0) is used to select the input channel. The second word of data (IM, FA, FB, SPD) is used to select the frequency rejection, speed mode (1x, 2x), and temperature measurement. After power-up, the device initiates an internal reset cycle which sets the input channel to CH0-CH1 (IN+ = CH0, IN– = CH1), the frequency rejection to simultaneous 50Hz/60Hz, and 1x output rate (auto-calibration enabled). The first conversion automatically begins at power-up using this default configuration. Once the conversion is complete, up to two words may be written into the device. The first three bits of the first input word consist of two preamble bits and one enable bit. Valid settings for these three bits are 000, 100, and 101. Other combinations should be avoided. If the first three bits are 000 or 100, the following data is ignored (don’t care) and the previously selected input channel remains valid for the next conversion. SCL 1 … 7 8 9 1 2 … 9 If the first three bits shifted into the device are 101, then the next five bits select the input channel for the next conversion cycle (see Table 3). The first input bit (SGL) following the 101 sequence determines if the input selection is differential (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL = 1, one of 4 channels is selected as the positive input. The negative input is COM for all single-ended operations. The remaining four bits (ODD, A2, A1, A0) determine which channel(s) is/are selected and the polarity (for a differential input). Once the first word is written into the device, a second word may be input in order to select a configuration mode. The first bit of the second word is the enable bit for the conversion configuration (EN2). If this bit is set to 0, then the next conversion is performed using the previously selected converter configuration. 1 2 3 4 5 6 7 8 9 SDA 7-BIT ADDRESS R ACK BY LTC2493 SIG MSB D31 ACK BY MASTER LSB NAK BY MASTER START BY MASTER SLEEP SUB LSBs DATA OUTPUT 2493 F03a Figure 3a. Timing Diagram for Reading from the LTC2493 SCL 1 2 … 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA 7-BIT ADDRESS W ACK BY LTC2493 SLEEP 1 0 EN SGL ODD A2 A1 A0 ACK BY LTC2493 DATA INPUT EN2 IM FA FB SPD ACK BY LTC2493 START BY MASTER (OPTIONAL 2ND BYTE) 2493 F03b Figure 3b. Timing Diagram for Writing to the LTC2493 2493fa  LTC2493 applicaTions inForMaTion Table 3 Channel Selection MUX ADDRESS SGL *0 0 0 0 1 1 1 1 ODD/ SIGN 0 0 1 1 0 0 1 1 A2 0 0 0 0 0 0 0 0 A1 0 0 0 0 0 0 0 0 A0 0 1 0 1 0 1 0 1 IN+ IN+ IN+ IN+ IN– IN+ IN– IN+ IN– IN– IN– IN– 0 IN+ CHANNEL SELECTION 1 IN– IN+ IN– 2 3 COM set the rejection frequency. The final bit (SPD) is used to select either the 1x output rate if SPD = 0 (auto-calibration is enabled and the offset is continuously calibrated and removed from the final conversion result) or the 2x output rate if SPD = 1 (offset calibration disabled, multiplexing output rates up to 15Hz with no latency). When IM = 1 (temperature measurement) SPD will be ignored and the device will operate in 1x mode. The configuration remains valid until a new input word with EN = 1 (the first three bits are 101 for the first word) and EN2 = 1 (for the second write byte) is shifted into the device. Rejection Mode (FA, FB) The LTC2493 includes a high accuracy on-chip oscillator with no required external components. Coupled with an integrated fourth order digital low pass filter, the LTC2493 rejects line frequency noise. In the default mode, the LTC2493 simultaneously rejects 50Hz and 60Hz by at least 87dB. If more rejection is required, the LTC2493 can be configured to reject 50Hz or 60Hz to better than 110dB. *Default at power up The second set of configuration data can be loaded into the device by setting EN2 = 1 (see Table 4). The first bit (IM) is used to select the internal temperature sensor. If IM = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. The next two bits (FA and FB) are used to Table 4. Converter Configuration 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 SGL X X X X X X X X X X X X X ODD X X X X X X X X X X X X X A2 X X X X X X X X X X X X X A1 X X X X X X X X X X X X X A0 X X X X X X X X X X X X X EN2 X 0 X 1 1 1 1 1 1 1 1 1 1 IM X X X 0 0 0 0 0 0 1 1 1 X FA X X X 0 0 1 0 0 1 0 0 1 1 FB X X X 0 1 0 0 1 0 0 1 0 1 SPD X X X 0 0 0 1 1 1 X X X X CONVERTER CONFIGURATION Keep Previous Keep Previous Keep Previous External Input (See Table 3) 50Hz/60Hz Rejection, 1x External Input (See Table 3) 50Hz Rejection, 1x External Input (See Table 3) 60Hz Rejection, 1x External Input (See Table 3) 50Hz/60Hz Rejection, 2x External Input (See Table 3) 50Hz Rejection, 2x External Input (See Table 3) 60Hz Rejection, 2x Measure Temperature 50Hz/60Hz Rejection, 1x Measure Temperature 50Hz Rejection, 1x Measure Temperature 60Hz Rejection, 1x Reserved, Do Not Use 2493fa  LTC2493 applicaTions inForMaTion Speed Mode (SPD) Every conversion cycle, two conversions are combined to remove the offset (default mode). This result is free from offset and drift. In applications where the offset is not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. While operating in the 2x mode (SPD = 1), the linearity and full-scale errors are unchanged from the 1x mode performance. In both the 1x and 2x mode there is no latency. This enables input steps or multiplexer changes to settle in a single conversion cycle, easing system overhead and increasing the effective conversion rate. During temperature measurements, the 1x mode is always used independent of the value of SPD. Temperature Sensor The LTC2493 includes an integrated temperature sensor. The temperature sensor is selected by setting IM = 1. The ADC internally connects to the temperature sensor and performs a conversion. The digital output is proportional to the absolute temperature of the device. This feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. The internal temperature sensor output is 28mV at 27ºC (300ºK), with a slope of 93.5µV/ºC independent of VREF 140000 VCC = 5V VREF = 5V 120000 SLOPE = 314 LSB /K 24 100000 DATAOUT24 80000 60000 40000 20000 0 0 100 200 300 TEMPERATURE (K) 400 2493 F04 (see Figures 4 and 5). Slope calibration is not required if the reference voltage (VREF) is known. A 5V reference has a slope of 314 LSBs24/ºC. The temperature is calculated from the output code (where DATAOUT24 is the decimal representation of the 24-bit result) for a 5V reference using the following formula: TK = DA TA OUT24 in Kelvin 314 If a different value of VREF is used, the temperature output is: DA TA OUT24 • VRE F TK = in Kelvin 1570 If the value of VREF is not known, the slope is determined by measuring the temperature sensor at a known temperature TN (in K) and using the following formula: S L OP E = DA TA OUT24 TN This value of slope can be used to calculate further temperature readings using: TK = DA TA OUT24 SL OP E All Kelvin temperature readings can be converted to TC (ºC) using the fundamental equation: TC = TK – 273 5 4 3 ABSOLUTE ERROR (°C) 2 1 0 –1 –2 –3 –4 –5 –55 –30 –5 20 45 70 TEMPERATURE (°C) 95 120 2493 F05 Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error 2493fa  LTC2493 applicaTions inForMaTion Initiating a New Conversion When the LTC2493 finishes a conversion, it automatically enters the sleep state. Once in the sleep state, the device is ready for a read operation. After the device acknowledges a read request, the device exits the sleep state and enters the data output state. The data output state concludes and the LTC2493 starts a new conversion once a Stop condition is issued by the master or all 32 bits of data are read out of the device. During the data read cycle, a Stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. This Stop command must be issued during the ninth clock cycle of a byte read when the bus is free (the ACK/NAK cycle). LTC2493 Address The LTC2493 has two address pins (CA0, CA1). Each may be tied high, low, or left floating enabling one of 9 possible addresses (see Table 5). In addition to the configurable addresses listed in Table 5, the LTC2493 also contains a global address (1110111) which may be used for synchronizing multiple LTC2493s or other LTC24XX delta-sigma I2C devices (see Synchronizing Multiple LTC2493s with a Global Address Call section). Operation Sequence The LTC2493 acts as a transmitter or receiver, as shown in Figure 6. The device may be programmed to perform several functions. These include input channel selection, Table 5. Address Assignment CA1 LOW LOW LOW HIGH HIGH HIGH FLOAT FLOAT FLOAT CA0 LOW HIGH FLOAT LOW HIGH FLOAT LOW HIGH FLOAT ADDRESS 0010100 0010110 0010101 0100110 0110100 0100111 0010111 0100101 0100100 measure the internal temperature, selecting the line frequency rejection (50Hz, 60Hz, or simultaneous 50Hz and 60Hz) and a 2x speed mode. Continuous Read In applications where the input channel/configuration does not need to change for each cycle, the conversion can be continuously performed and read without a write cycle (see Figure 7). The configuration/input channel remains unchanged from the last value written into the device. If the device has not been written to since power up, the configuration is set to the default value. At the end of a read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2493 generates a NAK signal indicating the conversion cycle is in progress. S 7-BIT ADDRESS R/W ACK DATA Sr DATA TRANSFERRING P CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2493 F05 Figure 6. Conversion Sequence 2493fa 0 LTC2493 applicaTions inForMaTion Continuous Read/Write Once the conversion cycle is concluded, the LTC2493 can be written to and then read from using the Repeated Start (Sr) command. Figure 8 shows a cycle which begins with a data Write, a repeated Start, followed by a Read and concluded with a Stop command. The following conversion begins after all 32 bits are read out of the device or after a Stop command. The following conversion will be performed using the newly programmed data. In cases where the same speed (1x/2x mode) and rejection frequency (50Hz, 60Hz, 50Hz and 60Hz) is used but the channel is changed, a Stop or Repeated Start may be issued after the first byte (channel selection data) is written into the device. Discarding a Conversion Result and Initiating a New Conversion with Optional Write At the conclusion of a conversion cycle, a write cycle can be initiated. Once the write cycle is acknowledged, a Stop command will start a new conversion. If a new input channel or conversion configuration is required, this data can be written into the device and a Stop command will initiate the next conversion (see Figure 9). S 7-BIT ADDRESS R ACK READ P S 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPU T CONVERSION SLEEP DATA OUTPUT CONVERSION 2493 F07 Figure 7. Consecutive Reading with the Same Input/Configuration S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPU T ADDRESS DATA OUTPUT CONVERSION 2493 F08 Figure 8. Write, Read, Start Conversion S 7-BIT ADDRESS W ACK WRITE (OPTIONAL) P CONVERSION SLEEP DATA INPU T CONVERSION 2493 F09 Figure 9. Start a New Conversion Without Reading Old Conversion Result 2493fa  LTC2493 applicaTions inForMaTion Synchronizing Multiple LTC2493s with a Global Address Call In applications where several LTC2493s (or other I2C delta-sigma ADCs from Linear Technology Corporation) are used on the same I2C bus, all converters can be synchronized through the use of a global address call. Prior to issuing the global address call, all converters must have completed a conversion cycle. The master then issues a Start, followed by the global address 1110111, and a write request. All converters will be selected and acknowledge the request. The master then sends a write byte (optional) followed by the Stop command. This will update the channel selection (optional) converter configuration (optional) and simultaneously initiate a start of conversion for all delta-sigma ADCs on the bus (see Figure 10). In order SCL SDA LTC2493 S GLOBAL ADDRESS ALL LTC2493s IN SLEEP LTC2493 W ACK … WRITE (OPTIONAL) LTC2493 P CONVERSION OF ALL LTC2493s 2493 F10 to synchronize multiple converters without changing the channel or configuration, a Stop may be issued after acknowledgement of the global write command. Global read commands are not allowed and the converters will NAK a global read request. Driving the Input and Reference The input and reference pins of the LTC2493 are connected directly to a switched capacitor network. Depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. Each time a capacitor is switched between two of these pins, a small amount of charge is transferred. A simplified equivalent circuit is shown in Figure 11. DATA INPUT Figure 10. Synchronize Multiple LTC2493s with a Global Address Call INPUT MULTIPLEXER 100Ω INTERNAL SWITCH NETWORK 10kΩ IIN + IN+ I IN+ () ( AVG = I IN– ≈ () AVG = VIN(CM) − VREF(CM) 0.5 • REQ IIN– IN– 100Ω 10kΩ I REF + where : ) 1.5VREF + VREF(CM) – VIN(CM) 0.5 • REQ ( AVG )– VIN2 VREF • REQ VREF = REF + − REF − CEQ 12µF IREF+ REF+ 10kΩ  REF + – REF − VREF(CM) =   2      VIN = IN+ − IN− , WHERE IN+ AND IN− ARE THE SELECTED INPUT CHANNELS  IN+ – IN−  VIN(CM) =     2   REQ = 2.71MW INTERNAL OSCILLATOR 60Hz MODE IREF– REF– SWITCHING FREQUENCY fSW = 123kHz INTERNAL OSCILLATOR fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR 10kΩ 2493 F11a REQ = 2.98 MW INTERNAL OSCILLATOR 50Hz/60Hz MODE REQ = 0.833 • 1012 /fEOSC EXTERNAL OSCILLATOR ( ) Figure 11. Equivalent Analog Input Circuit 2493fa  LTC2493 applicaTions inForMaTion When using the LTC2493’s internal oscillator, the input capacitor array is switched at 123kHz. The effect of the charge transfer depends on the circuitry driving the input/reference pins. If the total external RC time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. Typically, the reference inputs are driven from a low impedance source. In this case, complete settling occurs even with large external bypass capacitors. The inputs (CH0-CH3, COM), on the other hand, are typically driven from larger source resistances. Source resistances up to 10k may interface directly to the LTC2493 and settle completely; however, the addition of external capacitors at the input terminals in order to filter unwanted noise (antialiasing) results in incomplete settling. Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low (up to 10kW with no external bypass capacitor or up to 500W with 0.001µF bypass), complete settling of the input occurs. In this case, no errors are introduced and direct digitization is possible. For many applications, the sensor output impedance combined with external input bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy. For example, a 10kW bridge driving a 0.1µF capacitor has a time constant an order of magnitude greater than the required maximum. The LTC2493 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. This allows direct digitization of high impedance sensors without the need for buffers. The switching algorithm forces the average input current on the positive input (IIN+) to be equal to the average input current on the negative input (IIN–). Over the complete conversion cycle, the average differential input current (IIN+ – IIN–) is zero. While the differential input current is zero, the common mode input current (IIN+ + IIN–)/2 is proportional to the difference between the common mode input voltage (VIN(CM)) and the common mode reference voltage (VREF(CM)). In applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and common mode input current are zero. The accuracy of the converter is not compromised by settling errors. In applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between VIN(CM) and VREF(CM). For a reference common mode voltage of 2.5V and an input common mode of 1.5V, the common mode input current is approximately 0.74µA (in simultaneous 50Hz/60Hz rejection mode). This common mode input current does not degrade the accuracy if the source impedances tied to IN+ and IN– are matched. Mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full-scale reading. A 1% mismatch in a 1kW source resistance leads to a 74µV shift in offset voltage. In applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. For the case of balanced input impedances, the common mode input current effects are rejected by the large CMRR of the LTC2493, leading to little degradation in accuracy. Mismatches in source impedances lead to gain errors proportional to the difference between the common mode input and common mode reference. 1% mismatches in 1k source resistances lead to gain errors on the order of 15ppm. Based on the stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will remove this error. In addition to the input sampling current, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 1k source resistance will create a 1µV typical and a 10µV maximum offset voltage. 2493fa  LTC2493 applicaTions inForMaTion Reference Current Similar to the analog inputs, the LTC2493 samples the differential reference pins (REF+ and REF–) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. For relatively small values of external reference capacitance (CREF < 1nF), the voltage on the sampling capacitor settles 90 80 70 +FS ERROR (ppm) 60 50 40 30 20 10 0 –10 0 10 1k 100 RSOURCE (Ω) 10k 100k 2493 F12 for reference impedances of many kW (if CREF = 100pF up to 10kW will not degrade the performance (see Figures 12 and 13)). In cases where large bypass capacitors are required on the reference inputs (CREF > .01µF), full-scale and linearity errors are proportional to the value of the reference resistance. Every ohm of reference resistance produces a full-scale error of approximately 0.5ppm (while operating in simultaneous 50Hz/60Hz mode (see Figures 14 and 15)). If the input common mode voltage is equal to 10 0 –10 –FS ERROR (ppm) –20 –30 –40 –50 VCC = 5V –60 VREF = 5V V + = 1.25V –70 VIN– = 3.75V IN –80 FO = GND TA = 25°C –90 10 0 CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C CREF = 0.01µF CREF = 0.001µF CREF = 100pF CREF = 0pF 1k 100 RSOURCE (Ω) 10k 100k 2493 F13 Figure 12. +FS Error vs RSOURCE at VREF (Small CREF) Figure 13. –FS Error vs RSOURCE at VREF (Small CREF) 500 400 +FS ERROR (ppm) 300 CREF = 0.1µF –FS ERROR (ppm) VCC = 5V VREF = 5V VIN+ = 3.75V VIN– = 1.25V FO = GND TA = 25°C 0 CREF = 1µF, 10µF –100 CREF = 0.01µF –200 CREF = 1µF, 10µF –300 VCC = 5V VREF = 5V VIN+ = 1.25V VIN– = 3.75V FO = GND TA = 25°C 0 200 600 400 RSOURCE (Ω) CREF = 0.1µF 200 CREF = 0.01µF 100 –400 0 0 200 600 400 RSOURCE (Ω) 800 1000 2493 F14 –500 800 1000 2493 F15 Figure 14. +FS Error vs RSOURCE at VREF (Large CREF) Figure 15. –FS Error vs RSOURCE at VREF (Large CREF) 2493fa  LTC2493 applicaTions inForMaTion the reference common mode voltage, a linearity error of approximately 0.67ppm per 100W of reference resistance results (see Figure 16). In applications where the input and reference common mode voltages are different, the errors increase. A 1V difference in between common mode input and common mode reference results in a 6.7ppm INL error for every 100W of reference resistance. In addition to the reference sampling charge, the reference ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max) results in a small gain error. A 100W reference resistance will create a 0.5µV full-scale error. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversample ratio, the LTC2493 significantly simplifies antialiasing filter requirements. Additionally, the input current cancellation feature allows external low pass filtering without degrading the DC performance of the device. 10 VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10µF 2 0 –2 –4 –6 –8 –10 – 0.5 – 0.3 0.1 – 0.1 VIN/VREF 0.3 0.5 2493 F16 The SINC4 digital filter provides excellent normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS) (see Figures 17 and 18). The modulator sampling frequency is fS = 15,360Hz while operating with its internal oscillator and fS = fEOSC/20 when operating with an external oscillator of frequency fEOSC . 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 – 100 – 110 – 120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2493 F17 Figure 17. Input Normal Mode Rejection, Internal Oscillator and 50Hz Rejection Mode 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 – 100 – 110 – 120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2493 F18 R = 1k INL (ppm OF VREF) R = 500Ω R = 100Ω Figure 16. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1µF Figure 18. Input Normal Mode Rejection, Internal Oscillator and 60Hz Rejection Mode 2493fa  LTC2493 applicaTions inForMaTion When using the internal oscillator, the LTC2493 is designed to reject line frequencies. As shown in Figure 19, rejection nulls occur at multiples of frequency fN, where fN is determined by the input control bits FA and FB (fN = 50Hz or 60Hz or 55Hz for simultaneous rejection). Multiples of the modulator sampling rate (fS = fN • 256) only reject noise to 15dB (see Figure 20); if noise sources are present at these frequencies antialiasing will reduce their effects. The user can expect to achieve this level of performance using the internal oscillator, as shown in Figures 21, 22, and 23. Measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 – 100 – 110 – 120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN Traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2493 third order modulator resolves this problem and guarantees stability with input signals 150% of full scale. In many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts if peak-to-peak noise. Figures 24 and 25 show measurement results for the rejection of a 7.5V peak-to-peak noise source (150% of full scale) applied to the LTC2493. These curves show that the rejection performance is maintained even in extremely noisy environments. fN = fEOSC/5120 2493 F19 Figure 19. Input Normal Mode Rejection at DC 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 – 100 – 110 fN = fEOSC/5120 – 120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2493 F20 Figure 20. Input Normal Mode Rejection at fS = 256 • fN 2493fa  LTC2493 applicaTions inForMaTion 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 – 100 – 120 MEASURED DATA CALCULATED DATA NORMAL MODE REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 – 60 –80 – 100 – 120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2493 F21 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2493 F22 Figure 21. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (60Hz Notch) Figure 22. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 – 100 – 120 MEASURED DATA CALCULATED DATA NORMAL MODE REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 –20 –40 – 60 –80 – 100 – 120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2493 F23 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2493 F24 Figure 23. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz/60Hz Notch) Figure 24. Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 – 100 – 120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2493 F25 Figure 25. Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (50Hz Notch) 2493fa  LTC2493 applicaTions inForMaTion Using the 2X speed mode of the LTC2493 alters the rejection characteristics around DC and multiples of fS. The device bypasses the offset calibration in order to increase the output rate. The resulting rejection plots are shown in Figures 26 and 27. 1x type frequency rejection can be achieved using the 2x mode by performing a running average of the previoius two conversion results (see Figure 28). Output Data Rate When using its internal oscillator, the LTC2493 produces up to 15 samples per second (sps) with a notch frequency of 60Hz. The actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. When operating with an external conversion clock (fO connected to an external oscillator), the LTC2493 output data rate can be increased. The duration of the conversion cycle is 41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves as if the internal oscillator is used. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate (up to a maximum of 100sps). The increase in 0 INPUT NORMAL REJECTION (dB) –20 –40 –60 –80 INPUT NORMAL REJECTION (dB) 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (fN) 8fN output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. When using the integrated temperature sensor, the internal oscillator should be used or an external oscillator fEOSC = 307.2kHz maximum. A change in fEOSC results in a proportional change in the internal notch position. This leads to reduced differential mode rejection of line frequencies. The common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the IN+ and IN – pins will continue to reject line frequency noise. An increase in fEOSC also increases the effective dynamic input and reference current. External RC networks will continue to have zero differential input current, but the time required for complete settling (580ns for fEOSC = 307.2kHz) is reduced, proportionally. Once the external oscillator frequency is increased above 1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade. This results in larger offset errors, full-scale errors, and decreased resolution, as seen in Figures 29-36. 0 –20 –40 –60 –80 –100 –120 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY (fN) 2493 F27 –100 –120 2493 F26 Figure 26. Input Normal Mode Rejection 2x Speed Mode Figure 27. Input Normal Mode Rejection 2x Speed Mode 2493fa  LTC2493 applicaTions inForMaTion –70 NORMAL MODE REJECTION (dB) –80 NO AVERAGE –90 –100 –110 –120 –130 –140 60 62 48 50 54 56 58 52 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2493 F28 50 40 30 20 10 0 OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK TA = 85°C 3500 3000 2500 2000 1500 1000 500 0 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK TA = 85°C WITH RUNNING AVERAGE TA = 25°C TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F29 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F30 Figure 28. Input Normal Mode Rejection 2x Speed Mode with and Without Running Averaging 0 –500 –FS ERROR (ppm OF VREF) RESOLUTION (BITS) –1000 TA = 25°C TA = 85°C 24 22 20 18 16 14 12 10 Figure 29. Offset Error vs Output Data Rate and Temperature Figure 30. +FS Error vs Output Data Rate and Temperature 22 TA = 25°C TA = 85°C RESOLUTION (BITS) 20 18 16 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F33 –1500 –2000 TA = 85°C TA = 25°C –2500 V = VREF(CM) –3000 IN(CM) VCC = VREF = 5V FO = EXT CLOCK –3500 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F32 Figure 31.–FS Error vs Output Data Rate and Temperature 2493 F31 Figure 32. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature Figure 33. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 20 OFFSET ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25°C RESOLUTION (BITS) 10 5 0 –5 VCC = VREF = 5V 24 22 20 18 16 14 VIN(CM) = VREF(CM) VIN = 0V FO = EXT CLOCK 12 T = 25°C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F35 VCC = VREF = 5V VCC = 5V, VREF = 2.5V RESOLUTION (BITS) 22 20 18 VCC = VREF = 5V 16 VCC = 5V, VREF = 2.5V VCC = 5V, VREF = 2.5V 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F34 –10 VIN(CM) = VREF(CM) 14 VIN = 0V REF– = GND 12 FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2493 F36 Figure 34. Offset Error vs Output Data Rate and Temperature Figure 35. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature Figure 36. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 2493fa  LTC2493 applicaTions inForMaTion Easy Drive ADCs Simplify Measurement of High Impedance Sensors Delta-Sigma ADCs, with their high accuracy and high noise immunity, are ideal for directly measuring many types of sensors. Nevertheless, input sampling currents can overwhelm high source impedances or low-bandwidth, micropower signal conditioning circuits. The LTC2493 solves this problem by balancing the input currents, thus simplifying or eliminating the need for signal conditioning circuits. A common application for a delta-sigma ADC is thermistor measurement. Figure 37 shows two examples of thermistor digitization benefiting from the Easy Drive technology. The first circuit (applied to input channels CH0 and CH1) uses balanced reference resistors in order to balance the common mode input/reference voltage and balance the differential input source resistance. If reference resistors R1 and R4 are exactly equal, the input current is zero and no errors result. If these resistors have a 1% tolerance, the maximum error in measured resistance is 1.6W due to a shift in common mode voltage; far less than the 1% error of the reference resistors themselves. No amplifier is required, making this an ideal solution in micropower applications. Easy Drive also enables very low power, low bandwidth amplifiers to drive the input to the LTC2493. As shown in Figure 7, CH2 is driven by the LT1494. The LT1494 has excellent DC specs for an amplifier with 1.5µA supply current (the maximum offset voltage is 150µV and the open loop gain is 100,000). Its 2kHz bandwidth makes it unsuitable for driving conventional delta sigma ADCs. Adding a 1kW, 0.1µF filter solves this problem by providing a charge reservoir that supplies the LTC2493 instantaneous current, while the 1k resistor isolates the capacitive load from the LT1494. Conventional delta sigma ADCs input sampling current lead to DC errors as a result of incomplete settling in the external RC network. The Easy Drive technology cancels the differential input current. By balancing the negative input (CH3) with a 1kW, 0.1µF network errors due to the common mode input current are cancelled. 2493fa 0 LTC2493 package DescripTion (Reference LTC DWG # 05-08-1708 Rev B) DE Package 14-Lead Plastic DFN (4mm × 3mm) 0.70 ± 0.05 3.60 ± 0.05 2.20 ± 0.05 3.30 ± 0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) R = 0.05 TYP 3.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 8 R = 0.115 TYP 0.40 ± 0.10 14 3.30 ± 0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 1 0.25 ± 0.05 0.50 BSC 3.00 REF (DE14) DFN 0806 REV B 7 0.200 REF 0.75 ± 0.05 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2493fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LTC2493 Typical applicaTion 5V R1 51.1k C4 0.1µF IIN+ = 0 R3 10k TO 100k R4 IIN– = 0 51.1k 10µF 13 0.1µF C3 0.1µF 5V 102k 5V 14 8 9 10 11 LT1494 1k 0.1µF 1k 0.1µF 7 5V 12 VCC LTC2493 REF + REF– CH0 CH1 CH2 CH3 COM GND 2493 F37 FO 1 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 1.7k SDA SCL 5 4 2-WIRE I2C INTERFACE CA0 CA1 6 2 3 9-PIN SELECTABLE ADDRESSES + 0.1µF 10k TO 100k – Figure 37. Easy Drive ADCs Simplify Measurement of High Impedance Sensors relaTeD parTs PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 LTC2440 LTC2442 LTC2449 LTC2480/LTC2482/ LTC2484 LTC2481/LTC2483/ LTC2485 LTC2486/LTC2488/ LTC2492 LTC2487 LTC2489 LTC2495/LTC2497/ LTC2499 LTC2496/LTC2498 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency DS ADC in SO-8 24-Bit, No Latency DS ADC with Differential Inputs 24-Bit, High Speed, Low Noise DS ADC 24-Bit, High Speed, 2-/4-Channel DS ADC with Integrated Amplifier 24-Bit, High Speed, 8-/16-Channel DS ADC 16-Bit/24-Bit DS ADCs with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit/24-Bit DS ADCs with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit/24-Bit 2-/4-Channel DS ADC with Easy Drive Inputs, SPI Interface, Programmable Gain, and Temperature Sensor 16-Bit 2-/4-Channel DS ADC with Easy Drive Inputs and I2C Interface, Temperature Sensor 16-Bit 2-/4-Channel DS ADC with Easy Drive Inputs 16-Bit/24-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and SPI Interface COMMENTS 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.05% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA 0.8µVRMS Noise, 2ppm INL 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz Rejection 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz Rejection Pin Compatible 16-Bit and 24-Bit Versions Pin Compatible 16-Bit and 24-Bit Versions Pin-Compatible 16-Bit and 24-Bit Versions Pin-Compatible with LTC2493/LTC2489 Pin-Compatible with LTC2487/LTC2493 Pin-Compatible 16-Bit and 24-Bit Versions Pin-Compatible with LTC2498/LTC2449 2493fa  Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/CGRAFX 0407 REV A • PRINTED IN USA www.linear.com  LINEAR TECHNOLOGY CORPORATION 2007