LTC2494IUHF-TRPBF

FEATURES ■ ■ LTC2494 16-Bit 8-/16-Channel ΔΣ ADC with PGA and Easy Drive Input Current Cancellation DESCRIPTION The LTC®2494 is a 16-channel (8-differential), 16-bit, No Latency ΔΣ™ ADC with Easy Drive™ technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances, and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2494 includes programmable gain, a high accuracy temperature sensor and an integrated oscillator. This device can be configured to measure an external signal (from combinations of 16 analog input channels operating in single ended or differential modes) or its internal temperature sensor. The integrated temperature sensor offers 1/2°C resolution and 2°C absolute accuracy. The LTC2494 can be configured to provide a progammable gain from 1 to 256 in 8 steps. The LTC2494 allows a wide common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion, after a new channel is selected, is valid. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Up to 8 Differential or 16 Single-Ended Inputs Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise Programmable Gain from 1 to 256 Integrated High Accuracy Temperature Sensor GND to VCC Input/Reference Common Mode Range Programmable 50Hz, 60Hz or Simultaneous 50Hz/60Hz Rejection Mode 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error 2x Speed Mode/Reduced Power Mode (15Hz Using Internal Oscillator and 80μA at 7.5Hz Output) No Latency: Digital Filter Settles in a Single Cycle, Even After a New Channel is Selected Single Supply 2.7V to 5.5V Operation Internal Oscillator Tiny 5mm × 7mm QFN Package APPLICATIONS ■ ■ ■ ■ Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control TYPICAL APPLICATION Data Acquisition System with Temperature Compensation 2.7V TO 5.5V 0.1μF 10μF ABSOLUTE ERROR (°C) 5 4 CH0 CH1 • • • CH7 CH8 16-CHANNEL MUX • • • CH15 COM TEMPERATURE SENSOR FO MUXOUT/ ADCIN OSC 2494 TA01a Absolute Temperature Error MUXOUT/ ADCIN REF + VCC 3 2 1 0 –1 –2 –3 –4 –5 –55 –30 –5 20 45 70 TEMPERATURE (°C) 95 120 IN + 16-BIT ΔΣ ADC WITH EASY-DRIVE IN– REF – SDI SCK SDO CS 4-WIRE SPI INTERFACE 2494 TA01b 2494fb 1 LTC2494 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW GND GND 31 GND 30 REF– 29 REF+ 28 VCC 27 MUXOUTN 39 26 ADCINN 25 ADCINP 24 MUXOUTP 23 CH15 22 CH14 21 CH13 20 CH12 13 14 15 16 17 18 19 CH5 CH6 CH7 CH8 CH9 CH10 CH11 SDO SCK SDI CS FO 38 37 36 35 34 33 32 GND 1 NC 2 GND 3 GND 4 GND 5 GND 6 COM 7 CH0 8 CH1 9 CH2 10 CH3 11 CH4 12 Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (CH0 to CH15, COM) ................–0.3V to (VCC + 0.3V) REF+, REF– ................................–0.3V to (VCC + 0.3V) ADCINN, ADCINP, MUXOUTP, MUXOUTN ................................–0.3V to (VCC + 0.3V) Digital Input Voltage......................–0.3V to (VCC + 0.3V) Digital Output Voltage ...................–0.3V to (VCC + 0.3V) Operating Temperature Range LTC2494C ................................................ 0°C to 70°C LTC2494I ............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2494CUHF#PBF LTC2494IUHF#PBF TAPE AND REEL LTC2494CUHF#TRPBF LTC2494IUHF#TRPBF PART MARKING* 2494 2494 PACKAGE DESCRIPTION 38-Lead (5mm × 7mm) Plastic QFN 38-Lead (5mm × 7mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2494fb 2 LTC2494 ELECTRICAL CHARACTERISTICS (NORMAL SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 2.7V ≤ VCC ≤ 5.5V, 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) TA = 27°C (Note 14) ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 16 TYP 2 1 0.5 10 0.1 ● MAX 20 5 32 32 Output Noise Internal PTAT Signal Internal PTAT Temperature Coefficient Programmable Gain 0.1 15 15 15 0.6 27.8 ● UNITS Bits ppm of VREF ppm of VREF μV nV/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF μVRMS mV μV/°C 28.0 93.5 28.2 256 1 ELECTRICAL CHARACTERISTICS (2X SPEED) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Output Noise Programmable Gain The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) CONDITIONS 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 5V ≤ VCC ≤ 2.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC MIN 16 ● ● ● TYP 2 1 0.2 100 0.1 MAX 20 2 32 32 ● 0.1 0.85 ● UNITS Bits ppm of VREF ppm of VREF mV nV/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C μVRMS 1 128 CONVERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 60Hz ±2% Input Common Mode Rejection 50Hz ±2% Input Normal Mode Rejection 50Hz ±2% Input Normal Mode Rejection 60Hz ±2% Input Normal Mode Rejection 50Hz/60Hz ±2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ±2% Power Supply Rejection, 60Hz ±2% The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) VREF = 2.5V, IN+ = IN– = GND VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9) VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9) ● ● ● ● ● ● ● MIN 140 140 140 110 110 87 120 TYP MAX 120 120 140 120 120 120 UNITS dB dB dB dB dB dB dB dB dB dB 2494fb 3 LTC2494 ANALOG INPUT AND REFERENCE SYMBOL IN+ IN– VIN FS LSB REF+ REF– VREF CS(IN+) CS(IN–) CS(VREF) IDC_LEAK(IN+) IDC_LEAK(IN–) IDC_LEAK(REF+) IDC_LEAK(REF–) tOPEN QIRR PARAMETER Absolute/Common Mode IN+ Voltage (IN+ Corresponds to the Selected Positive Input Channel) Absolute/Common Mode IN– Voltage (IN– Corresponds to the Selected Negative Input Channel) Input Differential Voltage Range (IN+ – IN–) Full Scale of the Differential Input (IN+ – IN–) Least Significant Bit of the Output Code Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Voltage Range (REF+ – REF–) IN+ Sampling Capacitance IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current REF+ DC Leakage Current REF– DC Leakage Current MUX Break-Before-Make MUX Off Isolation VIN = 2VP-P DC to 1.8MHz Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, REF+ = VCC Sleep Mode, REF– = GND ● ● ● ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN GND – 0.3V GND – 0.3V –FS 0.5VREF/Gain FS/216 0.1 GND 0.1 11 11 11 –10 –10 –100 –100 1 1 1 1 50 120 10 10 100 100 VCC REF+ – 0.1V VCC V V V pF pF pF nA nA nA nA ns dB TYP MAX VCC + 0.3V VCC + 0.3V +FS UNITS V V V V DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage (CS, FO, SDI) Low Level Input Voltage (CS, FO, SDI) High Level Input Voltage (SCK) Low Level Input Voltage (SCK) Digital Input Current (CS, FO, SDI) Digital Input Current (SCK) Digital Input Capacitance (CS, FO, SDI) Digital Input Capacitance (SCK) High Level Output Voltage (SDO) Low Level Output Voltage (SDO) High Level Output Voltage (SCK) Low Level Output Voltage (SCK) Hi-Z Output Leakage (SDO) (Notes 10, 15) IO = –800μA IO = 1.6mA CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN ● ● ● ● ● ● TYP MAX 0.5 UNITS V V V V μA μA pF pF V VCC – 0.5 VCC – 0.5 0.5 –10 –10 10 10 10 10 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Notes 10, 15) ● ● ● ● ● VCC – 0.5 0.4 VCC – 0.5 0.4 –10 10 V V V μA IO = –800μA (Notes 10, 17) IO = 1.6mA (Notes 10, 17) POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● MIN 2.7 ● ● ● TYP 160 200 1 MAX 5.5 275 300 2 UNITS V μA μA μA 2494fb Conversion Current (Note 12) Temperature Measurement (Note 12) Sleep Mode (Note 12) 4 LTC2494 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL fEOSC tHEO tLEO tCONV_1 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time for 1x Speed Mode 50Hz Mode 60Hz Mode Simultaneous 50/60Hz Mode External Oscillator 50Hz Mode 60Hz Mode Simultaneous 50/60Hz Mode External Oscillator Internal Oscillator (Notes 10, 17) External Oscillator (Notes 10, 11, 15) (Notes 10, 17) (Notes 10, 11, 15) (Notes 10, 11, 15) (Notes 10, 11, 15) Internal Oscillator (Notes 10, 17) External Oscillator (Notes 10, 11, 15) (Notes 10, 11, 15) ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS (Note 16) ● ● ● ● ● ● ● ● ● MIN 10 0.125 0.125 157.2 131 144.1 78.7 65.6 72.2 TYP MAX 4000 50 50 UNITS kHz μs μs ms ms ms ms ms ms ms ms kHz kHz 160.3 133.6 146.9 41036/fEOSC (in kHz) 80.3 66.9 73.6 20556/fEOSC (in kHz) 38.4 fEOSC/8 163.5 136.3 149.9 81.9 68.2 75.1 tCONV_2 Conversion Time for 2x Speed Mode fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t7 t8 Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time CS↓ to SDO Low CS↑ to SDO High Z CS↓ to SCK↑ CS↓ to SCK↑ SCK↓ to SDO Valid SDO Hold After SCK↓ SCK Set-Up Before CS↓ SDI Setup Before SCK↑ SDI Hold After SCK↑ 45 125 125 0.61 0.625 192/fEOSC (in kHz) 24/fESCK (in kHz) 0 0 0 50 55 4000 % kHz ns ns 0.64 ms ms ms ns ns ns ns ns ns ns ns ns 200 200 200 200 Internal SCK Mode External SCK Mode (Note 5) (Note 5) (Note 5) ● ● ● ● ● ● ● 15 50 100 100 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = 0.5VREF/Gain VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the selected input channels. Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless other wise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator). Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as a digital input and the driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a digital output and the output clock signal during the data output is fISCK. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses its internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: The converter is in external SCK mode of operation such that the SCK pin is used as a digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in Hz. Note 16: Refer to Applications Information section for performance vs data rate graphs. Note 17: The converter is in internal SCK mode of operation such that the SCK pin is used as a digital output. 2494fb 5 LTC2494 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) 1 0 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND INL (ppm OF VREF) –45°C 25°C 3 2 1 0 –1 –2 –3 –1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) –45°C, 25°C, 85°C 3 2 1 0 –1 –2 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 85°C 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2494 G02 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2494 G03 2494 G01 Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 12 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND 12 85°C 25°C 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 25°C 85°C 25°C 85°C –45°C –45°C 2 2.5 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2494 G05 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2494 G06 2494 G04 Noise Histogram (6.8sps) 14 12 NUMBER OF READINGS (%) 10,000 CONSECUTIVE READINGS RMS = 0.60μV VCC = 5V AVERAGE = –0.69μV VREF = 5V 10 VIN = 0V TA = 25°C 8 GAIN = 256 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (μV) 1.2 1.8 14 12 NUMBER OF READINGS (%) Noise Histogram (7.5sps) 10,000 CONSECUTIVE READINGS RMS = 0.59μV VCC = 2.7V AVERAGE = –0.19μV VREF = 2.5V 10 VIN = 0V TA = 25°C 8 GAIN = 256 6 4 2 0 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 OUTPUT READING (μV) 1.2 1.8 5 Long-Term ADC Readings VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V 4 TA = 25°C, RMS NOISE = 0.60μV, GAIN = 256 3 ADC READING (μV) 2 1 0 –1 –2 –3 –4 –5 0 10 30 40 20 TIME (HOURS) 50 60 2494 G09 2494 G07 2494 G08 2494fb 6 LTC2494 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs Input Differential Voltage 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 0.4 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C RMS NOISE (μV) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 –1 0 1 2 3 4 5 6 VIN(CM) (V) 2494 G11 RMS Noise vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND TA = 25°C GAIN = 256 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 RMS Noise vs Temperature (TA) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND GAIN = 256 2.5 0.4 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2494 G10 2494 G12 RMS Noise vs VCC 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 0.4 2.7 VREF = 2.5V VIN = 0V VIN(CM) = GND TA = 25°C GAIN = 256 1.0 0.9 RMS NOISE (μV) 0.8 0.7 0.6 0.5 0.4 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 RMS Noise vs VREF VCC = 5V VIN = 0V VIN(CM) = GND TA = 25°C GAIN = 256 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0 1 2 3 VREF (V) 4 5 2494 G14 Offset Error vs VIN(CM) VCC = 5V VREF = 5V VIN = 0V TA = 25°C OFFSET ERROR (ppm OF VREF) –1 0 1 3 2 VIN(CM) (V) 4 5 6 2494 G13 2494 G15 Offset Error vs Temperature 0.3 0.2 0.1 0 0.3 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.2 0.1 0 –0.1 –0.2 Offset Error vs VCC REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C 0.3 0.2 0.1 0 Offset Error vs VREF VCC = 5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 –0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 OFFSET ERROR (ppm OF VREF) –0.1 –0.2 –0.3 0 1 2 3 VREF (V) 4 5 2494 G18 2494 G16 2494 G17 2494fb 7 LTC2494 TYPICAL PERFORMANCE CHARACTERISTICS On-Chip Oscillator Frequency vs Temperature 310 310 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 302 –120 –140 PSRR vs Frequency at VCC VCC = 4.1V DC VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 308 FREQUENCY (kHz) FREQUENCY (kHz) 75 90 308 306 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (°C) 304 302 300 –45 –30 –15 300 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2494 G20 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2494 G19 2494 G21 PSRR vs Frequency at VCC 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2494 G22 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 FO = GND TA = 25°C –60 –80 –100 –120 –140 30600 0 200 Conversion Current vs Temperature FO = GND CS = GND SCK = NC SDO = NC SDI = GND CONVERSION CURRENT (μA) REJECTION (dB) VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 180 VCC = 5V 160 VCC = 2.7V 140 120 30650 30750 FREQUENCY AT VCC (Hz) 30700 30800 2494 G23 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2494 G24 Sleep Mode Current vs Temperature 2.0 FO = GND 1.8 CS = VCC SCK = NC 1.6 SDO = NC 1.4 SDI = GND 1.2 1.0 0.8 0.6 0.4 0.2 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 150 100 VCC = 2.7V VCC = 5V 500 450 SUPPLY CURRENT (μA) 400 350 300 250 200 Conversion Current vs Output Data Rate VREF = VCC IN+ = GND IN– = GND SCK = NC SDO = NC SDI = GND CS GND FO = EXT OSC TA = 25°C 3 2 INL (ppm OF VREF) VCC = 5V 1 0 –1 Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 5V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND SLEEP MODE CURRENT (μA) 25°C, 85°C VCC = 3V –45°C –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 G26 2 2.5 2494 G25 2494 G27 2494fb 8 LTC2494 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (2x Speed Mode; VCC = 5V, VREF = 2.5V) 3 2 INL (ppm OF VREF) 1 0 –1 –2 –3 –1.25 –45°C, 25°C VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) 85°C 3 2 1 0 –1 –2 2 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2494 G28 Integral Nonlinearity (2x Speed Mode; VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 85°C 16 Noise Histogram (2x Speed Mode) RMS = 0.85μV 10,000 CONSECUTIVE AVERAGE = 0.184mV 14 READINGS VCC = 5V 12 VREF = 5V VIN = 0V GAIN = 128 10 TA = 25°C 8 6 4 –45°C, 25°C –3 –1.25 NUMBER OF READINGS (%) 1.25 2494 G29 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 0 179 181.4 183.8 186.2 OUTPUT READING (μV) 188.6 2494 G30 RMS Noise vs VREF (2x Speed Mode) 1.0 200 198 0.8 OFFSET ERROR (μV) RMS NOISE (μV) 196 194 192 190 188 186 184 182 3 2 VREF (V) 4 5 2494 G31 Offset Error vs VIN(CM) (2x Speed Mode) VCC = 5V VREF = 5V VIN = 0V FO = GND TA = 25°C 240 230 OFFSET ERROR (μV) 220 210 200 190 180 170 –1 0 1 3 VIN(CM) (V) 2 4 5 6 2494 G32 Offset Error vs Temperature (2x Speed Mode) VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.6 0.4 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C GAIN = 128 0 1 0.2 0 180 160 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 2494 G33 Offset Error vs VCC (2x Speed Mode) 250 VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C 240 230 OFFSET ERROR (μV) 220 210 200 190 180 170 0 2 2.5 3 4 3.5 VCC (V) 4.5 5 5.5 2494 G34 Offset Error vs VREF (2x Speed Mode) 0 VCC = 5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 0 1 2 3 VREF (V) 4 5 2494 G35 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C 200 OFFSET ERROR (μV) 150 100 50 160 1 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M 2494 G36 2494fb 9 LTC2494 TYPICAL PERFORMANCE CHARACTERISTICS PSRR vs Frequency at VCC (2x Speed Mode) 0 –20 –40 –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2494 G37 PSRR vs Frequency at VCC (2x Speed Mode) VCC = 4.1V DC ±0.7V REF+ = 2.5V REF– = GND IN+ = GND –40 IN– = GND FO = GND –60 TA = 25°C –20 –80 –100 –120 –140 30600 0 RREJECTION (dB) REJECTION (dB) VCC = 4.1V DC ±1.4V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2494 G38 PIN FUNCTIONS GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a common ground plane through a low impedance connection. All eight pins must be connected to ground for proper operation. NC (Pin 2): No Connection, this pin can be left floating or tied to GND. COM (Pin 7): The common negative input (IN–) for all single-ended multiplexer configurations. The voltage on CH0 to CH15 and COM pins can have any value between GND – 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range VIN = (IN+ – IN–) from –0.5 • VREF/Gain to 0.5 • VREF /Gain. Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be programmed for single-ended or differential mode. MUXOUTP (Pin 24): Positive Multiplexer Output. Used to drive an external buffer/amplifier or can be shorted directly to ADCINP. ADCINP (Pin 25): Positive ADC Input. Tie to the output of a buffer/amplifier driven by MUXOUTP or tie directly to MUXOUTP. ADCINN (Pin 26): Negative ADC Input. Tie to the output of a buffer/amplifier driven by MUXOUTN or tie directly to MUXOUTN. MUXOUTN (Pin 27): Negative Multiplexer Output. Used to drive an external buffer/amplifier or can be shorted directly to ADCINN. VCC (Pin 28): Positive Supply Voltage. Bypass to GND with a 10μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor as close to the part as possible. REF+ (Pin 29), REF– (Pin 30): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF–, by at least 0.1V. The differential voltage VREF = (REF+ – REF–) sets the full-scale range (–0.5 • VREF/Gain to 0.5 • VREF/Gain) for all input channels. When performing an on-chip temperature measurement, the minimum value of REF = 2V. SDI (Pin 34): Serial Data Input. This pin is used to select the gain, line frequency rejection mode, 1x or 2x speed mode, temperature sensor, as well as the input channel. The serial data input is applied under control of the serial clock (SCK) during the data output/input operation. The first conversion following a new input or mode change is valid. 2494fb 10 LTC2494 PIN FUNCTIONS FO (Pin 35): Frequency Control Pin. Digital input that controls the internal conversion clock rate. When FO is connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate and the digital filter rejection null. CS (Pin 36): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output aborts the data transfer and starts a new conversion. SDO (Pin 37): Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select pin is HIGH, the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. When the conversion is in progress this pin is HIGH; once the conversion is complete SDO goes low. The conversion status is monitored by pulling CS LOW. SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In Internal Serial Clock Operation mode, SCK is generated internally and is seen as an output on the SCK pin . In External Serial Clock Operation mode, the digital I/O clock is externally applied to the SCK pin. The Serial Clock operation mode is determined by the logic level applied to the SCK pin at power up and during the most recent falling edge of CS. Exposed Pad (Pin 39): Ground. This pin is ground and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating. FUNCTIONAL BLOCK DIAGRAM VCC GND REF + REF – CH0 CH1 • • • MUX TEMP SENSOR MUXOUTP ADCINP INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL FO (INT/EXT) – + SERIAL INTERFACE DECIMATING FIR ADDRESS 2494 BD CH15 COM DIFFERENTIAL 3RD ORDER ΔΣ MODULATOR SDI SCK SDO CS MUXOUTN ADCINN Figure 1. Functional Block Diagram 2494fb 11 LTC2494 TEST CIRCUITS VCC 1.69k SDO 1.69k CLOAD = 20pF SDO CLOAD = 20pF Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 2494 TC01 Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2494 TC02 TIMING DIAGRAMS Timing Diagram Using Internal SCK (SCK HIGH with CS↓) CS t1 SDO Hi-Z tKQMIN t2 Hi-Z t3 SCK t7 SDI SLEEP t8 tKQMAX 2494 TD01 DATA IN/OUT CONVERSION Timing Diagram Using External SCK (SCK LOW with CS↓) CS t1 SDO Hi-Z t5 SCK t7 SDI SLEEP DATA IN/OUT t8 tKQMIN t2 Hi-Z t4 tKQMAX 2494 TD02 CONVERSION 2494fb 12 LTC2494 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2494 is a multi-channel, low power, delta-sigma, analog-to-digital converter with an easy-to-use, 4-wire interface and automatic differential input current cancellation. Its operation is made up of four states (See Figure 2). The converter’s operating cycle begins with the conversion, followed by the sleep state, and ends with the data input/output cycle. The 4-wire interface consists of serial data output (SDO), serial clock (SCK), chip select (CS) and serial data input (SDI).The interface, timing, operation cycle, and data output format is compatible with Linear’s entire family of ΔΣ converters. Initially, at power up, the LTC2494 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, if CS in HIGH, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. Once CS is pulled LOW, the device powers up, exits the sleep state, and enters the data input/output state. If CS is brought HIGH before the first rising edge of SCK, the device returns to the sleep state and the power is reduced. If CS is brought HIGH after the first rising edge of SCK, the POWER UP IN+= CH0, IN–= CH1 GAIN = 1, 50/60Hz,1X data output cycle is aborted and a new conversion cycle begins. The data output corresponds to the conversion just completed. This result is shifted out on the serial data output pin (SDO) under the control of the serial clock pin (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (See Figure 3). The configuration data for the next conversion is also loaded into the device at this time. Data is loaded from the serial data input pin (SDI) on each rising edge of SCK. The data input/output cycle is concluded once 24 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2494 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming and do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2494 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input or mode, is valid and accurate to the full specifications of the device. The LTC2494 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected. This calibration is transparent to the user and has no effect with the operation cycle described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. Easy Drive Input Current Cancellation The LTC2494 combines a high precision, delta-sigma ADC with an automatic, differential, input current cancellation front end. A proprietary front end passive sampling network 2494fb CONVERT SLEEP CS = LOW AND SCK CHANNEL SELECT CONFIGURATION SELECT DATA OUTPUT 2494 F02 Figure 2. LTC2494 State Transition Diagram 13 LTC2494 APPLICATIONS INFORMATION transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2494 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Differential Input Current Cancellation section). This unique architecture does not require on-chip buffers, thereby enabling signals to swing beyond ground or up to VCC. Moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external RC networks. Power-Up Sequence The LTC2494 automatically enters an internal reset state when the power supply voltage, VCC, drops below approximately 2V. This feature guarantees the integrity of the conversion result, input channel selection, and serial clock mode. When VCC rises above this threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. The conversion immediately following a POR cycle is performed on the input channels IN+ = CH0 and IN– = CH1 with simultaneous 50Hz/60Hz rejection 1x output rate, and gain = 1. The first conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7V to 5.5V) before the end of the POR interval. A new input channel, rejection mode, speed mode, temperature selection, or gain can be programmed into the device during this first data input/output cycle. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage range for the REF+ and REF– pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF must be positive (REF+ > REF–). The LTC2494 differential reference input range is 0.1V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF– can be shorted to GND. The converter output noise is determined by the thermal noise of the front end circuits, and as such, its value in nano volts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a decreased reference will improve the converter’s overall INL performance. Input Voltage Range The analog input is truly differential with an absolute, common mode range for CH0 to CH15 and COM input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD projection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2494 converts the bipolar differential input signal VIN = IN+ + IN– (where IN+ and IN– are the selected input channels), from –FS = –0.5 • VREF/Gain to +FS = 0.5 • VREF/Gain where VREF = REF+ – REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Signals applied to the input (CH0 to CH15, COM) may extend 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the input. The effect of series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent error due to input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. MUXOUT/ADCIN The output of the multiplexer (MUXOUT) and the input to the ADC (ADCIN) can be used to perform input signal conditioning on any of the selected input channels or simply shorted together for direct digitization. If an external amplifier is used, the LTC2494 automatically calibrates both the offset and drift of this circuit and the Easy Drive sampling scheme enables a wide variety of amplifiers to be used. 2494fb 14 LTC2494 APPLICATIONS INFORMATION In order to achieve optimum performance, if an external amplifier is not used, short these pins directly together (ADCINP to MUXOUTP and ADCINN to MUXOUTN) and minimize their capacitance to ground. SERIAL INTERFACE PINS The LTC2494 transmits the conversion result, reads the input configuration, and receives a start of conversion command through a synchronous 3- or 4-wire interface. During the conversion and sleep states, this interface can be used to access the converter status. During the data output state, it is used to read the conversion result, program the input channel, rejection frequency, speed multiplier, select the temperature sensor and set the gain. Serial Clock Input/Output (SCK) The serial clock pin (SCK) is used to synchronize the data input/output transfer. Each bit is shifted out of the SDO pin on the falling edge of SCK and data is shifted into the SDI pin on the rising edge of SCK. The serial clock pin (SCK) can be configured as either a master (SCK is an output generated internally) or a slave (SCK is an input and applied externally). Master mode (Internal SCK) is selected by simply floating the SCK pin. Slave mode (External SCK) is selected by driving SCK low during power up and each falling edge of CS. Specific details of these SCK modes are described in the Serial Interface Timing Modes section. Serial Data Output (SDO) The serial data output pin (SDO) provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS is HIGH, the SDO driver is switched to a high impedance state in order to share the data output line with other devices. If CS is brought LOW during the conversion phase, the EOC bit (SDO pin) will be driven HIGH. Once the conversion is complete, if CS is brought LOW, EOC will be driven LOW indicating the conversion is complete and the result is ready to be shifted out of the device. Chip Select (CS) The active low CS pin is used to test the conversion status, enable I/O data transfer, initiate a new conversion, control the duration of the sleep state, and set the SCK mode. At the conclusion of a conversion cycle, while CS is HIGH, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude. In order to exit the sleep state and enter the data output state, CS must be pulled low. Data is now shifted out the SDO pin under control of the SCK pin as described previously. A new conversion cycle is initiated either at the conclusion of the data output cycle (all 24 data bits read) or by pulling CS HIGH any time between the first and 24th rising edges of the serial clock (SCK). In this case, the data output is aborted and a new conversion begins. Serial Data Input (SDI) The serial data input (SDI) is used to select the input channel, rejection frequency, speed multiplier, gain, and to access the integrated temperature sensor. Data is shifted into the device during the data output/input state on the rising edge of SCK while CS is low. OUTPUT DATA FORMAT The LTC2494 serial output stream is 24 bits long. The first bit indicates the conversion status, the second bit is always zero, and the third bit conveys sign information. The next 17 bits are the conversion result, MSB first. The remaining 4 bits are always LOW. Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available on the SDO pin during the conversion and sleep states whenever CS is LOW. This bit is HIGH during the conversion cycle, goes LOW once the conversion is complete, and is HIGH-Z when CS is HIGH. 2494fb 15 LTC2494 APPLICATIONS INFORMATION Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If the selected input (VIN = IN+ – IN–) is greater than or equal to 0V, this bit is HIGH. If VIN < 0, this bit is LOW. Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides underrange and overrange indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below –FS. The function of these bits is summarized in Table 1. Table 1. LTC2494 Status Bits Input Range VIN ≥ 0.5 • VREF/Gain 0V ≤ VIN < 0.5 • VREF/Gain –0.5 • VREF/Gain ≤ VIN < 0V VIN < –0.5 • VREF/Gain Bit 23 EOC 0 0 0 0 Bit 22 DMY 0 0 0 0 Bit 21 SIG 1 1 0 0 Bit 20 MSB 1 0 1 0 Data is shifted out of the SDO pin under control of the serial clock (SCK) (see Figure 3). Whenever CS is HIGH, SDO remains high impedance and SCK is ignored. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. `E`O`C changes in real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN– pins remains between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • VREF/Gain to +FS = 0.5 • VREF /Gain. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the value –FS – 1LSB. Bits 20 to 4 are the 16-bit plus sign conversion result MSB first. Bit 4 is the least significant bit (LSB16). Bits 3 to 0 are always LOW. CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0 DON'T CARE SDO Hi-Z EOC “0” SIG MSB BIT 9 BIT 0 Hi-Z BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2494 F03 Figure 3. Channel Selection, Configuration Selection and Data Output Timing 2494fb 16 LTC2494 APPLICATIONS INFORMATION Table 2. LTC2494 Output Data Format DIFFERENTIAL INPUT VOLTAGE VIN* VIN* ≥ FS** FS** – 1LSB 0.5 • FS** 0.5 • FS** – 1LSB 0 –1LSB –0.5 • FS** –0.5 • FS** – 1LSB –FS** VIN* < –FS** BIT 23 EOC 0 0 0 0 0 0 0 0 0 0 BIT 22 DMY 0 0 0 0 0 0 0 0 0 0 BIT 21 SIG 1 1 1 1 1 0 0 0 0 0 BIT 20 MSB 1 0 0 0 0 1 1 1 1 0 BIT 19 0 1 1 0 0 1 1 0 0 1 BIT 18 0 1 0 1 0 1 0 1 0 1 BIT 17 0 1 0 1 0 1 0 1 0 1 … … … … … … … … … … … BIT 4 0 1 0 1 0 1 0 1 0 1 BITS 3 TO 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF /Gain. INPUT DATA FORMAT The LTC2494 serial input word is 16 bits long and contains two distinct sets of data. The first set (SGL, ODD, A2, A1, A0) is used to select the input channel. The second set of data (IM, FA, FB, SPD, GS2, GS1, GS0) is used to select the frequency rejection, speed mode (1x, 2x), temperature measurement, and gain. After power up, the device initiates an internal reset cycle which sets the input channel to CH0 – CH1 (IN+ = CH0, IN– = CH1), the frequency rejection to simultaneous 50Hz/60Hz, 1x output rate (auto-calibration enabled), and gain = 1. The first conversion automatically begins at power up using this default configuration. Once the conversion is complete, a new word may be written into the device. The first three bits shifted into the device consist of two preamble bits and an enable bit. These bits are used to enable the device configuration and input channel selection. Valid settings for these three bits are 000, 100 and 101. Other combinations should be avoided. If the first three bits are 000 or 100, the following data is ignored (don’t care) and the previously selected input channel and configuration remain valid for the next conversion. If the first three bits shifted into the device are 101, then the next five bits select the input channel for the next conversion cycle (see Table 3). The first input bit following the 101 sequence (SGL) determines if the input selection is differential (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL = 1, one of 16 channels is selected as the positive input. The negative input is COM for all single ended operations. The remaining 4 bits (ODD, A2, A1, A0) determine which channel(s) is/are selected and the polarity (for a differential input). The next serial input bit immediately following the input channel selection is the enable bit for the conversion configuration (EN2). If this bit is set to 0, then the next conversion is performed using the previously selected converter configuration. This is useful in systems using the same rejection/speed for all input channels and for backward compatibility with the LTC2418/LTC2414 families of delta sigma ADCs. The second set of configuration data can be loaded into the device by setting EN2 = 1 (see Table 4). The first bit (IM) is used to select the internal temperature sensor. If IM = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. The next 2 bits (FA and FB) are used to set the rejection frequency. The next bit (SPD) is used to select either the 1x output rate if SPD = 0 (auto-calibration is enabled and the offset is continuously calibrated and removed from the final conversion result) or the 2x output rate if SPD = 1 (offset calibration disabled, multiplexing output rates up to 15Hz with no latency). When IM = 1 (temperature measurement), SPD, GS2, GS1, GS0 will be ignored and the device will operate in 1x mode. The final 3 bits (GS2, 2494fb 17 LTC2494 APPLICATIONS INFORMATION Table 3 Channel Selection MUX ADDRESS ODD/ SGL SIGN *0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– 0 IN+ 1 IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– 2 3 4 5 6 CHANNEL SELECTION 7 8 9 10 11 12 13 14 15 COM *Default at power up 2494fb 18 LTC2494 APPLICATIONS INFORMATION Table 4. Converter Configuration 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SGL ODD A2 A1 A0 EN2 0 X 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Any 1 1 Input Channel 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IM X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 FA X X FB X X SPD X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Any Speed X X X X X X X X GS2 GS1 GS0 X X X X X X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Any Gain X X X X X X X X CONVERTER CONFIGURATION Keep Previous Keep Previous External Input, Gain = 1, Autocalibration External Input, Gain = 4, Autocalibration External Input, Gain = 8, Autocalibration External Input, Gain = 16, Autocalibration External Input, Gain = 32, Autocalibration External Input, Gain = 64, Autocalibration External Input, Gain = 128, Autocalibration External Input, Gain = 264, Autocalibration External Input, Gain = 1, 2x Speed External Input, Gain = 2, 2x Speed External Input, Gain = 4, 2x Speed External Input, Gain = 8, 2x Speed External Input, Gain = 16, 2x Speed External Input, Gain = 32, 2x Speed External Input, Gain = 64, 2x Speed External Input, Gain = 128, 2x Speed External Input, Simultaneous 50Hz/60Hz Rejection External Input, 50Hz Rejection External Input, 60Hz Rejection Reserved, Do Not Use Temperature Input, Simultaneous 50Hz/60Hz Rejection Temperature Input, 50Hz Rejection Temperature Input, 60Hz Rejection Reserved, Do Not Use Any Rejection Mode 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 GS1, GS0) are used to select the gain. The configuration remains valid until a new input word with EN = 1 (the first 3 bits are 101) and EN2 = 1 is shifted into the device. Rejection Mode (FA, FB) The LTC2494 includes a high accuracy on-chip oscillator with no required external components. Coupled with an integrated 4th order digital low pass filter, the LTC2494 rejects line frequency noise. In the default mode, the LTC2494 simultaneously rejects 50Hz and 60Hz by at least 87dB. If more rejection is required, the LTC2494 can be configured to reject 50Hz or 60Hz to better than 110dB. Speed Mode (SPD) Every conversion cycle, two conversions are combined to remove the offset (default mode). This result is free from offset and drift. In applications where the offset is not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. While operating in the 2x mode (SPD = 1), the linearity and full-scale errors are unchanged from the 1x mode performance. In both the 1x and 2x mode there is no latency. This enables input steps or multiplexer changes to settle in a single conversion cycle easing system overhead and increasing the effective conversion rate. During temperature measurements, the 1x mode is always used independent of the value of SPD. GAIN (GS2, GS1, GS0) The input referred gain of the LTC2494 is adjustable from 1 to 256 (see Tables 5a and 5b). With a gain of 1, the differential input range is ±VREF/2 and the common mode input range is rail-to-rail. As the gain is increased, the differential input range is reduced to ±0.5 • VREF/Gain but the common mode input range remains rail-to-rail. As the differential gain is increased, low level voltages are digitized with greater resolution. At a gain of 256, the LTC2494 digitizes an input signal range of ±9.76mV with over 16,000 counts. 2494fb 19 LTC2494 APPLICATIONS INFORMATION Table 5a. Performance vs Gain in Normal Speed Mode (VCC = 5V, VREF = 5V) GAIN Input Span LSB Noise Free Resolution* Gain Error Offset Error 1 ±2.5 38.1 65536 5 0.5 4 ±0.625 9.54 65536 5 0.5 8 ±0.312 4.77 65536 5 0.5 16 ±0.156 2.38 65536 5 0.5 32 ±78m 1.19 65536 5 0.5 64 ±39m 0.596 65536 5 0.5 128 ±19.5m 0.298 32768 5 0.5 256 ±9.76m 0.149 16384 8 0.5 UNIT V μV Counts ppm of FS μV Table 5b. Performance vs Gain in 2x Speed Mode (VCC = 5V, VREF = 5V) GAIN Input Span LSB Noise Free Resolution* Gain Error Offset Error 1 ±2.5 38.1 65536 5 200 2 ±1.25 19.1 65536 5 200 4 ±0.625 9.54 65536 5 200 8 ±0.312 4.77 65536 5 200 16 ±0.156 2.38 65536 5 200 32 ±78m 1.19 65536 5 200 64 ±39m 0.596 45875 5 200 128 ±19.5m 0.298 22937 5 200 UNIT V μV Counts ppm of FS μV *The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger. Temperature Sensor The LTC2494 includes an integrated temperature sensor. The temperature sensor is selected by setting IM = 1. During temperature readings, MUXOUTN/MUXOUTP remains connected to the selected input channel. The ADC internally connects to the temperature sensor and performs a conversion. The digital output is proportional to the absolute temperature of the device. This feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. The internal temperature sensor output is 28mV at 27°C (300°K), with a slope of 93.5μV/°C independent of VREF. Slope calibration is not required if the reference voltage (VREF) is known. A 5V reference has a slope of 2.45 LSBs16/°C. The temperature is calculated from the output code (where DATAOUT16 is the decimal representation of the 16-bit result) for a 5V reference using the following formula: TK = DATAOUT16/2.45 in Kelvin If a different value of VREF is used, the temperature output is: TK = DATAOUT16 • VREF/12.25 in Kelvin If the value of VREF is not known, the slope is determined by measuring the temperature sensor at a known temperature TN (in °K) and using the following formula: SLOPE = DATAOUT16/TN This value of slope can be used to calculate further temperature readings using: TK = DATAOUT16/SLOPE All Kelvin temperature readings can be converted to TC (°C) using the fundamental equation: TC = TK – 273 SERIAL INTERFACE TIMING MODES The LTC2494’s 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 3- or 4-wire I/O, single cycle or continuous conversion. The following sections describe each of these timing modes in detail. In all cases, the converter can use the internal oscillator (FO = LOW) or an external oscillator connected to the FO pin. For each mode, the operating cycle, data input format, data output format, and performance remain the same. Refer to Table 6 for a summary. 2494fb 20 LTC2494 APPLICATIONS INFORMATION 1020 5 4 3 ABSOLUTE ERROR (°C) 2 1 0 –1 –2 –3 160 0 –4 0 100 200 300 TEMPERATURE (K) 400 2494 F04 VCC = 5V VREF = 5V 960 SLOPE = 2.45 LSB /K 16 800 DATAOUT16 640 480 320 –5 –55 –30 –5 20 45 70 TEMPERATURE (°C) 95 120 2494 F05 Figure 4. Internal PTAT Digital Output vs Temperature Table 6. LTC2494 Interface Timing Modes CONFIGURATION External SCK, Single Cycle Conversion External SCK, 3-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 3-Wire I/O, Continuous Conversion Figure 5. Absolute Temperature Error SCK CONVERSION DATA OUTPUT CONNECTION AND SOURCE CYCLE CONTROL CONTROL WAVEFORMS External External Internal Internal CS and SCK SCK CS↓ Continuous CS and SCK SCK CS↓ Internal Figures 6, 7 Figure 8 Figures 9, 10 Figure 11 External Serial Clock, Single Cycle Operation This timing mode uses an external serial clock to shift out the conversion result and CS to monitor and control the state of the conversion cycle (see Figure 6). The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to enter and remain in the external SCK mode of operation, SCK must be driven LOW both at power up and on each CS falling edge. If SCK is HIGH on the falling edge of CS, the device will switch to the internal SCK mode. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the conversion is complete and the device is in the sleep state. Independent of CS, the device automatically enters the sleep state once the conversion is complete; however, in order to reduce the power, CS must be HIGH. When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. The input data is then shifted in via the SDI pin on each rising edge of SCK (including the first rising edge). The channel selection and converter configuration mode will be used for the following conversion cycle. If the input channel or converter configuration is changed during this I/O cycle, the new settings take effect on the conversion cycle following the data input/output cycle. The output data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion and SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. 2494fb 21 LTC2494 APPLICATIONS INFORMATION 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • VCC LTC2494 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 29 30 8 15 16 • • • REF + REF – CH0 • CH7 CH8 • CH15 COM • • • • SDI SCK 34 38 4-WIRE SPI INTERFACE SDO CS 37 36 ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0 DON'T CARE Hi-Z SDO EOC “0” SIG MSB BIT 12 BIT 11 BIT 10 BIT 9 BIT 0 Hi-Z 2494 F06 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION Figure 6. External Serial Clock, Single Cycle Operation Typically, CS remains LOW during the data output/input state. However, the data output state may be aborted by pulling CS HIGH any time between the 1st falling edge and the 24th falling edge of SCK (see Figure 7). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. In order to program a new input channel, 8 SCK clock pulses are required. If the data output sequence is aborted prior to the 8th falling edge of SCK, the new input data is ignored and the previously selected input channel remains valid. If the rising edge of CS occurs after the 8th falling edge of SCK, the new input channel is loaded and valid for the next conversion cycle. If CS goes high between the 8th falling edge and the 16th falling edge of SCK, the new channel is still loaded, but the converter configuration remains unchanged. In order to program both the input channel and converter configuration, CS must go high after the 16th falling edge of SCK (at this point all data has been shifted into the device). External Serial Clock, 3-Wire I/O This timing mode uses a 3-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal (see Figure 8). CS is permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is typically concluded 4ms after VCC exceeds 2V. The level applied to SCK at this time determines if SCK is internally generated or externally applied. In order to enter the external SCK mode, SCK must be driven LOW prior to the end of the POR cycle. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion is complete. 2494fb 22 LTC2494 APPLICATIONS INFORMATION 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • VCC LTC2494 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 29 30 8 15 16 • • • REF + REF – CH0 • CH7 CH8 • CH15 COM • • • • SDI SCK 34 38 4-WIRE SPI INTERFACE SDO CS 37 36 ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 DON'T CARE SDO EOC “0” SIG MSB BIT 15 Hi-Z 2494 F07 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION SLEEP Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • VCC LTC2494 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 29 30 8 15 16 • • • REF + REF – CH0 • CH7 CH8 • CH15 COM • • • • SDI SCK 34 38 3-WIRE SPI INTERFACE 37 36 SDO CS ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0 DON'T CARE SDO EOC “0” SIG MSB BIT 12 BIT 11 BIT 10 BIT 9 BIT 0 2494 F08 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION Figure 8. External Serial Clock, 3-Wire Operation (CS = 0) 2494fb 23 LTC2494 APPLICATIONS INFORMATION On the falling edge of EOC, the conversion result is loading into an internal static shift register. The output data can now be shifted out the SDO pin under control of the externally applied SCK signal. Data is updated on the falling edge of SCK. The input data is shifted into the device through the SDI pin on the rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH, indicating a new conversion has begun. This data now serves as EOC for the next conversion. Internal Serial Clock, Single Cycle Operation This timing mode uses the internal serial clock to shift out the conversion result and CS to monitor and control the state of the conversion cycle (see Figure 9). In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating or pulled HIGH before the conclusion of the POR cycle and prior to each falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal SCK mode is automatically selected if SCK is not externally driven. 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled low in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and `E`O`C is output to the SDO pin. EOC= 1 while the conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit sleep state. In order to return to the sleep state and reduce the power consumption, CS must be pulled HIGH before the device pulls SCK HIGH. When the device is using its own internal oscillator (FO is tied LOW), the first rising edge of SCK occurs 12μs (tEOCTEST = 12μs) after the falling edge of CS. If FO is driven by an external oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC. If CS remains LOW longer than tEOCTEST, the first rising edge of SCK will occur and the conversion result is shifted out the SDO pin on the falling edge of SCK. The serial input word (SDI) is shifted into the device on the rising edge of SCK. VCC LTC2494 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR VCC 29 30 8 15 16 • • • REF + REF – CH0 • CH7 CH8 • CH15 COM • • • • SDI SCK 34 38 4-WIRE SPI INTERFACE OPTIONAL 10k SDO CS 37 36 ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 1μF 2494fb 30 LTC2494 APPLICATIONS INFORMATION INPUT NORMAL MODE REJECTION (dB) In addition to the reference sampling charge, the reference ESD projection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max) results in a small gain error. A 100Ω reference resistance will create a 0.5μV full scale error. Normal Mode Rejection and Anti-aliasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversample ratio, the LTC2494 significantly simplifies anti-aliasing filter requirements. Additionally, the input current cancellation feature allows external low pass filtering without degrading the DC performance of the device. The SINC4 digital filter provides excellent normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS) (see Figures 19 and 20). The modulator sampling frequency is fS = 15,360Hz while operating with its internal oscillator and fS = FEOSC/20 when operating with an external oscillator of frequency FEOSC. When using the internal oscillator, the LTC2494 is designed to reject line frequencies. As shown in Figure 21, rejection nulls occur at multiples of frequency fN, where fN is determined by the input control bits FA and FB (fN = 50Hz or 60Hz or 55Hz for simultaneous rejection). Multiples of the modulator sampling rate (fS = fN • 256) only reject noise to 15dB (see Figure 22), if noise sources are present at these frequencies anti-aliasing will reduce their effects. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2494 F19 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2494 F20 Figure 20. Input Normal Mode Rejection, Internal Oscillator and 60Hz Rejection Mode 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN fN = fEOSC/5120 2494 F21 Figure 21. Input Normal Mode Rejection at DC 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2494 F22 Figure 19. Input Normal Mode Rejection, Internal Oscillator and 50Hz Rejection Mode Figure 22. Input Normal Mode Rejection at fS = 256 • fN 2494fb 31 LTC2494 APPLICATIONS INFORMATION NORMAL MODE REJECTION (dB) The user can expect to achieve this level of performance using the internal oscillator, as shown in Figures 23, 24, and 25. Measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes. Traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2494 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale. In many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted volt level error sources with several volts of peak-to-peak noise. Figures 26 and 27 show measurement results for the rejection of a 7.5V peak-to-peak noise source (150% of full scale) applied to the LTC2494. From these curves, it is shown that the rejection performance is maintained even in extremely noisy environments. Using the 2x speed mode of the LTC2494 alters the rejection characteristics around DC and multiples of fS. The device bypasses the offset calibration in order to increase the output rate. The resulting rejection plots are shown in Figures 28 and 29. 1x type frequency rejection can be achieved using the 2x mode by performing a running average of the conversion results (see Figure 30). Output Data Rate When using its internal oscillator, the LTC2494 produces up to 15 samples per second (sps) with a notch frequency of 60Hz. The actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. When operating with an external conversion clock (FO connected to an external oscillator), the LTC2494 output data rate can be increased. The duration of the conversion cycle is 41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves as if the internal oscillator is used. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate (up to a maximum of 100sps). The increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. When using the integrated temperature sensor, the internal 0 –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2494 F23 Figure 23. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2494 F24 Figure 24. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2494 F25 Figure 25. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz/60Hz Notch) oscillator should be used (FO = 0) or an external oscillator applied to FO, fEOSC, should be set to 307.2kHz Max. A change in fEOSC results in a proportional change in the internal notch position. This leads to reduced differential mode rejection of line frequencies. The common mode 2494fb 32 LTC2494 APPLICATIONS INFORMATION 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) INPUT NORMAL REJECTION (dB) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 –20 –40 –60 –80 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2494 F26 –100 –120 0 fN Figure 26. Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (fN) 8fN 2494 F28 Figure 28. Input Normal Mode Rejection 2x Speed Mode 0 INPUT NORMAL REJECTION (dB) –20 –40 –60 –80 –100 –120 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY (fN) 2494 F29 – 60 –80 –100 –120 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2494 F27 Figure 27. Measure Input Normal Mode Rejection vs Input Frequency With input Perturbation of 150% (50Hz Notch) rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the IN+ and IN– pins will continue to reject line frequency noise. An increase in fEOSC also increases the effective dynamic input and reference current. External RC networks will continue to have zero differential input current, but the time required for complete settling (580ns for fEOSC = 307.2kHz) is reduced, proportionally. Once the external oscillator frequency is increased above 1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade. This results in larger offset errors, full scale errors, and decreased resolution (see Figures 31 to 38). Figure 29. Input Normal Mode Rejection 2x Speed Mode –70 NORMAL MODE REJECTION (dB) –80 NO AVERAGE –90 –100 –110 –120 –130 –140 60 62 54 56 58 48 50 52 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2494 F30 WITH RUNNING AVERAGE Figure 30. Input Normal Mode Rejection 2x Speed Mode with and Without Running Averaging 2494fb 33 LTC2494 APPLICATIONS INFORMATION 50 40 30 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F31 OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) 2500 TA = 85°C 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F32 –FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK TA = 85°C 3500 3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 –500 –1000 TA = 25°C TA = 85°C –2000 –1500 TA = 25°C –2500 –3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F33 –3500 Figure 31. Offset Error vs Output Data Rate and Temperature 18 TA = 25°C, 85°C RESOLUTION (BITS) RESOLUTION (BITS) 16 Figure 32. +FS Error vs Output Data Rate and Temperature 18 OFFSET ERROR (ppm OF VREF) 20 Figure 33.–FS Error vs Output Data Rate and Temperature VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F36 16 TA = 85°C 14 TA = 25°C 14 12 VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F34 10 12 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F35 Figure 34. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature 18 Figure 35. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature 18 Figure 36. Offset Error vs Output Data Rate and Reference Voltage RESOLUTION (BITS) 16 VCC = 5V, VREF = 2.5V, 5V 14 RESOLUTION (BITS) 16 VCC = 5V, VREF = 2.5V 14 VCC = VREF = 5V VIN(CM) = VREF(CM) 12 VIN = 0V FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F37 VIN(CM) = VREF(CM) VIN = 0V 12 REF– = GND FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2494 F38 Figure 37. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage Figure 38. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage 2494fb 34 LTC2494 PACKAGE DESCRIPTION UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 ± 0.05 5.50 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 3.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.15 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 0.00 – 0.05 3.15 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 37 38 0.40 ± 0.10 1 2 PIN 1 TOP MARK (SEE NOTE 6) 7.00 ± 0.10 (2 SIDES) 5.15 ± 0.10 (2 SIDES) 0.40 ± 0.10 0.200 REF 0.25 ± 0.05 0.75 ± 0.05 0.200 REF 0.00 – 0.05 0.50 BSC R = 0.115 TYP (UH) QFN 0205 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2494fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC2494 TYPICAL APPLICATION External Buffers Provide High Impedance Inputs and Amplifier Offsets are Automatically Cancelled. LTC2494 ΔΣ ADC WITH EASY DRIVE INPUTS SDI SCK SDO CS ANALOG 17 INPUTS INPUT MUX MUXOUTN 2 MUXOUTP – 1/2 LTC6078 1 1k 0.1μF 3 + 6 – 1/2 LTC6078 7 1k 0.1μF 2494 TA02 5 + RELATED PARTS PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 LTC2413 LTC2414/LTC2418 LTC2440 LTC2480 LTC2481 LTC2482 LTC2483 LTC2484 LTC2485 LTC2486 LTC2496 LTC2498 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency ΔΣ ADC in SO-8 24-Bit, No Latency ΔΣ ADC with Differential Inputs 24-Bit, No Latency ΔΣ ADC with Differential Inputs 8-/16-Channel 24-Bit, No Latency ΔΣ ADCs High Speed, Low Noise 24-Bit ΔΣ ADC 16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit ΔΣ ADC with Easy Drive Inputs 16-Bit ΔΣ ADC with Easy Drive Inputs, and I2C Interface 24-Bit ΔΣ ADC with Easy Drive Inputs 24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface, and COMMENTS 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.05% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.8μVRMS Noise, 2ppm INL Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs Pin Compatible with LTC2482/LTC2484 Pin Compatible with LTC2483/LTC2485 Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2481/LTC2485 Pin Compatible with LTC2480/LTC2482 LTC2415/LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate Pin Compatible with LTC2481/LTC2483 Temperature Sensor 16-Bit 2-/4-Channel ΔΣ ADC with PGA and Temperature Sensor Pin Compatible with LTC2492/LTC2488 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation 24-Bit ΔΣ ADC with SPI Interface and Temperature Sensor Pin Compatible with LTC2494/LTC2449/LTC2498 Pin Compatible with LTC2494/LTC2496/LTC2449 2494fb 36 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1008 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007