LTC2496

LTC2496 16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation FEATURES ■ ■ DESCRIPTION The LTC®2496 is a 16-channel (8-differential) 16-bit No Latency ΔΣ™ ADC with Easy Drive™ technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances, and rail-to-rail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC2496 includes an integrated oscillator. This device can be configured to measure an external signal (from combinations of 16 analog input channels operating in single ended or differential modes). It automatically rejects line frequencies of 50Hz and 60Hz, simultaneously. The LTC2496 allows a wide common mode input range (0V to VCC), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion after a new channel is selected is valid. Access to the multiplexer output enables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Up to 8 Differential or 16 Single-Ended Inputs Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise (0.02 LSB Transition Noise) GND to VCC Input/Reference Common Mode Range Simultaneous 50Hz/60Hz Rejection 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Full-Scale Error No Latency: Digital Filter Settles in a Single Cycle, Even After a New Channel is Selected Single Supply 2.7V to 5.5V Operation (0.8mW) Internal Oscillator QFN 5mm × 7mm Package APPLICATIONS ■ ■ ■ ■ Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control TYPICAL APPLICATION Data Acquisition System 2.7V TO 5.5V 0.1μF 10μF +FS ERROR (ppm) 80 +FS Error vs RSOURCE VCC = 5V 60 VREF = 5V VIN+ = 3.75V VIN– = 1.25V 40 FO = GND 20 TA = 25°C CIN = 1μF 0 –20 –40 –60 F0 CH0 CH1 • • • CH7 CH8 16-CHANNEL MUX • • • CH15 COM MUXOUT/ ADCIN REF + VCC IN+ 16-BIT ΔΣ ADC WITH EASY-DRIVE IN– REF – SDI SCK SDO CS 4-WIRE SPI INTERFACE MUXOUT/ ADCIN OSC 2496 TA01a –80 1 10 100 1k RSOURCE (Ω) 10k 100k 2498 TA01b 2496fa 1 LTC2496 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PACKAGE/ORDER INFORMATION TOP VIEW GND GND 31 GND 30 REF– 29 REF+ 28 VCC 27 MUXOUTN 39 26 ADCINN 25 ADCINP 24 MUXOUTP 23 CH15 22 CH14 21 CH13 20 CH12 13 14 15 16 17 18 19 CH5 CH6 CH7 CH8 CH9 CH10 CH11 SDO SCK SDI CS FO 38 37 36 35 34 33 32 GND 1 NC 2 GND 3 GND 4 GND 5 GND 6 COM 7 CH0 8 CH1 9 CH2 10 CH3 11 CH4 12 Supply Voltage (VCC) ................................... –0.3V to 6V Analog Input Voltage (CH0 to CH15, COM) .................................................–0.3V to (VCC + 0.3V) Reference Input Voltage .................................................–0.3V to (VCC + 0.3V) ADCINN, ADCINP, MUXOUTP, MUXOUTN .................................................–0.3V to (VCC + 0.3V) Digital Input Voltage......................–0.3V to (VCC + 0.3V) Digital Output Voltage ...................–0.3V to (VCC + 0.3V) Operating Temperature Range LTC2496C ................................................ 0°C to 70°C LTC2496I ............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC2496CUHF LTC2496IUHF QFN PART MARKING* 2496 2496 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS PARAMETER Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MIN 16 ● ● TYP 2 1 0.5 10 MAX 20 5 32 UNITS Bits ppm of VREF ppm of VREF μV nV/ºC ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF μVRMS 2496fa Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6) 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V 2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V 5.5V ≤ VCC ≤ 2.7V, 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) ● 0.1 ● 32 0.1 15 15 15 0.6 Output Noise 2 LTC2496 CONVERTER CHARACTERISTICS PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 60Hz ±2% Input Common Mode Rejection 50Hz ±2% Input Normal Mode Rejection 50Hz ±2% Input Normal Mode Rejection 60Hz ±2% Input Normal Mode Rejection 50Hz/60Hz ±2% Reference Common Mode Rejection DC Power Supply Rejection DC Power Supply Rejection, 50Hz ±2% Power Supply Rejection, 60Hz ±2% CONDITIONS 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) VREF = 2.5V, IN+ = IN– = GND VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9) VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9) ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN 140 140 140 110 110 87 120 140 120 120 120 120 120 TYP MAX UNITS dB dB dB dB dB dB dB dB dB dB ANALOG INPUT AND REFERENCE SYMBOL IN+ IN– VIN FS LSB REF+ REF– VREF CS(IN+) CS(IN–) CS(VREF) IDC_LEAK (IN+) IDC_LEAK IDC_LEAK tOPEN QIRR (IN–) (REF+) PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS MIN GND – 0.3V GND – 0.3V ● ● ● ● ● ● TYP MAX VCC + 0.3V VCC + 0.3V +FS UNITS V V V V Absolute/Common Mode IN+ Voltage (IN+ Corresponds to the Selected Positive Input Channel) Absolute/Common Mode IN– Voltage (IN– Corresponds to the Selected Positive Input Channel) Input Differential Voltage Range (IN+ – IN–) Full Scale of the Differential Input (IN+ – IN–) Least Significant Bit of the Output Code Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Voltage Range (REF+ – REF–) IN+ Sampling Capacitance IN– Sampling Capacitance VREF Sampling Capacitance IN+ DC Leakage Current IN– DC Leakage Current REF+ DC Leakage Current MUX Break-Before-Make MUX Off Isolation VIN = 2VP-P DC to 1.8MHz Sleep Mode, IN+ = GND Sleep Mode, IN– = GND Sleep Mode, REF+ = V CC –FS 0.5 VREF FS/216 0.1 GND 0.1 11 11 11 VCC REF+ – 0.1V VCC V V V pF pF pF ● ● ● ● –10 –10 –100 –100 1 1 1 1 50 120 10 10 100 100 nA nA nA nA ns dB IDC_LEAK (REF–) REF– DC Leakage Current Sleep Mode, REF– = GND 2496fa 3 LTC2496 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage (⎯C⎯S, FO, SDI) Low Level Input Voltage (⎯C⎯S, FO, SDI) High Level Input Voltage (SCK) Low Level Input Voltage (SCK) Digital Input Current (⎯C⎯S, FO, SDI) Digital Input Current (SCK) Digital Input Capacitance (⎯C⎯S, FO, SDI) Digital Input Capacitance (SCK) High Level Output Voltage (SDO) Low Level Output Voltage (SDO) High Level Output Voltage (SCK) Low Level Output Voltage (SCK) Hi-Z Output Leakage (SDO) (Notes 10, 17) IO = –800μA IO = 1.6mA IO = –800μA (Notes 10, 17) IO = 1.6mA (Notes 10, 17) ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) 2.7V ≤ VCC ≤ 5.5V (Notes 10, 15) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Notes 10, 15) ● ● ● ● ● ● MIN VCC – 0.5 TYP MAX 0.5 UNITS V V V V μA μA pF pF V VCC – 0.5 0.5 –10 –10 10 10 VCC – 0.5 0.4 VCC – 0.5 0.4 –10 10 10 10 V V V μA POWER REQUIREMENTS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● MIN 2.7 ● ● TYP 160 1 MAX 5.5 275 2 UNITS V μA μA Conversion Current (Note 12) Sleep Mode (Note 12) DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL fEOSC tHEO tLEO tCONV fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time Simultaneous 50/60Hz External Oscillator CONDITIONS (Note 16) The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN ● ● ● ● TYP MAX 4000 100 100 UNITS kHz μs μs ms ms kHz kHz 10 0.125 0.125 144.1 146.9 41036/fEOSC (in kHz) 38.4 fEOSC /8 149.9 Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 10) (Note 10) (Note 10) Internal Oscillator External Oscillator (Note 10) ● ● ● ● ● 45 125 125 0.61 0.625 192/fEOSC (in kHz) 24/fESCK (in kHz) 55 4000 % kHz ns ns 0.64 ms ms ms 2496fa 4 LTC2496 DIGITAL INPUTS AND DIGITAL OUTPUTS SYMBOL t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 t7 t8 PARAMETER ⎯CS↓ to SDO Low ⎯ ⎯CS↑ to SDO High Z ⎯ ⎯CS↓ to SCK↓ ⎯ ⎯C⎯S↓ to SCK↑ SCK↓ to SDO Valid SDO Hold After SCK↓ SCK Set-Up Before ⎯C⎯S↓ SCK Hold After ⎯C⎯S↓ SDI Setup Before SCK↑ SDI Hold After SCK↑ (Note 5) (Note 5) (Note 5) Internal SCK Mode External SCK Mode CONDITIONS ● ● ● ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) MIN 0 0 0 50 200 15 50 50 100 100 TYP MAX 200 200 200 UNITS ns ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREFCM = VREF/2, FS = 0.5VREF VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, where IN+ and IN– are the selected input channels Note 4: Use internal conversion clock or external conversion clock source with fEOSC = 307.2kHz unless other wise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: fEOSC = 256kHz ±2% (external oscillator). Note 8: fEOSC = 307.2kHz ±2% (external oscillator). Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz ±2% (external oscillator). Note 10: The SCK can be configured in external SCK mode or internal SCK mode. In external SCK mode, the SCK pin is used as a digital input and the driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a digital output and the output clock signal during the data output is fISCK. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses its internal oscillator. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: The converter is in external SCK mode of operation such that the SCK pin is used as a digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in Hz. Note 16: Refer to Applications Information section for performance vs data rate graphs. Note 17: The converter is in internal SCK mode of operation such that the SCK pin is used as a digital output. 2496fa 5 LTC2496 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 3 2 INL (ppm OF VREF) 1 0 85°C –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND INL (ppm OF VREF) –45°C 25°C 3 2 1 0 –1 –2 –3 –1.25 Integral Nonlinearity (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 2.5V VIN(CM) = 1.25V FO = GND INL (ppm OF VREF) –45°C, 25°C, 90°C 3 2 1 0 –1 –2 Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND –45°C, 25°C, 90°C 2 2.5 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2496 G20 –3 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2496 G21 2496 G19 Total Unadjusted Error (VCC = 5V, VREF = 5V) 12 8 TUE (ppm OF VREF) 4 0 –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) –45°C VCC = 5V VREF = 5V VIN(CM) = 2.5V FO = GND 12 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 5V, VREF = 2.5V) VCC = 5V VREF = 5V VIN(CM) = 1.25V FO = GND 12 85°C 25°C 8 TUE (ppm OF VREF) 4 0 –4 –8 Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) VCC = 2.7V VREF = 2.5V VIN(CM) = 1.25V FO = GND 25°C 85°C 25°C 85°C –45°C –45°C 2 2.5 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2496 G23 –12 –1.25 –0.75 –0.25 0.25 0.75 INPUT VOLTAGE (V) 1.25 2496 G24 2496 G22 2496fa 6 LTC2496 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs VIN(CM) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –1 0 1 3 2 VIN(CM) (V) 4 5 6 2496 G25 Offset Error vs Temperature 0.3 0.2 0.1 0 VCC = 5V VREF = 5V VIN = 0V VIN(CM) = GND FO = GND 0.3 0.2 0.1 0 –0.1 –0.2 Offset Error vs VCC REF+ = 2.5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C OFFSET ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) –0.1 –0.2 OFFSET ERROR (ppm OF VREF) VCC = 5V VREF = 5V VIN = 0V TA = 25°C –0.3 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 –0.3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 2496 G26 2496 G27 Offset Error vs VREF 0.3 0.2 0.1 0 VCC = 5V REF– = GND VIN = 0V VIN(CM) = GND TA = 25°C 310 On-Chip Oscillator Frequency vs Temperature 310 On-Chip Oscillator Frequency vs VCC VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND TA = 25°C OFFSET ERROR (ppm OF VREF) 308 FREQUENCY (kHz) FREQUENCY (kHz) 75 90 308 306 306 304 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND FO = GND 0 15 30 45 60 TEMPERATURE (°C) 304 –0.1 –0.2 302 302 –0.3 0 1 2 3 VREF (V) 4 5 2496 G28 300 –45 –30 –15 300 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 2496 G30 2496 G29 2496fa 7 LTC2496 TYPICAL PERFORMANCE CHARACTERISTICS PSRR vs Frequency at VCC 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 0 10 10k 100k 1k 100 FREQUENCY AT VCC (Hz) 1M VCC = 4.1V DC VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 0 –20 –40 REJECTION (dB) –60 –80 –100 –120 –140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 2496 G32 PSRR vs Frequency at VCC VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND FO = GND TA = 25°C 0 PSRR vs Frequency at VCC VCC = 4.1V DC ±0.7V VREF = 2.5V –20 IN+ = GND IN– = GND –40 FO = GND TA = 25°C –60 –80 –100 –120 –140 30600 REJECTION (dB) 30650 30700 30750 FREQUENCY AT VCC (Hz) 30800 2496 G33 2496 G31 Conversion Current vs Temperature 200 FO = GND CS = GND SCK = NC SDO = NC VCC = 5V 160 VCC = 2.7V 2.0 Sleep Mode Current vs Temperature FO = GND 1.8 CS = VCC SCK = NC 1.6 SDO = NC 1.4 1.2 1.0 0.8 0.6 0.4 0.2 150 100 0 15 30 45 60 TEMPERATURE (°C) 75 90 VCC = 2.7V VCC = 5V 500 450 SUPPLY CURRENT (μA) Conversion Current vs Data Output Rate VREF = VCC IN+ = GND IN– = GND 400 SCK = NC SDO = NC 350 CS = GND FO = EXT OSC TA = 25°C 300 250 200 CONVERSION CURRENT (μA) SLEEP MODE CURRENT (μA) 180 VCC = 5V 140 VCC = 3V 120 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 0 –45 –30 –15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 G36 2496 G34 2496 G35 2496fa 8 LTC2496 PIN FUNCTIONS GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a common ground plane through a low impedance connection. All 8 pins must be connected to ground for proper operation. NC (Pin 2): No Connection, this pin can be left floating or tied to GND. COM (Pin 7): The common negative input (IN–) for all single-ended multiplexer configurations. The voltage on CH0 to CH15 and COM pins can have any value between GND – 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be programmed for single-ended or differential mode. MUXOUTP (Pin 24): Positive Multiplexer Output. Used to drive an external buffer/amplifier or can be shorted directly to ADCINP. ADCINP (Pin 25): Positive ADC Input. Tie to the output of a buffer/amplifier driven by MUXOUTP or short directly to MUXOUTP. ADCINN (Pin 26): Negative ADC Input. Tie to the output of a buffer/amplifier driven by MUXOUTN or short directly to MUXOUTN. MUXOUTN (Pin 27): Negative Multiplexer Output. Used to drive an external buffer/amplifier or can be shorted directly to ADCINN. VCC (Pin 28): Positive Supply Voltage. Bypass to GND with a 10μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor as close to the part as possible. REF+ (Pin 29), REF– (Pin 30): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, remains more positive than the negative reference input, REF–, by at least 0.1V. The differential voltage (REF = REF+ – REF–) sets the full-scale range for all input channels. SDI (Pin 34): Serial Data Input. This pin is used to select the input channel. The serial data input is applied under control of the serial clock (SCK) during the data output operation. The first conversion following a new input is valid. FO (Pin 35): Frequency Control Pin. Digital input that controls the internal conversion clock rate. When FO is connected to VCC or GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also be overridden by driving the FO pin with an external clock in order to change the output rate and the digital filter rejection null. ⎯C⎯S (Pin 36): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as ⎯C⎯S is HIGH. A LOW-to-HIGH transition on ⎯C⎯S during the Data Output aborts the data transfer and starts a new conversion. SDO (Pin 37): Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select pin is HIGH, the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. When the conversion is in progress this pin is HIGH; once the conversion is complete SDO goes low. The conversion status is monitored by pulling ⎯C⎯S LOW. SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In Internal Serial Clock Operation mode, SCK is generated internally and is seen as an output on the SCK pin. In External Serial Clock Operation mode, the digital I/O clock is externally applied to the SCK pin. The Serial Clock operation mode is determined by the logic level applied to the SCK pin at power up and during the most recent falling edge of ⎯C⎯S. Exposed Pad (Pin 39): Ground. This pin is ground and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating. 2496fa 9 LTC2496 FUNCTIONAL BLOCK DIAGRAM VCC GND REF + REF – CH0 CH1 • • • MUX MUXOUTP ADCINP AUTOCALIBRATION AND CONTROL INTERNAL OSCILLATOR FO (INT/EXT) – + SERIAL INTERFACE DECIMATING FIR ADDRESS 2496 BD CH15 COM DIFFERENTIAL 3RD ORDER ΔΣ MODULATOR SDI SCK SDO CS MUXOUTN ADCINN Figure 1. Functional Block Diagram TEST CIRCUITS SDO 1.69k CLOAD = 20pF SDO Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD = 20pF 2496 TC01 VCC 1.69k Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2496 TC02 2496fa 10 LTC2496 TIMING DIAGRAMS Timing Diagram Using Internal SCK (SCK HIGH with ⎯C⎯S↓) CS t1 SDO t3 SCK t7 SDI SLEEP DATA IN/OUT t8 tKQMIN tKQMAX t2 2496 TD01 CONVERSION Timing Diagram Using External SCK (SCK LOW with ⎯C⎯S↓) CS t1 SDO t5 SCK t7 SDI SLEEP DATA IN/OUT t8 t6 t4 tKQMIN tKQMAX t2 2496 TD02 CONVERSION 2496fa 11 LTC2496 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2496 is a multi-channel, low power, delta-sigma analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation. Its operation is made up of three states (See Figure 2). The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/output cycle. The 4-wire interface consists of serial data output (SDO), serial clock (SCK), chip select (⎯C⎯S) and serial data input (SDI).The interface, timing, operation cycle, and data output format is compatible with Linear’s entire family of ΔΣ converters. Initially, at power up, the LTC2496 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, if ⎯C⎯S is HIGH, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as ⎯C⎯S is HIGH. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. Once ⎯C⎯S is pulled LOW, the device powers up, exits the sleep mode, and enters the data input/output state. If ⎯C⎯S is brought HIGH before the first rising edge of SCK, the device returns to the sleep state and the power is reduced. POWER UP IN+= CH0, IN–= CH1 If ⎯C⎯S is brought HIGH after the first rising edge of SCK, the data output cycle is aborted and a new conversion cycle begins. The data output corresponds to the conversion just completed. This result is shifted out on the serial data output pin (SDO) under the control of the serial clock pin (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (See Figure 3). The channel selection data for the next conversion is also loaded into the device at this time. Data is loaded from the serial data input pin (SDI) on each rising edge of SCK. The data input/output cycle is concluded once 24 bits are read out of the ADC or when ⎯C⎯S is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. ⎯⎯ Through timing control of the CS and SCK pins, the LTC2496 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming and do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2496 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input, is valid and accurate to the full specifications of the device. The LTC2496 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected. This calibration is transparent to the user and has no effect with the operation cycle described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. Easy Drive Input Current Cancellation The LTC2496 combines a high precision delta-sigma ADC with an automatic, differential, input current cancellation 2496fa CONVERT SLEEP CS = LOW AND SCK CHANNEL SELECT DATA OUTPUT 2496 F02 Figure 2. LTC2496 State Transition Diagram 12 LTC2496 APPLICATIONS INFORMATION front end. A proprietary front end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2496 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Differential Input Current Cancellation Section). This unique architecture does not require on-chip buffers thereby enabling signals to swing beyond ground or up to VCC. Moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full-scale + offset + linearity + drift) is maintained even with external RC networks. Power-Up Sequence The LTC2496 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result, input channel selection, and serial clock mode. When VCC rises above this threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. The conversion immediately following a POR cycle is performed on the input channel IN+ = CH0, IN– = CH1. The first conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7V to 5.5V) before the end of the POR interval. A new input channel, can be programmed into the device during this first data input/output cycle. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage range for REF+ and REF– pins covers the entire operating range of the device (GND to VCC). For correct converter operation, VREF must be positive (REF+ > REF–) The LTC2496 differential reference input range is 0.1V to VCC. For the simplest operation, REF+ can be shorted to VCC and REF– can be shorted to GND. The converter output noise is determined by the thermal noise of the front end circuits. Since the transition noise is well below 1LSB (0.02LSB), a decrease in reference voltage will proportionally improve the converter’s effective resolution and improve the INL. Input Voltage Range The analog input is truly differential with an absolute, common mode range for CH0 to CH15 and COM input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD projection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2496 converts the bipolar differential input signal VIN = IN+ + IN– (where IN+ and IN– are the selected input channels), from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–. Outside this range, the converter indicates the over range or the under range condition using distinct output codes. Signals applied to the input (CH0 to CH15, COM) may extend 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the input. The effect of series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent error due to input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. MUXOUT/ADCIN The output of the multiplexer (MUXOUT) and the input to the ADC (ADCIN) can be used to perform input signal conditioning on any of the selected input channels or simply shorted together for direct digitization. If an external amplifier is used, the LTC2496 automatically calibrates both the offset and drift of this circuit and the Easy Drive sampling scheme enables a wide variety of amplifiers to be used. 2496fa 13 LTC2496 APPLICATIONS INFORMATION In order to achieve optimum performance, if an external amplifier is not used, short these pins directly together (ADCINP to MUXOUTP and ADCINN to MUXOUTN) and minimize their capacitance to ground. SERIAL INTERFACE PINS The LTC2496 transmits the conversion result, reads the input channel selection, and receives a start of conversion command through a synchronous 3- or 4-wire interface. During the conversion and sleep states, this interface can be used to access the converter status. During the data output state, it is used to read the conversion result and program the input channel for the next conversion cycle. Serial Clock Input/Output (SCK) The serial clock pin (SCK) is used to synchronize the data input/output transfer. Each bit is shifted out of the SDO pin on the falling edge of SCK and data is shifted into the SDI pin on the rising edge of SCK. The serial clock pin (SCK) can be configured as either a master (SCK is an output generated internally) or a slave (SCK is an input and applied externally). Master mode (Internal SCK) is selected by simply floating the SCK pin. Slave mode (External SCK) is selected by driving SCK low during power up and each falling edge of ⎯C⎯S. Specific details of these SCK modes are described in the Serial Interface Timing Modes section. Serial Data Output (SDO) The serial data output pin (SDO) provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When ⎯C⎯S is HIGH, the SDO driver is switched to a high impedance state in order to share the data output line with other devices. If ⎯C⎯S is brought LOW during the conversion phase, the ⎯E⎯O⎯C bit (SDO pin) will be driven HIGH. Once the conversion is complete, if ⎯C⎯S is brought LOW ⎯E⎯O⎯C will be driven LOW indicating the conversion is complete and the result is ready to be shifted out of the device. Chip Select (⎯C⎯S) The active low ⎯C⎯S pin is used to test the conversion status, enable I/O data transfer, initiate a new conversion, control the duration of the sleep state, and set the SCK mode. At the conclusion of a conversion cycle, while ⎯C⎯S is HIGH, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude. In order to exit the sleep state and enter the data output state, ⎯C⎯S must be pulled low. Data is now shifted out the SDO pin under control of the SCK pin as described previously. A new conversion cycle is initiated either at the conclusion of the data output cycle (all 24 data bits read) or by pulling ⎯C⎯S HIGH any time between the first and 24th rising edges of the serial clock (SCK). In this case, the data output is aborted and a new conversion begins. Serial Data Input (SDI) The serial data input (SDI) is used to select the input channel. Data is shifted into the device during the data output/input ⎯⎯ state on the rising edge of SCK while CS is low. OUTPUT DATA FORMAT The LTC2496 serial output stream is 24 bits long. The first bit indicates the conversion status, the second bit is always zero, and the third bit conveys sign information. The next 17 bits are the conversion result, MSB first. The remaining 4 bits are always LOW. Bit 23 (first output bit) is the end of conversion (⎯E⎯O⎯C) indicator. This bit is available on the SDO pin during the conversion and sleep states whenever ⎯C⎯S is LOW. This bit is HIGH during the conversion cycle, goes LOW once the conversion is complete, and is HIGH-Z when ⎯C⎯S is HIGH. Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If the selected input (VIN = IN+ – IN–) is greater than 0V, this bit is HIGH. If VIN < 0, this bit is LOW. 2496fa 14 LTC2496 APPLICATIONS INFORMATION Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides under range and over range indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below –FS. The function of these bits is summarized in Table 1. Table 1. LTC2496 Status Bits Input Range VIN ≥ 0.5 • VREF 0V ≤ VIN < 0.5 • VREF –0.5 • VREF ≤ VIN < 0V VIN < –0.5 • VREF Bit 23 ⎯E⎯O⎯C 0 0 0 0 Bit 22 DMY 0 0 0 0 Bit 21 SIG 1 1 0 0 Bit 20 MSB 1 0 1 0 In order to shift the conversion result out of the device, ⎯CS must first be driven LOW. ⎯E⎯O⎯C is seen at the SDO pin ⎯ of the device once ⎯C⎯S is pulled LOW. ⎯E⎯O⎯C changes in real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (⎯E⎯O⎯C) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as ⎯E⎯O⎯C (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN– pins remains between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any differential input voltage VIN from –FS = –0.5 • VREF to +FS = 0.5 • VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the value –FS – 1LSB. Bits 20 to 4 are the 16-bit plus sign conversion result MSB first. Bit 4 is the least significant bit (LSB16). Bits 3 to 0 are always LOW. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever ⎯C⎯S is HIGH, SDO remains high impedance and SCK is ignored. CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 19 20 21 22 23 24 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 DON'T CARE SDO Hi-Z EOC “0” SIG MSB LSB BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Hi-Z BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2496 F03 Figure 3. Channel Selection and Data Output Timing 2496fa 15 LTC2496 APPLICATIONS INFORMATION Table 2. LTC2496 Output Data Format DIFFERENTIAL INPUT VOLTAGE VIN* VIN* ≥ FS** FS** – 1LSB 0.5 • FS** 0.5 • FS** – 1LSB 0 –1LSB –0.5 • FS** –0.5 • FS** – 1LSB –FS** VIN* < –FS** BIT 23 EOC 0 0 0 0 0 0 0 0 0 0 BIT 22 DMY 0 0 0 0 0 0 0 0 0 0 BIT 21 SIG 1 1 1 1 1 0 0 0 0 0 BIT 20 MSB 1 0 0 0 0 1 1 1 1 0 BIT 19 0 1 1 0 0 1 1 0 0 1 BIT 18 0 1 0 1 0 1 0 1 0 1 BIT 17 0 1 0 1 0 1 0 1 0 1 … … … … … … … … … … … BIT 4 0 1 0 1 0 1 0 1 0 1 BITS 3 TO 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 *The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF. INPUT DATA FORMAT The LTC2496 serial input word is 8 bits long. The input data (SGL, ODD, A2, A1, A0) is used to select the input channel. After power up, the device initiates an internal reset cycle which sets the input channel to CH0 – CH1 (IN+ = CH0, IN– = CH1), The first conversion automatically begins at power up using the default input channel. Once the conversion is complete a new word can be written into the device in order to select the input channel for the next conversion cycle. The first 3 bits shifted into the device consist of two preenable bits and one enable bit. As demonstrated in Figure 3, the first three bits shifted into the device enable the device input channel selection. Valid settings for these three bits are 000, 100, and 101. Other combinations should be avoided. If the first three bits are 000 or 100, the following data is ignored (don’t care) and the previously selected input channel remains valid for the next conversion If the first 3 bits shifted into the device are 101, then the next 5 bits select the input channel for the next conversion cycle, see Table 3. The first input bit following the 101 sequence (SGL) determines if the input selection is differential (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL = 1, one of 16-channels is selected as the positive input. The negative input is COM for all single ended operations. The remaining 4 bits (ODD, A2, A1, A0) determine which channel(s) is/are selected and the polarity (for a differential input). This data sequence is backward compatible with the LTC2448 and LTC2418 families of delta sigma ADCs. SERIAL INTERFACE TIMING MODES The LTC2496’s 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 3- or 4-wire I/O, single cycle or continuous conversion. The following sections describe each of these timing modes in detail. In all cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. For each mode, the operating cycle, data input format, data output format, and performance remain the same. Refer to Table 4 for a summary. 2496fa 16 LTC2496 APPLICATIONS INFORMATION Table 3 Channel Selection MUX ADDRESS ODD/ SGL SIGN *0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– IN– 0 IN+ 1 IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– IN+ IN– 2 3 4 5 6 CHANNEL SELECTION 7 8 9 10 11 12 13 14 15 COM *Default at power up 2496fa 17 LTC2496 APPLICATIONS INFORMATION Table 4. Serial Interface Timing Modes CONFIGURATION External SCK, Single Cycle Conversion External SCK, 3-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 3-Wire I/O, Continuous Conversion SCK CONVERSION DATA OUTPUT CONNECTION AND SOURCE CYCLE CONTROL CONTROL WAVEFORMS ⎯⎯ ⎯C⎯S and SCK CS and SCK Figures 4, 5 External External Internal Internal SCK ⎯CS↓ ⎯ Continuous SCK ⎯C⎯S↓ Internal Figure 6 Figures 7, 8 Figure 9 External Serial Clock, Single Cycle Operation This timing mode uses an external serial clock to shift out the conversion result and ⎯C⎯S to monitor and control the state of the conversion cycle, see Figure 4. The external serial clock mode is selected during the powerup sequence and on each falling edge of ⎯C⎯S. In order to enter and remain in the external SCK mode of operation, SCK must be driven LOW both at power up and on each ⎯C⎯S falling edge. If SCK is HIGH on the falling edge of ⎯C⎯S, the device will switch to the internal SCK mode. 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • The serial data output pin (SDO) is Hi-Z as long as ⎯C⎯S is HIGH. At any time during the conversion cycle, ⎯C⎯S may be pulled LOW in order to monitor the state of the converter. While ⎯C⎯S is LOW, ⎯E⎯O⎯C is output to the SDO pin. ⎯E⎯O⎯C = 1 while a conversion is in progress and ⎯E⎯O⎯C = 0 if the conversion is complete and the device is in the sleep state. Independent of ⎯C⎯S, the device automatically enters the sleep state once the conversion is complete; however, in order to reduce the power, ⎯C⎯S must be HIGH. VCC LTC2496 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 29 30 8 15 16 • • • REF + REF • • SDI SCK 34 38 4-WIRE SPI INTERFACE – CH0 • CH7 CH8 • CH15 COM GND • • SDO CS 37 36 ANALOG INPUTS 23 7 1,3,4,5,6,31,32,33,39 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 19 20 21 22 23 24 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 DON'T CARE SDO EOC “0” SIG MSB LSB BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Hi-Z BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2496 F04 Figure 4. External Serial Clock, Single Cycle Operation 2496fa 18 LTC2496 APPLICATIONS INFORMATION When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while ⎯C⎯S is LOW. The input data is then shifted in via the SDI pin on each rising edge of SCK (including the first rising edge). The channel selection will be used for the following conversion cycle. If the input channel is changed during this I/O cycle, the new settings take effect on the conversion cycle following the data input/output cycle. The output data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. ⎯E⎯O⎯C can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion and SDO goes HIGH (⎯E⎯O⎯C = 1) indicating a conversion is in progress. At the conclusion of the data cycle, ⎯C⎯S may remain LOW and ⎯E⎯O⎯C monitored as an end-of-conversion interrupt. Typically, ⎯C⎯S remains LOW during the data output/input state. However, the data output state may be aborted by pulling ⎯C⎯S HIGH any time between the 1st falling edge and the 24th falling edge of SCK, see Figure 5. On the rising edge of ⎯C⎯S, the device aborts the data output state and immediately initiates a new conversion. In order to program a new input channel, 8 SCK clock pulses are required. If the data output sequence is aborted prior to the 8th falling edge of SCK, the new input data is ignored and the previously selected input channel remains valid. If the rising edge of ⎯C⎯S occurs after the 8th falling edge of SCK, the new input channel is loaded and valid for the next conversion cycle. 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • VCC LTC2496 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 29 30 8 15 16 • • • REF + REF – CH0 • CH7 CH8 • CH15 COM • • • • SDI SCK 34 38 4-WIRE SPI INTERFACE SDO CS 37 36 ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 DON'T CARE SDO EOC “0” SIG MSB BIT 15 Hi-Z BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION SLEEP 2496 F05 Figure 5. External Serial Clock, Reduced Output Data Length and Valid Channel Selection 2496fa 19 LTC2496 APPLICATIONS INFORMATION External Serial Clock, 3-Wire I/O This timing mode uses a 3-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 6. ⎯C⎯S is permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is typically concluded 4ms after VCC exceeds 2V. The level applied to SCK at this time determines if SCK is internally generated or externally applied. In order to enter the external SCK mode, SCK must be driven LOW prior to the end of the POR cycle. Since ⎯C⎯S is tied LOW, the end-of-conversion (⎯E⎯O⎯C) can be continuously monitored at the SDO pin during the convert and sleep states. ⎯E⎯O⎯C may be used as an interrupt to an external controller. ⎯E⎯O⎯C = 1 while the conversion is in progress and ⎯E⎯O⎯C = 0 once the conversion is complete. On the falling edge of ⎯E⎯O⎯C, the conversion result is loading into an internal static shift register. The output data can now be shifted out the SDO pin under control of the externally applied SCK signal. Data is updated on the falling edge of SCK. The input data is shifted into the device through the SDI pin on the rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH, indicating a new conversion has begun. This data now serves as ⎯E⎯O⎯C for the next conversion. 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • VCC LTC2496 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 29 30 8 15 16 • • • REF + REF – CH0 • CH7 CH8 • CH15 COM • • • • SDI SCK 34 38 3-WIRE SPI INTERFACE 37 36 SDO CS ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 CS 1 SCK (EXTERNAL) 2 3 4 5 6 7 8 9 19 20 21 22 23 24 SDI DON'T CARE 1 0 EN SGL ODD A2 A1 A0 DON'T CARE SDO EOC “0” SIG MSB LSB BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CONVERSION 2496 F06 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 CONVERSION SLEEP DATA INPUT/OUTPUT Figure 6. External Serial Clock, 3-Wire Operation (⎯C⎯S = 0) 2496fa 20 LTC2496 APPLICATIONS INFORMATION Internal Serial Clock, Single Cycle Operation This timing mode uses the internal serial clock to shift out the conversion result and ⎯C⎯S to monitor and control the state of the conversion cycle, see Figure 7. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating or pulled HIGH before the conclusion of the POR cycle and prior to each ⎯⎯ falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of ⎯C⎯S; therefore, the internal SCK mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as ⎯C⎯S is HIGH. At any time during the conversion cycle, ⎯C⎯S may be pulled low in order to monitor the state of the converter. Once ⎯C⎯S is pulled LOW, SCK goes LOW and ⎯E⎯O⎯C is output to the SDO pin. ⎯E⎯O⎯C =1 while the conversion is in progress and ⎯E⎯O⎯C = 0 if the device is in the sleep state 2.7V TO 5.5V 10μF 28 0.1μF REFERENCE VOLTAGE 0.1V TO VCC • • • When testing ⎯E⎯O⎯C, if the conversion is complete (⎯E⎯O⎯C = 0), the device will exit sleep state. In order to return to the sleep state and reduce the power consumption, ⎯C⎯S must be pulled HIGH before the device pulls SCK HIGH. When the device is using its own internal oscillator (FO is tied LOW), the first rising edge of SCK occurs 12μs (tEOCTEST = 12μs) after the falling edge of ⎯C⎯S. If FO is driven by an external oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC. If ⎯C⎯S remains LOW longer than tEOCTEST, the first rising edge of SCK will occur and the conversion result is shifted out the SDO pin on the falling edge of SCK. The serial input word (SDI) is shifted into the device on the rising edge of SCK. After the 24th rising edge of SCK a new conversion automatically begins. SDO goes HIGH (⎯E⎯O⎯C = 1) and SCK remains HIGH for the duration of the conversion cycle. Once the conversion is complete, the cycle repeats. VCC LTC2496 FO 35 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR VCC 29 30 8 15 16 • • • REF + SDI SCK 34 38 4-WIRE SPI INTERFACE REF – CH0 • CH7 CH8 • CH15 COM • • • • OPTIONAL 10k SDO CS 37 36 ANALOG INPUTS 23 7 GND 1,3,4,5,6,31,32,33,39 1μF 2496fa 27 LTC2496 APPLICATIONS INFORMATION The user can expect to achieve this level of performance using the internal oscillator, as shown in Figure 19. Measured values of normal mode rejection are shown superimposed over the theoretical rejection. Traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2496 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale. In many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts of peak-to-peak noise. Figure 20 shows measurement results for the rejection of a 7.5V peak-to-peak noise source (150% of full scale) applied to the LTC2496. From these curves, it is shown that the rejection performance is maintained even in extremely noisy environments. 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN –120 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2496 F19 Output Data Rate When using its internal oscillator, the LTC2496 produces up to 6.9 samples per second (sps) with a notch frequency of 55Hz. The actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. When operating with an external conversion clock (FO connected to an external oscillator), the LTC2496 output data rate can be increased. The duration of the conversion cycle is 41036/fEOSC. If fEOSC = 307.2kHz, the converter notch frequency is 60Hz. An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output data rate (up to a maximum of 100sps). The increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C fN = fEOSC/5120 2496 F17 Figure 17. Input Normal Mode Rejection at DC Figure 19. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (50Hz/60Hz Notch) 0 NORMAL MODE REJECTION (dB) –20 –40 – 60 –80 –100 –120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) 0 INPUT NORMAL MODE REJECTION (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2496 F18 VCC = 5V VREF = 5V VIN(CM) = 2.5V TA = 25°C 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2496 F20 Figure 18. Input Normal Mode Rejection at fS = 256 • fN Figure 20. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (60Hz Notch) 2496fa 28 LTC2496 APPLICATIONS INFORMATION A change in fEOSC results in a proportional change in the internal notch position. This leads to reduced differential mode rejection of line frequencies. The common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the IN+ and IN– pins will continue to reject line frequency noise. An increase in fEOSC also increases the effective dynamic input and reference current. External RC networks will 50 40 30 20 10 0 TA = 25°C –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F21 continue to have zero differential input current, but the time required for complete settling (580ns for fEOSC = 307.2kHz) is reduced, proportionally. Once the external oscillator frequency is increased above 1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade. This results in larger offset errors, full-scale errors, and decreased resolution, see Figures 21 to 28. OFFSET ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) 2500 TA = 85°C 2000 1500 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F22 –FS ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK TA = 85°C 3500 3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 –500 –1000 TA = 25°C TA = 85°C –2000 –1500 TA = 25°C –2500 –3000 VIN(CM) = VREF(CM) VCC = VREF = 5V FO = EXT CLOCK 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F23 –3500 Figure 21. Offset Error vs Output Data Rate and Temperature Figure 22. +FS Error vs Output Data Rate and Temperature Figure 23.–FS Error vs Output Data Rate and Temperature 24 TA = 25°C 22 TA = 85°C RESOLUTION (BITS) RESOLUTION (BITS) 20 18 TA = 25°C, 85°C 16 14 12 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F24 22 20 18 16 TA = 85°C 14 VIN(CM) = VREF(CM) 12 VCC = VREF = 5V FO = EXT CLOCK RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F25 20 OFFSET ERROR (ppm OF VREF) VIN(CM) = VREF(CM) VIN = 0V 15 FO = EXT CLOCK TA = 25°C 10 VCC = VREF = 5V 5 0 –5 VCC = 5V, VREF = 2.5V TA = 25°C VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V FO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F26 Figure 24. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature Figure 25. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature Figure 26. Offset Error vs Output Data Rate and Reference Voltage 2496fa 29 LTC2496 APPLICATIONS INFORMATION 24 VCC = VREF = 5V 22 RESOLUTION (BITS) RESOLUTION (BITS) 20 18 VCC = 5V, VREF = 5V, 2.5V 16 14 VIN(CM) = VREF(CM) VIN = 0V FO = EXT CLOCK 12 T = 25°C A RES = LOG 2 (VREF/NOISERMS) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F27 22 20 VCC = 5V, VREF = 2.5V 18 16 VCC = 5V, VREF = 2.5V 14 VIN(CM) = VREF(CM) VIN = 0V REF– = GND 12 FO = EXT CLOCK TA = 25°C RES = LOG 2 (VREF/INLMAX) 10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2496 F28 VCC = VREF = 5V Figure 27. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Reference Voltage Figure 28. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Reference Voltage 2496fa 30 LTC2496 PACKAGE DESCRIPTION UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 ± 0.05 5.50 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 3.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.15 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 0.00 – 0.05 3.15 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 37 38 0.40 ± 0.10 1 2 PIN 1 TOP MARK (SEE NOTE 6) 7.00 ± 0.10 (2 SIDES) 5.15 ± 0.10 (2 SIDES) 0.40 ± 0.10 0.200 REF 0.25 ± 0.05 0.75 ± 0.05 0.200 REF 0.00 – 0.05 0.50 BSC R = 0.115 TYP (UH) QFN 0205 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2496fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2496 TYPICAL APPLICATION External Buffers Provide High Impedance Inputs and Amplifier Offsets are Automatically Cancelled. LTC2496 ΔΣ ADC WITH EASY DRIVE INPUTS SDI SCK SDO CS ANALOG 17 INPUTS INPUT MUX MUXOUTN 2 MUXOUTP – 1/2 LT6078 1 1k 0.1μF 3 + 6 – 1/2 LT6078 7 1k 0.1μF 2496 TA02 5 + RELATED PARTS PART NUMBER LT1236A-5 LT1460 LT1790 LTC2400 LTC2410 DESCRIPTION Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT-23 Low Dropout Reference Family 24-Bit, No Latency ΔΣ ADC in SO-8 24-Bit, No Latency ΔΣ ADC with Differential Inputs COMMENTS 0.05% Max Initial Accuracy, 5ppm/°C Drift 0.075% Max Initial Accuracy, 10ppm/°C Max Drift 0.05% Max Initial Accuracy, 10ppm/°C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA 0.8μVRMS Noise, 2ppm INL 1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection (LTC2411-1) Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise Pin Compatible with the LTC2410 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs Pin Compatible with LTC2482/LTC2484 Pin Compatible with LTC2483/LTC2485 Pin Compatible with LTC2480/LTC2484 Pin Compatible with LTC2481/LTC2485 Pin Compatible with LTC2480/LTC2482 Pin Compatible with LTC2481/LTC2483 Pin Compatible with LTC2496/LTC2449 2496fa LTC2411/LTC2411-1 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP LTC2413 LTC2414/LTC2418 LTC2440 LTC2480 LTC2481 LTC2482 LTC2483 LTC2484 LTC2485 LTC2498 24-Bit, No Latency ΔΣ ADC with Differential Inputs 8-/16-Channel 24-Bit, No Latency ΔΣ ADCs High Speed, Low Noise 24-Bit ΔΣ ADC 16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, Programmable Gain, and Temperature Sensor 16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, I2C Interface, Programmable Gain, and Temperature Sensor 16-Bit ΔΣ ADC with Easy Drive Inputs 16-Bit ΔΣ ADC with Easy Drive Inputs, and I2C Interface 24-Bit ΔΣ ADC with Easy Drive Inputs 24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface, and Temperature Sensor 24-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current Cancellation LTC2415/LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0407 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006