LTC2606CDD

LTC2606/LTC2616/LTC2626 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface FEATURES ■ DESCRIPTIO ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Smallest Pin-Compatible Single DACs: LTC2606: 16 Bits LTC2616: 14 Bits LTC2626: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature 27 Selectable Addresses 400kHz I2CTM Interface Wide 2.7V to 5.5V Supply Range Low Power Operation: 270µA at 3V Power Down to 1µA, Max High Rail-to-Rail Output Drive (± 15mA, Min) Double-Buffered Data Latches Asynchronous DAC Update Pin LTC2606/LTC2616/LTC2626: Power-On Reset to Zero Scale LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset to Midscale Tiny (3mm × 3mm) 10-Lead DFN Package The LTC®2606/LTC2616/LTC2626 are single 16-, 14and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a 10-lead DFN package. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive and load regulation in single-supply, voltage-output DACs. The parts use a 2-wire, I2C compatible serial interface. The LTC2606/LTC2616/LTC2626 operate in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). An asynchronous DAC update pin (LDAC) is also included. The LTC2606/LTC2616/LTC2626 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place. The power-on reset circuit resets the LTC2606-1/LTC2616-1/ LTC2626-1 to midscale. The voltage outputs stay at midscale until a valid write and update take place. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment BLOCK DIAGRA SCL 9 VCC 6 REF 3 INPUT REGISTER I2C INTERFACE SDA DAC REGISTER 16-BIT DAC VOUT 7 2 CONTROL LOGIC DNL (LSB) 4 5 1 CA0 CA1 CA2 I2C ADDRESS DECODE LDAC 10 GND 8 2606 BD U Differential Nonlinearity (LTC2606) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2606 G02 W U VCC = 5V VREF = 4.096V 26061626f 1 LTC2606/LTC2616/LTC2626 ABSOLUTE AXI U RATI GS (Note 1) Operating Temperature Range: LTC2606C/LTC2616C/LTC2626C LTC2606-1C/LTC2616-1C/LTC2626-1C ... 0°C to 70°C LTC2606I/LTC2616I/LTC2626I LTC2606-1I/LTC2616-1I/LTC2626-1I .. – 40°C to 85°C Any Pin to GND ........................................... – 0.3V to 6V Any Pin to VCC .............................................– 6V to 0.3V Maximum Junction Temperature ......................... 125°C Storage Temperature Range ................ – 65°C to 125°C Lead Temperature (Soldering, 10 sec)................ 300°C PACKAGE/ORDER I FOR ATIO TOP VIEW CA2 SDA SCL CA0 CA1 1 2 3 4 5 11 10 LDAC 9 VCC 8 GND 7 VOUT 6 REF ORDER PART NUMBER LTC2606CDD LTC2606IDD LTC2606CDD-1 LTC2606IDD-1 DD PART MARKING LAJX LAJW DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL Differential Nonlinearity INL Integral Nonlinearity Load Regulation CONDITIONS ● ELECTRICAL CHARACTERISTICS ZSE VOS GE Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient (Note 2) (Note 2) (Note 2) VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.7V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking Code = 0 (Note 5) 2 U U W WW U W ORDER PART NUMBER LTC2616CDD LTC2616IDD LTC2616CDD-1 LTC2616IDD-1 DD PART MARKING LBPQ LBPR ORDER PART NUMBER LTC2626CDD LTC2626IDD LTC2626CDD-1 LTC2626IDD-1 DD PART MARKING LBPS LBPT LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX 12 12 ±1 ±0.5 ±4 14 14 ±4 0.1 0.2 0.2 0.4 1 ±1 ±5 ±1 ± 16 0.5 0.5 1 1 9 ±9 16 16 ± 14 0.5 0.7 0.9 1.5 1 ±1 ±5 ±1 ± 64 2 2 4 4 9 ±9 UNITS Bits Bits LSB LSB LSB/mA LSB/mA LSB/mA LSB/mA mV mV µV/°C %FSR ppm/°C ● ● ● ● ● ● ● ● ● 0.025 0.125 0.05 0.125 0.05 0.1 1 ±1 ±5 0.25 0.25 9 ±9 ● ±0.1 ±0.7 ±8.5 ±0.1 ±0.7 ±8.5 ±0.1 ±0.7 ±8.5 26061626f LTC2606/LTC2616/LTC2626 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. (Note 11) SYMBOL PSR ROUT ISC PARAMETER Power Supply Rejection DC Output Impedance Short-Circuit Output Current CONDITIONS VCC = ±10% VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA VREF = VCC = 2.7V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.7V, VREF = 2.7V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN TYP –81 0.05 0.06 MAX 0.15 0.15 60 60 50 50 VCC 160 1 5.5 0.5 0.4 1 1 0.3VCC UNITS dB Ω Ω mA mA mA mA V kΩ pF µA V mA mA µA µA V V 15 15 7.5 7.5 0 88 34 36 22 29 Reference Input Input Voltage Range Resistance Capacitance IREF Reference Current, Power Down Mode Power Supply VCC Positive Supply Voltage ICC Supply Current Normal Mode DAC Powered Down For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) DAC Powered Down (Note 3) VCC = 5V DAC Powered Down (Note 3) VCC = 3V ● ● ● ● ● ● ● ● 124 15 0.001 2.7 0.340 0.27 0.35 0.10 –0.5 0.7VCC Digital I/O (Note 11) VIL Low Level Input Voltage (SDA and SCL) VIH High Level Input Voltage (SDA and SCL) VIL(LDAC) Low Level Input Voltage (LDAC) VIH(LDAC) VIL(CAn) VIH(CAn) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAX High Level Input Voltage (LDAC) Low Level Input Voltage on CAn (n = 0, 1, 2) High Level Input Voltage on CAn (n = 0, 1, 2) Resistance from CAn (n = 0, 1, 2) to VCC to Set CAn = VCC Resistance from CAn (n = 0, 1, 2) to GND to Set CAn = GND Resistance from CAn (n = 0, 1, 2) to VCC or GND to Set CAn = Float Low Level Output Voltage Output Fall Time Pulse Width of Spikes Suppressed by Input Filter Input Leakage I/O Pin Capacitance Capacitive Load for Each Bus Line External Capacitive Load on Address Pins CAn (n = 0, 1, 2) (Note 8) VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current = 3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 9) ● ● ● ● ● ● ● ● ● ● ● 0.8 0.6 2.4 2.0 0.15VCC 0.85VCC 10 10 2 0.4 250 50 1 10 400 10 V V V V V V kΩ kΩ MΩ V ns ns µA pF pF pF 26061626f 0 ● 20 + 0.1CB ● 0 0.1VCC ≤ VIN ≤ 0.9VCC ● ● ● ● 3 LTC2606/LTC2616/LTC2626 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER AC Performance tS Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) 7 7 9 2.7 4.8 0.75 1000 12 180 120 100 15 7 9 10 2.7 4.8 5.2 0.75 1000 12 180 120 100 15 µs µs µs µs µs µs V/µs pF nV • s kHz nV/√Hz nV/√Hz µVP-P CONDITIONS LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS Settling Time for 1LSB Step (Note 7) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise 2.7 0.75 1000 At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz 12 180 120 100 15 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11) SYMBOL PARAMETER VCC = 2.7V to 5.5V fSCL SCL Clock Frequency tHD(STA) Hold Time (Repeated) Start Condition tLOW Low Period of the SCL Clock Pin tHIGH High Period of the SCL Clock Pin tSU(STA) Set-Up Time for a Repeated Start Condition tHD(DAT) Data Hold Time tSU(DAT) Data Set-Up Time tr Rise Time of Both SDA and SCL Signals tf Fall Time of Both SDA and SCL Signals tSU(STO) Set-Up Time for Stop Condition tBUF Bus Free Time Between a Stop and Start Condition t1 Falling Edge of 9th Clock of the 3rd Input Byte to LDAC High or Low Transition t2 LDAC Low Pulse Width CONDITIONS ● ● ● ● ● ● ● TI I G CHARACTERISTICS Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: Guaranteed by design and not production tested. Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1), code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at full scale. 4 UW MIN 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 400 20 TYP MAX 400 UNITS kHz µs µs µs µs µs ns ns ns µs µs ns ns 0.9 300 300 (Note 9) (Note 9) ● ● ● ● ● ● Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND. Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale and half scale – 1. Load is 2k in parallel with 200pF to GND. Note 8: Maximum VIH = VCC(MAX) + 0.5V Note 9: CB = capacitance of one bus line in pF. Note 10: All values refer to VIH(MIN) and VIL(MAX) levels. Note 11: These specifications apply to LTC2606/LTC2606-1, LTC2616/LTC2616-1, LTC2626/LTC2626-1. 26061626f LTC2606/LTC2616/LTC2626 TYPICAL PERFOR A CE CHARACTERISTICS LTC2606 Integral Nonlinearity (INL) 32 24 16 DNL (LSB) INL (LSB) 8 0 –8 –16 –24 –32 0 16384 32768 CODE 49152 65535 2606 G01 VCC = 5V VREF = 4.096V 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2606 G02 INL (LSB) DNL vs Temperature 1.0 0.8 0.6 16 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 –16 –0.6 –0.8 –1.0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –24 –32 DNL (NEG) DNL (POS) INL (LSB) VCC = 5V VREF = 4.096V 0 –8 INL (NEG) DNL (LSB) Settling to ±1LSB VOUT 100µV/DIV SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE 9.7µs VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS UW 2606 G04 Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 0.2 16 8 0 –8 –16 –24 VCC = 5V VREF = 4.096V 32 24 INL vs Temperature VCC = 5V VREF = 4.096V INL (POS) INL (NEG) –32 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2606 G03 INL vs VREF 32 24 VCC = 5.5V 1.5 1.0 INL (POS) 0.5 DNL vs VREF VCC = 5.5V 8 DNL (POS) 0 DNL (NEG) –0.5 –1.0 –1.5 0 1 2 3 VREF (V) 4 5 2606 G05 0 1 2 3 VREF (V) 4 5 2606 G06 Settling of Full-Scale Step VOUT 100µV/DIV SCR 2V/DIV 12.3µs 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV 2606 G07 5µs/DIV SETTLING TO ±1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS 2606 G08 26061626f 5 LTC2606/LTC2616/LTC2626 TYPICAL PERFOR A CE CHARACTERISTICS LTC2616 Integral Nonlinearity (INL) 8 6 4 0.4 DNL (LSB) INL (LSB) 2 0 –2 –4 –0.6 –6 –8 0 4096 8192 CODE 12288 16383 2606 G09 VCC = 5V VREF = 4.096V LTC2626 Integral Nonlinearity (INL) 2.0 1.5 1.0 0.4 DNL (LSB) VCC = 5V VREF = 4.096V INL (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 1024 2048 CODE 3072 4095 2606 G12 6 UW Differential Nonlinearity (DNL) 1.0 0.8 0.6 VOUT 100µV/DIV SCL 2V/DIV Settling to ±1LSB VCC = 5V VREF = 4.096V 0.2 0 –0.2 –0.4 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 8.9µs 2606 G11 –0.8 –1.0 0 4096 8192 CODE 12288 16383 2606 G10 Differential Nonlinearity (DNL) 1.0 0.8 0.6 VCC = 5V VREF = 4.096V Settling to ±1LSB 6.8µs VOUT 1mV/DIV 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2606 G14 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE 3072 4095 2606 G13 SCL 2V/DIV 26061626f LTC2606/LTC2616/LTC2626 TYPICAL PERFOR A CE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Current Limiting 0.10 0.08 0.06 0.04 1.0 CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V ∆VOUT (mV) OFFSET ERROR (mV) 25 35 ∆VOUT (V) 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 –40 –30 –20 –10 0 10 IOUT (mA) 20 30 40 VREF = VCC = 3V VREF = VCC = 5V Zero-Scale Error vs Temperature 3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 –50 0.4 0.3 OFFSET ERROR (mV) –30 –10 10 30 50 TEMPERATURE (°C) Gain Error vs VCC 0.4 0.3 0.2 GAIN ERROR (%FSR) 0.1 ICC (nA) 0 –0.1 –0.2 –0.3 –0.4 2.5 3 UW 70 2606 G20 Load Regulation CODE = MIDSCALE 3 2 1 0 –1 –2 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –35 –25 –15 –5 5 IOUT (mA) 15 VREF = VCC = 3V VREF = VCC = 5V Offset Error vs Temperature –3 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2606 G17 2606 G18 2606 G19 Gain Error vs Temperature 3 2 1 0 –1 –2 Offset Error vs VCC 0.2 0.1 0 –0.1 –0.2 –0.3 90 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –3 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 2606 G22 2606 G21 ICC Shutdown vs VCC 450 400 350 300 250 200 150 100 50 3.5 4 VCC (V) 4.5 5 5.5 2606 G23 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 2606 G24 26061626f 7 LTC2606/LTC2616/LTC2626 TYPICAL PERFOR A CE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Large-Signal Response Midscale Glitch Impulse TRANSITION FROM MS-1 TO MS VOUT 0.5V/DIV VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5µs/DIV 2606 G25 Headroom at Rails vs Output Current 5.0 4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 456 IOUT (mA) 7 8 9 10 3V SINKING 5V SINKING VCC VOUT Supply Current vs Logic Voltage 650 600 550 500 ICC (µA) 450 400 350 300 – 250 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5 ICC (µA) VCC = 5V SWEEP LDAC 0V TO VCC 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 8 UW Power-On Reset Glitch VOUT 10mV/DIV 9TH CLOCK OF 3RD DATA BYTE TRANSITION FROM MS TO MS-1 VCC 1V/DIV 4mV PEAK VOUT 10mV/DIV SCL 2V/DIV 2.5µs/DIV 2606 G26 250µs/DIV 2606 G27 Power-On Reset to Midscale VREF = VCC 5V SOURCING 3V SOURCING 1V/DIV 500µs/DIV 2606 G29 2606 G28 Supply Current vs Logic Voltage VCC = 5V SWEEP SCL AND SDA 0V TO VCC AND VCC TO 0V HYSTERESIS 370mV 0 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 5 2606 G30 2606 G31 26061626f LTC2606/LTC2616/LTC2626 TYPICAL PERFOR A CE CHARACTERISTICS LTC2606/LTC2616/LTC2626 Multiplying Bandwidth 0 –3 –6 –9 –12 –15 VOUT 10µV/DIV dB –18 –21 –24 –27 –30 –33 –36 VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 1k 10k 100k FREQUENCY (Hz) 1M 2606 G32 Short-Circuit Output Current vs VOUT (Sinking) 0mA 10mA/DIV 0mA VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 1V/DIV 2606 G18 10mA/DIV UW Output Voltage Noise, 0.1Hz to 10Hz 0 1 2 3 456 SECONDS 7 8 9 10 2606 G33 Short-Circuit Output Current vs VOUT (Sourcing) VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 1V/DIV 2606 G19 26061626f 9 LTC2606/LTC2616/LTC2626 PIN FUNCTIONS CA2 (Pin 1): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. SCL (Pin 3): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. CA0 (Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). CA1 (Pin 5): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC. VOUT (Pin 7): DAC Analog Voltage Output. The output range is 0V to VREF. GND (Pin 8): Analog Ground. VCC (Pin 9): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. LDAC (Pin 10): Asynchronous DAC Update. A falling edge on this input after four bytes have been written into the part immediately updates the DAC register with the contents of the input register. A low on this input without a complete 32-bit (four bytes including the slave address) data write transfer to the part does not update the DAC output. Software power-down is disabled when LDAC is low. Exposed Pad (Pin 11): Ground. Must be soldered to PCB ground. 10 U U U 26061626f LTC2606/LTC2616/LTC2626 BLOCK DIAGRA W 9 VCC SCL INPUT REGISTER I2C INTERFACE SDA 2 CONTROL LOGIC DAC REGISTER 16-BIT DAC 6 REF VOUT 7 I2C ADDRESS DECODE LDAC 10 GND 8 2606 BD 3 4 5 1 CA0 CA1 CA2 TEST CIRCUITS Test Circuit 1 Test Circuit 2 VDD 100Ω CAn VIH(CAn)/VIL(CAn) RINH/RINL/RINF CAn GND 2606 TC 26061626f 11 SDA tf tLOW tr SCL tHD(STA) tHD(DAT) tHIGH S P S 2606 F01 tSU(DAT) tHD(STA) tSP tr tBUF tf TI I G DIAGRA S ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS LTC2606/LTC2616/LTC2626 Figure 1 SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE X X X ACK ACK A0 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 ACK C3 C2 C1 C0 X 3RD DATA BYTE ACK START SDA A6 A5 A4 A3 A2 A1 SCL 1 2 3 4 5 6 9 1 2 3 4 5 6 7 8 9 t1 t2 2606 F02A LDAC Figure 2a 9TH CLOCK OF 3RD DATA BYTE SCL t1 LDAC 2606 F02b Figure 2b W S tSU(STA) tSU(STO) UW 12 26061626f LTC2606/LTC2616/LTC2626 OPERATIO Power-On Reset The LTC2606/LTC2616/LTC2626 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. The LTC2606-1/ LTC2616-1/LTC2626-1 set the voltage outputs to midscale when power is first applied. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2606/ LTC2616/LTC2626 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range – 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 9) is in transition. Transfer Function The digital-to-analog transfer function is: ⎛k⎞ VOUT(IDEAL) = ⎜ N ⎟ VREF ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). Serial Digital Interface The LTC2606/LTC2616/LTC2626 communicate with a host using the standard 2-wire I2C interface. The Timing Diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the U power supply and can be obtained from the I 2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2606/LTC2616/LTC2626 are receive-only (slave) devices. The master can write to the LTC2606/LTC2616/ LTC2626. The LTC2606/LTC2616/LTC2626 do not respond to a read from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA bus line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2606/LTC2616/LTC2626 respond to a write by a master in this manner. The LTC2606/LTC2616/ LTC2626 do not acknowledge a read (retains SDA HIGH during the period of the Acknowledge clock pulse). Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC, GND or float. This results in 27 selectable addresses for the part. The slave address assignments are shown in Table 1. 26061626f 13 LTC2606/LTC2616/LTC2626 OPERATIO CA2 GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT VCC VCC VCC VCC VCC VCC VCC VCC VCC CA1 GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC Table 1. Slave Address Map CA0 GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC A6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A4 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GLOBAL ADDRESS In addition to the address selected by the address pins, the parts also respond to a global address. This address allows a common write to all LTC2606, LTC2616 and LTC2626 parts to be accomplished with one 3-byte write transaction on the I2C bus. The global address is a 7-bit on-chip hardwired address and is not selectable by CA0, CA1 and CA2. The addresses corresponding to the states of CA0, CA1 and CA2 and the global address are shown in Table 1. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. 14 U Write Word Protocol The master initiates communication with the LTC2606/ LTC2616/LTC2626 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2606/ LTC2616/LTC2626 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by CA0, CA1 and CA2) or the global address. The master then transmits three bytes of data. The LTC2606/LTC2616/LTC2626 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2606/LTC2616/LTC2626 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2606/LTC2616/LTC2626 do not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command and four don’t care bits. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16-, 14- or 12-bit input code, MSB to LSB, followed by 0, 2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626 respectively). A typical LTC2606 write transaction is shown in Figure 4. The command assignments (C3-C0) are shown in Table 2. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register and converted to an analog voltage at the DAC output. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever the DAC output is not needed. When in power-down, the buffer amplifier, bias circuit and reference input is disabled and draws essentially zero current. The DAC output is put into 26061626f LTC2606/LTC2616/LTC2626 OPERATIO Table 2 COMMAND* C3 C2 C1 C0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 1 Write to Input Register Update (Power Up) DAC Register Write to and Update (Power Up) Power Down No Operation *Command codes not shown are reserved and should not be used. a high impedance state, and the output pin is passively pulled to ground through 90k resistors. Input- and DACregister contents are not disturbed during power-down. The DAC channel can be put into power-down mode by using command 0100b. The 16-bit data word is ignored. The supply and reference currents are reduced to almost zero when the DAC is powered down; the effective resistance at REF becomes a high impedance input (typically > 1GΩ). Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 2 or performing an asychronous update (LDAC) as described in the next section. The DAC is powered up as its voltage output is updated. When the DAC in powereddown state is powered up and updated, normal settling is delayed. The main bias generation circuit block has been U Write Word Protocol for LTC2606/LTC2616/LTC1626 S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE INPUT WORD A 3RD DATA BYTE A P Input Word (LTC2606) C3 C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 2ND DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 D0 1ST DATA BYTE 3RD DATA BYTE Input Word (LTC2616) C3 C2 C1 C0 X X X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Input Word (LTC2626) C3 C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 2606 F03 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Figure 3 automatically shut down in addition to the DAC amplifier and reference input and so the power up delay time is 12µs (for VCC = 5V) or 30µs (for VCC = 3V) Asynchronous DAC Update Using LDAC In addition to the update commands shown in Table 2, the LDAC pin asynchronously updates the DAC register with the contents of the input register. Asynchronous update is disabled when the input word is being clocked into the part. If a complete input word has been written to the part, a low on the LDAC pin causes the DAC register to be updated with the contents of the input register. If the input word is being written to the part, a low going pulse on the LDAC pin before the completion of three bytes of data powers up the DAC but does not cause the output to be updated. If LDAC remains low after a complete input word has been written to the part, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC output is updated. The DAC is powered up when LDAC is taken low, independent of any activity on the I2C bus. If LDAC is low at the falling edge of the 9th clock of the 3rd byte of data, it inhibits any software power-down command that was specified in the input word. 26061626f 15 LTC2606/LTC2616/LTC2626 OPERATIO Voltage Output The rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers’ DC output impedance is 0.050Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25Ω • 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation performance is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away 16 U from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.050Ω ). Note that the LTC2606/LTC2616/ LTC2626 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 26061626f SLAVE ADDRESS COMMAND MS DATA X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 A0 WR C3 C2 C1 C0 X LS DATA D5 D4 D3 D2 D1 D0 STOP A6 A5 A4 A3 A2 A1 START A0 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ACK ACK ACK C3 C2 C1 C0 X X X X ACK SDA A6 A5 A4 A3 A2 A1 SCL 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 2606 F05 VOUT X = DON’T CARE Figure 4. Typical LTC2606 Input Waveform—Programming DAC Output for Full Scale U OPERATIO LTC2606/LTC2616/LTC2626 17 26061626f VREF = VCC POSITIVE FSE LTC2606/LTC2616/LTC2626 VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) 2606 F05 OUTPUT VOLTAGE 0 32, 768 INPUT CODE 65, 535 (a) 0V NEGATIVE OFFSET INPUT CODE (b) Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale U OPERATIO 18 26061626f LTC2606/LTC2616/LTC2626 PACKAGE DESCRIPTIO U DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 ± 0.10 10 3.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 5) 5 0.200 REF 0.75 ± 0.05 2.38 ± 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1 0.25 ± 0.05 0.50 BSC 1.65 ± 0.10 (2 SIDES) (DD10) DFN 0403 3.50 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) 0.00 – 0.05 26061626f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2606/LTC2616/LTC2626 TYPICAL APPLICATIO Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters CA0 I C BUS CA1 CA2 2 10 4 2 3 5 1 9 6 LDAC VCC VREF CA0 SDA LTC2606 VOUT SCL CA1 GND CA2 8 RELATED PARTS PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610 LTC2620 LTC2601/LTC2611 LTC2621 LTC2602/LTC2612 LTC2622 LTC2604/LTC2614 LTC2624 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DACs with Serial Interface in SO-8 Parallel 5V/3V 16-Bit VOUT DACs Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2µs for 10V Step 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U 5V 0.1µF VREF 1V TO 5V 2 FSSET 7 100Ω 7.5k 100pF DAC OUTPUT ZSSET GND 5 6 2606 TA01 5V 0.1µF 1 VCC 3 VIN LTC2421 9 SCK 8 SDO 7 CS 10 FO SPI BUS 26061626f LT/TP 1204 1K • PRINTED IN THE USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004