LTC2610IGNPBF

FEATURES n LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTION The LTC®2600/LTC2610/LTC2620 are octal 16-, 14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP and 20-lead 4mm × 5mm QFN packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. The parts use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisychain capability and a hardware CLR function are included. The LTC2600/LTC2610/LTC2620 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero-scale; and after power-up, they stay at zero-scale until a valid write and update take place. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n n n n n n n n n Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.5V Supply Range Low Power Operation: 250μA per DAC at 3V Individual Channel Power-Down to 1μA, Max Ultralow Crosstalk Between DACs ( 1GΩ) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay is 5μs. If, on the other hand, all eight DACs are powered down, then the master bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12μs for VCC = 5V, 30μs for VCC = 3V. Voltage Outputs Each of the 8 rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers’ DC output impedance is 0.025Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25Ω • 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF . Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance to just 0.005Ω. 2600fe 14 LTC2600/LTC2610/LTC2620 OPERATION The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.025Ω), and will degrade DC crosstalk. Note that the LTC2600/LTC2610/LTC2620 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2600fe 15 OPERATION LTC2600/LTC2610/LTC2620 16 1 2 7 13 14 17 D7 YYYY F02a CS/LD 3 4 10 21 D3 D2 D1 D0 23 D14 DATA WORD D13 D12 D11 D10 D9 D8 D6 D5 D4 11 12 18 24 16 20 22 C0 ADDRESS WORD A3 A2 A1 A0 D15 5 6 8 9 15 19 C1 SCK C2 COMMAND WORD SDI C3 24-BIT INPUT WORD Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word). LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits; LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits CS/LD 6 7 13 14 17 D15 D14 D13 D12 D11 D10 A2 ADDRESS WORD C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 A1 A0 A3 X COMMAND WORD X X X C3 C2 C1 X C3 C2 C1 C0 8 9 10 21 11 12 18 16 20 15 19 X 22 23 D9 24 D8 25 D7 DATA WORD D8 D7 D6 D5 D4 D3 D2 D1 D0 26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0 SCK 1 2 3 4 5 SDI X X X X X DON’T CARE SDO X X X X X PREVIOUS 32-BIT INPUT WORD t1 t2 SCK SDI SDO 17 t3 D15 t8 PREVIOUS D15 PREVIOUS D14 t4 D14 18 CURRENT 32-BIT INPUT WORD YYYY F02b Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation). LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits; LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits 2600fe LTC2600/LTC2610/LTC2620 OPERATION VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 32, 768 INPUT CODE (a) 65, 535 0V NEGATIVE OFFSET INPUT CODE (b) 2600 F03 Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0165 ± .0015 .0250 BSC 1 .015 ± .004 × 45° (0.38 ± 0.10) .0532 – .0688 (1.35 – 1.75) 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) RECOMMENDED SOLDER PAD LAYOUT .007 – .0098 (0.178 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 2600fe 17 LTC2600/LTC2610/LTC2620 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 0.05 4.50 0.05 3.10 1.50 REF 0.05 2.65 0.05 3.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 1.50 REF 19 20 0.40 0.10 PIN 1 NOTCH R = 0.20 OR C = 0.35 1 2 5.00 0.10 (2 SIDES) 2.50 REF 3.65 0.10 2.65 0.10 (UFD20) QFN 0506 REV B 0.200 REF 0.00 – 0.05 R = 0.115 TYP 0.25 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2600fe 18 LTC2600/LTC2610/LTC2620 REVISION HISTORY REV D E DATE 03/10 05/10 DESCRIPTION Revise GN Part Markings in Order Information Changed “No Connect” pins to “Do Not Connect” in Pin Configuration and Pin Functions sections (Revision history begins at Rev D) PAGE NUMBER 2 2, 10 2600fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2600/LTC2610/LTC2620 TYPICAL APPLICATION Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428 1 TP1 4 3 2 1 VSS SDA A2 A1 A0 SCL WP VCC 5 6 7 8 C3 0.1μF 1 VCC TP2 R1, R3, R4 R1 are 4.99k, 1% R3 R4 VREF C1 0.1μF R2 7.5k 11 CLR C2 0.1μF VCC VOUTA VOUTB SCK CS 14 12 10 8 6 4 2 + + + + + + + + + + + + + + 13 11 9 7 5 3 1 8 7 9 10 MOSI MISO 1 VIN VOUTC SCK LS/LD SDI SDO GND 1 TP16 U2 LTC2600CGN VOUTD VOUTE VOUTF VOUTG VOUTH 16 2 3 4 5 12 13 14 15 1 1 1 1 1 1 1 1 1 1 VCC 6 REF U1 24LC025 TP3 DAC A TP4 DAC B TP5 DAC C TP6 DAC D TP7 DAC E TP8 DAC F TP9 DAC G TP10 DAC H C10 100pF 7 MUXOUT TP14 GND TP15 GND VREF VCC VCC 5V J1 HD2X7 R5 7.5k R8 22Ω 4 ADCIN 3 FSSET C4 0.1μF C5 0.1μF JP1 ON/OFF DISABLE ADC 3 2 2 8 1 VCC VCC VIN 2 U4 LT1236ACS8-5 VIN GND C6 0.1μF 4 VOUT 6 1 5V 4.096V 2 3 JP2 VREF VREF 9 1 C7 4.7μF 6.3V TP11 VREF 10 11 12 13 14 15 6 1 5VREF C8 REGULATOR 1μF 16V 2 3 JP3 VCC 5V VCC 1 1 TP12 VCC TP13 GND 17 5 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ZSSET CSADC CSMUX 4-/8-CHANNEL MUX + 20-BIT ADC – LTC2424/LTC2428 SCK CLK DIN SD0 FO GND GND GND GND GND GND GND 6 16 18 22 27 28 23 20 25 19 21 24 26 R7 7.5k R6 7.5k CS SCK U5 LT1461ACS8-4 2 3 C9 0.1μF VIN SHDN GND 4 VOUT 1 U3 LTC2428CG RELATED PARTS PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2μs for 10V Step 2600fe 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0510 REV E • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003