LTC2629CGN-1

LTC2609/LTC2619/LTC2629 Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface DESCRIPTIO The LTC®2609/LTC2619/LTC2629 are quad 16-, 14- and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a 16-lead SSOP package. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive and load regulation in single-supply, voltage-output DACs. The parts use a 2-wire, I2C compatible serial interface. The LTC2609/LTC2619/LTC2629 operate in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2609/LTC2619/LTC2629 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; after power-up, they stay at zero scale until a valid write and update take place. The power-on reset circuit resets the LTC2609-1/LTC2619-1/ LTC2629-1 to midscale. The voltage outputs stay at midscale until a valid write and update take place. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245. Patent pending. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Smallest Pin-Compatible Quad DACs: LTC2609: 16 Bits LTC2619: 14 Bits LTC2629: 12 Bits Guaranteed Monotonic Over Temperature Separate Reference Inputs 27 Selectable Addresses 400kHz I2C™ Interface Wide 2.7V to 5.5V Supply Range Low Power Operation: 250µA per DAC at 3V Individual Channel Power Down to 1µA (Max) High Rail-to-Rail Output Drive (± 15mA, Min) Ultralow Crosstalk Between DACs (5µV) LTC2609/LTC2619/LTC2629: Power-On Reset to Zero Scale LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset to Midscale Tiny 16-Lead Narrow SSOP Package APPLICATIO S ■ ■ ■ Mobile Communications Process Control and Industrial Automation Automatic Test Equipment and Instrumentation BLOCK DIAGRA REFA VOUTA 3 DAC REGISTER 4 DAC A REFLO 2 INPUT REGISTER GND 1 INPUT REGISTER VCC 16 15 REFD DAC REGISTER DAC D 14 VOUTD 1.0 DAC REGISTER INPUT REGISTER INPUT REGISTER DAC REGISTER VOUTB 5 6 DAC B DAC C 13 VOUTC 12 REFC REFB CONTROL LOGIC DNL (LSB) 32-BIT SHIFT REGISTER 11 CA0 SCL SDA 8 9 I2C INTERFACE ADDRESS DECODE LOGIC 10 CA1 7 CA2 2609 BD U W U Differential Nonlinearity (LTC2609) 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2609 G02 VCC = 5V VREF = 4.096V 26091929f 1 LTC2609/LTC2619/LTC2629 ABSOLUTE AXI U RATI GS (Note 1) Operating Temperature Range: LTC2609C/LTC2619C/LTC2629C LTC2609C-1/LTC2619C-1/LTC2629C-1 ... 0°C to 70°C LTC2609I/LTC2619I/LTC2629I LTC2609I-1/LTC2619I-1/LTC2629I-1 .. – 40°C to 85°C Any Pin to GND ........................................... – 0.3V to 6V Any Pin to VCC .............................................– 6V to 0.3V Maximum Junction Temperature ......................... 125°C Storage Temperature Range ................ – 65°C to 125°C Lead Temperature (Soldering, 10 sec)................ 300°C PACKAGE/ORDER I FOR ATIO TOP VIEW GND REFLO REFA VOUTA VOUTB REFB CA2 SCL 1 2 3 4 5 6 7 8 16 VCC 15 REFD 14 VOUTD 13 VOUTC 12 REFC 11 CA0 10 CA1 9 SDA GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 135°C, θJA = 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER DC Performance Resolution Monotonicity DNL Differential Nonlinearity INL Integral Nonlinearity Load Regulation CONDITIONS ● ELECTRICAL CHARACTERISTICS ZSE VOS GE Zero-Scale Error Offset Error VOS Temperature Coefficient Gain Error Gain Temperature Coefficient (Note 2) (Note 2) (Note 2) VREF = VCC = 5V, Midscale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking VREF = VCC = 2.7V, Midscale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking Code = 0 (Note 4) 2 U U W WW U W ORDER PART NUMBER LTC2609CGN LTC2609CGN-1 LTC2609IGN LTC2609IGN-1 LTC2619CGN LTC2619CGN-1 LTC2619IGN LTC2619IGN-1 LTC2629CGN LTC2629CGN-1 LTC2629IGN LTC2629IGN-1 GN PART MARKING 2609 26091 2609I 2609I1 2619 26191 2619I 2619I1 2629 26291 2629I 2629I1 LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX 12 12 ±1 ± 0.5 ±4 14 14 ±4 0.1 0.1 0.2 0.2 1.5 ±1 ±6 ±0.1 ±3 ±1 ± 16 0.5 0.5 1 1 9 ±9 16 16 ± 16 0.3 0.4 0.7 0.8 1.5 ±1 ±6 ±0.1 ±3 ±1 ± 64 2 2 4 4 9 ±9 UNITS Bits Bits LSB LSB LSB/mA LSB/mA LSB/mA LSB/mA mV mV µV/°C %FSR ppm/°C 26091929f ● ● ● ● ● ● ● ● ● 0.02 0.125 0.02 0.125 0.04 0.05 1.5 ±1 ±6 ±0.1 ±3 0.25 0.25 9 ±9 ● ±0.7 ±0.7 ±0.7 LTC2609/LTC2619/LTC2629 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted. (Note 9) SYMBOL PSR ROUT PARAMETER Power Supply Rejection DC Output Impedance DC Crosstalk (Note 10) CONDITIONS VCC ±10% VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA VREF = VCC = 2.7V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA Due to Full-Scale Output Change (Note 11) Due to Load Current Change Due to Powering Down (Per Channel) VCC = 5.5V, VREF = 5.5V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND VCC = 2.7V, VREF = 2.7V Code: Zero Scale; Forcing Output to VCC Code: Full Scale; Forcing Output to GND Reference Input Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current, Power Down Mode DAC Powered Down Positive Supply Voltage Supply Current For Specified Performance VCC = 5V (Note 3) VCC = 3V (Note 3) DAC Powered Down (Note 3) VCC = 5V DAC Powered Down (Note 3) VCC = 3V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN TYP –80 0.030 0.035 ±5 ±4 ±4 MAX 0.15 0.15 UNITS dB Ω Ω µV µV/mA µV ISC Short-Circuit Output Current 15 15 7.5 7.5 0 88 36 36 22 30 60 60 50 50 VCC mA mA mA mA V kΩ pF µA V mA mA µA µA V V Normal Mode ● 125 14 0.001 160 1 5.5 Power Supply 2.7 1.25 1 0.35 0.15 2 1.6 1 1 0.3VCC 0.7VCC 0.15VCC 0.85VCC 10 10 2 0 0.4 250 50 1 10 400 10 Digital I/O (Note 9) VIL VIH VIL(CAn) VIH(CAn) RINH RINL RINF VOL tOF tSP IIN CIN CB CCAX Low Level Input Voltage (SDA and SCL) High Level Input Voltage (SDA and SCL) Low Level Input Voltage on CAn (n = 0, 1, 2) High Level Input Voltage on CAn (n = 0, 1, 2) Resistance from CAn (n = 0, 1, 2) to VCC to Set CAn = VCC Resistance from CAn (n = 0, 1, 2) to GND to Set CAn = GND Resistance from CAn (n = 0, 1, 2) to VCC or GND to Set CAn = Float Low Level Output Voltage Output Fall Time Pulse Width of Spikes Suppressed by Input Filter Input Leakage I/O Pin Capacitance Capacitive Load for Each Bus Line External Capacitive Load on Address Pins CAn (n = 0, 1, 2) 0.1VCC ≤ VIN ≤ 0.9VCC (Note 12) See Test Circuit 1 See Test Circuit 1 See Test Circuit 2 See Test Circuit 2 See Test Circuit 2 Sink Current = 3mA VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 7) ● ● ● ● ● ● V V kΩ kΩ MΩ V ns ns µA pF pF pF 26091929f ● 20 + 0.1CB ● ● ● ● ● 0 3 LTC2609/LTC2619/LTC2629 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER AC Performance tS Settling Time (Note 5) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) ±0.024% (±1LSB at 12 Bits) ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) 7 7 9 2.7 4.8 0.7 1000 12 180 120 100 15 7 9 10 2.7 4.8 5.2 0.7 1000 12 180 120 100 15 µs µs µs µs µs µs V/µs pF nV • s kHz nV/√Hz nV/√Hz µVP-P CONDITIONS LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS Settling Time for 1LSB Step (Note 6) Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth en Output Voltage Noise Density Output Voltage Noise 2.7 0.7 1000 At Midscale Transition At f = 1kHz At f = 10kHz 0.1Hz to 10Hz 12 180 120 100 15 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9) SYMBOL PARAMETER VCC = 2.7V to 5.5V fSCL SCL Clock Frequency tHD(STA) Hold Time (Repeated) Start Condition tLOW Low Period of the SCL Clock Pin tHIGH High Period of the SCL Clock Pin tSU(STA) Set-Up Time for a Repeated Start Condition tHD(DAT) Data Hold Time tSU(DAT) Data Set-Up Time tr Rise Time of Both SDA and SCL Signals tf Fall Time of Both SDA and SCL Signals tSU(STO) Set-Up Time for Stop Condition tBUF Bus Free Time Between a Stop and Start Condition t1 Falling Edge of 9th Clock of the 3rd Input Byte to LDAC High or Low Transition t2 LDAC Low Pulse Width CONDITIONS ● ● ● ● ● ● ● TI I G CHARACTERISTICS Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 floating. Note 4: Inferred from measurement at code kL (see Note 2) and at full scale. Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND. 4 UW MIN 0 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3 400 20 TYP MAX 400 UNITS kHz µs µs µs µs µs ns ns ns µs µs ns ns 0.9 300 300 (Note 7) (Note 7) ● ● ● ● ● ● Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale and half scale – 1. Load is 2k in parallel with 200pF to GND. Note 7: CB = capacitance of one bus line in pF. Note 8: All values refer to VIH(MIN) and VIL(MAX) levels. Note 9: These specifications apply to LTC2609/LTC2609-1, LTC2619/LTC2619-1, LTC2629/LTC2629-1. Note 10: DC crosstalk is measured with VCC = 5V, REFA = REFB = REFC = REFD = 4.096V, with the measured DAC at midscale, unless otherwise noted. Note 11: RL = 2kΩ to GND or VCC. Note 12: Guaranteed by design and not production tested. 26091929f LTC2609/LTC2619/LTC2629 TYPICAL PERFOR A CE CHARACTERISTICS LTC2609 Integral Nonlinearity (INL) 32 24 16 DNL (LSB) INL (LSB) 8 0 –8 –16 –24 –32 0 16384 32768 CODE 49152 65535 2609 G01 VCC = 5V VREF = 4.096V 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2609 G02 INL (LSB) DNL vs Temperature 1.0 0.8 0.6 16 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 –16 –0.6 –0.8 –1.0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –24 –32 DNL (NEG) DNL (POS) INL (LSB) VCC = 5V VREF = 4.096V 0 –8 INL (NEG) DNL (LSB) Settling to ±1LSB VOUT 100µV/DIV SCL 2V/DIV 9TH CLOCK OF 3RD DATA BYTE VCC = 5V, VREF = 4.096V 1/4 SCALE TO 3/4 SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS UW 2609 G04 Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 0.2 16 8 0 –8 –16 –24 VCC = 5V VREF = 4.096V 32 24 INL vs Temperature VCC = 5V VREF = 4.096V INL (POS) INL (NEG) –32 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2609 G03 INL vs VREF 32 24 VCC = 5.5V 1.5 1.0 INL (POS) 0.5 DNL vs VREF VCC = 5.5V 8 DNL (POS) 0 DNL (NEG) –0.5 –1.0 –1.5 0 1 2 3 VREF (V) 4 5 2609 G05 0 1 2 3 VREF (V) 4 5 2609 G06 Settling of Full-Scale Step 9.7µs VOUT 100µV/DIV SCR 2V/DIV 12.3µs 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV 2609 G07 5µs/DIV SETTLING TO ±1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS 2609 G08 26091929f 5 LTC2609/LTC2619/LTC2629 TYPICAL PERFOR A CE CHARACTERISTICS LTC2619 Integral Nonlinearity (INL) 8 6 4 0.4 DNL (LSB) INL (LSB) 2 0 –2 –4 –0.6 –6 –8 0 4096 8192 CODE 12288 16383 2609 G09 VCC = 5V VREF = 4.096V LTC2629 Integral Nonlinearity (INL) 2.0 1.5 1.0 0.4 DNL (LSB) VCC = 5V VREF = 4.096V INL (LSB) 0.5 0 –0.5 –1.0 –1.5 –2.0 0 1024 2048 CODE 3072 4095 2609 G12 6 UW Differential Nonlinearity (DNL) 1.0 0.8 0.6 VOUT 100µV/DIV SCL 2V/DIV Settling to ±1LSB VCC = 5V VREF = 4.096V 0.2 0 –0.2 –0.4 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV VCC = 5V, VREF = 4.096V 1/4 SCALE TO 3/4 SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 8.9µs 2609 G11 –0.8 –1.0 0 4096 8192 CODE 12288 16383 2609 G10 Differential Nonlinearity (DNL) 1.0 0.8 0.6 VCC = 5V VREF = 4.096V Settling to ±1LSB 6.8µs VOUT 1mV/DIV 9TH CLOCK OF 3RD DATA BYTE 2µs/DIV VCC = 5V, VREF = 4.096V 1/4 SCALE TO 3/4 SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2609 G14 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE 3072 4095 2609 G13 SCL 2V/DIV 26091929f LTC2609/LTC2619/LTC2629 TYPICAL PERFOR A CE CHARACTERISTICS LTC2609/LTC2619/LTC2629 Current Limiting 0.10 0.08 0.06 0.04 ∆VOUT (V) CODE = MIDSCALE VREF = VCC = 5V VREF = VCC = 3V ∆VOUT (mV) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 20 30 40 –1.0 –35 –25 –15 –5 5 IOUT (mA) 15 25 35 VREF = VCC = 3V VREF = VCC = 5V OFFSET ERROR (mV) 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 –40 –30 –20 –10 0 10 IOUT (mA) VREF = VCC = 3V VREF = VCC = 5V Zero-Scale Error vs Temperature 3 2.5 ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 2.0 1.5 1.0 0.5 0 –50 0.4 0.3 OFFSET ERROR (mV) –30 –10 10 30 50 TEMPERATURE (°C) Gain Error vs VCC 0.4 0.3 0.2 GAIN ERROR (%FSR) 0.1 ICC (nA) 0 –0.1 –0.2 –0.3 –0.4 2.5 3 UW 70 2609 G18 Load Regulation 1.0 0.8 0.6 2 1 0 –1 –2 CODE = MIDSCALE 3 Offset Error vs Temperature –3 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2609 G15 2609 G16 2609 G17 Gain Error vs Temperature 3 2 1 0 –1 –2 Offset Error vs VCC 0.2 0.1 0 –0.1 –0.2 –0.3 90 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –3 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 2609 G20 2609 G19 ICC Shutdown vs VCC 450 400 350 300 250 200 150 100 50 3.5 4 VCC (V) 4.5 5 5.5 2609 G21 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 2609 G22 26091929f 7 LTC2609/LTC2619/LTC2629 TYPICAL PERFOR A CE CHARACTERISTICS LTC2609/LTC2619/LTC2629 Large-Signal Response Midscale Glitch Impulse Power-On Reset Glitch VOUT 0.5V/DIV VREF = VCC = 5V 1/4 SCALE TO 3/4 SCALE 2.5µs/DIV 2609 G23 Headroom at Rails vs Output Current 5.0 4.5 4.0 3.5 VOUT (V) 3V SOURCING 5V SOURCING ICC (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 5V SINKING 3V SINKING 456 IOUT (mA) 7 8 9 10 8 UW 2609 G26 TRANSITION FROM MS-1 TO MS VOUT 10mV/DIV 9TH CLOCK OF 3RD DATA BYTE TRANSITION FROM MS TO MS-1 4mV PEAK VOUT 10mV/DIV 2609 G24 VCC 1V/DIV SCL 2V/DIV 2.5µs/DIV 250µs/DIV 2609 G25 Power-On Reset to Midscale 1.9 VREF = VCC Supply Current vs Logic Voltage 1.8 1.7 1.6 1.5 1.4 1.3 VCC = 5V SWEEP SCL AND SDA 0V TO VCC AND VCC TO 0V 1V/DIV VCC VOUT 500µs/DIV 2606 G27 1.2 1.1 1.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 LOGIC VOLTAGE (V) 5 2609 G28 26091929f LTC2609/LTC2619/LTC2629 TYPICAL PERFOR A CE CHARACTERISTICS LTC2609/LTC2619/LTC2629 Multiplying Bandwidth 0 –3 –6 –9 –12 –15 VOUT 10µV/DIV dB –18 –21 –24 –27 –30 –33 –36 VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE 1k 10k 100k FREQUENCY (Hz) 1M 2609 G29 Short-Circuit Output Current vs VOUT (Sinking) 50 VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 10mA/DIV 0 40 10mA/DIV 30 20 10 0 0 1 2 UW 3 1V/DIV Output Voltage Noise, 0.1Hz to 10Hz 0 1 2 3 456 SECONDS 7 8 9 10 2609 G30 Short-Circuit Output Current vs VOUT (Sourcing) VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V –10 –20 –30 –40 4 5 6 2609 G31 –50 0 1 2 3 1V/DIV 4 5 6 2609 G32 26091929f 9 LTC2609/LTC2619/LTC2629 PIN FUNCTIONS GND (Pin 1): Analog Ground. REFLO (Pin 2): Reference Low. The voltage at this pin sets the zero scale (ZS) voltage of all DACs. This pin can be raised up to 1V above ground at VCC = 5V or 100mV above ground at VCC = 3V. REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage Inputs for each DAC. REFx sets the full-scale voltage of the DACs. REFLO ≤ REFx ≤ VCC. VOUTA to VOUTD (Pins 4, 5, 13, 14): DAC Analog Voltage Outputs. The output range is from REFLO to REFx. CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance pin while data is shifted in and is an open-drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (Table 1). VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. 10 U U U 26091929f LTC2609/LTC2619/LTC2629 BLOCK DIAGRA REFA VOUTA 3 INPUT REGISTER DAC REGISTER INPUT REGISTER DAC REGISTER 4 DAC A DAC D INPUT REGISTER DAC REGISTER INPUT REGISTER VOUTB 5 6 DAC B DAC REGISTER REFB SCL SDA 8 9 W REFLO 2 GND 1 VCC 16 15 REFD 14 VOUTD DAC C 13 VOUTC 12 REFC CONTROL LOGIC 32-BIT SHIFT REGISTER 11 CA0 I2C INTERFACE ADDRESS DECODE LOGIC 10 CA1 7 CA2 2609 BD 26091929f 11 LTC2609/LTC2619/LTC2629 TEST CIRCUITS Test Circuit 1 Test Circuit 2 VDD 100Ω CAn VIH(CAn)/VIL(CAn) RINH/RINL/RINF CAn GND 2609 TC TI I G DIAGRA S SDA tf SCL tHD(STA) tSU(STA) tSU(STO) tLOW tr tSU(DAT) tf tHD(STA) tSP tr tBUF S ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS 12 W UW tHD(DAT) tHIGH S P S 2609 F01 Figure 1 26091929f LTC2609/LTC2619/LTC2629 OPERATIO Power-On Reset The LTC2609/LTC2619/LTC2629 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. The LTC2609-1/ LTC2619-1/LTC2629-1 set the voltage outputs to midscale when power is first applied. For some applications, downstream circuits are active during DAC power-up and may be sensitive to nonzero outputs from the DAC during this time. The LTC2609/ LTC2619/LTC2629 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REFx (Pins 3, 6, 12 and 15) should be kept within the range – 0.3V ≤ REFx ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. The REFx pins can be clamped to stay below the maximum voltage by using Schottky diodes as shown in Figure 2, thereby easing sequencing constraints. VCC LTC2609/ LTC2619/ LTC2629 REFA REFB REFC REFD 16 VCC Figure 2. Use of Schottky Diodes for Power Supply Sequencing Transfer Function The digital-to-analog transfer function is: ⎛k⎞ VOUT (IDEAL) = ⎜ ⎟ [REFx – REFLO] + REFLO ⎝ 2N ⎠ U where k is the decimal equivalent of the binary DAC input code, N is the resolution and REFx is the voltage at REFA, REFB, REFC and REFD (Pins 3, 6, 12 and 15). Serial Digital Interface The LTC2609/LTC2619/LTC2629 communicate with a host using the standard 2-wire I2C interface. The Timing Diagram (Figure 1) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2609/LTC2619/LTC2629 are receive-only (slave) devices. The master can write to the LTC2609/LTC2619/ LTC2629. The LTC2609/LTC2619/LTC2629 do not respond to a read from the master. The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) generated by the slave lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA bus line during the Acknowledge clock pulse so that it 3 6 12 15 2609 F02 REFA REFB REFC REFD 26091929f 13 LTC2609/LTC2619/LTC2629 OPERATIO remains a stable LOW during the HIGH period of this clock pulse. The LTC2609/LTC2619/LTC2629 respond to a write by a master in this manner. The LTC2609/LTC2619/ LTC2629 do not acknowledge a read (retains SDA HIGH during the period of the Acknowledge clock pulse). Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part. The pins CA0, CA1 and CA2 can be each set to any one of three states: VCC, GND or float. This results in 27 selectable addresses for the part. The slave address assignments are shown in Table 1. Table 1. Slave Address Map CA2 GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT VCC VCC VCC VCC VCC VCC VCC VCC VCC CA1 GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC GND GND GND FLOAT FLOAT FLOAT VCC VCC VCC CA0 GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC GND FLOAT VCC SA6 SA5 SA4 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GLOBAL ADDRESS 14 U In addition to the address selected by the address pins, the parts also respond to a global address. This address allows a common write to all LTC2609, LTC2619 and LTC2629 parts to be accomplished with one 3-byte write transaction on the I2C bus. The global address is a 7-bit on-chip hardwired address and is not selectable by CA0, CA1 and CA2. The addresses corresponding to the states of CA0, CA1 and CA2 and the global address are shown in Table 1. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. Write Word Protocol The master initiates communication with the LTC2609/ LTC2619/LTC2629 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2609/ LTC2619/LTC2629 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the parts (set by CA0, CA1 and CA2) or the global address. The master then transmits three bytes of data. The LTC2609/LTC2619/LTC2629 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2609/LTC2619/LTC2629 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2609/LTC2619/LTC2629 do not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command and 4-bit DAC address. The next two bytes consist of the 16-bit data word. The 16-bit data word consists of the 16-, 14- or 12-bit input code, MSB to LSB, followed by 0, 2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629 respectively). A typical LTC2609 write transaction is shown in Figure 4. The command (C3-C0) and address (A3-A0) assignments are shown in Table 2. The first four commands in the table consist of write and update operations. A write operation 26091929f LTC2609/LTC2619/LTC2629 OPERATIO Table 2 COMMAND* C3 C2 C1 C0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Write to Input Register n Update (Power Up) DAC Register n Write to Input Register n, Update (Power Up) All n Write to and Update (Power Up) n Power Down n No Operation ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 DAC A DAC B DAC C DAC D All DACs *Command and address codes not shown are reserved and should not be used. loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. U Write Word Protocol for LTC2609/LTC2619/LTC1629 S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE INPUT WORD A 3RD DATA BYTE A P Input Word (LTC2609) C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 2ND DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 D0 1ST DATA BYTE 3RD DATA BYTE Input Word (LTC2619) C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Input Word (LTC2629) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 2609 F03 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Figure 3 Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four outputs are needed. When in power-down, the buffer amplifiers, bias circuits and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to REFLO through individual 90k resistors. Input- and DAC-register contents are not disturbed during power down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply current is reduced by approximately 1/4 for each DAC powered down. The effective resistance at REFx (Pins 3, 6, 12 and 15) are at high impedance (typically > 1GΩ) when the corresponding DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 2. The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than four DACs are in a powered-down state prior to the update command, the power-up delay time is 5µs. If on the other hand, all four DACs are powered down, 26091929f 15 LTC2609/LTC2619/LTC2629 OPERATIO then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power-up delay time is 12µs (for VCC = 5V) or 30µs (for VCC = 3V). Voltage Output The rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 2.7V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifier’s DC output impedance is 0.035Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 30Ω • 1mA = 30mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separate. 16 U The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin functions as a return path for power supply currents in the device and should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. When a zero scale DAC output voltage of zero is desired, REFLO (Pin 2) should be connected to system star ground. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full scale when the REF pins are tied to VCC. If REFx = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 4c. No fullscale limiting can occur if REFx is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 26091929f SLAVE ADDRESS COMMAND MS DATA A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 SA0 WR C3 C2 C1 C0 A3 LS DATA D5 D4 D3 D2 D1 D0 STOP SA6 SA5 SA4 SA3 SA2 SA1 START SA0 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ACK ACK ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK SDA SA6 SA5 SA4 SA3 SA2 SA1 SCL 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 2609 F04 VOUT X = DON’T CARE Figure 4. Typical LTC2609 Input Waveform—Programming DAC Output for Full Scale U OPERATIO LTC2609/LTC2619/LTC2629 17 26091929f REFx = VCC POSITIVE FSE LTC2609/LTC2619/LTC2629 REFx = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE 2609 F05 OUTPUT VOLTAGE 0 32, 768 INPUT CODE 65, 535 (5c) 0V (5a) NEGATIVE OFFSET INPUT CODE (5b) Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale U OPERATIO 18 26091929f LTC2609/LTC2619/LTC2629 TYPICAL APPLICATIO Demo Board Schematic—Onboard 20-Bit ADC Measures Key Performance Parameters REFA JP3 1 C1 VCC 0.1µF VCC 16 VCC 11 10 7 LTC2609CGN 4 CA0 VOUTA 3 CA1 REFA 5 CA2 VOUTB 6 REFB 13 VOUTC 12 REFC 14 SDA VOUTD 15 SCL REFD REFLO 2 GND 1 JP1 REFLO EXT GND C3 100pF VREF C4 0.1µF R5 7.5k VCC C5 0.1µF E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 3 5 A B C 2 4 6 1 3 5 REFB JP4 A B C 2 4 6 1 3 5 REFC JP5 A B C 2 4 6 1 3 5 REFD JP6 A B C 2 4 6 1 3 5 ADC REF JP7 A B C VREF 9 I2C 8 EXT REFLO REFLO VIN 4 C6 0.1µF 3 LT1790ACS6-5 VIN NC VOUT NC 6 5 5VREF C7 1µ F 6.3V GND GND 1 2 VIN C8 0.1µF LT1790ACS6-4.096 6 4 VIN VOUT 3 5 NC NC GND GND 1 2 4.096VREF C9 1µF 6.3V VIN C10 0.1µF LT1790ACS6-2.048 6 4 VIN VOUT 3 5 NC NC GND GND 1 2 2.048VREF C11 1µF 6.3V Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 2 4 6 5VREF 4.096VREF 2.048VREF VOUTA REFA VOUTB REFB VOUTC REFC VOUTD REFD GND GND 9 10 11 12 13 14 15 17 5 LTC2428CG CH0 CH1 CH2 CH3 8-CHANNEL CH4 MUX CH5 CH6 CH7 ZSSET R8 22Ω 28 7 4 3 MUXOUT ADCIN FSSET VCC VCC JP2 VCC ON/OFF DISABLE ADC 23 20 25 19 21 24 26 R7 7.5k 2609 TA02 + – 20-BIT ADC CSADC CSMUX SCK CLK DIN SD0 F0 R6 7.5k CS SCK MOSI MISO SPI BUS GND GND GND GND GND GND GND 1 6 16 18 22 27 28 26091929f 19 LTC2609/LTC2619/LTC2629 PACKAGE DESCRIPTIO U GN Package 16-Lead Plastic SSOP (Reference LTC DWG # 05-08-1641) .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE .0532 – .0688 (1.35 – 1.75) 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610 LTC2620 LTC2601/LTC2611 LTC2621 LTC2602/LTC2612 LTC2622 LTC2604/LTC2614 LTC2624 LTC2605/LTC2615 LTC2625 LTC2606/LTC2616 LTC2626 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DACs with Serial Interface in SO-8 Parallel 5V/3V 16-Bit VOUT DACs Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP Octal 16-/14-/12-Bit VOUT DACs with I2C Interface in 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN with I2C Interface COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2µs for 10V Step 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output 270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output 26091929f 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/LW/TP 0505 500 • PRINTED IN THE USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005