LTC2630

Electrical Specifications Subject to Change LTC2379-18 18-Bit, 1.6Msps, Low Power SAR ADC with 101dB SNR FEATURES n n n n n n n n n n n n n n n DESCRIPTION The LTC®2379-18 is a low noise, low power, high speed 18-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2379-18 has a ± VREF fully differential input range with VREF ranging from 2.5V to 5.1V. The LTC2379-18 consumes only 18mW and achieves ±2LSB INL maximum, no missing codes at 18-bits with 101dB SNR. The LTC2379-18 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisychain mode. The fast 1.6Msps throughput with no cycle latency makes the LTC2379-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2379-18 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate. The LTC2379-18 offers a digital gain compression (DGC) feature that allows a full-scale input to be achieved with inputs that swing between 10% and 90% of the ±VREF analog input range. This allows the input buffer amplifier to be operated from a single positive supply without headroom issues, resulting in a lower power system. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 1.6Msps Throughput Rate ±2LSB INL (Max) Guaranteed 18-Bit No Missing Codes Low Power: 18mW at 1.6Msps, 18μW at 1.6ksps 101dB SNR (typ) at fIN = 2kHz Digital Gain Compression (DGC) Guaranteed Operation to 125°C 2.5V Supply Fully Differential Input Range ±VREF VREF Input Range from 2.5V to 5.1V No Pipeline Delay, No Cycle Latency 1.8V to 5V I/O Voltages SPI-Compatible Serial I/O with Daisy-Chain Mode Internal Conversion Clock 16-pin MSOP and 4mm × 3mm DFN Packages APPLICATIONS n n n n n n Medical Imaging High Speed Data Acquisition Portable or Compact Instrumentation Industrial Process Control Low Power Battery-Operated Instrumentation ATE TYPICAL APPLICATION 32k Point FFT fS = 1.6Msps, fIN = 2kHz 2.5V 10μF AMPLITUDE (dBFS) VDD IN+ 3300pF LTC2379-18 IN– 20Ω 3300pF REF 2.5V TO 5.1V 47μF (X5R, 0805 SIZE) GND OVDD CHAIN RDL/SDI SDO SCK BUSY CNV REF/DGC 237918 TA01 1.8V TO 5V 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 0 SNR = 101.2dB THD = –120dB SINAD = 101.1dB SFDR = 121dB VREF 0V VREF 0V + – 20Ω 3300pF SAMPLE CLOCK VREF 100 200 300 400 500 600 700 800 FREQUENCY (kHz) 237918 TA02 237918p 1 LTC2379-18 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD) ...............................................2.8V Supply Voltage (OVDD) ................................................6V Reference Input (REF).................................................6V Analog Input Voltage (Note 3) IN+, IN– ......................... (GND –0.3V) to (REF + 0.3V) REF/DGC Input (Note 3) .... (GND –0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC2379C ................................................ 0°C to 70°C LTC2379I .............................................–40°C to 85°C LTC2379H .......................................... –40°C to 125°C Storage Temperature Range .................. –65°C to 150°C PIN CONFIGURATION TOP VIEW CHAIN VDD GND IN + 1 2 3 4 5 6 7 8 17 GND 16 GND 15 OVDD 14 SDO 13 SCK 12 RDL/SDI 11 BUSY 10 GND 9 CNV TOP VIEW CHAIN VDD GND IN+ IN– GND REF REF/DGC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OVDD SDO SCK RDL/SDI BUSY GND CNV IN– GND REF REF/DGC DE PACKAGE 16-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB MS PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 110°C/W ORDER INFORMATION LEAD FREE FINISH LTC2379CMS-18#PBF LTC2379IMS-18#PBF LTC2379HMS-18#PBF LTC2379CDE-18#PBF LTC2379IDE-18#PBF TAPE AND REEL LTC2379CMS-18#TRPBF LTC2379IMS-18#TRPBF LTC2379HMS-18#TRPBF LTC2379CDE-18#TRPBF LTC2379IDE-18#TRPBF PART MARKING* 237918 237918 237918 23798 23798 PACKAGE DESCRIPTION 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead (4mm × 3mm) Plastic DFN 16-Lead (4mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C –40°C to 125°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 237918p 2 LTC2379-18 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIN+ VIN – VIN+ – VIN– VCM IIN CIN CMRR PARAMETER Absolute Input Range (IN+) Absolute Input Range (IN–) Input Differential Voltage Range Common-Mode Input Range Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio Sample Mode Hold Mode CONDITIONS (Note 5) (Note 5) VIN = VIN+ – VIN– l l l l l ELECTRICAL CHARACTERISTICS MIN –0.05 –0.05 –VREF VREF/2– 0.05 TYP MAX VREF VREF +VREF UNITS V V V V μA pF pF dB VREF/2 VREF/2+ 0.05 ±1 45 5 TBD CONVERTER CHARACTERISTICS SYMBOL PARAMETER Resolution No Missing Codes Transition Noise INL DNL BZE FSE Integral Linearity Error Differential Linearity Error Bipolar Zero-Scale Error Bipolar Zero-Scale Error Drift Bipolar Full-Scale Error Bipolar Full-Scale Error Drift The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l l MIN 18 18 TYP MAX UNITS Bits Bits 0.8 (Note 6) (Note 7) (Note 7) –2 –1 –6 –14 ±1 ±0.4 ±0.25 3 ±3 ±0.1 14 2 1 6 LSBRMS LSB LSB LSB mLSB/°C LSB ppm/°C DYNAMIC ACCURACY SYMBOL PARAMETER SINAD SNR The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8) CONDITIONS fIN = 2kHz fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 5V, REF/DGC = GND fIN = 2kHz, VREF = 2.5V fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 5V, REF/DGC = GND fIN = 2kHz, VREF = 2.5V fIN = 2kHz l l MIN 98 98 TYP 100.5 101 99 96 –118 TBD TBD 120 TBD TBD TBD MAX UNITS dB dB dB dB dB dB dB dB MHz ns ps ns Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio THD Total Harmonic Distortion l –115 SFDR Spurious Free Dynamic Range –3dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response Full-Scale Step 200 237918p 3 LTC2379-18 REFERENCE INPUT SYMBOL VREF IREF VIHDGC VILDGC PARAMETER Reference Voltage Reference Input Current High Level Input Voltage REF/DGC Pin Low Level Input Voltage REF/DGC Pin The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS (Note 5) (Note 9) l l l l MIN 2.5 TYP 1 MAX 5.1 1.2 0.2VREF UNITS V mA V V 0.8VREF The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current Output Source Current Output Sink Current IO = –500 μA IO = 500 μA VOUT = 0V to OVDD VOUT = 0V VOUT = OVDD l l l DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS MIN l l TYP MAX 0.2 • OVDD UNITS V V μA pF V 0.8 • OVDD –10 5 OVDD – 0.2 0.2 –10 –10 10 10 10 VIN = 0V to OVDD l V μA mA mA POWER REQUIREMENTS SYMBOL VDD OVDD IVDD IOVDD IPD IPD PD PARAMETER Supply Voltage Supply Voltage Supply Current Supply Current Power Down Mode Power Down Mode Power Dissipation Power Down Mode Power Down Mode The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l l MIN 2.375 1.71 TYP 2.5 7.2 0.8 0.5 0.5 18 1.25 1.25 MAX 2.625 5.25 8 1 40 110 20 100 275 UNITS V V mA mA μA μA mW μW μW 1.6Msps Sample Rate 1.6Msps Sample Rate (CL = 20pF) Conversion Done (IVDD + IOVDD + IREF) Conversion Done (IVDD + IOVDD + IREF, H-Grade) 1.6Msps Sample Rate Conversion Done (IVDD + IOVDD + IREF) Conversion Done (IVDD + IOVDD + IREF, H-Grade) ADC TIMING CHARACTERISTICS SYMBOL fSMPL tCONV tACQ tCYC tCNVH tBUSYLH tCNVL tQUIET tSCK tSCKH PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Time Between Conversions CNV High Time CNV ↑ to BUSY Delay Minimum Low Time for CNV SCK Quiet Time from CNV ↑ SCK Period SCK High Time The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l MIN 380 200 625 20 TYP MAX 1.6 410 UNITS Msps ns ns ns ns tACQ = tCYC –tCONV – tBUSYLH (Note 10) l l l l l l l l CL = 20pF (Note 11) (Note 11) (Note 10) (Notes 11, 12) 15 20 20 10 4 ns ns ns ns ns 237918p 4 LTC2379-18 ADC TIMING CHARACTERISTICS SYMBOL tSCKL tSSDISCK tHSDISCK tSCKCH tDSDO tHSDO tDSDOBUSYL tEN tDIS PARAMETER SCK Low Time SDI Setup Time From SCK ↑ SDI Hold Time From SCK ↑ SCK Period in Chain Mode SDO Data Valid Delay from SCK ↑ SDO Data Remains Valid Delay from SCK ↑ SDO Data Valid Delay from BUSY ↓ Bus Enable Time After RDL ↓ Bus Relinquish Time After RDL ↑ (Note 11) (Note 11) tSCKCH = tSSDISCK + tDSDO (Note 11) CL = 20pF (Note 11) CL = 20pF (Note 10) CL = 20pF (Note 10) (Note 11) (Note 11) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS l l l l l l l l l MIN 4 4 1 13.5 TYP MAX UNITS ns ns ns ns 9.5 1 5 16 13 ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may effect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above REF or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without latch-up. Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1.6MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero-scale error is the offset voltage measured from –0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale ±5V input with a 5V reference voltage. Note 9: fSMPL = 1.6MHz, IREF varies proportionately with sample rate. Note 10: Guaranteed by design, not subject to test. Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 12: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture. 0.8*OVDD 0.2*OVDD tDELAY 0.8*OVDD 0.2*OVDD tDELAY 0.8*OVDD 0.2*OVDD 50% tWIDTH 50% 237918 F01 Figure 1. Voltage Levels for Timing Specifications 237918p 5 LTC2379-18 fSMPL = 1.6Msps, unless otherwise noted. Integral Nonlinearity vs Output Code 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0 65536 131072 196608 OUTPUT CODE 262144 238018 G01 TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity vs Output Code 1.0 TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, DC Histogram 70000 60000 0.5 DNL ERROR (LSB) COUNTS INL ERROR (LSB) 50000 40000 30000 20000 0.0 –0.5 10000 –1.0 0 65536 131072 196608 OUTPUT CODE 262144 237918 G02 0 131068 131069 131070 131071 131072 131073 CODE 237918 G03 32k Point FFT fS = 1.6Msps, fIN = 2kHz 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 FREQUENCY (kHz) 237918 G04 SNR, SINAD vs Input Frequency 105 –80 –90 SNR HARMONICS, THD (dBFS) –100 THD, Harmonics vs Input Frequency SNR = 101.2dB THD = –120dB SINAD = 101.1dB SFDR = 121dB SNR, SINAD (dBFS) 100 95 SINAD 90 THD –110 2ND –120 –130 –140 85 3RD 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz) 237918 G06 80 0 25 50 75 100 125 150 175 200 FREQUENCY (kHz) 237918 G05 SNR, SINAD vs Input level, fIN = 2kHz 102.0 102 101 101.5 SNR, SINAD (dBFS) SNR 101.0 SINAD SNR, SINAD (dBFS) SNR, SINAD vs Reference Voltage, fIN = 2kHz –100 –105 HARMONICS, THD (dBFS) –110 –115 –120 –125 –130 –135 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 237918 G16 THD, Harmonics vs Reference Voltage, fIN = 2kHz 100 SNR 99 SINAD 98 97 96 THD 3RD 2ND 100.5 100.0 –40 95 –30 –20 –10 INPUT LEVEL (dB) 237918 G07 0 –140 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 237918 G17 237918p 6 LTC2379-18 TYPICAL PERFORMANCE CHARACTERISTICS fSMPL = 1.6Msps, unless otherwise noted. SNR, SINAD vs Temperature, fIN = 2kHz 103 SNR 102 HARMONICS, THD (dBFS) SINAD SNR, SINAD (dBFS) 101 100 99 98 97 96 –55 –35 –15 –135 –55 –35 –15 –2 –55 –35 –15 –115 THD –120 3RD INL/DNL ERROR (LSB) 1 MAX INL –110 TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, THD, Harmonics vs Temperature, fIN = 2kHz 2 INL/DNL vs Temperature MAX DNL 0 MIN DNL MIN INL –125 2ND –130 –1 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G08 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G09 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G10 Full-Scale Error vs Temperature 8 6 FULL-SCALE ERROR (LSB) 4 2 0 –2 –4 –6 –8 –55 –35 –15 +FS 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G11 Offset Error vs Temperature 0.50 POWER SUPPLY CURRENT (mA) 8 7 6 5 4 3 2 1 0.25 OFFSET ERROR (LSB) 0 –0.25 –0.50 –0.75 –1.00 –1.25 –55 –35 –15 Supply Current vs Temperature IVDD –FS IOVDD IREF 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G12 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G13 Shutdown Current vs Temperature 45 40 POWER SUPPLY CURRENT (mA) POWER-DOWN CURRENT (μA) 35 30 25 20 15 10 5 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 237918 G14 Supply Current vs Sampling Rate 8 7 6 5 4 3 2 1 0 0 IOVDD IREF 200 400 600 800 1000 1200 1400 1600 SAMPLING RATE (kHz) 237918 G15 Reference Current vs Reference Voltage 1.0 0.9 REFERENCE CURRENT (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 237918 G18 IVDD + IOVDD + IREF IVDD 237918p 7 LTC2379-18 PIN FUNCTIONS CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2379-18 operates in Normal Mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2379-18 operates in Chain Mode and the RDL/ SDI pin functions as SDI, the daisychain serial data input. VDD (Pin 2): 2.5V Power Supply. The range of VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10μF ceramic capacitor. GND (Pins 3, 6, 10 and 16): Ground. IN+, IN– (Pins 4, 5): Positive and Negative Differential Analog Inputs. REF (Pin 7): Reference Input. The range of REF is 2.5V to 5.1V. This pin is referred to the GND pin and should be decoupled closely to the pin with a 47μF ceramic capacitor (X5R, 0805 size). REF/DGC (Pin 8): When tied to REF digital gain compression , is disabled and the LTC2379-18 defines full-scale according to the ±VREF analog input range. When tied to GND, digital gain compression is enabled and the LTC2379-18 defines full-scale with inputs that swing between 10% and 90% of the ±VREF analog input range. CNV (Pin 9): Convert Input. A rising edge on this input powers up the part and initiates a new conversion. BUSY (Pin 11): BUSY indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. RDL/SDI (Pin 12): When CHAIN is low, the part is in Normal Mode and the pin is treated as a bus enabling input. When CHAIN is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another ADC in the daisychain is input. SCK (Pin 13): Serial Data Clock Input. When SDO is enabled, the conversion result or daisychain data from another ADC is shifted out on the rising edges of this clock MSB first. SDO (Pin 14): Serial Data Output. The conversion result or daisychain data is output on this pin on each rising edge of SCK MSB first. The output data is in 2’s complement format. OVDD (Pin 15): I/O Interface Digital Power. The range of OVDD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V, or 5V). Bypass OVDD to GND with a 0.1μF capacitor. GND (Exposed Pad Pin 17 – DFN Package Only): Ground. Exposed pad must be soldered directly to the ground plane. FUNCTIONAL BLOCK DIAGRAM VDD = 2.5V REF = 5V LTC2379-18 CHAIN SDO RDL/SDI SCK OVDD = 1.8V to 5V IN+ + 18-BIT SAMPLING ADC IN– – SPI PORT CONTROL LOGIC CNV BUSY REF/DGC GND 237918 BD01 237918p 8 LTC2379-18 TIMING DIAGRAM Conversion Timing Using the Serial Interface CHAIN, RDL/SDI = 0 CNV POWER-DOWN AND ACQUIRE BUSY CONVERT SCK D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO 237918 TD02 237918p 9 LTC2379-18 APPLICATIONS INFORMATION OUTPUT CODE (TWO’S COMPLEMENT) OVERVIEW The LTC2379-18 is a low noise, low power, high speed 18-bit successive approximation register (SAR) ADC. Operating from a single 2.5V supply, the LTC2379-18 supports a large and flexible ±VREF fully differential input range with VREF ranging from 2.5V to 5.1V, making it ideal for high performance applications which require a wide dynamic range. The LTC2379-18 achieves ±2LSB INL max, no missing codes at 18-bits and 101dB SNR. Fast 1.6Msps throughput with no cycle latency makes the LTC2379-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2379-18 dissipates only 18mW at 1.6Msps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. The LTC2379-18 offers a digital gain compression (DGC) feature that allows a full-scale input to be achieved with inputs that swing between 10% and 90% of the ±VREF analog input range. This allows the input buffer amplifier to be operated from a single positive supply without headroom issues, resulting in a lower power system. CONVERTER OPERATION The LTC2379-18 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A converter (CDAC) is connected to the IN+ and IN– pins to sample the differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the 18-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 … VREF/262144) using the differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 18-bit digital output code for serial transfer. TRANSFER FUNCTION The LTC2379-18 digitizes the full-scale voltage of 2 × REF into 218 levels, resulting in an LSB size of 38μV with REF = 5V. The ideal transfer function is shown in Figure 2. The output data is in 2’s complement format. 011...111 011...110 BIPOLAR ZERO 000...001 000...000 111...111 111...110 100...001 100...000 –FSR/2 FSR = +FS – –FS 1LSB = FSR/262144 –1 0V 1 FSR/2 – 1LSB LSB LSB INPUT VOLTAGE (V) 237918 F02 Figure 2. LTC2379-18 Transfer Function ANALOG INPUT The analog inputs of the LTC2379-18 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each input sees approximately 45pF (CIN) from the sampling CDAC in series with 40Ω (RON) from the on-resistance of the sampling switch. Any unwanted signal that is common to both REF RON 40Ω CIN 45pF IN+ REF IN– RON 40Ω CIN 45pF BIAS VOLTAGE 237918 F03 Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2379-18 inputs will be reduced by the common mode rejection of the ADC. The inputs draw a current spike while charging the CIN capacitors during acquisition. During conversion, the analog inputs draw only a small leakage current. INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance inputs of the LTC2379-18 without gain error. A high impedance source should be buffered to minimize 237918p 10 LTC2379-18 APPLICATIONS INFORMATION settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC inputs draw a current spike when entering acquisition. For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2379-18. The amplifier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the current spike the ADC inputs draw. Input Filtering The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise. The simple 1-pole RC lowpass filter (LPF1) shown in Figure 4 is sufficient for many applications. Another filter network consisting of LPF2 should be used between the buffer and ADC input to both minimize the noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients. Long RC time constants at the analog inputs will slow down the settling of the analog inputs. Therefore, LPF2 requires a wider bandwidth than LPF1. A buffer amplifier with a low noise density must be selected to minimize degradation of the SNR. High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. LPF2 SINGLE-ENDEDINPUT SIGNAL LPF1 500Ω 6600pF 20Ω SINGLE-ENDED- 3300pF BW = 48kHz TO-DIFFERENTIAL DRIVER BW = 800kHz 3300pF 20Ω 3300pF IN– 237918 F04 Single-Ended-to-Differential Conversion For single-ended input signals, a single-ended to differential conversion circuit must be used to produce a differential signal at the inputs of the LTC2379-18. The LT6350 ADC driver is recommended for performing single-ended-todifferential conversions. The LT6350 is flexible and may be configured to convert single-ended signals of various amplitudes to the ±5V differential input range of the LTC2379-18. The LT6350 is also available in H-grade to complement the extended temperature operation of the LTC2379-18 up to 125°C. Figure 5a shows the LT6350 being used to convert a 0V to 5V single-ended input signal. In this case, the first amplifier is configured as a unity gain buffer and the singleended input signal directly drives the high-impedance input of the amplifier. As shown in the FFT of Figure 5b, the LT6350 drives the LTC2379-18 to near full datasheet performance. LT6350 5V 8 0V 1 4 OUT1 0V 5V 5 OUT2 0V 5V RINT RINT + – 2 – + VCM = VREF/2 + – 237918 F05a Figure 5a. LT6350 Converting a 0V-5V Single-Ended Signal to a ±5V Differential Input Signal 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 FREQUENCY (kHz) 237918 F05b SNR = 101dB THD = –111.5dB SINAD = 100.8dB SFDR = 114.5dB IN+ LTC2379-18 Figure 4. Input Signal Chain Figure 5b. 32k Point FFT Plot with fIN = 10kHz for Circuit Shown in Figure 5a 237918p 11 LTC2379-18 APPLICATIONS INFORMATION The LT6350 can also be used to buffer and convert large true bipolar signals which swing below ground to the ±5V differential input range of the LTC2379-18 in order to maximize the signal swing that can be digitized. Figure 6a shows the LT6350 being used to convert a ±10V true bipolar signal for use by the LTC2379-18. In this case, the first amplifier in the LT6350 is configured as an inverting amplifier stage, which acts to attenuate and level shift the input signal to the 0V to 5V input range of the LTC2379-18. In the inverting amplifier configuration, the single-ended input signal source no longer directly drives a high impedance input of the first amplifier. The input impedance is instead set by resistor RIN. RIN must be chosen carefully based on the source impedance of the signal source. Higher values of RIN tend to degrade both the noise and distortion of the LT6350 and LTC2379-18 as a system. R1, R2, R3 and R4 must be selected in relation to RIN to achieve the desired attenuation and to maintain a balanced input impedance in the first amplifier. Table 1 shows the resulting SNR and THD for several values of RIN, R1, R2, R3 and R4 in this configuration. Figure 6b shows the resulting FFT when using the LT6350 as shown in Figure 6a. Table 1. SNR, THD vs RIN for ±10V Single-Ended Input Signal. RIN (Ω) 2k 10k 100k R1 (Ω) 499 2.49k 24.9k R2 (Ω) 499 2.49k 24.9k R3 (Ω) 2k 10k 100k R4 (Ω) 402 2k 20k SNR (dB) 100.8 109.5 94.8 THD (dB) 99 TBD 96 5V 0V LT6203 3 2 VCM R2 = 499k 200pF LT6350 4 10μF R4 = 402k R3 = 2k 8 OUT1 0V 5V 5 OUT2 0V 5V RINT RINT + – 1 10V 0V –10V RIN = 2k R1 = 499k 2 – + VCM = VREF/2 + – 220pF 237918 F06a Figure 6a. LT6350 Converting a ±10V Single-Ended Signal to a ±5V Differential Input Signal 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 FREQUENCY (kHz) 237918 F06b SNR = 100.8dB THD = –99.3dB SINAD = 97.8dB SFDR = 101.2dB Figure 6b. 32k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 6a + – + – 5V 1 0V Fully Differential Inputs 5V To achieve the full distortion performance of the LTC2379-18, a low distortion fully differential signal source driven through the LT6203 configured as two unity gain buffers as shown in Figure 7 can be used to get the full data sheet THD specification of –118dB. Digital Gain Compression The LTC2379-18 offers a digital gain compression (DGC) feature which defines the full-scale input swing to be between 10% and 90% of the ±VREF analog input range. To 5 0V 6 5V 7 0V 237918 F07 Figure 7. LT6203 Buffering a Fully Differential Signal Source enable digital gain compression, bring the REF/DGC pin low. This feature allows the LT6350 to be powered off of a single +5.5V supply since each input swings between 0.5V and 4.5V as shown in Figure 8. Needing only one positive supply to power the LT6350 results in additional power savings for the entire system. 237918p 12 LTC2379-18 APPLICATIONS INFORMATION 5V 4.5V 0.5V 0V 237918 F08 Figure 8. Input Swing of the LTC2379 with Gain Compression Enabled Figure 9a shows how to configure the LT6350 to accept a ±10V true bipolar input signal and attenuate and level shift the signal to the reduced input range of the LTC2379-18 when digital gain compression is enabled. Figure 9b shows an FFT plot with the LTC2379-18 being driven by the LT6350 with digital gain compression enabled. ADC REFERENCE The LTC2379-18 requires an external reference to define its input range. A low noise, low temperature drift reference is critical to achieving the full datasheet performance of the ADC. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power and high accuracy, the LTC6655-5 is particularly well suited for use with the LTC2379-18. The LTC6655-5 offers 0.025% (max) initial accuracy and 2ppm/°C (max) temperature coefficient for high precision applications. The LTC6655-5 is fully specified over the H-grade temperature range and complements the extended temperature operation of the LTC2379-18 up to 125°C. We recommend bypassing the LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805 size) close to the REF pin. The REF pin of the LTC2379-18 draws charge (QCONV) from the 47μF bypass capacitor during each conversion cycle. The reference replenishes this charge with a DC current, IREF = QCONV/tCYC. The DC current draw of the REF pin, IREF, depends on the sampling rate and output code. If the LTC2379-18 is used to continuously sample a signal at a constant rate, the LTC6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5LSBs. When idling, the REF pin on the LTC2379-18 draws only a small leakage current (< 1μA). In applications where a burst of samples is taken after idling for long periods as shown in Figure 10, IREF quickly goes from approximately 0μA to a maximum of 1.2mA at 1.6Msps. This step in DC VIN 0 –20 –40 AMPLITUDE (dBFS) 5.5V 5V 1k VCM 10μF 1k LT6350 6.04k 8 4.32k 10μF V+ 3 4 OUT1 0.5V 20Ω 3300pF 47μF 4.5V 3300pF IN+ REF LTC6655-5 VOUT_S SNR = 99dB THD = –95dB SINAD = 94.6dB SFDR = 96.3dB 2.5V VDD –60 –80 –100 –120 –140 + – RINT RINT LTC2379-18 IN 3300pF – 1 10V 0V –10V RIN = 15k 3.01k 2 VCM – + 20Ω 5 V– 6 0.5V OUT2 4.5V REF/DGC 237918 F09a –160 –180 0 100 200 300 400 500 600 700 800 FREQUENCY (kHz) 237918 F09b Figure 9a. LT6350 Configured to Accept a ±10V Input Signal While Running Off of a Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2379-18 Figure 9b. 32k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 9a CNV IDLE PERIOD IDLE PERIOD 237918 F10 Figure 10. CNV Waveform Showing Burst Sampling 237918p 13 LTC2379-18 APPLICATIONS INFORMATION current draw triggers a transient response in the reference that must be considered since any deviation in the reference output voltage will affect the accuracy of the output code. In applications where the transient response of the reference is important, the fast settling LTC6655-5 reference is also recommended. DYNAMIC PERFORMANCE Fast Fourier Transform (FFT) techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2379-18 provides guaranteed tested limits for both AC distortion and noise measurements. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 11 shows that the LTC2379-18 achieves a typical SINAD of 100.5dB at a 1.6MHz sampling rate with a 2kHz input. 0 –20 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –140 –160 –180 0 100 200 300 400 500 600 700 800 FREQUENCY (kHz) 237918 F11 Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 11 shows that the LTC2379-18 achieves a typical SNR of 101dB at a 1.6MHz sampling rate with a 2kHz input. Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: THD = 20log V22 + V32 + V42 +…+ VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. POWER CONSIDERATIONS The LTC2379-18 provides two power supply pins: the 2.5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2379-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Power Supply Sequencing The LTC2379-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2379-18 has a power-on-reset (POR) circuit that will reset the LTC2379-18 at initial power-up or whenever the power supply voltage drops below 1V. Once the supply voltage reenters the nominal supply voltage range, the POR will SNR = 101.2dB THD = –120dB SINAD = 101.1dB SFDR = 121dB Figure 11. 32k Point FFT of the LTC2379-18 237918p 14 LTC2379-18 APPLICATIONS INFORMATION reinitialize the ADC. No conversions should be initiated until 20μs after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. TIMING AND CONTROL CNV Timing The LTC2379-18 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the LTC2379-18. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2379-18 powers down and begins acquiring the input signal. Internal Conversion Clock The LTC2379-18 has an internal clock that is trimmed to achieve a maximum conversion time of 410ns. With a minimum acquisition time of 200ns, throughput performance of 1.6Msps is guaranteed without any external adjustments. Auto Power-Down The LTC2379-18 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of CNV. During power down, data from the last conversion can be clocked out. To minimize power dissipation during power down, disable SDO and turn off SCK. The auto power-down feature will reduce the power dissipation of the LTC2379-18 as the sampling frequency is reduced. Since power is consumed only during a conversion, the LTC2379-18 remains powered-down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 12. DIGITAL INTERFACE The LTC2379-18 has a serial digital interface. The flexible OVDD supply allows the LTC2379-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 100MHz, a 1.6Msps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D17 remains valid till the first rising edge of SCK. The serial interface on the LTC2379-18 is simple and straightforward to use. The following sections describe the operation of the LTC2379-18. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy-chained. 8 POWER SUPPLY CURRENT (mA) 7 6 5 4 3 2 1 0 0 IOVDD IREF 200 400 600 800 1000 1200 1400 1600 SAMPLING RATE (kHz) 237918 F12 IVDD Figure 12. Power Supply Current of the LTC2379-18 Versus Sampling Rate 237918p 15 LTC2379-18 TIMING DIAGRAM Normal Mode, Single Device When CHAIN = 0, the LTC2379-18 operates in Normal mode. In Normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high-impedance. If RDL/SDI is low, SDO is driven. Figure 13 shows a single LTC2379-18 operated in Normal Mode with CHAIN and RDL/SDI tied to ground. With RDL/ SDI grounded, SDO is enabled and the MSB(D17) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2379-18. CONVERT CNV CHAIN LTC2379-18 RDL/SDI SCK CLK SDO DATA IN BUSY IRQ DIGITAL HOST 238018 F13a POWER-DOWN AND ACQUIRE CONVERT POWER-DOWN AND ACQUIRE CONVERT CHAIN = 0 RDL/SDI = 0 tCNVH CNV tCYC tCNVL tACQ = tCYC – tCONV – tBUSYLH BUSY tBUSYLH tCONV tSCK tACQ tSCKH 2 3 16 17 18 tQUIET SCK 1 tHSDO tDSDOBUSYL SDO D17 D16 tDSDO D15 tSCKL D1 D0 237918 F13 Figure 13. Using a Single LTC2379-18 in Normal Mode 237918p 16 LTC2379-18 TIMING DIAGRAM Normal Mode, Multiple Devices Figure 14 shows multiple LTC2379-18 devices operating in Normal Mode(CHAIN = 0) sharing CNV, SCK and SDO. By sharing CNV, SCK and SDO, the number of required signals to operate multiple ADCs in parallel is reduced. Since SDO is shared, the RDL/SDI input of each ADC must be used to allow only one LTC2379-18 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 14, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. RDLB RDLA CONVERT CNV CHAIN LTC2379-18 B RDL/SDI SCK SDO RDL/SDI SCK DATA IN CLK 237918 F15 CHAIN CNV LTC2379-18 A BUSY SDO IRQ DIGITAL HOST POWER-DOWN AND ACQUIRE CONVERT POWER-DOWN AND ACQUIRE CONVERT CHAIN = 0 CNV tCONV BUSY tBUSYLH RDL/SDIA tCNVL RDL/SDIB tSCK SCK 1 2 3 tHSDO SDO tEN Hi-Z D17A D16A D15A tDSDO D1A tDIS D0A Hi-Z D17B D16B D15B D1B D0B Hi-Z 237918 F14 tSCKH 16 17 18 tSCKL 19 20 21 34 35 36 tQUIET Figure 14. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO 237918p 17 LTC2379-18 TIMING DIAGRAM When CHAIN = OVDD, the LTC2379-18 operates in Chain Mode. In Chain Mode, SDO is always enabled and RDL/SDI serves as the serial data input pin (SDI) where daisychain data output from another ADC can be input. This is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. Figure 15 shows an example with two daisy chained devices. The MSB of converter A will appear at SDO of converter B after 18 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. CONVERT OVDD CHAIN RDL/SDI CNV LTC2379-18 A SCK SDO OVDD CHAIN RDL/SDI CNV LTC2379-18 B SCK BUSY SDO IRQ DATA IN DIGITAL HOST CLK 237918 F15a POWER-DOWN AND ACQUIRE CHAIN = OVDD RDL/SDIA = 0 CONVERT POWER-DOWN AND ACQUIRE CONVERT tCYC tCNVL CNV BUSY tBUSYLH tCONV tSCKCH tSCKH 18 tHSDO tDSDO 19 20 tSCKL 34 35 36 tQUIET SCK 1 2 3 tSSDISCK tHSDISCK 16 17 SDOA = RDL/SDIB D17A tDSDOBUSYL D16A D15A D1A D0A SDOB D17B D16B D15B D1B D0B D17A D16A D1A D0A 237918 F15 Figure 15. Chain Mode Timing Diagram 237918p 18 LTC2379-18 BOARD LAYOUT To obtain the best performance from the LTC2379-18 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1783A, the evaluation kit for the LTC2379-18. Partial Top Silkscreen 237918p 19 LTC2379-18 BOARD LAYOUT Partial Layer 1 Component Side Partial Layer 2 Ground Plane 237918p 20 LTC2379-18 BOARD LAYOUT Partial Layer 3 PWR Plane Partial Layer 4 Bottom Layer 237918p 21 LTC2379-18 BOARD LAYOUT 1 2 3 C18 OPT –IN1 C61 10μF 6.3V C39 3300pF R16 0Ω 4 NPO OUT2 5 R36 20Ω LTC2379-18 IN– GND GND GND GND 5 RDL/SDI R7 1k 3 6 10 16 1 C40 3300pF NPO C19 3300pF 1206 NPO R19 0Ω VDD 2 OVDD 15 REF 7 8 REF/DGC IN+ CNV SCK SDO BUSY R45 ØΩ R15 OPT R9 OPT C42 15pF C58 OPT C9 10μF 6.3V C10 0.1μF +2.5V R34 0Ω R37 OPT C62 1μF V+ C57 0.1μF V– C55 1μF R35 OPT R38 OPT 6 C45 V – 10μF C8 1μF R18 1k JP2 CM Partial Schematic of Demoboard 1 VREF/2 2 EXT C63 10μF 6.3V C43 0.1μF C59 1μF C44 1μF C60 0.1μF 9V TO 10V 3 E7 HD1X3-100 EXT_CM C46 1μF R40 1k COUPLING AC DC JP5 HD1X3-100 1 2 3 J8 C49 OPT AIN – R39 0Ω R41 OPT C47 OPT C48 10μF 6.3V + – 2 +IN2 – + 22 R1 33Ω +3.3V C2 0.1μF +3.3V C3 0.1μF 1 +3.3V 6 CLR\ Q\ 3 3 5 DB17 DB16 J2 CON-EDGE 40-100 PR\ Q 5 U3 NL17SZ74 C56 0.1μF JP6 FS 1 2 3 HD1X3-100 U6 OPT NC7SZ66P5X 5 CNV VCC 9 2B A1 13 SCK OE 4 14 SDO GND 11 BUSY 3 12 RD +3.3V +3.3V C13 0.8VREF 0.1μF VREF R8 33Ω DC590 DETECT TO CPLD 4 R4 7 33Ω 4 CP GND 8 D VCC 2 +3.3V C4 0.1μF 5 4 2 C11 0.1μF R31 OPT V+ +3.3V C7 0.1μF C20 47μF 6.3V 0805 4 U4 NC7SVU04P5X 2 CNVST_33 FROM CPLD 9V TO 10V R3 CLK 33Ω TO CPLD U20 LTC6655AHMS8-5 1 8 SHDN GND 2 7 VIN OUT_F 3 6 GND OUT_S 4 5 GND GND R32 0Ω 8 +IN1 OUT1 4 R32 20Ω +2.5V 3 V+ U15 7 LT6350CMS8 SHDN C6 10μF 6.3V DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 4 5 3 U9 NC7SZ04P5X 2 R17 R13 2k 1k C15 0.1μF CLKOUT C16 1 0.1μF 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J3 DC590 R10 4.99k R11 4.99k R12 4.99k SDO 1 3 5 7 9 11 13 2 4 6 8 10 12 14 U7 C14 0.1μF 8 24LC025-I/ST VCC SCL SCK SDA WP CNV ARRAY A2 EEPROM A1 A0 VSS 4 237918 BL +3.3V C5 0.1μF R2 1k +3.3V C1 0.1μF 5 J1 CLKIN 2 R5 49.9Ω 1206 U2 R6 3 U8 3 NC7SZ04P5X NC7SVU04P5X 1k COUPLING AC DC JP1 HD1X3-100 J4 AIN+ R14 0Ω C17 10μF 6 5 7 3 2 1 237918p LTC2379-18 PACKAGE DESCRIPTION DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) 4.00 ±0.10 (2 SIDES) 0.70 ±0.05 3.30 ±0.05 1.70 ± 0.05 PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 0.25 ± 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.200 REF R = 0.05 TYP 3.00 ±0.10 (2 SIDES) 3.30 ±0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45° CHAMFER (DE16) DFN 0806 REV Ø R = 0.115 TYP 9 0.40 ± 0.10 16 3.60 ±0.05 2.20 ±0.05 8 0.75 ±0.05 1 0.23 ± 0.05 0.45 BSC 3.15 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 4.039 0.102 (.159 .004) (NOTE 3) 16151413121110 9 0.889 (.035 0.127 .005) 0.280 0.076 (.011 .003) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) GAUGE PLANE 0.254 (.010) DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.305 0.038 (.0120 .0015) TYP 0.50 (.0197) BSC 0.18 (.007) 0.53 0.152 (.021 .006) DETAIL “A” 12345678 1.10 (.043) MAX 0.86 (.034) REF RECOMMENDED SOLDER PAD LAYOUT SEATING NOTE: PLANE 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MS16) 1107 REV Ø 237918p Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2379-18 TYPICAL APPLICATION LT6350 Configured to Accept a ±10V Input Signal While Running Off of a Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2379-18 5.5V 5V 1k VCM 10μF 1k LT6350 6.04k 8 4.32k 10μF V+ 3 4 OUT1 0.5V 20Ω 3300pF 47μF 4.5V 3300pF IN+ REF VDD 2.5V VIN LTC6655-5 VOUT_S + – RINT RINT LTC2379-18 IN– 3300pF REF/DGC 237918 TA03 1 10V 0V –10V RIN = 15k 3.01k 2 VCM – + 20Ω 5 V– 6 0.5V OUT2 4.5V RELATED PARTS PART NUMBER ADCs LTC2383-16/LTC2382-16/ 16-Bit, 1Msps/500ksps/250ksps Serial, Low power ADC 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin LTC2381-16 Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 package LTC2393-16/LTC2392-16/ 16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC LTC2391-16 LTC1864/LTC1864L LTC1865/LTC1865L LTC2306 LTC2355-14/LTC2356-14 DACS LTC2641 LTC2630 REFERENCES LTC6655 LTC6652 AMPLIFIERS LT6350 LT6200/LT6200-5/ LT6200-10 LT6202/LT6203 LTC1992 Low Noise Single-Ended-to-Differential ADC Driver 165MHz/800MHz/1.6GHz Op Amp with Unity Gain/AV = 5/AV = 10 Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at 1MHz, TSOT23-6 Package Precision Low Drift Low Noise Buffered Reference Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package 2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package 16-Bit Single Serial VOUT DACs 12-Bit/10-Bit/8-Bit Single VOUT DACs ±1LSB INL, ±1LSB DNL, MSOP-8 Package, 0V to 5V Output SC70 6-Pin Package, Internal Reference, ±1LSB INL (12Bits) 16-Bit, 250ksps/150ksps 1-Channel μPower, ADC 16-Bit, 250ksps 2-Channel μPower ADC 12-Bit, 500ksps, 1-Channel/2-Channel, Low Noise, ADC 14-Bit, 3.5Msps Serial ADC 3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package 5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, Pin Compatible Family in 7mm × 7mm LQFP-48 and QFN package 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package DESCRIPTION COMMENTS Single/Dual 100MHz Rail-to-Rail Input/Output Noise Low 1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth Power Amplifiers Low Power, Fully Differential Input/Output Amplifier/ Driver Family 1mA Supply Current 237918p 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0111 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORA TION 2011