LTC2641

LTC2641/LTC2642 16-/14-/12-Bit VOUT DACs in 3mm × 3mm DFN FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LTC®2641/LTC2642 are families of 16-, 14- and 12-bit unbuffered voltage output DACs. These DACs operate from a single 2.7V to 5.5V supply and are guaranteed monotonic over temperature. The LTC2641-16/LTC2642-16 provide 16-bit performance (±2LSB INL and ±1LSB DNL) over temperature. Unbuffered DAC outputs result in low supply current of 120μA and a low offset error of ±1LSB. Both the LTC2641 and LTC2642 feature a reference input range of 2V to VDD. VOUT swings from 0V to VREF. For bipolar operation, the LTC2642 includes matched scaling resistors for use with an external precision op amp (such as the LT1678), generating a ±VREF output swing at RFB. The LTC2641/LTC2642 use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz and can interface directly with optocouplers for applications requiring isolation. A power-on reset circuit clears the LTC2641’s DAC output to zero scale and the LTC2642’s DAC output to midscale when power is initially applied. A logic low on the ⎯C⎯L⎯R pin asynchronously clears the DAC to zero scale (LTC2641) or midscale (LTC2642). These DACs are all specified over the commercial and industrial ranges. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Tiny 3mm × 3mm 8-Pin DFN Package Maximum 16-Bit INL Error: ±2LSB over Temperature Low 120μA Supply Current Guaranteed Monotonic over Temperature Low 0.5nV•sec Glitch Impulse 2.7V to 5.5V Single Supply Operation Fast 1μs Settling Time to 16 Bits Unbuffered Voltage Output Directly Drives 60k Loads 50MHz SPITM/QSPITM/MICROWIRETM Compatible Serial Interface Power-On Reset Clears DAC Output to Zero Scale (LTC2641) or Midscale (LTC2642) Schmitt-Trigger Inputs for Direct Optocoupler Interface Asynchronous ⎯C⎯L⎯R Pin 8-Lead MSOP and 3mm × 3mm DFN Packages (LTC2641) 10-Lead MSOP and 3mm × 3mm DFN Packages (LTC2642) APPLICATIONS ■ ■ ■ ■ High Resolution Offset and Gain Adjustment Process Control and Industrial Automation Automatic Test Equipment Data Aquisition Systems TYPICAL APPLICATION Bipolar 16-Bit DAC 2.7V TO 5.5V 0.1μF VDD REF 1μF 0.1μF RFB VREF 2V TO VDD LTC2642-16 Integral Nonlinearity 1.0 0.8 0.6 VDD = 5V VREF = 2.5V ±2.5V RANGE LTC2642 1/2 LT1678 POWER-ON RESET CS SCLK DIN CLR 16-BIT DAC 16-BIT DATA LATCH CONTROL LOGIC 16-BIT SHIFT REGISTER GND 26412 TA01a + VOUT INL (LSB) – BIPOLAR VOUT –VREF TO VREF INV 5pF 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE INL 25°C INL 90°C INL –45°C 49152 65535 LT1372 • G10 26412f 1 LTC2641/LTC2642 ABSOLUTE MAXIMUM RATINGS (Note 1) VDD to GND .................................................. –0.3V to 6V ⎯C⎯S, SCLK, DIN, ⎯C⎯L⎯R to GND ........................ –0.3V to (VDD + 0.3V) or 6V REF, VOUT, INV to GND ........ –0.3V to (VDD + 0.3V) or 6V RFB to INV ....................................................... –6V to 6V RFB to GND ..................................................... –6V to 6V Operating Temperature Range LTC2641C/LTC2642C ............................... 0°C to 70°C LTC2641I/LTC2642I ............................. –40°C to 85°C Maximum Junction Temperature .......................... 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C PIN CONFIGURATION LTC2641 TOP VIEW REF 1 CS 2 SCLK 3 DIN 4 9 8 7 6 5 GND VDD VOUT CLR REF CS SCLK DIN 1 2 3 4 TOP VIEW 8 7 6 5 GND VDD VOUT CLR DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C (NOTE 2), θJA = 43°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C (NOTE 2), θJA = 200°C/W LTC2642 TOP VIEW REF CS SCLK DIN CLR 1 2 3 4 5 11 10 GND 9 VDD 8 RFB 7 INV 6 VOUT REF CS SCLK DIN CLR 1 2 3 4 5 TOP VIEW 10 9 8 7 6 GND VDD RFB INV VOUT DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C (NOTE 2), θJA = 43°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C (NOTE 2), θJA = 120°C/W 26412f 2 LTC2641/LTC2642 ORDER INFORMATION LTC2641 LEAD FREE FINISH LTC2641CDD-16#PBF LTC2641CDD-14#PBF LTC2641CDD-12#PBF LTC2641IDD-16#PBF LTC2641IDD-14#PBF LTC2641IDD-12#PBF LTC2641CMS8-16#PBF LTC2641CMS8-14#PBF LTC2641CMS8-12#PBF LTC2641IMS8-16#PBF LTC2641IMS8-14#PBF LTC2641IMS8-12#PBF LTC2642 LTC2642CDD-16#PBF LTC2642CDD-14#PBF LTC2642CDD-12#PBF LTC2642IDD-16#PBF LTC2642IDD-14#PBF LTC2642IDD-12#PBF LTC2642CMS-16#PBF LTC2642CMS-14#PBF LTC2642CMS-12#PBF LTC2642IMS-16#PBF LTC2642IMS-14#PBF LTC2642IMS-12#PBF LTC2642CDD-16#TRPBF LTC2642CDD-14#TRPBF LTC2642CDD-12#TRPBF LTC2642IDD-16#TRPBF LTC2642IDD-14#TRPBF LTC2642IDD-12#TRPBF LTC2642CMS-16#TRPBF LTC2642CMS-14#TRPBF LTC2642CMS-12#TRPBF LTC2642IMS-16#TRPBF LTC2642IMS-14#TRPBF LTC2642IMS-12#TRPBF LCZW LCZV LCZT LCZW LCZV LCZT LTCZZ LTCZY LTCZX LTCZZ LTCZY LTCZX 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 0°C to 70°C 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C –40°C to 85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C –40°C to 85°C TAPE AND REEL LTC2641CDD-16#TRPBF LTC2641CDD-14#TRPBF LTC2641CDD-12#TRPBF LTC2641IDD-16#TRPBF LTC2641IDD-14#TRPBF LTC2641IDD-12#TRPBF LTC2641CMS8-16#TRPBF LTC2641CMS8-14#TRPBF LTC2641CMS8-12#TRPBF LTC2641IMS8-16#TRPBF LTC2641IMS8-14#TRPBF LTC2641IMS8-12#TRPBF PART MARKING* LCZP LCZN LCZM LCZP LCZN LCZM LTCZS LTCZR LTCZQ LTCZS LTCZR LTCZQ PACKAGE DESCRIPTION 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead (3mm × 3mm) Plastic DFN 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP TEMPERATURE RANGE 0°C to 70°C 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C –40°C to 85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C –40°C to 85°C –40°C to 85°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 26412f 3 LTC2641/LTC2642 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. LTC2641-12 LTC2642-12 SYMBOL PARAMETER Static Peformance N DNL INL ZSE ZSTC GE GETC ROUT Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Zero Code Offset Error Zero Code Tempco Gain Error Gain Error Tempco DAC Output Resistance Bipolar Resistor Matching BZE BZSTC PSR Bipolar Zero Offset Error Bipolar Zero Tempco Power Supply Rejection (Note 4) (LTC2642) RFB/RINV Ratio Error (Note 7) ● (LTC2642) (LTC2642) ΔVDD = ±10% ● ● ● ● ● LTC2641-14 LTC2642-14 MAX MIN 14 14 ±0.5 ±0.5 1 ±0.5 ±0.5 ±0.05 ±2 ±1 ±0.1 6.2 1 ±0.1 ±0.03 ±0.5 ±0.1 ±0.5 ±0.5 ±4 ±2 ±4 ±1 ±1 2 TYP MAX MIN 16 16 LTC2641-16 LTC2642-16 TYP MAX UNITS Bits Bits ±0.5 ±0.5 ±0.05 ±2 ±0.1 6.2 1 ±0.015 ±2 ±0.1 ±1 ±5 % LSB ppm/°C LSB ±5 ±1 ±2 2 LSB LSB LSB ppm/°C LSB ppm/°C kΩ CONDITIONS MIN 12 12 TYP (Note 2) (Note 2) Code = 0 ● ● ● ±0.05 ±0.5 ±0.1 6.2 1 ±0.5 ±0.1 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL Reference Input VREF RREF Reference Input Range Reference Input Resistance (Note 5) Unipolar Mode (LTC2641) Bipolar Mode (LTC2642) Measured from 10% to 90% To ±0.5LSB of FS Major Carry Transition Code = 0000hex; NCS = VDD; SCLK, DIN 0V to VDD Levels Code = FFFFhex Code = 0000hex, VREF = 1VP-P at 100kHz Code = 0000hex Code = FFFFhex VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V ● ● ● ● ● ● ● PARAMETER CONDITIONS MIN 2.0 11 8.5 TYP MAX VDD UNITS V kΩ kΩ V/μs μs nV•s nV•s 14.8 11.4 15 1 0.5 0.2 Dynamic Performance—VOUT SR Voltage Output Slew Rate Output Settling Time DAC Glitch Impulse Digital Feedthrough Dynamic Performance—Reference Input BW SNR CIN(REF) Digital Inputs VIH VIL Digital Input High Voltage Digital Input Low Voltage 2.4 2.0 0.8 0.6 V V V V 26412f Reference –3dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance 1.3 1 92 75 120 MHz mVP-P dB pF pF 4 LTC2641/LTC2642 ELECTRICAL CHARACTERISTICS SYMBOL IIN CIN VH Power Supply VDD IDD PD Supply Voltage Supply Current, VDD Power Dissipation Digital Inputs = 0V or VDD Digital Inputs = 0V or VDD, VDD = 5V Digital Inputs = 0V or VDD, VDD = 3V ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. PARAMETER Digital Input Current Digital Input Capacitance Hysteresis Voltage 2.7 120 0.60 0.36 CONDITIONS VIN = GND to VCC (Note 6) ● ● MIN TYP 3 0.15 MAX ±1 10 UNITS μA pF V 5.5 200 V μA mW mW TIMING CHARACTERISTICS SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 fSCLK PARAMETER DIN Valid to SCLK Setup Time DIN Valid to SCLK Hold Time SCLK Pulse Width High SCLK Pulse Width Low ⎯CS Pulse High Width ⎯ LSB SCLK High to ⎯C⎯S High ⎯C⎯S Low to SCLK High ⎯C⎯S High to SCLK Positive Edge ⎯CLR Pulse Width Low ⎯⎯ The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. CONDITIONS ● ● ● ● ● ● ● ● ● ● MIN 10 0 9 9 10 8 8 8 15 TYP MAX UNITS ns ns ns ns ns ns ns ns ns SCLK Frequency ⎯⎯ VDD High to CS Low (Power-Up Delay) 50% Duty Cycle 50 30 MHz μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale. LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale. Note 4: ROUT tolerance is typically ±20%. Note 5: Reference input resistance is code dependent. Minimum is at 871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar mode. Note 6: Guaranteed by design and not production tested. Note 7: Guaranteed by gain error and offset error testing, not production tested. 26412f 5 LTC2641/LTC2642 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 INL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 26412 G01 Integral Nonlinearity (INL) vs Supply (VDD) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 3 4 VDD (V) 5 6 26412 G02 INL vs VREF 1.0 0.8 0.6 VDD = 5.5V LTC2642-16 VREF = 2.5V VDD = 5V VREF = 2.5V +INL INL (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 3 +INL –INL –INL 4 VREF (V) 5 6 26412 G03 Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 DNL (LSB) DNL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 26412 G04 Differential Nonlinearity (DNL) vs Supply (VDD) 1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 2 3 4 VDD (V) 26412 G05 DNL vs VREF 1.0 0.8 0.6 0.4 VDD = 5.5V LTC2642-16 VREF = 2.5V VDD = 5V VREF = 2.5V +DNL –DNL 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 +DNL –DNL 5 6 2 3 4 VREF (V) 5 6 26412 G06 INL vs Temperature 1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –15 35 10 TEMPERATURE (°C) 60 85 26412 G07 DNL vs Temperature 1.0 5 VREF = 2.5V VDD = 5V 4 3 2 BZE (LSB) +DNL –DNL 1 0 –1 –2 –3 –4 –15 35 10 TEMPERATURE (°C) 60 85 26412 G08 Bipolar Zero Error vs Temperature VREF = 2.5V VDD = 5V VREF = 2.5V VDD = 5V +INL DNL (LSB) 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –INL –1.0 –40 –5 –40 –15 35 10 TEMPERATURE (°C) 60 85 26412 G09 26412f 6 LTC2641/LTC2642 TYPICAL PERFORMANCE CHARACTERISTICS Bipolar Gain Error vs Temperature 5 4 3 2 BGE (LSB) ZSE (LSB) 1 0 –1 –2 –3 –4 –5 –40 –15 35 10 TEMPERATURE (°C) 60 85 26412 G10 Unbuffered Zero Scale Error vs Temperature (LTC2641-16) 1.0 0.8 0.6 0.4 FSE (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –15 35 10 TEMPERATURE (°C) 60 85 26412 G11 Unbuffered Full-Scale Error vs Temperature (LTC2641-16) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –15 35 10 TEMPERATURE (°C) 60 85 26412 G12 VREF = 2.5V VDD = 5V 14-Bit Integral Nonlinearity (INL) (LTC2642-14) 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16383 26412 G13 14-Bit Differential Nonlinearity (DNL) (LTC2642-14) 1.0 250 LTC2642-14 VREF = 2.5V VDD = 5V 0.8 0.6 0.4 IREF (μA) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16383 26412 G14 IREF vs Code (Unipolar LTC2641) VREF = 2.5V LTC2642-14 VREF = 2.5V VDD = 5V 200 150 100 50 0 0 16384 32768 CODE 49152 65535 26412 G15 12-Bit Integral Nonlinearity (INL) (LTC2642-12) 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE 3072 4095 26412 G16 12-Bit Differential Nonlinearity (DNL) (LTC2642-12) 1.0 250 LTC2642-12 VREF = 2.5V VDD = 5V 0.8 0.6 0.4 IREF (μA) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE 3072 4095 26412 G17 IREF vs Code (Bipolar LTC2642) VREF = 2.5V LTC2642-12 VREF = 2.5V VDD = 5V 200 150 100 50 0 0 16384 32768 CODE 49152 65535 26412 G18 26412f 7 LTC2641/LTC2642 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current (IDD) vs Temperature 150 125 VDD = 5V 100 IDD (μA) 75 50 25 0 –40 VDD = 3V IDD (μA) 100 IDD (μA) 75 50 25 100 –15 10 35 TEMPERATURE (°C) 60 85 26412 G19 Supply Current (IDD) vs Supply Voltage (VDD) 150 125 700 600 500 400 300 200 VREF = 2.5V 900 800 Supply Current (IDD) vs Digital Input Voltage VREF = 2.5V VDD = 5V VDD = 3V 0 0 2.5 3 3.5 4 VDD (V) 26412 G20 4.5 5 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 DIGITAL INPUT VOLTAGE (V) 5 26412 G21 Supply Current (IDD) vs VREF, VDD = 5V 150 125 100 IDD (μA) 75 50 25 0 1 1.5 2 2.5 3 VREF (V) 26412 G22 Supply Current (IDD) vs VREF, VDD = 3V 150 125 100 IDD (μA) 75 50 25 0 4.5 5 1 1.5 2 VREF (V) VDD = 3V CS 5V/DIV Midscale Glitch Impulse VDD = 5V VOUT 20mV/DIV CODE 32767 CODE 32768 CODE 32767 LTC2641-16 UNBUFFERED CL = 10pF 2.5 3 26412 G23 500ns/DIV 26412 G24 3.5 4 Full-Scale Transition CS 5V/DIV Full-Scale Settling (Zoomed In) VOUT vs VDD = 0V to 5.5V (POR Function) LTC2641 CS 5V/DIV SETTLE RESIDUE 250μV/DIV VDD = VREF 0V TO 5.5V 2V/DIV VOUT 10mV/DIV VOUT 1V/DIV LTC2641-16 UNBUFFERED CL = 10pF VREF = 2.5V VDD = 5V 500ns/DIV 26412 G25 LTC2641-16 500ns/DIV VREF = 2.5V CONSULT FACTORY FOR MEASUREMENT CIRCUIT 26412 G26 LTC2641-16 UNBUFFERED CL = 10pF 50ms/DIV 26412 G27 26412f 8 LTC2641/LTC2642 PIN FUNCTIONS LTC2641 REF (Pin 1): Reference Voltage Input. Apply an external reference at REF between 2V and VDD. ⎯C⎯S (Pin 2): Serial Interface Chip Select/Load Input. When ⎯C⎯S is low, SCLK is enabled for shifting in data on DIN. When ⎯C⎯S is taken high, SCLK is disabled, the 16-bit input word is latched and the DAC is updated. SCLK (Pin 3): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 4): Serial Interface Data Input. Data is applied to DIN for transfer to the device at the rising edge of SCLK. ⎯C⎯L⎯R (Pin 5): Asynchronous Clear Input. A logic low clears the DAC to code 0. VOUT (Pin 6): DAC Output Voltage. The output range is 0V to VREF. VDD (Pin 7): Supply Voltage. Set between 2.7V and 5.5V. GND (Pin 8): Circuit Ground. Exposed Pad (DFN Pin 9): Circuit Ground. Must be soldered to PCB ground. LTC2642 REF (Pin 1): Reference Voltage Input. Apply an external reference at REF between 2V and VDD. ⎯CS (Pin 2): Serial Interface Chip Select/Load Input. When ⎯ ⎯C⎯S is low, SCLK is enabled for shifting in data on DIN. When ⎯C⎯S is taken high, SCLK is disabled, the 16-bit input word is latched and the DAC is updated SCLK (Pin 3): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 4): Serial Interface Data Input. Data is applied to DIN for transfer to the device at the rising edge of SCLK. ⎯CL⎯R (Pin 5): Asynchronous Clear Input. A logic low clears ⎯ the DAC to midscale. VOUT (Pin 6): DAC Output Voltage. The output range is 0V to VREF. INV (Pin 7): Center Tap of Internal Scaling Resistors. Connect to an external amplifier’s inverting input in bipolar mode. RFB (Pin 8): Feedback Resistor. Connect to an external amplifier’s output in bipolar mode. The bipolar output range is –VREF to VREF. VDD (Pin 9): Supply Voltage. Set between 2.7V and 5.5V. GND (Pin 10): Circuit Ground. Exposed Pad (DFN Pin 11): Circuit Ground. Must be soldered to PCB ground. 26412f 9 LTC2641/LTC2642 BLOCK DIAGRAMS LTC2641 7 VDD LTC2641-16 LTC2641-14 LTC2641-12 POWER-ON RESET 2 3 4 5 CS SCLK DIN CLR CONTROL LOGIC 16-BIT DATA LATCH 16-BIT SHIFT REGISTER VOUT 1 REF LTC2642-16 LTC2642-14 LTC2642-12 POWER-ON RESET 2 3 4 GND 8 2641 BD LTC2642 9 VDD 1 REF RFB INV 8 7 16-/14-/12-BIT DAC 6 CS SCLK DIN CLR 16-/14-/12-BIT DAC VOUT 6 CONTROL LOGIC 16-BIT DATA LATCH 16-BIT SHIFT REGISTER 5 GND 10 2642 BD TIMING DIAGRAM t1 t2 SCK 1 t3 2 t4 3 15 t6 16 t8 SDI t5 CS/LD t7 26412 TD OPERATION General Description The LTC2641/LTC2642 family of 16-/14-/12-bit voltage output DACs offer full 16-bit performance with less than ±2LSB integral linearity error and less than ±1LSB differential linearity error, guaranteeing monotonic operation. They operate from a single supply ranging from 2.7V to 5.5V, consuming 120μA (typical). An external voltage reference of 2V to VDD determines the DAC’s full-scale output voltage. A 3-wire serial interface allows the LTC2641/LTC2642 to fit into a small 8-/10-pin MSOP or DFN 3mm × 3mm package. Digital-to-Analog Architecture The DAC architecture is a voltage switching mode resistor ladder using precision thin-film resistors and CMOS switches. The LTC2641/LTC2642 DAC resistor ladders are composed of a proprietary arrangement of matched DAC sections. The four MSBs are decoded to drive 15 equally weighted segments, and the remaining lower bits drive successively lower weighted sections. Major carry glitch impulse is very low at 500pV•sec, CL = 10pF, ten times lower than previous DACs of this type. 26412f 10 LTC2641/LTC2642 OPERATION The digital-to-analog transfer function at the VOUT pin is: ⎛k⎞ VOUT(IDEAL) = ⎜ N ⎟ VREF ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is between 2.0V and VDD (see Tables 1a, 1b and 1c). The LTC2642 includes matched resistors that are tied to an external amplifier to provide bipolar output swing (Figure 2). The bipolar transfer function at the RFB pin is: ⎞ ⎛k VOUT _ BIPOLAR(IDEAL) = VREF ⎜ N–1 – 1 ⎟ ⎠ ⎝2 (see Tables 2a, 2b and 2c). Serial Interface The LTC2641/LTC2642 communicates via a standard 3-wire SPI/QSPI/MICROWIRE compatible interface. The CS DAC UPDATED chip select input (⎯C⎯S) controls and frames the loading of serial data from the data input (DIN). Following a ⎯C⎯S high-to-low transition, the data on DIN is loaded, MSB first, into the shift register on each rising edge of the serial clock input (SCLK). After 16 data bits have been loaded into the serial input register, a low-to-high transition on ⎯C⎯S transfers the data to the 16-bit DAC latch, updating the DAC output (see Figures 1a, 1b, 1c). While ⎯C⎯S remains high, the serial input shift register is disabled. If there are less than 16 low-to-high transitions on SCLK while ⎯C⎯S remains low, the data will be corrupted, and must be reloaded. Also, if there are more than 16 low-to-high transitions on SCLK while ⎯C⎯S remains low, only the last 16 data bits loaded from DIN will be transferred to the DAC latch. For the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB remains in the same (left-justified) position in the input 16-bit data word. Therefore, two “don’t-care” bits must be loaded after the LSB, to make up the required 16 data bits (Figure 1b). Similarly, for the 12-bit family members (LTC2641-12/LTC2642-12) four “don’t-care” bits must follow the LSB (Figure 1c). SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DIN D15 D14 D13 D12 D11 D10 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 26412 F01a DATA (16 BITS) Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16) CS DAC UPDATED SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DIN D13 D12 D11 D10 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB X X 26412 F01b DATA (14 BITS + 2 DON’T-CARE BITS) Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14) CS DAC UPDATED SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DIN D11 D10 MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB X X X X 26412 F01c DATA (12 BITS + 4 DON’T-CARE BITS) Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12) 26412f 11 LTC2641/LTC2642 OPERATION Power-On Reset The LTC2641/LTC2642 include a power-on reset circuit to ensure that the DAC ouput comes up in a known state. When VDD is first applied, the power-on reset circuit sets the output of the LTC2641 to zero-scale (code 0). The LTC2642 powers up to midscale (bipolar zero). Depending on the DAC number of bits, the midscale code is: 32,768 (LTC2642-16); 8,192 (LTC2642-14); or 2,048 (LTC2642-12). Clearing the DAC A 10ns (minimum) low pulse on the ⎯C⎯L⎯R pin asynchronously clears the DAC latch to code zero (LTC2641) or to midscale (LTC2642). APPLICATIONS INFORMATION Unipolar Configuration Figure 2 shows a typical unipolar DAC application for the LTC2641. Tables 1a, 1b and 1c show the unipolar binary code tables for 16-bit, 14-bit and 12-bit operation. VREF 2.5V OUT 5V/3V 0.1μF 4.7μF GND 0.1μF 7 VDD LTC2641-16 2 16-BIT DAC VOUT 6 1 REF 5V/3V 0.1μF IN 5V The external amplifier provides a unity-gain buffer. The LTC2642 can also be used in unipolar configuration by tying RFB and INV to REF. This provides power-up and clear to midscale. LT®1019CS8-2.5 Table 1a. 16-Bit Unipolar Binary Code Table (LTC2641-16) DIGITAL INPUT BINARY NUMBER IN DAC LATCH MSB UNIPOLAR VOUT 0V TO 2.5V ANALOG OUTPUT (VOUT) LSB 1/2 LTC6078 CS 3 SCLK 4 DIN 5 CLR GND 8 26412 F02 Figure 2. 16-Bit Unipolar Output (LTC2641-16) Unipolar VOUT = 0V to VREF Table 1b. 14-Bit Unipolar Binary Code Table (LTC2641-14) DIGITAL INPUT BINARY NUMBER IN DAC LATCH MSB LSB ANALOG OUTPUT (VOUT) 1111 1111 1111 11xx VREF (16,383/16,384) 1000 0000 0000 00xx VREF (8,192/16,384) = VREF/2 0000 0000 0000 01xx VREF (1/16,384) 0000 0000 0000 00xx 0V 12 + MSB – 1111 1111 1111 1111 VREF (65,535/65,536) 1000 0000 0000 0000 VREF (32,768/65,536) = VREF/2 0000 0000 0000 0001 VREF (1/65,536) 0000 0000 0000 0000 0V Table 1c. 12-Bit Unipolar Binary Code Table (LTC2641-12) DIGITAL INPUT BINARY NUMBER IN DAC LATCH LSB ANALOG OUTPUT (VOUT) 1111 1111 1111 xxxx VREF (4,095/4,096) 1000 0000 0000 xxxx VREF (2,048/4,096) = VREF/2 0000 0000 0001 xxxx VREF (1/4,096) 0000 0000 0000 xxxx 0V 26412f LTC2641/LTC2642 APPLICATIONS INFORMATION Bipolar Configuration Figure 3 shows a typical bipolar DAC application for the LTC2642. The on-chip bipolar offset/gain resistors, RFB and RINV, are connected to an external amplifier to produce a bipolar output swing from –VREF to VREF at the RFB pin. 5V/3V VREF 2.5V OUT 0.1μF 9 VDD LTC2642-16 INV 7 1 REF RFB 8 C1 10pF 5V 0.1μF 0.1μF 4.7μF GND IN 5V The amplifier circuit provides a gain of +2 from the VOUT pin, and gain of –1 from VREF. Tables 2a, 2b and 2c show the bipolar offset binary code tables for 16-bit, 14-bit and 12-bit operation. LT1019CS8-2.5 CS 3 SCLK 4 DIN 5 CLR 16-BIT DAC GND 10 26412 F02 Figure 3. 16-Bit Bipolar Output (LTC2642-16) VOUT = –VREF to VREF Table 2a. 16-Bit Bipolar Offset Binary Code Table (LTC2642-16) DIGITAL INPUT BINARY NUMBER IN DAC LATCH MSB LSB ANALOG OUTPUT (VOUT) Table 2b. 14-Bit Bipolar Offset Binary Code Table (LTC2642-14) DIGITAL INPUT BINARY NUMBER IN DAC LATCH MSB LSB ANALOG OUTPUT (VOUT) 1111 1111 1111 1111 VREF (32,767/32,768) 1000 0000 0000 0001 VREF (1/32,768) 1000 0000 0000 0000 0V 0111 1111 1111 1111 –VREF (1/32,768) 0000 0000 0000 0000 –VREF 1111 1111 1111 11xx VREF (8,191/8,192) 1000 0000 0000 01xx VREF (1/8,192) 1000 0000 0000 00xx 0V 0111 1111 1111 11xx –VREF (1/8,192) 0000 0000 0000 00xx –VREF + –5V 2 VOUT 6 – 1/2 LT1678 0.1μF BIPOLAR VOUT –2.5V TO 2.5V Table 2c. 12-Bit Bipolar Offset Binary Code Table (LTC2642-12) DIGITAL INPUT BINARY NUMBER IN DAC LATCH MSB LSB ANALOG OUTPUT (VOUT) 1111 1111 1111 xxxx VREF (2,047/2,048) 1000 0000 0001 xxxx VREF (1/2,048) 1000 0000 0000 xxxx 0V 0111 1111 1111 xxxx –VREF (1/2048) 0000 0000 0000 xxxx –VREF 26412f 13 LTC2641/LTC2642 APPLICATIONS INFORMATION Unbuffered Operation and VOUT Loading The DAC output is available directly at the VOUT pin, which swings from GND to VREF. Unbuffered operation provides the lowest possible offset, full-scale and linearity errors, the fastest settling time and minimum power consumption. However, unbuffered operation requires that appropriate loading be maintained on the VOUT pin. The LTC2641/ LTC2642 VOUT can be modeled as an ideal voltage source in series with a source resistance of ROUT, typically 6.2k (Figure 4). The DAC’s linear output impedance allows it to drive medium loads (RL > 60k) without degrading INL or DNL; only the gain error is increased. The gain error (GE) caused by a load resistance, RL, (relative to full scale) is: –1 GE = ⎛R ⎞ 1+ ⎜ OUT ⎟ ⎝ RL ⎠ In 16-bit LSBs: GE = –65536 [LSB] ⎛ ROUT ⎞ 1+ ⎜ ⎝ RL ⎟ ⎠ it is critical to protect the VOUT pin from any sources of leakage current. Unbuffered VOUT Settling Time The settling time at the VOUT pin can be closely approximated by a single-pole response where: τ = ROUT • (COUT + CL) (Figure 4). Settling to 1/2LSB at 16-bits requires about 12 time constants (ln(2 • 65,536)). The typical settling time of 1μs corresponds to a time constant of 83ns, and a total (COUT + CL) of about 83ns/6.2k = 13pF. The internal capacitance, COUT is typically 10pF, so an external CL of 3pF corresponds to 1μs settling to 1/2LSB. VREF LTC2641 LTC2642 CODE VREF 2N REF ROUT VOUT COUT RL CL IL ( )– + GND VOUT 0V TO VREF 26412 F04 Figure 4. VOUT Pin Equivalent Circuit Op Amp Selection The optimal choice for an external buffer op amp depends on whether the DAC is used in the unipolar or bipolar mode of operation, and also depends on the accuracy, speed, power dissipation and board area requirements of the application. The LTC2641/LTC2642’s combination of tiny package size, rail-to-rail single supply operation, low power dissipation, fast settling and nearly ideal accuracy specifications makes it impractical for one op amp type to fit every application. In bipolar mode (LTC2642 only), the amplifier operates with the internal resistors to provide bipolar offset and scaling. In this case, a precision amplifier operating from dual power supplies, such as the the LT1678 provides the ±VREF output range (Figure 3). In unipolar mode, the output amplifier operates as a unity gain voltage follower. For unipolar, single supply applications a precision, rail-to-rail input, single supply op amp 26412f ROUT has a low tempco (typically < ±50ppm/°C), and is independent of DAC code. The variation of ROUT, part-topart, is typically less than ±20%. Note on LSB units: For the following error descriptions, “LSB” means 16-bit LSB and 65,536 is rounded to 66k. To convert to 14-bit LSBs (LTC2641-14/LTC2642-14) divide by 4. To convert to 12-bit LSBs (LTC2641-12/LTC2642-12) divide by 16. A constant current, IL, loading VOUT will produce an offset of: VOFFSET = –IL • ROUT For VREF = 2.5V, a 16-bit LSB equals 2.5V/65,536, or 38μV. Since ROUT is 6.2k, an IL of 6nA produces an offset of 1LSB. Therefore, to avoid degrading DAC performance, 14 LTC2641/LTC2642 APPLICATIONS INFORMATION such as the LTC6078 is suitable, if the application does not require linear operation very near to GND, or zero scale (Figure 2). The LTC6078 typically swings to within 1mV of GND if it is not required to sink any load current. For an LSB size of 38μV, 1mV represents 26 missing codes near zero scale. Linearity will be degraded over a somewhat larger range of codes above GND. It is also unavoidable that settling time and transient performance will degrade whenever a single supply amplifier is operated very close to GND, or to the positive supply rail. The small LSB size of a 16-bit DAC, coupled with the tight accuracy specifications on the LTC2641/LTC2642, means that the accuracy and input specifications for the external op amp are critical for overall DAC performance. Op Amp Specifications and Unipolar DAC Accuracy Most op amp accuracy specifications convert easily to DAC accuracy. Op amp input bias current on the noninverting (+) input is equivalent to an IL loading the DAC VOUT pin and therefore produces a DAC zero-scale error (ZSE) (see Unbuffered Operation): ZSE = –IB(IN+) • ROUT [Volts] In 16-bit LSBs: ⎛ 66k ⎞ ZSE = –IB IN+ • 6.2k • ⎜ [LSB] ⎝ VREF ⎟ ⎠ Op amp input impedance, RIN, is equivalent to an RL loading the LTC2641/LTC2642 VOUT pin, and produces a gain error of: GE = –66k [LSB] ⎛ 6.2k ⎞ 1+ ⎜ ⎝ RIN ⎟ ⎠ voltage temperature coefficient (referenced to 25°C) of 0.6μV/°C will add 1LSB of zero-scale error. Also, IBIAS and the VOFFSET error it causes, will typically show significant relative variation over temperature. Op amp open-loop gain, AVOL, contributes to DAC gain error (GE): GE = 66k [LSB] A VOL Op amp input common mode rejection ratio (CMRR) is an input-referred error that corresponds to a combination of gain error (GE) and INL, depending on the op amp architecture and operating conditions. A conservative estimate of total CMRR error is: ⎛ ⎛ CMRR⎞ ⎞ ⎟ ⎜ Error = ⎜10⎝ 20 ⎠ ⎟ ⎟ ⎜ ⎝ ⎠ ⎛V ⎞ • ⎜ CMRR _ RANGE ⎟ • 66k [LSB] VREF ⎝ ⎠ () where VCMRR_RANGE is the voltage range that CMRR (in dB) is specified over. Op amp Typical Performance Characteristics graphs are useful to predict the impact of CMRR errors on DAC performance. Typically, a precision op amp will exhibit a fairly linear CMRR behavior (corresponding to DAC gain error only) over most of the common mode input range (CMR), and become nonlinear and produce significant errors near the edge of the CMR. Rail-to-rail input op amps are a special case, because they have 2 distinct input stages, one with CMR to GND and the other with CMR to V+. This results in a “crossover” CM input region where operation switches between the two input stages. The LTC6078 rail-to-rail input op amp typically exhibits remarkably low crossover linearity error, as shown in the VOS vs VCM Typical Performance Characteristics graphs (see the LTC6078 data sheet). Crossover occurs at CM inputs about 1V below V+, and an LTC6078 operating as a unipolar DAC buffer with VREF = 2.5V and V+ = 5V will typically add only about 1LSB of GE and almost no INL error due to CMRR. Even in a full rail-to-rail application, with VREF = V+ = 5V, a typical LTC6078 will add only about 1LSB of INL at 16-bits. 26412f Op amp offset voltage, VOS, corresponds directly to DAC zero code offset error, ZSE: ZSE = VOS • 66k [LSB] VREF Temperature effects also must be considered. Over the –40°C to 85°C industrial temperature range, an offset 15 LTC2641/LTC2642 APPLICATIONS INFORMATION Op Amp Specifications and Bipolar DAC Accuracy The op amp contributions to unipolar DAC error discussed above apply equally to bipolar operation. The bipolar application circuit gains up the DAC span, and all errors, by a factor of 2. Since the LSB size also doubles, the errors in LSBs are identical in unipolar and bipolar modes. One added error in bipolar mode comes from IB (IN–), which flows through RFB to generate an offset. The full bias current offset error becomes: VOFFSET = (IB (IN–) • RFB – IB (IN+) • ROUT • 2) [Volts] So: VOFFSET = IB (IN– ) • 28k – IB (IN+ ) • 12.4k • Settling Time with Op Amp Buffer When using an external op amp, the output settling time will still include the single pole settling on the LTC2641/LTC2642 VOUT node, with time constant ROUT • (COUT + CL) (see Unbuffered VOUT Settling Time). CL will include the buffer input capacitance and PC board interconnect capacitance. The external buffer amplifier adds another pole to the output response, with a time constant equal to (fbandwidth/2π). For example, assume that CL is maintained at the same value as above, so that the VOUT node time constant is 83ns = 1μs/12. The output amplifier pole will also have a time constant of 83ns if the closed-loop bandwidth equals (1/2π • 83ns) = 1.9MHz. The effective time constant of two cascaded single-pole sections is approximately the root square sum of the individual time constants, or √⎯2 • 83ns = 117ns, and 1/2 LSB settling time will be ~12 • 117ns = 1.4μs. This represents an ideal case, with no slew limiting and ideal op amp phase margin. In practice, it will take a considerably faster amplifier, as well as careful attention to maintaining good phase margin, to approach the unbuffered settling time of 1μs. The output settling time for bipolar applications (Figure 3) will be somewhat increased due to the feedback resistor network RFB and RINV (each 28k nominal). The parasitic capacitance, CP, on the op amp (–) input node will introduce a feedback loop pole with a time constant of (CP • 28k/2). A small feedback capacitor, C1, should be included, to introduce a zero that will partially cancel this pole. C1 should nominally be