LTC2704CGW-14

LTC2704 Quad 12-, 14- and 16-Bit Voltage Output SoftSpan DACs with Readback FEATURES ■ DESCRIPTIO ■ ■ ■ ■ ■ ■ ■ ■ Six Programmable Output Ranges: Unipolar: 0V to 5V, 0V to 10V Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V Serial Readback of All On-Chip Registers 1LSB INL and DNL Over the Industrial Temperature Range (LTC2704-14/LTC2704-12) Force/Sense Outputs Enable Remote Sensing Glitch Impulse: < 2nV-sec Outputs Drive ±5mA Pin Compatible 12-, 14- and 16-Bit Parts Power-On and Clear to Zero Volts 44-Lead SSOP Package The LTC®2704-16/LTC2704-14/LTC2704-12 are serial input, 12-, 14- or 16-bit, voltage output SoftSpan™ DACs that operate from 3V to 5V logic and ±5V to ±15V analog supplies. SoftSpan offers six output spans—two unipolar and four bipolar—fully programmable through the 3-wire SPI serial interface. INL is accurate to 1LSB (2LSB for the LTC2704-16). DNL is accurate to 1LSB for all versions. Readback commands allow verification of any on-chip register in just one 24- or 32- bit instruction cycle. All other commands produce a “rolling readback” response from the LTC2704, dramatically reducing the needed number of instruction cycles. A Sleep command allows any combination of DACs to be powered down. There is also a reset flag and an offset adjustment pin for each channel. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ Process Control and Industrial Automation Direct Digital Waveform Generation Software Controlled Gain Adjustment Automated Test Equipment SI PLIFIED BLOCK DIAGRA AGND 32 VOSB 40 C1B 39 RFBB 37 DAC B OUTB 38 AGNDB 41 VOSA 4 C1A 5 RFBA 7 DAC A OUTA 6 AGNDA 3 33 34 10 13 11 SDI 14 CLR 9 35 –1 –1 V+ 1 42 44 2 43 24 21 V– REFM1 REFG1 REF1 REF2 REFG2 REFM2 V+2 1,8,15,22,31,36 23 25 27 VOSC 28 C1C DAC C 30 RFBC 29 OUTC 26 AGNDC 19 VOSD 18 C1D 16 RFBD DAC D 17 OUTD 20 AGNDD 12 2704 BD INL (LSB) GND VDD CS/LD SCK LDAC RFLAG SRO U LTC2704-16 Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2704 TA01b W U W V+/V – = ±15V VREF = 5V ±10V RANGE ALL 4 DACS SUPERIMPOSED 2704f 1 LTC2704 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW V– REFG1 AGNDA VOSA C1A OUTA RFBA V– LDAC 1 2 3 4 5 6 7 8 9 44 REFM1 43 REF1 42 V+1 41 AGNDB 40 VOSB 39 C1B 38 OUTB 37 RFBB 36 V– 35 RFLAG 34 VDD 33 GND 32 AGND 31 V– 30 RFBC 29 OUTC 28 C1C 27 VOSC 26 AGNDC 25 V+2 24 REF2 23 REFM2 Total Supply Voltage V+1, V+2 to V – ........... –0.3V to 36V V+1, V+2, REF1, REF2, REFM1, REFM2, OUTx, RFBx, VOSx to GND, AGND, AGNDx, C1x, REFG1, REFG2 ................................... 18V GND, AGND, AGNDx, C1x, REFG1, REFG2 to V+1, V+2, V –, REF1, REF2, REFM1, REFM2, OUTx, RFBx, VOSx ............................................................... 18V OUTA, RFBA, VOSA, OUTB, RFBB, VOSB, REF1, REFM1 to GND, AGND ............... V– – 0.3V to V+1 + 0.3V OUTC, RFBC, VOSC, OUTD, RFBD, VOSD, REF2, REFM2 to GND, AGND ........................... V– – 0.3V to V+2 + 0.3V VDD, Digital Inputs/Outputs to GND ............. –0.3V to 7V Digital Inputs/Outputs to VDD ................................. 0.3V GND, AGNDx, REFG1, REFG2 to AGND ................ ±0.3V C1x to AGNDx ....................................................... ±0.3V V– to Any Pin .......................................................... 0.3V Maximum Junction Temperature ......................... 150°C Operating Temperature Range LTC2704C ............................................... 0°C to 70°C LTC2704I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC2704CGW-16 LTC2704IGW-16 LTC2704CGW-14 LTC2704IGW-14 LTC2704CGW-12 LTC2704IGW-12 CS/LD 10 SDI 11 SRO 12 SCK 13 CLR 14 V– 15 RFBD 16 OUTD 17 C1D 18 VOSD 19 AGNDD 20 REFG2 21 V – 22 GW PACKAGE 44-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 80°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Accuracy Resolution Monotonicity INL Integral Nonlinearity DNL Differential Nonlinearity GE Gain Error Gain Temperature Coefficient VOS Unipolar Zero-Scale Error CONDITIONS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. LTC2704-12 MIN TYP MAX ● ● LTC2704-14 MIN TYP MAX 14 14 LTC2704-16 MIN TYP MAX 16 16 UNITS Bits Bits LSB LSB LSB ppm/°C µV µV µV µV 12 12 ±1 ±1 ±2 VREF = 5V VREF = 5V VREF = 5V ∆Gain/∆Temperature Span = 0V to 5V, TA = 25°C Span = 0V to 10V, TA = 25°C Span = 0V to 5V Span = 0V to 10V ● ● ● ● ±0.5 ±2 ±80 ±100 ±140 ±150 ±1 ±2 ±80 ±100 ±140 ±150 ±1 ±1 ±5 ±4 ±2 ±80 ±100 ±140 ±150 ±2 ±1 ±20 ● ● ±200 ±300 ±400 ±600 ±200 ±300 ±400 ±600 ±200 ±300 ±400 ±600 2 U W U U WW W 2704f LTC2704 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VOS Temperature Coefficient BZE Bipolar Zero Error PSRR Power Supply Rejection Ratio CONDITIONS 0V to 5V Range 0V to 10V Range All Bipolar Ranges The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. LTC2704-12 MIN TYP MAX ±2 ±2 ±0.25 ±1 ±2 ±0.003 ±0.006 ±0.001 ±0.06 ±0.002 ±0.05 3 5 8 ● ● ● ● ● ● ● ● VDD = 5V ±10% (Note 3) VDD = 3V ±10% (Note 3) 0V to 10V Range, Code = 0 ● V+/V– = ±15V ±10% (Note 2) V+/V– = ±5V ±10%, VREF = 2V (Note 2) ● LTC2704-14 MIN TYP MAX ±2 ±2 ±0.5 ±2 ±2.5 ±0.013 ±0.025 ±0.005 ±0.25 ±0.01 ±0.13 3.5 5.5 9 LTC2704-16 MIN TYP MAX ±2 ±2 ±2 ±8 ±10 ±0.05 ±0.1 ±0.02 ±0.04 4 6 10 ±1 ±0.5 UNITS µV/°C µV/°C LSB LSB LSB/V LSB/V LSB/V LSB/V µs µs µs V V mA mA Analog Outputs (Note 4) Settling Time ISC SR 0V to 5V Range, 5V Step, to ±1LSB 0V to 10V or ±5V Range, 10V Step, to ±1LSB ±10V Range, 20V Step, to ±1LSB Output Swing V+/V– = ±15V, VREF = ±7.25V, 0V to 10V Range, ILOAD = ±3mA (Note 2) V+/V– = ±5V, VREF = ±2.25V, 0V to 10V Range, ILOAD = ±3mA (Note 2) Load Current V+/V– = ±10.8V to ±16.5V, VREF = ±5V, 0V to 10V Range, VOUT = ±10V (Note 2) V+/V– = ±4.5V to ±16.5V, VREF = ±2V, 0V to 10V Range, VOUT = ±4V (Note 2) Load Regulation V+/V– = ±15V, VREF = 5V, 0V to 10V Range, Code = 0, ±5mA Load (Note 2) V+/V– = ±5V, VREF = 2V, 0V to 10V Range, Code = 0, ±3mA Load (Note 2) Output VREF = 5V, 0V to 10V Range, Impedance Code = 0, ±5mA Load Short-Circuit V+/V– = ±16.5V, VREF = 5V, ±10V Range Current Code = 0, VOUT Shorted to V+ (Note 2) Code = Full Scale, VOUT Shorted to V– V+/V– = ±5.5V, VREF = 2V, ±10V Range Code = 0, VOUT Shorted to V+ (Note 2) Code = Full Scale, VOUT Shorted to V– Slew Rate RL= 2k, V+/V– = ±15V (Note 2) RL= 2k, V+/V– = ±5V (Note 2) Capacitive Load Within Maximum Load Current Driving –14.5 –4.5 14.5 4.5 ±5 ±3 ±0.005 ±0.01 –14.5 –4.5 14.5 4.5 ±5 ±3 ±0.01 ±0.013 –14.5 –4.5 14.5 4.5 ±5 ±3 ±0.04 LSB/mA ±0.05 LSB/mA Ω ● ● 0.015 0.006 0.006 ● ● ● ● ● ● 38 –36 38 –36 2.2 2.0 3 2.8 1000 –36 2.2 2.0 3 2.8 1000 –36 38 –36 38 –36 2.2 2.0 3 2.8 1000 38 mA mA mA mA V/µs V/µs pF 38 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. SYMBOL PARAMETER Reference Inputs REF1, REF2 Input Voltage Resistances RREF1, RREF2 Reference Input Resistance RFBx Output Feedback Resistance RVOSX Offset Adjust Input Resistance CONDITIONS V+/V– = ±15V, 0V to 5V Span (Note 2) ● ● ● ● MIN –14.5 5 7 700 TYP MAX 14.5 UNITS V kΩ kΩ kΩ 2704f 7 10 1000 3 LTC2704 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C, V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V. SYMBOL PARAMETER AC Performance (Note 4) Glitch Impulse Crosstalk CONDITIONS 0V to 5V Range, Midscale Transition 10V Step on VOUTA DAC B: 0V to 5V Range, Full Scale DAC B: 0V to 10V Range, Full Scale ±10V Range, Midscale 0V to 10V Range, VREF = ±5V, 10kHz Sine Wave Span = 0V to 5V, Full Scale Span = 0V to 10V, Full Scale 10kHz Span = 0V to 5V, Midscale Span = 0V to 10V, Midscale 0.1Hz to 10Hz Span = 0V to 5V, Midscale Span = 0V to 10V, Midscale Digital Inputs = 0V or VDD V+/V– = ±15V, ±10%; VREF = 5V, VOUT = 0V (Note 2) V+/V– = ±5V, ±10%; VREF = 2V, VOUT = 0V (Note 2) Sleep Mode—All DACs (Note 4) ● ● ● ● ● ● ● MIN TYP 2 2 3 0.2 0.35 300 250 30 50 0.8 1.2 0.5 17.5 17.0 MAX UNITS nV-s nV-s nV-s nV-s mVP-P kHz kHz nV/√Hz nV/√Hz µVRMS µVRMS Digital Feedthrough Multiplying Feedthrough Error Multiplying Bandwidth Output Noise Voltage Density Output Noise Voltage Power Supply IDD Supply Current, VDD IS Supply Current, V+/V– VDD Logic Supply Voltage V+1/V+2 Positive Analog Supply Voltage V– Negative Analog Supply Voltage Digital Inputs/Outputs VIH Digital Input High Voltage VIL VOH VOL IIN CIN Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Current Digital Input Capacitance 2.7 4.5 –16.5 2.4 2.0 2 20 18 1 5.5 16.5 – 4.5 µA mA mA mA V V V V V V V V V µA pF VDD = 2.7V to 5.5V VDD = 2.7V to 3.3V VDD = 2.7V to 5.5V VDD = 4.5V to 5.5V IOH = 200µA IOL = 200µA VIN = 0V (Note 3) ● ● ● ● 0.6 0.8 0.4 ±1 5 ● VCC – 0.4 ● ● ● 0.001 TI I G CHARACTERISTICS range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER VDD = 4.5V to 5.5V t1 SDI Valid to SCK Setup t2 SDI Valid to SCK Hold t3 SCK High Time t4 SCK Low Time t5 CS/LD Pulse Width t6 LSB SCK High to CS/LD High t7 CS/LD Low to SCK Positive Edge t8 CS/LD High to SCK Positive Edge t9 SRO Propagation Delay t10 CLR Pulse Width 4 UW The ● denotes specifications which apply over the full operating temperature CONDITIONS ● ● ● ● ● ● ● ● MIN 7 7 11 11 9 0 12 12 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns 2704f CLOAD = 10pF ● ● 18 50 LTC2704 TI I G CHARACTERISTICS range, otherwise specifications are at TA = 25°C. SYMBOL t11 t12 t13 PARAMETER LDAC Pulse Width CLR Low to RFLAG Low CS/LD High to RFLAG High SCK Frequency VDD = 2.7V to 3.3V t1 SDI Valid to SCK Setup t2 SDI Valid to SCK Hold t3 SCK High Time t4 SCK Low Time t5 CS/LD Pulse Width t6 LSB SCK High to CS/LD High t7 CS/LD Low to SCK Positive Edge t8 CS/LD High to SCK Positive Edge t9 SRO Propagation Delay t10 CLR Pulse Width t11 LDAC Pulse Width t12 CLR Low to RFLAG Low t13 CS/LD High to RFLAG High SCK Frequency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The notation V+ is used to denote both V+1 and V+2 when the same voltage is applied to both pins. Note 3: Guaranteed by design, not subject to test. TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-16 Integral Nonlinearity (INL) V+/V – = ±15V 0.8 VREF = 5V ±10V RANGE 0.6 0.4 DNL (LSB) 1.0 INL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2704 G01 UW UW The ● denotes specifications which apply over the full operating temperature CONDITIONS ● MIN 15 TYP MAX 50 40 40 CLOAD = 10pF (Note 3) CLOAD = 10pF (Note 3) 50% Duty Cycle (Note 5) ● ● ● ● ● ● ● ● ● ● ● UNITS ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 9 9 15 15 12 0 12 12 26 90 20 70 60 25 CLOAD = 10pF ● ● ● CLOAD = 10pF CLOAD = 10pF 50% Duty Cycle (Note 5) ● ● ● Note 4: Measured in unipolar 0V to 5V mode. Note 5: When using SRO, maximum SCK frequency fMAX is limited by SRO propagation delay as follows: ⎛ ⎞ 1 fMAX = ⎜ ⎟ , where ts is the setup time of the receiving ⎝ 2 (t 9 + t S)⎠ device. Differential Nonlinearity (DNL) V+/V– = ±15V 0.8 VREF = 5V ±10V RANGE 0.6 INL vs VREF 1.0 V+/V– = ±15V 0.8 ±5V RANGE 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 MIN MAX MAX 1.0 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2704 G02 MIN –1.0 –10 –8 –6 –4 –2 0 2 VREF (V) 4 6 8 10 2704 G03 2704f 5 LTC2704 TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-16 INL vs Temperature 1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 –0.2 –0.4 –O.6 –0.8 –1.0 –50 –30 30 50 –10 10 TEMPERATURE (°C) 70 90 MIN V+/V– = ±15V VREF = 5V ±10V RANGE MAX DNL (LSB) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –O.6 –0.8 –1.0 –50 –30 30 50 –10 10 TEMPERATURE (°C) 70 90 –600 –50 –30 30 50 –10 10 TEMPERATURE (°C) 70 MAX OFFSET (µV) Bipolar Zero vs Temperature 8 6 4 GAIN ERROR (LSB) 2 V+/V– = ±15V VREF = 5V ±10V RANGE 16 12 8 4 0 –4 –8 –12 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 LSB 0 –2 –4 –6 –8 –50 Settling 0V to 5V VOUT 5V/DIV VOUT 1mV/DIV CS/LD 5V/DIV 2.5µs/DIV 2704 G18 6 UW 2704 G04 DNL vs Temperature V+/V– = ±15V VREF = 5V ±10V RANGE 600 400 200 0 Offset vs Temperature V+/V– = ±15V VREF = 5V 0V TO 10V RANGE MIN –200 –400 90 2704 G05 2704 G06 Gain Error vs Temperature V+/V– = ±15V VREF = 5V ±10V RANGE –16 –50 –30 30 50 –10 10 TEMPERATURE (°C) 70 90 2704 G07 2704 G08 Settling 0V to 10V Settling ±10V VOUT 10V/DIV VOUT 5V/DIV VOUT 1mV/DIV VOUT 1mV/DIV CS/LD 5V/DIV 2.5µs/DIV 2704 G19 CS/LD 5V/DIV 2.5µs/DIV 2704 G20 2704f LTC2704 TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-14 Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 0.2 V+/V– = ±15V VREF = 5V ±10V RANGE 1.0 0.8 0.6 0.4 0.2 LSB 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16383 2704 G09 LSB LTC2704-12 Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 0.2 LSB 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1536 1024 2048 2560 3072 3584 4095 CODE 2704 G11 V+/V– = ±15V VREF = 5V ±10V RANGE LSB LTC2704-16/LTC2704-14/LTC2704-12 Positive Slew Negative Slew CS/LD 5V/DIV 5V/DIV V+/V– = ±15V VREF = 5V ±10V RANGE 20V STEP 2.5µs/DIV UW 2704 G13 Differential Nonlinearity (DNL) V+/V– = ±15V VREF = 5V ±10V RANGE 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16383 2704 G10 Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1536 1024 2048 2560 3072 3584 4095 CODE 2704 G12 V+/V– = ±15V VREF = 5V ±10V RANGE Midscale Glitch 5V/DIV VOUT 2mV/DIV V+/V– = ±15V VREF = 5V ±10V RANGE 20V STEP 2.5µs/DIV 2704 G14 2.5µs/DIV 2704 G15 2704f 7 LTC2704 TYPICAL PERFOR A CE CHARACTERISTICS LTC2704-16/LTC2704-14/LTC2704-12 0.1Hz to 10Hz Noise 3.5 3.0 2.5 ICC (mA) 1µV/DIV V+/V– = ±15V VREF = 5V 0V TO 5V RANGE CODE = 0 PI FU CTIO S V– (Pins 1, 8, 15, 22, 31, 36): Analog Negative Supply, Typically –15V. –4.5V to –16.5V Range. REFG1 (Pin 2): Reference 1 Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. AGNDA (Pin 3): DAC A Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. VOSA (Pin 4): Offset Adjust for DAC A. Nominal input range is ±5V. VOS(DAC A) = –0.01• V(VOSA) [0V to 5V, ±2.5V modes]. See Operation section. C1A (Pin 5): Feedback Capacitor Connection for DAC A Output. This pin provides direct access to the negative input of the channel A output amplifier. OUTA (Pin 6): DAC A Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBA as close to the load as possible. RFBA (Pin 7): DAC A Output Feedback Resistor Pin. LDAC (Pin 9): Asynchronous DAC Load Input. When LDAC is a logic low, all DACs are updated. CS/LD (Pin 10): Synchronous Chip Select and Load Pin. SDI (Pin 11): Serial Data Input. Data is clocked in on the rising edge of the serial clock when CS/LD is low. SRO (Pin 12): Serial Readback Data Output. Data is clocked out on the falling edge of SCK. Readback data begins clocking out after the last address bit A0 is clocked in. SCK (Pin 13): Serial Clock. CLR (Pin 14): Asynchronous Clear Pin. When this pin is low, all code and span B2 registers are cleared to zero. All DAC outputs are cleared to zero volts. RFBD (Pin 16): DAC D Voltage Output Feedback Resistor Pin. OUTD (Pin 17): DAC D Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBD as close to the load as possible. 8 UW 1s/DIV VCC Supply Current vs Logic Voltage VDD = 5V SCK, SDI, CS/LD, LDAC CLR TIED TOGETHER 2.0 1.5 1.0 2704 G16 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC VOLTAGE (V) 2704 G17 U U U 2704f LTC2704 PI FU CTIO S C1D (Pin 18): Feedback Capacitor Connection for DAC D Output. This pin provides direct access to the negative input of the channel D output amplifier. VOSD (Pin 19): Offset Adjust for DAC D. Nominal input range is ±5V. VOS(DAC D) = –0.01• V(VOSD) [0V to 5V, ±2.5V modes]. See Operation section. AGNDD (Pin 20): DAC D Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. REFG2 (Pin 21): Reference 2 Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. REFM2 (Pin 23): Reference 2 Inverting Amp Output. The gain from REF2 to REFM2 is –1. Can swing to within 0.5V of the analog supplies V+/V–. REF2 (Pin 24): DAC C and DAC D Reference Input. V+2 (Pin 25): Analog Positive Supply for DACs C and D. Typically 15V. 4.5V to 16.5V Range. Can be different from V +1. AGNDC (Pin 26): DAC C Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. VOSC (Pin 27): Offset Adjust for DAC C. Nominal input range is ±5V. VOS(DAC C) = –0.01• V(VOSC) [0V to 5V, ±2.5V modes]. See Operation section. C1C (Pin 28): Feedback Capacitor Connection for DAC C Output. This pin provides direct access to the negative input of the channel C output amplifier. OUTC (Pin 29): DAC C Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBC as close to the load as possible. RFBC (Pin 30): DAC C Output Feedback Resistor Pin. AGND (Pin 32): Analog Ground Pin. Tie to clean analog ground. GND (Pin 33): Ground Pin. Tie to clean analog ground. VDD (Pin 34): Logic Supply. 2.7V to 5.5V Range. RFLAG (Pin 35): Reset Flag Pin. An active low output is asserted when there is a power on reset or a clear event. Returns high when an update command is executed. RFBB (Pin 37): DAC B Output Feedback Resistor Pin. OUTB (Pin 38): DAC B Voltage Output Pin. For best load regulation, this open-loop amplifier output is connected to RFBB as close to the load as possible. C1B (Pin 39): Feedback Capacitor Connection for DAC B Output. This pin provides direct access to the negative input of the channel B output amplifier. VOSB (Pin 40): Offset Adjust for DAC B. Nominal input range is ±5V. VOS(DAC B) = –0.01 • V(VOSB) [0V to 5V, ±2.5V modes]. See Operation section. AGNDB (Pin 41): DAC B Signal Ground. High impedance input, does not carry supply currents. Tie to clean analog ground. V+1 (Pin 42): Analog Positive Supply for DACs A DND B. Typically 15V. 4.5V to 16.5V Range. Can be different from V +2. REF1 (Pin 43): DAC A and DAC B Reference Input. REFM1 (Pin 44): Reference 1 Inverting Amp Output. The gain from REF1 to REFM1 is –1. Can swing to within 0.5V of the analog supplies V+/V–. U U U 2704f 9 LTC2704 BLOCK DIAGRA 43 40 39 37 38 C1B RFBB OUTB REF1 VOSB 42 V+1 V– 1,8,15,22,31,36 41 AGNDB VOSA 4 5 7 6 C1A RFBA OUTA DAC A DAC D 3 AGNDA + – 44 2 REFM1 REFG1 COMMAND DECODE CS/LD SCK SDI 10 13 11 INPUT SHIFT REGS DAC BUFFERS CLR LDAC 14 9 TI I G DIAGRA SCK t1 t2 1 t3 2 t4 31 t6 32 t8 SDI t5 CS/LD t11 LDAC t9 SRO Hi-Z LSB 2704 TD t7 10 + + + – – – W W 32 AGND 25 V+2 REF2 VOSC 27 C1C RFBC DAC B DAC C OUTC 28 30 29 24 + – AGNDC 26 VOSD 19 C1D RFBD OUTD 18 16 17 + – AGNDD 20 REFM2 REFG2 SRO 23 21 12 READBACK SHIFT REGS RFLAG 35 VDD 34 GND 33 POR 2704 BD UW LSB 2704f LTC2704 OPERATIO SERIAL INTERFACE When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock signal (SCK pin). The minimum (24-bit wide) loading sequence required for the LTC2704 is a 4-bit command word (C3 C2 C1 C0), followed by a 4-bit address word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB first. Figure 1 shows the SDI input word syntax to use when writing a code or span. If a 32-bit input sequence is needed, the first eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. Figure 2 shows the input and readback sequences for both 24-bit and 32-bit operations. When CS/LD is low, the Serial Readback Output (SRO) pin is an active output. The readback data begins after the command (C3-C0) and address (A3-A0) words have been shifted into SDI. For a 24-bit load sequence, the 16 readback bits are shifted out on the falling edges of clocks 8-23, suitable for shifting into a microprocessor on the rising edges of clocks 9-24. For a 32-bit load sequence, add 8 to these clock cycle counts; see Figure 2b. When CS/LD is high, the SRO pin presents a high impedance (three-state) output. At the beginning of a load sequence, when CS/LD is taken low, SRO outputs a logic low until the readback data begins. When the asynchronous load pin, LDAC, is taken low, all DACs are updated with code and span data (data in B1 buffers is copied into B2 buffers). CS/LD must be high during this operation. The use of LDAC is functionally identical to the “Update B1→B2” commands. The codes for the command word (C3-C0) are defined in Table 1; Table 2 defines the codes for the address word (A3-A0). READBACK Each DAC has two pairs of double-buffered digital registers, one pair for DAC code and the other for the output span (four buffers per DAC). Each double-buffered pair comprises two registers called buffer 1 (B1) and buffer 2 (B2). U B1 is the holding buffer. When data is shifted into B1 via a write operation, DAC outputs are not affected. The contents of B2 can only be changed by copying the contents of B1 into B2 via an update operation (B1 and B2 can be changed together, see commands 0110-1001 in Table 1). The contents of B2 (DAC code or DAC span) directly control the DAC output voltage or the DAC output range. Additionally each DAC has one readback register associated with it. When a readback command is issued to a DAC, the contents of one of its four buffers is copied into its readback register and serially shifted out onto the SRO pin. Figure 2 shows the loading and readback sequences. In the 16-bit data field (D15-D0 for the LTC2704-16, see Figure 2a) of any write or update command, the readback pin (SRO) shifts out the contents of the buffer which was specified in the preceding command. This “rolling readback” mode of operation can be used to reduce the number of operations, since any command can be verified during succeeding commands with no additional overhead. Table 1 shows the location (readback pointer) of the data which will be output from SRO during the next instruction. For readback commands, the data is shifted out during the readback instruction itself (on the 16 falling SCK edges immediately after the last address bit is shifted in on SDI). When programming the span of a DAC, the span bits are the last four bits shifted in; and when checking the span of a DAC using SRO, the span bits are likewise the last four bits shifted out. Table 3 shows the span codes. When span information is read back on SRO, the sleep status of the addressed DAC is also output. The sleep status bit, SLP, occurs sequentially just before the four span bits. The sequence is shown in Figures 2a and 2b. See Table 4 for SLP codes. Note that SLP is an output bit only; sleep is programmed by using command code 1110 along with the desired address. Any update command, including the use of LDAC, wakes the addressed DAC(s). 2704f 11 LTC2704 OPERATIO OUTPUT RANGES The LTC2704 is a quad DAC with software-programmable output ranges. SoftSpan provides two unipolar output ranges (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and – 2.5V to 7.5V). These ranges are obtained when an external precision 5V reference and analog supplies of ±12V to ±15V are used. When a reference voltage of 2V and analog supplies of ±5V are Table 1. Command Codes C3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CODE C2 C1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 COMMAND Write to B1 Span DAC n Write to B1 Code DAC n Update B1→B2 DAC n Update B1→B2 All DACs Write to B1 Span DAC n Update B1→B2 DAC n Write to B1 Code DAC n Update B1→B2 DAC n Write to B1 Span DAC n Update B1→B2 All DACs Write to B1 Code DAC n Update B1→B2 All DACs Read B1 Span DAC n Read B1 Code DAC n Read B2 Span DAC n Read B2 Code DAC n Sleep DAC n (Note 1) No Operation READBACK POINTER— CURRENT INPUT WORD W0 Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command B1 Span DAC n B1 Code DAC n B2 Span DAC n B2 Code DAC n Set by Previous Command Set by Previous Command B2 Span DAC n B2 Code DAC n READBACK POINTER— NEXT INPUT WORD W+1 B1 Span DAC n B1 Code DAC n B2 Span DAC n B2 Code DAC A B2 Span DAC n B2 Code DAC n B2 Span DAC n B2 Code DAC n Codes not shown are reserved and should not be used. Note 1: Normal operation can be resumed by issuing any update B1→B2 command to the sleeping DAC. Table 2. Address Codes A3 A2 A1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 A0 0 0 0 0 1 n DAC A DAC B DAC C DAC D All DACs READBACK POINTER n DAC A DAC B DAC C DAC D DAC A Codes not shown are reserved and should not be used. 12 U used, the SoftSpan ranges become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to 3V. The output ranges are linearly scaled for references other than 2V and 5V (appropriate analog supplies should be used within the range ±5V to ±15V). Each of the four DACs can be programmed to any one of the six output ranges. DAC outputs can swing to ±10V on ±10.8V supplies (±12V supplies with ±10% tolerance) while sourcing or sinking 5mA of load current. Table 3. Span Codes S3 0 0 0 0 0 0 S2 0 0 0 0 1 1 S1 0 0 1 1 0 0 S0 0 1 0 1 0 1 SPAN Unipolar 0V to 5V Unipolar 0V to 10V Bipolar –5V to 5V Bipolar –10V to 10V Bipolar – 2.5V to 2.5V Bipolar –2.5V to 7.5V Codes not shown are reserved and should not be used. 2704f MSB C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 16-BIT CODE MSB C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 14-BIT CODE MSB C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 12-BIT CODE ADDRESS WORD D3 D2 D1 LSB D0 0 0 0 4 ZEROS ADDRESS WORD D2 D1 LSB D0 0 ADDRESS WORD D2 D1 LSB D0 LTC2704-16 (WRITE CODE) C3 CONTROL WORD LTC2704-14 (WRITE CODE) C3 0 2 ZEROS SDI CONTROL WORD LTC2704-12 (WRITE CODE) C3 0 CONTROL WORD C3 C2 C1 C0 A3 A2 A1 A0 0 0 0 0 0 ADDRESS WORD 0 0 12 ZEROS 0 0 0 0 0 S3 S2 S1 SPAN S0 2704 F01 LTC2704-12 LTC2704-14 LTC2704-16 (WRITE SPAN) CONTROL WORD Figure 1. Input Words U OPERATIO LTC2704 13 2704f LTC2704 OPERATIO CONTROL WORD ADDRESS WORD DAC CODE OR DAC SPAN 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 SRO Hi-Z 0 READBACK CODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLP S3 S2 S1 S0 2704 F02a SRO SLEEP STATUS SPAN Hi-Z 0 READBACK SPAN Figure 2a. 24-Bit Load Sequence 32-BIT DATA STREAM CS/LD 5 6 7 13 14 17 D15 D14 D13 D12 A2 A1 A0 ADDRESS WORD 0 0 0 0 0 D15 D14 D13 D12 D11 D10 A3 0 0 C3 C2 C1 C0 CONTROL WORD 0 0 0 0 0 0 8 9 10 12 11 18 16 20 19 15 0 21 D11 22 D10 23 D9 24 D8 25 D7 26 D6 DAC CODE OR DAC SPAN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0 SCK 1 2 3 4 SDI 0 0 0 0 0 8 ZEROS SRO Hi-Z 0 0 0 0 0 READBACK CODE Hi-Z SRO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t1 0 0 0 0 0 0 SLP SLEEP STATUS t2 SCK 17 t3 SDI SRO D15 t8 D15 D14 t4 D14 18 S3 S2 S1 SPAN S0 2704 F02b READBACK SPAN Figure 2b. 32-Bit Load Sequence U 14 24-BIT DATA STREAM 2 7 13 14 17 D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 D11 21 23 A1 A0 D15 D14 D13 D12 C1 C0 A3 A2 3 4 10 12 11 18 24 22 16 20 5 6 8 9 19 15 CS/LD SCK 1 SDI C3 C2 2704f LTC2704 OPERATIO Examples 1. Using a 24-bit loading sequence, load DAC A with the unipolar range of 0V to 10V, output at zero volts and all other DACs with the bipolar range of ±10V, outputs at zero volts. Note all DAC outputs should change at the same time. a) CS/LD↓ b) Clock SDI = 0010 1111 0000 0000 0000 0011 c) CS/LD↑ B1-Range of all DACs set to bipolar ±10V. d) CS/LD↓ Clock SDI = 0010 0000 0000 0000 0000 0001 e) CS/LD↑ B1-Range of DAC A set to unipolar 0V to 10V. f) CS/LD↓ Clock SDI = 0011 1111 1000 0000 0000 0000 g) CS/LD↑ B1-Code of all DACs set to midscale. h) CS/LD↓ Clock SDI = 0011 0000 0000 0000 0000 0000 i) CS/LD↑ B1-Code of DAC A set to zero code. j) CS/LD↓ Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX k) CS/LD↑ Update all DACs B1s into B2s for both Code and Range. l) Alternatively steps j and k could be replaced with LDAC . U 2. Using a 32-bit load sequence, load DAC C with bipolar ± 2.5V and its output at zero volts. Use readback to check B1 contents before updating the DAC output (i.e., before copying B1 contents into B2). a) CS/LD↓ (Note that after power-on, the Code in B1 is zero) b) Clock SDI = 0000 0000 0011 0100 1000 0000 0000 0000 c) CS/LD↑ B1-Code of DAC C set to midscale setting. d) CS/LD↓ Clock SDI = 0000 0000 0010 0100 0000 0000 0000 0100 e) Read Data out on SRO = 1000 0000 0000 0000 Verifies that B1-Code DAC C is at midscale setting. f) CS/LD↑ B1-Range of DAC C set to Bipolar ±2.5V range. g) CS/LD↓ Clock SDI = 0000 0000 1010 0100 xxxx xxxx xxxx xxxx Data Out on SRO = 0000 0000 0000 0100 Verifies that B1-Range of DAC C set to Bipolar ±2.5V Range. CS/LD↑ h) CS/LD↓ Clock SDI = 0000 0000 0100 0100 xxxx xxxx xxxx xxxx i) CS/LD↑ Update DAC C B1 into B2 for both Code and Range j) Alternatively steps h and i could be replaced with LDAC . 2704f 15 LTC2704 OPERATIO System Offset Adjustment Many systems require compensation for overall system offset, which may be an order of magnitude or more greater than the excellent offset of the LTC2704. The LTC2704 has individual offset adjust pins for each of the four DACs. VOSA, VOSB, VOSC and VOSD are referred to their corresponding signal grounds, AGNDA, AGNDB, AGNDC and AGNDD. For noise immunity and ease of adjustment, the control voltage is attenuated to the DAC output: VOS = – 0.01 • V(VOSx) [0V to 5V, ±2.5V spans] VOS = – 0.02 • V(VOSx) [0V to 10V, ±5V, –2.5V to 7.5V spans] VOS = –0.04 • V(VOSx) [±10V span] The nominal input range of these pins is ±5V; other reference voltages of up to ±15V may be used if needed. The VOSx pins have an input impedance of 1MΩ. To preserve the settling performance of the LTC2704, these pins should be driven with a Thevenin-equivalent impedance of 10kΩ or less. If not used, they should be shorted to their respective signal grounds, AGNDx. POWER-ON RESET AND CLEAR When power is first applied to the LTC2704, all DACs power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All internal DAC registers are reset to 0 and the DAC outputs are zero volts. When the CLR pin is taken low, a system clear results. The command and address shift registers, and the code and configuration B2 buffers, are reset to 0; the DAC outputs are all reset to zero volts. The B1 buffers are left intact, so 16 U that any subsequent “Update B1→B2” command (including the use of LDAC) restores the addressed DACs to their respective previous states. If CLR is asserted during an operation, i.e., when CS/LD is low, the operation is aborted. Integrity of the relevant input (B1) buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. The RFLAG pin is used as a flag to notify the system of a loss of data integrity. The RFLAG output is asserted low at power-up, system clear, or if the logic supply VDD dips below approximately 2V; and stays asserted until any valid update command is executed. SLEEP MODE When a sleep command (C3 C2 C1 C0 = 1110) is issued, the addressed DAC or DACs go into power-down mode. DACs A and B share a reference inverting amplifier as do DACs C and D. If either DAC A or DAC B (similarly for DACs C and D) is powered down, its shared reference inverting amplifier remains powered on. When both DAC A and DAC B are powered down together, their shared reference inverting amplifier is also powered down (similarly for DACs C and D). To determine the sleep status of a particular DAC, a direct read span command is performed by addressing the DAC and reading its status on the readback pin SRO. The fifth LSB is the sleep status bit (see Figures 2a and 2b). Table 4 shows the sleep status bit’s functionality. Table 4. Readback Sleep Status Bit SLP 0 1 STATUS DAC n Awake DAC n in Sleep Mode 2704f LTC2704 APPLICATIO S I FOR ATIO Overview The LTC2704 is a highly integrated device, greatly simplifying design and layout as compared to a design using multiple current output DACs and separate amplifiers. A similar design using four separate current output DACs would require six precision op amps, compensation capacitors, bypass capacitors for each amplifier, several times as much PCB area and a more complicated serial interface. Still, it is important to avoid some common mistakes in order to achieve full performance. DC752A is the evaluation board for the LTC2704. It is designed to meet all data sheet specifications, and to allow the LTC2704 to be integrated into other prototype circuitry. All force/ sense lines are available to allow the addition of current booster stages or other output circuits. The DC752A design is presented as a tutorial on properly applying the LTC2704. This board shows how to properly return digital and analog ground currents, and how to compensate for small differences in ground potential between the two banks of two DACs. There are other ways to ground the LTC2704, but the one requirement is that analog and digital grounds be connected at the LTC2704 by a very low impedance path. It is NOT advisable to split the ground plane and connect them with a jumper or inductor. When in doubt, use a single solid ground plane rather than separate planes. The LTC2704 does allow the ground potential of the DACs to vary by ±300mV with respect to analog ground, allowing compensation for ground return resistance. Power Supply Grounding and Noise LTC2704 V+ and V– pins are the supplies to all of the output amplifiers, ground sense amplifiers and reference inversion amplifiers. These amplifiers have good power supply rejection, but the V+ and V– supplies must be free from wideband noise. The best scheme is to prefilter low noise regulators such as the LT®1761 (positive) and LT1964 (negative). Refer to Linear Technology Application Note 101, Minimizing Switching Regulator Residue in Linear Regulator Outputs. U The LTC2704 VDD pin is the supply for the digital logic and analog DAC switches and is very sensitive to noise. It must be treated as an analog supply. The evaluation board uses an LT1790 precision reference as the VDD supply to minimize noise. The GND pin is the return for digital currents and the AGND pin is a bias point for internal analog circuitry. Both of these pins must be tied to the same point on a quiet ground plane. Each DAC has a separate ground sense pin that can be used to compensate for small differences in ground potential within a system. Since DACs A and B are associated with REF1 and DACs C and D are associated with REF2, the grounds must be grouped together as follows: AGNDA, AGNDB and REFG1 tied together (“GND1” on DC752A) AGNDC, AGNDD and REFG2 tied together (“GND2” on DC752A) This scheme allows compensation for ground return IR drops, as long as the resistance is shared by both DACs in a group. This implies that the ground return for DACs A and B must be as close as possible, and GND1 must be connected to this point through a low current, low resistance trace. (Similar for DACs C and D.) Figure 3 shows the top layer of the evaluation board. The GND1 trace connects REFG1, AGNDA, AGNDB and the ground pin of the LT1236 precision reference (U4.) This point is the ground reference for DACs A and B. The GND2 trace connects REFG2, AGNDC, AGNDD and the ground pin of the other LT1236 precision reference (U5). This point is the ground reference for DACs C and D. Voltage Reference A high quality, low noise reference such as the LT1236 or LT1027 must be used to achieve full performance. The ground terminal of this reference must be connected directly to the common ground point. If GND1 and GND2 are separate, then two references must be used. 2704f W UU 17 LTC2704 APPLICATIO S I FOR ATIO Voltage Output/Feedback and Compensation The LTC2704 provides separate voltage output and feedback pins for each DAC. This allows compensation for resistance between the output and load, or a current boosting stage such as an LT1970 may be inserted without affecting accuracy. When OUTx is connected directly EXPOSED GROUND PLANE AROUND EDGE ALLOWS GROUNDING TO PROTOTYPE CIRCUITS GND1 TRACE, SEPARATED FROM AGND UNDER LTC2704 GND2 TRACE, SEPARATED FROM AGND UNDER LTC2704 Figure 3. DC752 Top Layer CUTOUT PREVENTS DIGITAL RETURN CURRENTS FROM COUPLING INTO ANALOG GROUND PLANE. NOTE THAT THERE IS A PLANE IN THIS REGION ON LAYER 3 Figure 4. DC752 Analog Ground Layer. No Currents are Returned to this Plane, so it May be Used as a Reference Point for Precise Voltage Measurements 18 U to RFBx and no additional capacitance is present, the internal frequency compensation is sufficient for stability and is optimized for fast settling time. If a low bandwidth booster stage is used, then a compensation capacitor from OUTx to C1x may be required. Similarly, extra compensation may be required to drive a heavy capacitive load. POWER AND LOAD RETURN CURRENTS FLOW IN THIS REGION VOUTA AND VOUTB LOAD RETURN CURRENTS FLOW IN THIS REGION WHEN JP8 IS SET TO “TIE” VOUTC AND VOUTD LOAD RETURN CURRENTS FLOW IN THIS REGION WHEN JP9 IS SET TO “TIE” 2704 F03 W UU 2704 F05 DIGITAL RETURN CURRENTS FLOW IN THIS REGION Figure 5. DC752A Load Return, Power Return and Digital Return 2704 F04 2704 F06 SMALL GROUND POUR ALLOWS LOW IMPEDANCE BYPASSING OF V+ AND V – Figure 6. DC752A Routing, Bypass 2704f LTC2704 PACKAGE DESCRIPTIO U GW Package 44-Lead Plastic SSOP (Wide .300 Inch) (Reference LTC DWG # 05-08-1642) 44 23 1.40 ± 0.127 17.73 – 17.93* (.698 – .706) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 10.804 MIN 7.75 – 8.258 10.11 – 10.55 (.398 – .415) 1 0.520 ±0.0635 22 0.800 BSC RECOMMENDED SOLDER PAD LAYOUT 7.417 – 7.595** (.292 – .299) 0.254 – 0.406 × 45° (.010 – .016) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2.44 – 2.64 (.096 – .104) 2.286 – 2.388 (.090 – .094) 0.355 REF 0° – 8° TYP 0.231 – 0.3175 (.0091 – .0125) 0.40 – 1.27 (.015 – .050) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.800 (.0315) BSC 0.28 – 0.51 (.011 – .02) TYP 0.1 – 0.3 (.004 – .0118) G44 SSOP 0204 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 2704f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2704 TYPICAL APPLICATIO Evaluation Board Schematic. Force/Sense Lines Allow for Remote Sensing and Optimal Grounding VDD 10k LDAC CS/LD VDD VDD SPI INTERFACE SDI SRO SCK 9 10 11 12 13 14 35 LDAC CS/LD SDI SRO SCK CLR RFLAG VOSB C1B REMOTE VOSx REFMx 5V 1 2 REF1 3 5VREF1 GND1 REFM1 2 43 44 REFG1 REF1 REFM1 RFBB OUTB AGNDB LTC2704 OFFSET ADJUSTMENT FOR VOSA, VOSB, VOSC, VOSC REMOTE 5V 1 2 REF2 3 5VREF2 BAT54S VDD 3 1 2 VDD 3 5V 0.1µF 1 2 VDD 14 33 32 4 LT1790ACS6-5 6 VIN VOUT GND 1 GND 2 4.7µF 15V 1µ F 1µ F 1µ F V+1 V+2 25 42 VDD GND AGND VOSD C1D RFBD OUTD AGNDD V– 19 18 16 17 20 GND2 OUTD 1 2 –15V 1µF BAV99LT1 3 TIE REMOTE VOSD GND2 REFM2 21 24 23 REFG2 REF2 REFM2 VOSC C1C RFBC OUTC AGNDC REF REGULATOR VS 15V 7V 1 1 2 2 0.1µF 27 28 30 29 26 GND2 OUTSC OUTC OUTC 1 2 BAV99LT1 3 VOSC 40 39 37 38 41 GND1 VOSB VOSA C1A RFBA OUTA AGNDA 4 5 7 6 3 GND1 VOSA OUTA BAV99LT1 1 2 3 REMOTE OUTSA OUTA OUTB BAV99LT1 1 2 3 TIE REFx 20k 15V 15V 4.7µF 25V 4.7µF 25V –15V 0.1µF VS 2 LT1236ACS8-5 6 VOUT VIN 5 TRIM GND 4 –15V GND1 RELATED PARTS PART NUMBER LT 1019 LT1236 LTC1588/LTC1589 LTC1592 LTC1595 LTC1596 LTC1597 LTC1650 LTC1857/LTC1858 LTC1859 LT1970 ® DESCRIPTION Precision Reference Precision Reference 12-/14-/16-Bit, Serial, SoftSpan IOUT DACs 16-Bit Serial Multiplying IOUT DAC in SO-8 16-Bit Serial Multiplying IOUT DAC 16-Bit Parallel, Multiplying DAC 16-Bit Serial VOUT DAC 12-/14-/16-Bit, Serial 100ksps SoftSpan ADC 500mA Power Op Amp 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U 10k 1k RFLAG CLR TIE REMOTE OUTSB OUTB TIE REMOTE OUTSD OUTD 1,8,15,22,31,36 5VREF1 VS 2 LT1236ACS8-5 6 VOUT VIN 5 TRIM GND 4 5VREF2 3 1 4.7µF GND1 BAT54S GND2 BAT54S 2 GND1 1 2 3 TIE 3 REMOTE 1 2 GND2 1 2 3 TIE REMOTE 4.7µF 0.1µF GND2 COMMENTS Ultralow Drift, 3ppm/°C, 0.05% Accuracy Ultralow Drift, 10ppm/°C, 0.05% Accuracy Software-Selectable Spans, ±1LSB INL/DNL ± 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade ± 1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade ± 1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors Low Power, Low Gritch, 4-Quadrant Multiplication Software-Selectable Spans, 40mW, Fault Protected to ±25V Adjustable Sink/Source Current Limits 2704f LT/LWI 0806 • PRINTED IN THE USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006