LTC2752ACLX-PBF

LTC2752 Dual16-Bit SoftSpan IOUT DACs FeaTures n n DescripTion The LTC®2752 is a dual 16-bit multiplying serial-input, current-output digital-to-analog converter. It operates from a single 3V to 5V supply and is guaranteed monotonic over temperature. The LTC2752A provides full 16-bit performance (±1LSB INL and DNL, max) over temperature without any adjustments. This SoftSpan™ DAC offers six output ranges (up to ±10V) that can be programmed through the 3-wire SPI serial interface, or pinstrapped for operation in a single range. Any on-chip register (including DAC output-range settings) can be read for verification in just one instruction cycle; and if you change register content, the altered register will be automatically read back during the next instruction cycle. Voltage-controlled offset and gain adjustments are also provided; and the power-on reset circuit and CLR pin both reset the DAC outputs to 0V regardless of output range. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178. n n n n n n n n n Program or Pin-Strap Six Output Ranges 0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V Maximum 16-Bit INL Error: ±1 LSB over Temperature Guaranteed Monotonic over Temperature Glitch Impulse 0.6nV•s (3V), 2.2nV•s (5V) Serial Readback of All On-Chip Registers 1μA Maximum Supply Current 2.7V to 5.5V Single-Supply Operation 16-Bit Settling Time: 2µs Voltage-Controlled Offset and Gain Trims Clear and Power-On-Reset to 0V Regardless of Output Range 48-Pin 7mm × 7mm LQFP Package applicaTions n n n n High Resolution Offset and Gain Adjustment Process Control and Industrial Automation Automatic Test Equipment Data Acquisition Systems Typical applicaTion Dual 16-Bit VOUT DAC with Software-Selectable Ranges REFERENCE 5V RCOMA ROFSA REFA RINA DAC A VDD SPI with READBACK GND LTC2752 IOUT2A VOSADJA RFBB INL (LSB) DAC B IOUT2B VOSADJB ROFSB REFB RCOMB RINB GEADJB ALL AMPLIFIERS 1/2 LT1469 REFERENCE 5V + – IOUT1B + – – + + – GEADJA Integral Nonlinearity (INL) RFBA IOUT1A 1.0 0.8 VOUTA 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2752 TA01b ±10V RANGE VOUTB 2752 TA01 2752f  LTC2752 absoluTe MaxiMuM raTings (Notes 1, 2) pin conFiguraTion TOP VIEW ROFSA ROFSA RFBA RFBA IOUT1A VOSADJA VOSADJB IOUT1B RFBB RFBB ROFSB ROFSB REFA 1 REFA 2 RCOMA 3 GEADJA 4 RINA 5 RINA 6 GND 7 IOUT2AS 8 IOUT2AF 9 GND 10 CS/LD 11 SDI 12 48 47 46 45 44 43 42 41 40 39 38 37 IOUT1X , IOUT2X to GND............................................±0.3V RINX, RCOMX , REFX, RFBX , ROFSX , VOSADJX , GEADJX to GND ....................................................... ±18V VDD to GND .................................................. –0.3V to 7V Digital Inputs to GND ................................... –0.3V to 7V Digital Outputs to GND ..... –0.3V to VDD+0.3V (max 7V) Operating Temperature Range LTC2752C ................................................ 0°C to 70°C LTC2752I .............................................–40°C to 85°C Maximum Junction Temperature .......................... 150°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C 36 35 34 33 32 31 30 29 28 27 26 25 REFB REFB RCOMB GEADJB RINB RINB GND IOUT2BS IOUT2BF GND LDAC S2 LX PACKAGE 48-LEAD (7mm 7mm) PLASTIC LQFP TJMAX = 150°C, θJA = 58°C/W orDer inForMaTion LEAD FREE FINISH LTC2752BCLX#PBF LTC2752BILX#PBF LTC2752ACLX#PBF LTC2752AILX#PBF PART MARKING* LTC2752LX LTC2752LX LTC2752LX LTC2752LX PACKAGE DESCRIPTION 48-Lead (7mm × 7mm) Plastic LQFP 48-Lead (7mm × 7mm) Plastic LQFP 48-Lead (7mm × 7mm) Plastic LQFP 48-Lead (7mm × 7mm) Plastic LQFP TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ SCK 13 SRO 14 GND 15 VDD 16 GND 17 GND 18 CLR 19 RFLAG 20 DNC 21 M-SPAN 22 S0 23 S1 24 2752f  LTC2752 elecTrical characTerisTics SYMBOL PARAMETER Resolution Monotonicity DNL INL GE Differential Nonlinearity Integral Nonlinearity Gain Error Gain Error Temperature Coefficient BZE Bipolar Zero Error Bipolar Zero Temperature Coefficient Unipolar Zero-Scale Error PSR ILKG Power Supply Rejection IOUT1 Leakage Current Unipolar Ranges (Note 3) VDD = 5V, ±10% VDD = 3V, ±10% TA = 25°C TMIN to TMAX l l l VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS l l l l MIN 16 16 LTC2752B TYP MAX MIN 16 16 LTC2752A TYP MAX UNITS Bits Bits Static Performance ±1 ±2 ±20 ±0.25 ±0.2 ±0.4 ±2 ±0.25 ±1 ±1 ±12 LSB LSB LSB ppm/°C All Output Ranges ∆Gain/∆Temp All Bipolar Ranges l l ±12 ±0.15 ±0.01 ±1 ±0.4 ±1 ±0.05 ±2 ±5 ±1 ±0.15 ±0.01 ±0.03 ±0.1 ±0.05 ±8 LSB ppm/°C ±1 ±0.2 ±0.5 ±2 ±5 LSB LSB/V LSB/V nA nA l VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL Analog Pins Reference Inverting Resistors RREF RFB ROFS RVOSADJ RGEADJ CIOUT1 DAC Input Resistance Feedback Resistors Bipolar Offset Resistors Offset Adjust Resistors Gain Adjust Resistors Output Capacitance Full-Scale Zero-Scale Span Code = 0000, 10V Step. To ±0.0015% FS (Note 7) VDD = 5V (Note 8) VDD = 3V (Note 8) (Note 9) 0V to 5V Range, VREF = 3VRMS, Code = Full Scale, –3dB BW 0V to 5V Range, VREF = ±10V, 10kHz Sine Wave (Note 10) (Note 11) Multiplying (Note 12) at IOUT1 (Note 4) (Notes 5, 6) (Note 6) (Note 6) l l l l l l PARAMETER CONDITIONS MIN 16 8 8 16 1024 2048 TYP 20 10 10 20 1280 2560 90 40 2 2.2 0.6 2 1 0.4 –109 –108 13 MAX UNITS kΩ kΩ kΩ kΩ kΩ kΩ pF Dynamic Performance Output Settling Time Glitch Impulse Digital-to-Analog Glitch Impulse Reference Multiplying BW Multiplying Feedthrough Error Analog Crosstalk THD Total Harmonic Distortion Output Noise Voltage Density μs nV•s nV•s nV•s MHz mV dB dB nV/√Hz 2752f  LTC2752 elecTrical characTerisTics SYMBOL Power Supply VDD IDD Digital Inputs VIH VIL Digital Input High Voltage Digital Input Low Voltage Hysteresis Voltage IIN CIN Digital Outputs VOH VOL Digital Output High Voltage Digital Output Low Voltage IOH = 200µA, 2.7V ≤ VDD ≤ 5.5V IOL = 200µA, 2.7V ≤ VDD ≤ 5.5V l l VDD = 5V, VRINX = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER Supply Voltage VDD Supply Current Digital Inputs = 0V or VDD 3.3V ≤ VDD ≤ 5.5V 2.7V ≤ VDD < 3.3V 4.5V < VDD ≤ 5.5V 2.7V ≤ VDD ≤ 4.5V VIN = GND to VDD VIN = 0V (Note 13) CONDITIONS l l MIN 2.7 TYP MAX 5.5 UNITS V μA V V 0.5 2.4 2 1 l l l l 0.8 0.6 0.1 ±1 6 VDD – 0.4 0.4 V V V µA pF V V Digital Input Current Digital Input Capacitance l l TiMing characTerisTics otherwise specifications are at TA = 25°C. PARAMETER SDI Valid to SCK Set-Up SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK Positive Edge CS/LD High to SCK Positive Edge SRO Propagation Delay CLR Pulse Width Low LDAC Pulse Width Low CLR Low to RFLAG Low CS/LD High to RFLAG High SCK Frequency VDD = 2.7V to 3.3V t1 t2 t3 t4 t5 t6 t7 SDI Valid to SCK Set-Up SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK Positive Edge SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 VDD = 4.5V to 5.5V The l denotes specifications that apply over the full operating temperature range, CONDITIONS l l l l l l l l MIN 7 7 11 11 9 4 4 4 TYP MAX UNITS ns ns ns ns ns ns ns ns CLOAD = 10pF l l l 18 36 15 50 40 40 9 9 15 15 12 5 5 ns ns ns ns ns MHz ns ns ns ns ns ns ns 2752f CLOAD = 10pF (Note 13) CLOAD = 10pF (Note 13) 50% Duty Cycle (Note 14) l l l l l l l l l l  LTC2752 TiMing characTerisTics otherwise specifications are at TA = 25°C. PARAMETER CS/LD High to SCK Positive Edge SRO Propagation Delay CLR Pulse Width Low LDAC Pulse Width Low CLR Low to RFLAG Low CS/LD High to RFLAG high SCK Frequency CLOAD = 10pF (Note 13) CLOAD = 10pF (Note 13) 50% Duty Cycle (Note 14) CLOAD = 10pF SYMBOL t8 t9 t10 t11 t12 t13 The l denotes specifications that apply over the full operating temperature range, CONDITIONS l l l l l l l MIN 5 TYP MAX 26 UNITS ns ns ns ns 60 20 70 60 25 ns ns MHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Calculation from feedback resistance and IOUT1 leakage current specifications; not production tested. In most applications, unipolar zeroscale error is dominated by contributions from the output amplifier. Note 4: Input resistors measured from RINX to RCOMX ; feedback resistors measured from RCOMX to REFX. Note 5: DAC input resistance is independent of code. Note 6: Parallel combination of the resistances from the specified pin to IOUT1X and from the specified pin to IOUT2X. Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0015% settling time of 1.7μs can be achieved by optimizing the time constant on an individual basis. See Application Note 74, Component and Measurement Advances Ensure 16-Bit DAC Settling Time. Note 8: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1468; CFB = 50pF. Note 9. Full-scale transition; REF = 0V. Note 10. Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA , expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave. Note 11. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1469. Note 12. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K (Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale. Note 13. Guaranteed by design, not subject to test. Note 14. When using SRO, maximum SCK frequency fMAX is limited by SRO propagation delay t9 as follows:   1 fMAX =   , where tS is the setup time of the receiving device.  2 (t 9 + t S ) 2752f  LTC2752 Typical perForMance characTerisTics VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted. Integral Nonlinearity (INL) 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2752 G01 Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2752 G02 INL vs Temperature 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –20 20 40 0 TEMPERATURE (°C) 60 80 2752 G03 ±10V RANGE ±10V RANGE ±10V RANGE +INL –INL DNL vs Temperature 1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –40 –20 20 40 0 TEMPERATURE (°C) 60 80 2752 G04 Gain Error vs Temperature 8 6 4 BZE (LSB) ±2.5V ±5V ±10V 0V TO 5V 0V TO 10V –2.5V TO 7.5V –20 40 60 20 TEMPERATURE (°C) 0 80 2752 G05 Bipolar Zero Error vs Temperature 8 6 4 2 0 –2 –4 –6 –8 –40 –20 ±2.5V ±5V ±10V –2.5V TO 7.5V 0 40 60 20 TEMPERATURE (°C) 80 2752 G06 ±10V RANGE ±0.25ppm/°C TYP ±0.15ppm/°C TYP +DNL GE (LSB) 2 0 –2 –4 –6 –8 –40 –DNL 2752f  LTC2752 Typical perForMance characTerisTics VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted. INL vs Reference Voltage 1.0 0.8 0.6 0.4 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –10 –8 –6 –4 –2 0 2 V(RIN) (V) 4 6 8 10 –INL –INL DNL (LSB) INL (LSB) 0.2 +INL +INL ±5V RANGE 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –10 –8 –6 –4 –2 0 2 V(RIN) (V) 4 6 8 10 –DNL –DNL +DNL +DNL DNL vs Reference Voltage ±5V RANGE 2752 G07 2752 G08 INL vs VDD 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 2752 G09 DNL vs VDD 1.0 0.8 0.6 +INL +INL ATTENUATION (dB) 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 2752 G17 Multiplying Frequency Response vs Digital Code 0 –20 –40 –60 –80 –100 –120 ALL BITS OFF ALL BITS ON D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ±10V RANGE ±10V RANGE –INL –INL –140 100 0V TO 5V OUTPUT RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 15pF 10k 100k FREQUENCY (Hz) 1M 10M 2752 G10 1k 2752f  LTC2752 Typical perForMance characTerisTics VDD = 5V, VRINX = 5V, TA = 25°C, unless otherwise noted. Supply Current vs Logic Input Voltage 5 CLR, LDAC, SDI, SCK, CS/LD TIED TOGETHER LOGIC THRESHOLD (V) 2 1.75 SUPPLY CURRENT (mA) 1.5 1.25 1 0.75 VDD = 3V 0 0 1 3 4 2 DIGITAL INPUT VOLTAGE (V) 5 2752 G11 Logic Threshold vs Supply Voltage 100 10 RISING 1 0.1 0.01 0.001 0.0001 Supply Current vs Clock Frequency ALTERNATING ZERO AND FULL-SCALE 4 SUPPLY CURRENT (mA) 3 VDD = 5V VDD = 3V 2 VDD = 5V 1 FALLING 0.5 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 2752 G12 1 100 10k 1M SCK FREQUENCY (Hz) 100M 2752 G13 Settling Full-Scale Step CS/LD 5V/DIV Midscale Glitch (VDD = 3V) 0.6nV•s TYP CS/LD 5V/DIV Midscale Glitch (VDD = 5V) 2.2nV•s TYP UPD 5V/DIV GATED SETTLING WAVEFORM 100µV/DIV (AVERAGED) 500ns/DIV LT1468 AMP; CFEEDBACK = 20pF 0V TO 10V STEP VREF = –10V; SPAN CODE = 0000 tSETTLE = 1.7µs to 0.0015% (16 BITS) 2752 G14 VOUT 5mV/DIV (AVERAGED) 500ns/DIV 2752 G15 VOUT 5mV/DIV (AVERAGED) 500ns/DIV 2752 G16 0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF FALLING MAJOR CARRY TRANSITION. RISING TRANSITION IS SIMILAR OR BETTER. 0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF FALLING MAJOR CARRY TRANSITION. RISING TRANSITION IS SIMILAR OR BETTER. 2752f  LTC2752 pin FuncTions REFA (Pins 1, 2): Feedback Resistor for the DAC A Reference Inverting Amplifier, and Reference Input for DAC A. The 20k feedback resistor is connected internally from REFA to RCOMA. For normal operation tie this pin to the output of the DAC A reference inverting amplifier (see Typical Applications). Typically –5V; accepts up to ±15V. Pins 1 and 2 are internally shorted together. RCOMA (Pin 3): Virtual Ground Point for the DAC A Reference Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RINA to RCOMA and from RCOMA to REFA, respectively (see Block Diagram). For normal operation tie RCOMA to the negative input of the external reference inverting amplifier (see Typical Applications). GEADJA (Pin 4): Gain Adjust Pin for DAC A. This control pin can be used to null gain error or to compensate for reference errors. The gain change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. RINA (Pins 5, 6): Input Resistor for External Reference Inverting Amplifier. The 20k input resistor is connected internally from RINA to RCOMA. For normal operation tie RINA to the external positive reference voltage (see Typical Applications). Either or both of these precision-matched resistor sets (each set comprising RINX, RCOMX and REFX) may be used to invert positive references to provide the negative voltages needed by the DACs. Typically 5V; accepts up to ±15V. Pins 5 and 6 are internally shorted together. GND (Pins 7, 10, 15, 17, 18, 27, 30): Ground; tie to ground. IOUT2AS, IOUT2AF (Pins 8, 9): DAC A Current Output Complement Sense and Force Pins. Tie to ground via a clean, low-impedance path. These pins may be used with a precision ground buffer amp as a Kelvin sensing pair (see the Typical Applications section). CS/LD (Pin 11): Synchronous Chip Select and Load Input Pin. SDI (Pin 12): Serial Data Input. Data is clocked in on the rising edge of the serial clock (SCK) when CS/LD is low. SCK (Pin 13): Serial Clock Input. SRO (Pin 14): Serial Readback Output. Data is clocked out on the falling edge of SCK. Readback data begins clocking out after the last address bit A0 is clocked in. SRO is an active output only when the chip is selected (i.e., when CS/LD is low). Otherwise SRO presents a high impedance output in order to allow other parts to control the bus. VDD (Pin 16): Positive Supply Input; 2.7V ≤ VDD ≤ 5.5V. Bypass with a 0.1μF low ESR ceramic capacitor to ground. CLR (Pin 19): Asynchronous Clear Input. When this pin is low, all DAC registers (both code and span) are cleared to zero. All DAC outputs are cleared to zero volts. RFLAG (Pin 20): Reset Flag Output. An active low output is asserted when there is a power-on reset or a clear event. Returns high when an Update command is executed. DNC (Pin 21): Do not connect this pin. M-SPAN (Pin 22): Manual Span Control Pin. M-SPAN is used in conjunction with pins S2, S1 and S0 (Pins 25, 24 and 23) to configure all DACs for operation in a single, fixed output range. To configure the part for manual span use, tie M-SPAN directly to VDD. The DAC output range is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. To configure the part for SoftSpan use, tie M-SPAN directly to GND. The output ranges are then individually controllable through the SPI port; and pins S2, S1 and S0 have no effect. See Manual Span Configuration in the Operation section. M-SPAN must be connected either directly to GND (SoftSpan configuration) or to VDD (manual span configuration). S0 (Pin 23): Span Bit 0 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. S1 (Pin 24): Span Bit 1 Input. In Manual Span mode (M-SPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. 2752f  LTC2752 pin FuncTions S2 (Pin 25): Span Bit 2 Input. In Manual Span mode (MSPAN tied to VDD), pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. LDAC (Pin 26): Asynchronous DAC Load Input. When LDAC is a logic low, all DACs are updated (CS/LD must be high). IOUT2BF, IOUT2BS (Pins 28, 29): DAC B Current Output Complement Force and Sense Pins. Tie to ground via a clean, low impedance path. These pins may be used with a precision ground buffer amp as a Kelvin sensing pair (see the Typical Applications section). RINB (Pins 31, 32): Input Resistor for the External Reference Inverting Amplifier. The 20k input resistor is connected internally from RINB to RCOMB. For normal operation tie RINB to the external positive reference voltage (see Typical Applications). Either or both of these precision matched resistor sets (each set comprising RINX, RCOMX and REFX) may be used to invert positive references to provide the negative voltages needed by the DACs. Typically 5V; accepts up to ±15V. Pins 31 and 32 are internally shorted together. GEADJB (Pin 33): Gain Adjust Pin for DAC B. This control pin can be used to null gain error or to compensate for reference errors. The gain change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. RCOMB (Pin 34): Virtual Ground Point for the DAC B Reference Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RINB to RCOMB and from RCOMB to REFB, respectively (see Block Diagram). For normal operation tie RCOMB to the negative input of the external reference inverting amplifier (see Typical Applications). REFB (Pins 35, 36): Feedback Resistor for the DAC B Reference Inverting Amplifier, and Reference Input for DAC B. The 20k feedback resistor is connected internally from REFB to RCOMB. For normal operation tie this pin to the output of the DAC B reference inverting amplifier (see Typical Applications). Typically –5V; accepts up to ±15V. Pins 35 and 36 are internally shorted together. ROFSB (Pins 37, 38): Bipolar Offset Resistor for DAC B. These pins provide the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RINB (Pins 31, 32). Pins 37 and 38 are internally shorted together. RFBB (Pins 39, 40): DAC B Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC B (see Typical Applications). The DAC output current from IOUT1B flows through the feedback resistor to the RFBB pins. Pins 39 and 40 are internally shorted together. IOUT1B (Pin 41): DAC B Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC B (see Typical Applications). VOSADJB (Pin 42): DAC B Offset Adjust Pin. This voltage control pin can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. VOSADJA (Pin 43): DAC A Offset Adjust Pin. This voltage control pin can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. IOUT1A (Pin 44): DAC A Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC A (see Typical Applications). RFBA (Pins 45, 46): DAC A Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC A (see Typical Applications). The DAC output current from IOUT1A flows through the feedback resistor to the RFBA pins. Pins 45 and 46 are internally shorted together. ROFSA (Pins 47, 48): Bipolar Offset Resistor for DAC A. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to ±15V; for normal operation tie to the positive reference voltage at RINA (Pins 5, 6). Pins 47 and 48 are internally shorted together. 2752f 0 LTC2752 block DiagraM 16 VDD RINA (5, 6) GEADJA RCOMA 2.56M 2.56M (31, 32) RINB GEADJB RCOMB 4 3 20k 20k 33 34 20k 20k REFA (1, 2) ROFSA (47, 48) 44 8 9 43 RFBA (45, 46) IOUT1A IOUT2AS IOUT2AF VOSADJA POWER-ON RESET GND (7, 10, 15, 17, 18, 27, 30) M-SPAN S0 22 23 S1 24 CONTROL AND READBACK LOGIC DAC A 16-BIT WITH SPAN SELECT 16 CODE REGISTERS DAC REG 3 INPUT REG CODE REGISTERS INPUT REG DAC REG 3 16 DAC B 16-BIT WITH SPAN SELECT (35, 36) REFB (37, 38) ROFSB (39, 40) RFBB IOUT1B IOUT2BS IOUT2BF VOSADJB 41 29 28 42 SPAN REGISTERS DAC REG INPUT REG SPAN REGISTERS INPUT REG DAC REG S2 25 RFLAG 20 CLR 19 CS/LD SDI 11 12 SCK 13 LDAC SRO 26 14 2752 BD 2752f  LTC2752 TiMing DiagraM t1 t2 SCK 1 t3 2 t4 31 t6 32 t8 SDI t5 CS/LD t11 LDAC t9 SRO Hi-Z LSB 2752 TD LSB t7 2752f  LTC2752 operaTion Output Ranges The LTC2752 is a dual, current-output, serial-input precision multiplying DAC with selectable output ranges. Ranges can either be programmed in software for maximum flexibility—each of the DACs can be programmed to any one of six output ranges—or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. The output ranges for other reference voltages are easy to calculate by observing that each range is a multiple of the external reference voltage. The ranges can then be expressed: 0 to 1×, 0 to 2×, ±0.5×, ±1×, ±2×, and –0.5× to 1.5×. Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2752 to operate in a single span without additional operational overhead, tie the M-SPAN pin directly to VDD. The active output range for all DACs is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. See Figure 1 and Table 3. VDD Tie the M-SPAN pin to ground for normal SoftSpan operation. Input and DAC Registers The LTC2752 has 5 internal registers for each DAC, a total of 10 registers (see Block Diagram). Each DAC channel has two sets of double-buffered registers—one set for the code data, and one for the output range of the DAC—plus one readback register. Double buffering provides the capability to simultaneously update the span (output range) and code, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs. Each set of double-buffered registers comprises an Input register and a DAC register. Input register: The Write operation shifts data from the SDI pin into a chosen Input register. The Input registers are holding buffers; Write operations do not affect the DAC outputs. DAC register: The Update operation copies the contents of an Input register to its associated DAC register. The contents of a DAC register directly updates the associated DAC output voltage or output range. Note that updates always include both Code and Span register sets; but the values held in the DAC registers will only change if the associated Input register values have previously been changed via a Write operation. LTC2752 VDD DAC A M-SPAN S2 S1 S0 CS/LD SDI SCK – + – + 2752 F01 ±10V Serial Interface When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock (SCK pin). The minimum (24-bit wide) loading sequence required for the LTC2752 is a 4-bit command word (C3 C2 C1 C0), followed by a 4-bit address word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB first. Figure 2 shows the SDI input word syntax to use when DAC B ±10V Figure 1. Using M-SPAN to Configure the LTC2752 for Single-Span Operation (±10V Range Shown) 2752f  LTC2752 operaTion writing code or span. If a 32-bit input sequence is used, the first eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. Figure 3 shows the input and readback sequences for both 24-bit and 32-bit operations. When CS/LD is low, the SRO pin (Serial Readback Output) is an active output.The readback data begins after the command (C3-C0) and address (A3-A0) words have been shifted into SDI. SRO outputs a logic low (when CS/LD is low) until the readback data begins. For a 24-bit input sequence, the 16 readback bits are shifted out on the falling edges of clocks 8-23, suitable for shifting into a microprocessor on the rising edges of clocks 9-24. For a 32-bit sequence, the bits are shifted out on clocks 16-31; see Figure 3b. When CS/LD is high, the SRO pin presents a high impedance (three-state) output. LDAC is an asynchronous update pin. When LDAC is taken low, all DACs are updated with code and span data (data in the Input buffers is copied into the DAC buffers). CS/LD must be high during this operation; otherwise LDAC is locked out and will have no effect. The use of LDAC is functionally identical to the “Update All DACs” serial input command. The codes for the command word (C3-C0) are defined in Table 1; Table 2 defines the codes for the address word (A3-A0). Readback In addition to the Input and DAC registers, each DAC has one Readback register associated with it. When a Read command is issued to a DAC, the contents of one of its four buffers (Input and DAC registers for each of Span and Code) is copied into its Readback register and serially shifted out through the SRO pin. Figure 3 shows the loading and readback sequences. In the data field (D15-D0) of any non-read instruction cycle, SRO shifts out the contents of the buffer that was specified in the preceding command. This “rolling readback” default mode of operation can dramatically reduce the number of instruction cycles needed, since any command can be verified during succeeding commands with no additional overhead. See Figure 4. Table 1 shows the storage location (‘readback pointer’) of the data which will be output from SRO during the next instruction. For Read commands, the data is shifted out during the Read instruction itself (on the 16 falling SCK edges immediately after the last address bit is shifted in on SDI). When checking the span of a DAC using SRO, the span bits are the last four bits shifted out, corresponding to their sequence and positions when writing a span. See Figure 3. Span Readback in Manual Span Configuration If a Span DAC register is chosen for readback, SRO responds by outputting the actual output span; this is true whether the LTC2752 is configured for SoftSpan (M-SPAN tied to GND) or manual span (M-SPAN tied to VDD) use. In SoftSpan configuration, SRO outputs the span code from the Span DAC register (programmed through the SPI port). In manual span configuration, the active span is controlled by pins S2, S1 and S0, so SRO outputs the logic values of these pins. The span code bits S2, S1 and S0 always appear in the same order and positions in the SRO output sequence; see Figure 3. 2752f  operaTion MSB C2 ADDRESS WORD 16-BIT CODE C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 (WRITE CODE) C3 SDI COMMAND WORD (WRITE SPAN) C2 ADDRESS WORD 12 ZEROS C1 C0 A3 A2 A1 A0 0 0 0 0 0 0 0 0 C3 0 0 0 0 S3 S2 S1 SPAN S0 2752 F02 COMMAND WORD Figure 2. Serial Input Write Sequence LTC2752  2752f LTC2752  24-BIT DATA STREAM 2 7 14 17 D7 D6 D5 D4 D3 D2 D1 D0 D10 DAC CODE OR DAC SPAN 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 A1 A0 D15 D14 D13 D12 D11 13 C2 ADDRESS WORD 0 0 0 0 C1 C0 A3 A2 3 4 10 21 23 11 12 18 24 16 20 22 5 6 8 9 15 19 COMMAND WORD 0 0 0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0 2752 F03 operaTion CS/LD SCK 1 SDI C3 SRO Hi-Z 0 READBACK CODE SRO Hi-Z 0 READBACK SPAN Figure 3a. 24-Bit Instruction Sequence 32-BIT DATA STREAM CS/LD 6 7 14 17 D15 D14 D13 D12 D11 A2 ADDRESS WORD 0 0 0 0 0 0 0 0 0 0 0 0 D15 D14 D13 0 D12 0 D11 0 t1 SCK SDI SRO D15 t9 D15 D14 17 t3 t4 D14 D10 0 A1 A0 0 COMMAND WORD 0 0 0 0 0 0 0 0 0 0 0 0 0 C3 C2 C1 C0 A3 8 9 10 13 21 11 12 18 16 20 15 19 0 22 D10 23 D9 24 D8 25 D7 26 D6 DAC CODE OR DAC SPAN D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 S3 D2 S2 D1 S1 SPAN t2 18 D0 S0 2752 F04 SCK 1 2 3 4 5 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0 SDI 0 0 0 0 0 8 ZEROS SRO Hi-Z 0 0 0 0 0 READBACK CODE Hi-Z SRO 0 0 0 0 0 READBACK SPAN Figure 3b. 32-Bit Instruction Sequence 2752f LTC2752 operaTion SDI WRITE CODE DAC A WRITE CODE DAC B WRITE SPAN DAC C WRITE SPAN DAC B UPDATE ALL DACs ... READ CODE DAC REGISTER DAC A 2754 F04 SRO ... READ CODE INPUT REGISTER DAC A READ CODE INPUT REGISTER DAC B READ SPAN INPUT REGISTER DAC A READ SPAN INPUT REGISTER DAC B Figure 4. Rolling Readback Table 1. Command Codes C3 0 0 0 0 0 0 1 1 1 1 1 1 1 CODE C2 C1 0 0 1 1 1 1 0 0 0 0 1 1 1 – – 1 1 0 0 1 1 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 1 COMMAND Write Span DAC n Write Code DAC n Update DAC n Update All DACs Write Span DAC n Update DAC n Write Code DAC n Update DAC n Write Span DAC n Update All DACs Write Code DAC n Update All DACs Read Input Span Register DAC n Read Input Code Register DAC n Read DAC Span Register DAC n Read DAC Code Register DAC n No Operation System Clear Initial Power-Up or Power Interupt – – READBACK POINTER– CURRENT INPUT WORD W0 Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command READBACK POINTER– NEXT INPUT WORD W+1 Input Span Register DAC n Input Code Register DAC n DAC Span Register DAC n DAC Code Register DAC n DAC Span Register DAC n DAC Code Register DAC n DAC Span Register DAC n DAC Code Register DAC n Input Span Register DAC n Input Code Register DAC n DAC Span Register DAC n DAC Code Register DAC n Set by Previous Command DAC Code Register DAC n DAC Span Register DAC A DAC Span Register DAC A Codes not shown are reserved–do not use Table 2. Address Codes A3 0 0 1 Table 3. Span Codes n DAC A DAC B All DACs (Note 1) A2 0 0 1 A1 0 1 1 A0 × × × S3 0 0 0 0 0 0 S2 0 0 0 0 1 1 S1 0 0 1 1 0 0 S0 0 1 0 1 0 1 SPAN Unipolar 0V to 5V Unipolar 0V to 10V Bipolar –5V to 5V Bipolar –10V to 10V Bipolar –2.5V to 2.5V Bipolar –2.5V to 7.5V Codes not shown are reserved–do not use. × = Don’t Care. Note 1. If readback is taken using the All DACs address, the LTC2752 defaults to DAC A. Codes not shown are reserved–do not use 2752f  LTC2752 operaTion Examples 1. Using a 24-bit instruction, load DAC A with the unipolar range of 0V to 10V, output at zero volts and DAC B with the bipolar range of ±10V, outputs at zero volts. Note all DAC outputs should change at the same time. a) CS/LD↓ Clock SDI = 0010 1111 0000 0000 0000 0011 b) CS/LD↑ Span Input register- Range of all DACs set to bipolar ±10V. c) CS/LD↓ Clock SDI = 0010 0000 0000 0000 0000 0001 d) CS/LD↑ Span Input register- Range of DAC A set to unipolar 0V to 10V. e) CS/LD↓ Clock SDI = 0011 1111 1000 0000 0000 0000 f) CS/LD↑ Code Input register- Code of all DACs set to midscale. g) CS/LD↓ Clock SDI = 0011 0000 0000 0000 0000 0000 h) CS/LD↑ Code Input register- Code of DAC A set to zero code. i) CS/LD↓ Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX j) CS/LD↑ Update all DACs for both Code and Range. k) Alternatively steps i and j could be replaced with LDAC . 2. Using a 32-bit load sequence, load DAC B with bipolar ±2.5V and its output at zero volts. Use readback to check Input register contents before updating the DAC output (i.e., before copying Input register contents into DAC register). a) CS/LD↓ (Note that after power-on, the code in Input register is zero) Clock SDI = 0000 0000 0011 0010 1000 0000 0000 0000 b) CS/LD↑ Code Input register- Code of DAC B set to midscale setting. c) CS/LD↓ Clock SDI = 0000 0000 0010 0010 0000 0000 0000 0100 Data out on SRO = 1000 0000 0000 0000 Verifies that Code Input register- DAC B is at midscale setting. d) CS/LD↑ Span Input register- Range of DAC B set to Bipolar ±2.5V range. e) CS/LD↓ Clock SDI = 0000 0000 1010 0010 XXXX XXXX XXXX XXXX Data Out on SRO = 0000 0000 0000 0100 Verifies that Span Input register- range of DAC B set to Bipolar ±2.5V Range. CS/LD↑ f) CS/LD↓ Clock SDI = 0000 0000 0100 0010 XXXX XXXX XXXX XXXX g) CS/LD↑ Update DAC B for both Code and Range h) Alternatively steps f and g could be replaced with LDAC . System Offset and Reference Adjustments Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the LTC2752, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps. 2752f  LTC2752 operaTion The offset adjust pin VOSADJX can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range: ∆VOS [LSB] = – VVOSADJX • 512 VRINX The VOSADJX pins have an input impedance of 1.28MΩ. These pins should be driven with a Thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2752. They should be shorted to GND if not used. The GEADJX pins have an input impedance of 2.56MΩ, and are intended for use with fixed reference voltages only. They should be shorted to GND if not used. Power-On Reset and Clear When power is first applied to the LTC2752, all DACs power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All internal DAC registers are reset to 0 and the DAC outputs initialize to zero volts. If the part is configured for manual span operation, all DACs will be set into the pin-strapped range at the first Update command. This allows the user to simultaneously update span and code for a smooth voltage transition into the chosen output range. When the CLR pin is taken low, a system clear results. The DAC buffers are reset to 0 and the DAC outputs are all reset to zero volts. The Input buffers are left intact, so that any subsequent Update command (including the use of LDAC) restores the addressed DACs to their respective previous states. If CLR is asserted during an instruction, i.e., when CS/LD is low, the instruction is aborted. Integrity of the relevant Input buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. The RFLAG pin is used as a flag to notify the system of a loss of data integrity. The RFLAG output is asserted low at power-up, system clear, or if the supply VDD dips below approximately 2V; and stays asserted until any valid Update command is executed. A 5V control voltage applied to VOSADJX produces ∆VOS = –512 LSB in any output range, assuming a 5V reference voltage at RINX. In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.) ∆VOS = –(1/128)VOSADJX ∆VOS = –(1/64)VOSADJX ∆VOS = –(1/32)VOSADJX [0V to 5V, ±2.5V spans] [0V to 10V, ±5V, –2.5V to 7.5V spans] [±10V span] The gain error adjust pins GEADJX can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range: ∆GE = VGEADJX • 512 VRINX The gain-error delta is non-inverting for positive reference voltages. Note that this pin compensates the gain by altering the inverted reference voltage VREFX. In voltage terms, the VREFX delta is inverted and attenuated by a factor of 128. ∆VREFX = –(1/128)GEADJX The nominal input range of these pins is ±5V; other voltages of up to ±15V may be used if needed. However, do not use voltages divided down from power supplies; reference-quality, low-noise inputs are required to maintain the best DAC performance. 2752f  LTC2752 applicaTions inForMaTion Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC2752, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 4 and 5 contain equations for evaluating the effects of op amp parameters on the LTC2752’s accuracy when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Table 6 contains a partial list of Linear Technology precision op amps recommended for use with the LTC2752. The easy-to-use design equations simplify the selection of op amps to meet the system’s specified error budget. Select the amplifier from Table 6 and insert the specified op amp parameters in Table 5. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate. Table 4. Coefficients for the Equations of Table 5 OUTPUT RANGE 5V 10V ±5V ±10V ±2.5V –2.5V to 7.5V A1 1.1 2.2 2 4 1 1.9 A2 2 3 2 4 1 3 A3 1 0.5 1 0.83 1.4 0.7 1 1 1 0.5 A4 A5 1 1.5 1.5 2.5 1 1.5 Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp. OP AMP VOS1 (mV) INL (LSB) DNL (LSB) UNIPOLAR OFFSET (LSB) BIPOLAR ZERO ERROR (LSB) 5V A3 • VOS1 • 19.6 • V REF 5V IB1 • 0.13 • V REF 0 A4 • VOS2 • 13.1 • 5V VREF 5V A4 • IB2 • 0.13 • VREF 66 A4 • AVOL2 UNIPOLAR GAIN ERROR (LSB) BIPOLAR GAIN ERROR (LSB) 5V 5V 5V VOS1 • 3 • V VOS1 • 0.78 • V A3 • VOS1 • 13.1 • V REF REF REF 5V 5V 5V IB1 (nA) IB1 • 0.0003 • V IB1 • 0.00008 • V IB1 • 0.13 • V REF REF REF 16.5 1.5 AVOL1 (V/mV) A1 • A A2 • A 0 VOL1 VOL1 VOS2 (mV) IB2 (nA) AVOL2 (V/mV) 0 0 0 0 0 0 0 0 0 5V 5V VOS1 • 13.1 • V VOS1 • 13.1 • V REF REF 5V 5V IB1 • 0.0018 • V I • 0.0018 • V REF B1 REF 131 131 A5 • A5 • AVOL1 AVOL1 5V 5V VOS2 • 26.2 • VOS2 • 26.2 • VREF VREF 5V 5V IB2 • 0.26 • IB2 • 0.26 • VREF VREF 131 131 AVOL2 AVOL2 Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2752 with Relevant Specifications AMPLIFIER SPECIFICATIONS VOS µV 25 50 60 70 75 125 IB nA 2 0.35 0.25 20 10 10 A VOL V/mV 800 1000 1500 4000 5000 2000 VOLTAGE NOISE nV/√Hz 10 14 14 2.7 5 5 CURRENT NOISE pA/√Hz 0.12 0.008 0.008 0.3 0.6 0.6 SLEW RATE V/µs 0.25 0.2 0.16 4.5 22 22 GAIN BANDWIDTH PRODUCT MHz 0.8 0.7 0.75 12.5 90 90 tSETTLING with LTC2752 µs 120 120 115 19 2 2 POWER DISSIPATION mW 46 11 10.5/Op Amp 69/Op Amp 117 123/Op Amp AMPLIFIER LT1001 LT1097 LT1112 (Dual) LT1124 (Dual) LT1468 LT1469 (Dual) 2752f 0 LTC2752 applicaTions inForMaTion Op amp offset will contribute mostly to output offset and gain error, and has minimal effect on INL and DNL. For example, for the LTC2752 with a 5V reference in 5V unipolar mode, a 250µV op amp offset will cause a 3.3LSB zeroscale error and a 3.3LSB gain error; but only 0.75LSB of INL degradation and 0.2LSB of DNL degradation. While not directly addressed by the simple equations in Tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp’s data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers into the VOS and IB equations from Table 5 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 74, Component and Measurement Advances Ensure 16-Bit DAC Settling Time, offers a thorough discussion of 16-bit DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC2752 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2752 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (±0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference’s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit’s apparent INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system’s noise floor. This in turn can degrade system dynamic range and signal-to-noise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236 and LTC6655, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level Table 7. Partial List of LTC Precision References Recommended for Use with the LTC2752 with Relevant Specifications REFERENCE LT1019A-5, LT1019A-10 LT1236A-5, LT1236A-10 LT1460A-5, LT1460A-10 LT1790A-2.5 LTC6652A-2.048 LTC6652A-2.5 LTC6652A-3 LTC6652A-3.3 LTC6652A-4.096 LTC6652A-5 LT6655A-25, LT6655A-5 ±0.025% Max 2ppm/°C Max INITIAL TOLERANCE ±0.05% Max ±0.05% Max ±0.075% Max ±0.05% Max ±0.05% Max TEMPERATURE DRIFT 5ppm/°C Max 5ppm/°C Max 10ppm/°C Max 10ppm/°C Max 5ppm/°C Max 0.1Hz to 10Hz NOISE 12µVP-P 3µVP-P 20µVP-P 12µVP-P 2.1ppmP-P 2.1ppmP-P 2.1ppmP-P 2.2ppmP-P 2.3ppmP-P 2.8ppmP-P 0.25ppmP-P 2752f  LTC2752 applicaTions inForMaTion in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane is necessary, as are star grounding techniques. Keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept without using separate star traces. The IOUT2 pins are of particular concern; INL will be degraded by the code dependent currents carried by the IOUT2XF and IOUT2XS pins if voltage drops to ground are allowed to develop. The best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part. Alternatively, the pins may be routed to the star ground point if necessary; join the force and sense pins together at the part and route one trace for each channel of no more than 120 squares of 1oz. copper. In the rare case in which neither of these alternatives is practicable, a force/sense amplifier should be used as a ground buffer (see Typical Applications). Note, however, that the voltage offset of the ground buffer amp directly contributes to the effects on accuracy specified in Table 5 under VOS1. The combined effects of the offsets can be calculated by substituting the total offset from IOUT1X to IOUT2XS for VOS1 in the equations. ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE IOUT2AS 8 200Ω 200Ω 1000pF 3 IOUT2AS 8 2 IOUT2AF ZETEX BAT54S 9 1 6 LT1468 IOUT2AF 9 1 6 LT1012 2 3 2 3 ZETEX* BAT54S VREF 5V 47, 48 ROFSA 3 5, 6 RINA *SCHOTTKY BARRIER DIODE LTC2752 RFBA 45, 46 15pF 1/2 LT1469 2 150pF 4 GEADJA 3 RCOMA DAC A IOUT1A 44 3 IOUT2A 8, 9 1, 2 REFA VOSADJA 43 DAC B – + 2752 F05 Figure 5. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier  + – 1 2 – + 2 – + 3 – + 1/2 LT1469 1 VOUTA 2752f LTC2752 package DescripTion (Reference LTC DWG # 05-08-1760 Rev Ø) 7.15 – 7.25 5.50 REF 48 9.00 BSC 7.00 BSC LX Package 48-Lead Plastic LQFP (7mm × 7mm) 0.50 BSC 1 2 48 1 2 SEE NOTE: 4 9.00 BSC 5.50 REF 0.20 – 0.30 7.15 – 7.25 A A 7.00 BSC PACKAGE OUTLINE C0.30 – 0.50 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 11° – 13° 1.60 1.35 – 1.45 MAX R0.08 – 0.20 GAUGE PLANE 0.25 0° – 7° 11° – 13° 1.00 REF 0.45 – 0.75 SECTION A – A 0.09 – 0.20 0.50 BSC 0.17 – 0.27 0.05 – 0.15 LX48 LQFP 0907 REVØ NOTE: 1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE 2. DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT 4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 5. DRAWING IS NOT TO SCALE 2752f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LTC2752 Typical applicaTion Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply 2 15V 2 C6 10µF IN OUT LT1236-5 4 1 VCC CS2 SPI BUS SDI SCK 4 6 5 CS/LD SDI SCK GND LTC2634-MSELMX12 10, 11 6 C7 10µF 5V REFERENCE 15V 7 7 REF VOUTA VOUTB VOUTC VOUTD 2 3 8 9 10 1 10 1 10 1 LT1991 LT1991 LT1991 C2 0.1µF 16 VDD 6 4 43 33 42 6 LTC2752 6 22 23 6 24 25 RFBB 39, 40 C4 27pF 15V 7 10k 26 LDAC 10k 19 CLR 47, 48 ROFSA RINA 5, 6 3 RCOMA 1, 2 REFA RFBA 45, 46 C3 27pF 15V 7 C1 –15V 100pF LT1991 450k 1 450k 4 –15V GEADJB VOSADJB IOUT1A IOUT2A 8, 9 3 IOUT1B IOUT2B S0 S1 S2 CS/LD 11 SDI 12 SCK 13 SRO 14 ROFSB 37, 38 RINB RCOMB 34 28, 29 3 GND REFB C5 100pF 15V 7 31, 32 7, 10, 15, 17, 18, 27, 30 35, 36 CS1 SDI SCK SRO SPI BUS 2 relaTeD parTs PART NUMBER LTC2757 LTC2754 LTC2751 LTC2753 LTC2755 LTC1590 LTC1592 LTC2704 References LTC6655 LT1027 LT1236A-5 Amplifiers LT1012 LT1001 LT1468/LT1469 Precision Operational Amplifier Precision Operational Amplifier Single/Dual 16-Bit Accurate Op-Amp 25µV Max Offset, 100pA Max Bias Current, 0.5µVP-P Noise, 380µA Supply Current 25µV Max Offset, 0.3µVP-P Noise, High Output Drive 90MHz GBW, 22V/μs Slew Rate, 0.3µVP-P Noise 2752f LT 0510 • PRINTED IN USA DESCRIPTION Single Parallel 18-Bit IOUT SoftSpan DAC Quad Serial 16-Bit/12-Bit IOUT SoftSpan DACs Dual Parallel 16-Bit/14-Bit/12-Bit IOUT SoftSpan DACs Dual Serial 12-Bit Multiplying IOUT DAC Single Serial 16-Bit/14-Bit/12-Bit IOUT SoftSpan DAC Quad Serial 16-Bit/14-Bit/12-Bit VOUT SoftSpan DACs Precision Reference Precision Reference Precision Reference COMMENTS ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm LQFP-48 Package ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 8mm QFN-52 Package ±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm QFN-48 Package ± 0.5LSB INL/DNL 2-Quadrant, 16-Pin Narrow SO and PDIP Packages ±1LSB INL/DNL, Software-Selectable Ranges, 16-Lead SSOP Package ±1LSB INL/DNL, Integrated 4-Quadrant Resistors, 28-Lead SSOP Package ±1LSB INL/DNL, Software-Selectable Ranges, Integrated Amplifiers 0.025% Maximum Tolerance, 0.25ppmP-P 0.1Hz to 10Hz Noise 2ppm/°C Maximum Drift 0.05% Maximum Tolerance, 1ppmP-P 0.1Hz to 10Hz Noise Single Parallel 16-Bit/14-Bit/12-Bit IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, 5mm × 7mm QFN-38 Package Quad Parallel 16-Bit/14-Bit/12-Bit IOUT SoftSpan DACs ±1LSB INL/DNL, Software-Selectable Ranges, 9mm × 9mm QFN-64 Package LTC1591/LTC1597 Single Parallel 16-Bit/14-Bit IOUT DACs  Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com – + 3 6 4 LT1012A –15V  LINEAR TECHNOLOGY CORPORATION 2010 + – M-SPAN 41 2 + – + – 10 450k GEADJA VOSADJA – + 3 15V LT1012A 7 6 4 44 2 6 VOUT DACA 4 LT1468 –15V 6 VOUT DACB 4 LT1468 –15V 2752 TA02