LTC2912CTS8-2

LTC2912 Single UV/OV Voltage Monitor FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LTC®2912 voltage monitor is designed to detect power supply undervoltage and overvoltage events. The VL and VH monitor inputs include filtering to reject brief glitches, thereby ensuring reliable reset operation without false or noisy triggering. An adjustable timer defines the duration of the overvoltage and undervoltage reset outputs which function independently. While the LTC2912 operates directly from 2.3V to 6V supplies, an internal VCC shunt regulator coupled with low supply current demand allows operation from higher voltages such as 12V, 24V or 48V. Three output configurations are available: the LTC29121 has a latch control for the OV output; the LTC2912-2 has an OV and UV output disable feature for margining applications; the LTC2912-3 is identical to the LTC2912-1 but with a noninverting, OV output. The LTC2912 provides a precise, versatile, space-conscious micropower solution for voltage monitoring. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Monitors Single Voltage Adjustable UV and OV Trip Values Guaranteed Threshold Accuracy: ±1.5% Power Supply Glitch Immunity Adjustable Reset Timeout with Timeout Disable 29μA Quiescent Current Open-Drain OV and UV Outputs Guaranteed OV and UV for VCC ≥ 1V Available in 8-Lead ThinSOTTM and (3mm × 2mm) DFN Packages APPLICATIONS ■ ■ ■ Desktop and Notebook Computers Network Servers Core, I/O Voltage Monitors TYPICAL APPLICATION Single OV/UV Supply Monitor, 3.3V ±10% Tolerance POWER SUPPLY 3.3V 0.1μF UV/OV TIMEOUT PERIOD, tUOTO (ms) Reset Time-Out Period vs Capacitance 10000 1000 27.4k VH 1k VL 4.53k GND VCC LTC2912-1 OV UV SYSTEM 100 10 LATCH TMR 22nF 2912 TA01a TIMEOUT = 200ms 1 0.1 1 10 100 TMR PIN CAPACITANCE, CTMR (nF) 1000 2912 G08 2912fa 1 LTC2912 ABSOLUTE MAXIMUM RATINGS (Note 1) Terminal Voltages VCC (Note 3)............................................. –0.3V to 6V OV, UV, OV ............................................ –0.3V to 16V TMR ..........................................–0.3V to (VCC + 0.3V) VH, VL, LATCH, DIS .............................. –0.3V to 7.5V Terminal Currents IVCC ....................................................................10mA IUV, IOV, IOV ........................................................10mA Operating Temperature Range LTC2912C ................................................ 0°C to 70°C LTC2912I.............................................. –40°C to 85°C LTC2912H .......................................... –40°C to 125°C Storage Temperature Range TSOT.................................................. –65°C to 125°C DFN.................................................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) TSOT................................................................. 300°C PACKAGE/ORDER INFORMATION TOP VIEW TOP VIEW LATCH 1 UV 2 OV 3 GND 4 8 VCC 7 VH 6 VL 5 TMR VCC 1 VH 2 VL 3 TMR 4 9 8 LATCH 7 UV 6 OV 5 GND TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 195°C/W DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL ORDER PART NUMBER LTC2912CTS8-1 LTC2912ITS8-1 LTC2912HTS8-1 TOP VIEW DIS 1 UV 2 OV 3 GND 4 TS8 PART MARKING* LTCJW LTCJW LTCJW ORDER PART NUMBER LTC2912CDDB-1 LTC2912IDDB-1 LTC2912HDDB-1 TOP VIEW VCC 1 VH 2 VL 3 TMR 4 9 DDB PART MARKING* LCJZ LCJZ LCJZ 8 DIS 7 UV 6 OV 5 GND 8 VCC 7 VH 6 VL 5 TMR TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 195°C/W DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL ORDER PART NUMBER LTC2912CTS8-2 LTC2912ITS8-2 LTC2912HTS8-2 TOP VIEW LATCH 1 UV 2 OV 3 GND 4 TS8 PART MARKING* LTCJX LTCJX LTCJX ORDER PART NUMBER LTC2912CDDB-2 LTC2912IDDB-2 LTC2912HDDB-2 TOP VIEW VCC 1 VH 2 VL 3 TMR 4 9 DDB PART MARKING* LCKB LCKB LCKB 8 LATCH 7 UV 6 OV 5 GND 8 VCC 7 VH 6 VL 5 TMR TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 195°C/W DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL ORDER PART NUMBER LTC2912CTS8-3 LTC2912ITS8-3 LTC2912HTS8-3 TS8 PART MARKING* LTCJY LTCJY LTCJY ORDER PART NUMBER LTC2912CDDB-3 LTC2912IDDB-3 LTC2912HDDB-3 DDB PART MARKING* LCKC LCKC LCKC 2912fa Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. 2 LTC2912 ELECTRICAL CHARACTERISTICS SYMBOL VSHUNT ΔVSHUNT VCC VCCR(MIN) VCC(UVLO) ΔVCC(UVHYST) ICC VUOT tUOD IVHL tUOTO VLATCH(VIH) VLATCH(VIL) ILATCH IDIS VDIS(VIH) VDIS(VIL) ITMR(UP) ITMR(DOWN) VTMR(DIS) VOH VOL PARAMETER VCC Shunt Regulator Voltage VCC Shunt Regulator Load Regulation Supply Voltage (Note 3) Minimum VCC Output Valid Supply Undervoltage Lockout Supply Undervoltage Lockout Hysteresis Supply Current Undervoltage/Overvoltage Threshold Undervoltage/Overvoltage Threshold to Output Delay VH, VL Input Current –40°C < TA < 125° UV/OV Time-Out Period OV Latch Clear Input High OV Latch Clear Input Low LATCH Input Current DIS Input Current DIS Input High DIS Input Low TMR Pull-Up Current TMR Pull-Down Current Timer Disable Voltage Output Voltage High UV/OV/OV Output Voltage Low UV/OV/OV VTMR = 0V –40°C < TA < 125° VTMR = 1.6V –40°C < TA < 125° Referenced to VCC VCC = 2.3V, IUV/OV = –1μA VCC = 2.3V, IUV/OV = 2.5mA VCC = 1V, IUV = 100μA VLATCH > 0.5V VDIS > 0.5V CTMR = 1nF –40°C < TA < 125° VHn = VUOT – 5mV or VLn = VUOT + 5mV DIS = 0V DIS = 0V, VCC Rising DIS = 0V VCC = 2.3V to 6V The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VL = 0.45V, VH = 0.55V, LATCH = VCC unless otherwise noted. (Note 2) CONDITIONS ICC = 5mA –40°C < TA < 125° ICC = 2mA to 10mA ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN 6.2 6.2 2.3 1.9 5 492 50 TYP 6.6 6.6 200 MAX 7.2 7.3 300 VSHUNT 1 UNITS V V mV V V V mV μA mV μs nA nA ms ms V V μA μA V V μA μA μA μA mV V 2 25 29 500 125 2.1 50 70 508 500 ±15 ±30 6 6 1.2 8.5 8.5 12.5 14 0.8 ±1 1 1.2 2 3.3 0.8 –1.3 –1.2 1.3 1.2 –180 1 –2.1 –2.1 2.1 2.1 –270 0.10 0.01 –2.8 –2.8 2.8 2.8 0.30 0.15 V V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: VCC maximum pin voltage is limited by input current. Since the VCC pin has an internal 6.5V shunt regulator, a low impedance supply that exceeds 6V may exceed the rated terminal current. Operation from higher voltage supplies requires a series dropping resistor. See Applications Information. 2912fa 3 LTC2912 TIMING DIAGRAMS VH Monitor Timing VH VUOT tUOD UV 1V 2912 TD01 VL Monitor Timing VL VUOT tUOD OV 1V 2912 TD02 tUOTO tUOTO VH Monitor Timing (TMR Pin Strapped to VCC) VH VUOT tUOD UV 1V 2912 TD03 VL Monitor Timing (TMR Pin Strapped to VCC) VL VUOT tUOD OV 1V 2912 TD04 tUOD tUOD TYPICAL PERFORMANCE CHARACTERISTICS Input Threshold Voltage vs Temperature 0.505 0.504 THRESHOLD VOLTAGE, VUOT (V) 0.503 0.502 ICC (μA) 0.501 0.500 0.499 0.498 0.497 0.496 0.495 –50 –25 25 50 0 TEMPERATURE (°C) 75 100 2912 G01 Supply Current vs Temperature 45 40 VCC = 5V 35 30 25 VCC = 2.3V 20 15 –50 VCC = 3.3V VCC (V) 6.6 6.5 6.4 6.3 6.8 6.7 VCC Shunt Voltage vs Temperature 10mA 5mA 2mA 1mA 200μA –25 0 25 50 TEMPERATURE (°C) 75 100 2912 G02 6.2 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2912 G03 VCC Shunt Voltage vs ICC 6.75 TYPICAL TRANSIENT DURATION (μs) 700 600 500 400 300 200 100 Typical Transient Duration vs Comparator Overdrive 0.8 UV Output Voltage vs VCC 6.65 VCC (V) 6.55 UV VOLTAGE (V) RESET OCCURS ABOVE CURVE 0.6 VCC 0.4 UV WITH 10k PULL-UP 0.2 UV WITHOUT PULL-UP 0 0 0.2 0.6 0.8 0.4 SUPPLY VOLTAGE, VCC (V) 1 2912 G06 6.45 –40°C 6.35 25°C 85°C 6.25 –2 0 2 6 4 ICC (mA) 8 10 12 VCC = 6V VCC = 2.3V 50 0.1 1 10 100 COMPARATOR OVERDRIVE PAST THRESHOLD (%) 2912 G05 2912 G04 2912fa 4 LTC2912 TYPICAL PERFORMANCE CHARACTERISTICS UV Output Voltage vs VCC 5 UV/OV TIMEOUT PERIOD, tUOTO (ms) VH = 0.55V SEL = VCC 10000 PULL-DOWN CURRENT, IUV (mA) Reset Time-Out Period vs Capacitance 5 UV, ISINK vs VCC VH = 0.45V SEL = VCC UV AT 150mV 3 4 UV VOLTAGE (V) 1000 4 3 100 2 2 UV AT 50mV 1 1 10 0 0 1 3 4 2 SUPPLY VOLTAGE, VCC (V) 5 2912 G07 1 0.1 0 1 10 100 TMR PIN CAPACITANCE, CTMR (nF) 1000 2912 G08 0 1 3 4 2 SUPPLY VOLTAGE, VCC (V) 5 2912 G09 UV/OV, Voltage Output Low vs Output Sink Current 1.0 85°C 0.8 UV/OV, VOL (V) –40°C 0.6 25°C UV/OV TIMEOUT PERIOD, tOUTO (ms) 12 11 10 9 8 7 Reset Timeout Period vs Temperature CTMR = 1nF 0.4 0.2 0 0 5 10 15 20 IUV/OV (mA) 25 30 1912 G10 6 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2912 G11 PIN FUNCTIONS (DFN/TSOT Packages) DIS (Pin 8/Pin 1, LTC2912-2): Output Disable Input. Disables the OV and UV output pins. When DIS is pulled high, the OV and UV pins are not asserted except during a UVLO condition. Pin has a weak (2μA) internal pull-down to GND. Leave pin open if unused. Exposed Pad (Pin 9, DDB Package): Exposed Pad may be left open or connected to device ground. GND (Pin 5/Pin 4): Device Ground. LATCH (Pin 8/Pin 1, LTC2912-1, LTC2912-3): OV/OV Latch Clear/Bypass Input. When pulled high, OV/OV latch is cleared. While held high, OV/OV has a similar delay and output characteristic as UV. OV (Pin 6/Pin 3, LTC2912-1, LTC2912-2): Overvoltage Logic Output. Asserts low when the VL input voltage is above threshold. Latched low (LTC2912-1). Held low for programmed delay time after VL input is valid (LTC2912-2). Pin has a weak pull-up to VCC and may be pulled above VCC using an external pull-up. Leave pin open if unused. 2912fa 5 LTC2912 PIN FUNCTIONS (DFN/TSOT Packages) OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output. Asserts high with a weak internal pull-up to VCC when the VL input is above threshold. Latches high. May be pulled above VCC using an external pull-up. Leave pin open if unused. TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external capacitor (CTMR) of at least 10pF to GND to set a reset delay time of 9ms/nF A 1nF capacitor will generate an . 8.5ms reset delay time. Tie pin to VCC to bypass timer. UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low when the VH input voltage is below threshold. Held low for a programmed delay time after the VH input is valid. Pin has a weak pull-up to VCC and may be pulled above VCC using an external pull-up. Leave pin open if unused. VCC (Pin 1/Pin 8): Supply Voltage. Bypass this pin to GND with a 0.1μF (or greater) capacitor. Operates as a direct supply input for voltages up to 6V. Operates as a shunt regulator for supply voltages greater than 6V and should have a resistance between the pin and the supply to limit input current to no greater than 10mA. When used without a current-limiting resistance, pin voltage must not exceed 6V. VH (Pin 2/Pin 7): Voltage High Input. When the voltage on this pin is below 0.5V, an undervoltage condition is triggered. Tie pin to VCC if unused. VL (Pin 3/Pin 6): Voltage Low Input. When the voltage on this pin is above 0.5V, an overvoltage condition is triggered. Tie pin to GND if unused. BLOCK DIAGRAM 1 VCC 4 TMR VCC 400k UV UV PULSE GENERATOR DISABLE UVLO UVLO OSCILLATOR 2 3 VL 0.5V GND LTC2912-3 5 LTC2912-2 2912 BD 6 + – + – + – 2V VCC VH 7 VCC 400k OV PULSE GENERATOR DISABLE LTC2912-1 LTC2912-2 OV/OV + – 6 OV LATCH CLEAR/BYPASS + – LTC2912-1, LTC2912-3 LATCH 1V 8 1V DIS 2μA 8 2912fa LTC2912 APPLICATIONS INFORMATION Voltage Monitoring The LTC2912 is a low power voltage monitoring circuit with an undervoltage and an overvoltage input. A timeout period that holds OV and UV asserted after a fault has cleared is adjustable using an external capacitor and may be externally disabled. When configured to monitor a positive voltage Vn using the 3-resistor circuit configuration shown in Figure 1, VH will be connected to the high side tap of the resistive divider and VL will be connected to the low side tap of the resistive divider. 3-Step Design Procedure The following 3-step design procedure allows selecting appropriate resistances to obtain the desired UV and OV trip points for the voltage monitor circuit in Figure 1. For supply monitoring, Vn is the desired nominal operating voltage, In is the desired nominal current through the resistive divider, VOV is the desired overvoltage trip point and VUV is the desired undervoltage trip point. 1. Choose RA to obtain the desired OV trip point RA is chosen to set the desired trip point for the overvoltage monitor. V R A = 0.5V • n In VOV Vn RC LTC2912 VH 2. Choose RB to obtain the desired UV trip point Once RA is known, RB is chosen to set the desired trip point for the undervoltage monitor. V RB = 0.5V • n – RA In VUV 3. Choose RC to complete the design Once RA and RB are known, RC is determined by: RC = Vn – RA – RB In (3) (2) If any of the variables Vn, In, VUV or VOV change, then each step must be recalculated. Voltage Monitor Example A typical voltage monitor application is shown in Figure 2. The monitored voltage is a 5V ±10% supply. Nominal current in the resistive divider is 10μA. 1. Find RA to set the OV trip point of the monitor. RA = 0.5V • 5V ≈ 45.3k 10µA 5.5V 2. Find RB to set the UV trip point of the monitor. RB = 0.5V • 5V – 45.3k ≅ 10.2k 10µA 4.5V 3. Determine RC to complete the design. (1) RB + – 0.5V V1 5V ±10% OV RC 442k VH1 RB 10.2k 2912 F01 RA Figure 1. 3-Resistor Positive UV/OV Monitoring Configuration + VL + – – UV RC = 5V – 45.3k − 10.2k ≈ 442k 10µA VCC 5V VCC OV UV GND 2912 F02 LTC2912-1 VL1 RA 45.3k Figure 2. Typical Supply Monitor 2912fa 7 LTC2912 APPLICATIONS INFORMATION Power-Up/Power-Down As soon as VCC reaches 1V during power up, the UV output asserts low and the OV output weakly pulls to VCC. The LTC2912 is guaranteed to assert UV low, OV high (LTC2912-1, LTC2912-2) and OV low (LTC2912-3) under conditions of low VCC, down to VCC = 1V. Above VCC = 2V (2.1V maximum), the VH and VL inputs take control. Once the VH input and VCC become valid an internal timer is started. After an adjustable delay time, UV weakly pulls high. Threshold Accuracy Reset threshold accuracy is important in a supply-sensitive system. Ideally, such a system resets only if supply voltages fall outside the exact thresholds for a specified margin. Both LTC2912 inputs have a relative threshold accuracy of ±1.5% over the full operating temperature range. For example, when the LTC2912 is programmed to monitor a 5V input with a 10% tolerance, the desired UV trip point is 4.5V. Because of the ±1.5% relative accuracy of the LTC2912, the UV trip point can be anywhere between 4.433V and 4.567V which is 4.5V ±1.5%. Likewise, the accuracy of the resistances chosen for RA, RB and RC can affect the UV and OV trip points as well. Using the example just given, if the resistances used to set the UV trip point have 1% accuracy, the UV trip range is between 4.354V and 4.650V. This is illustrated in the following calculations. The UV trip point is given as: VUV = 0.5V 1 + RC RA + RB Therefore, VUV(MIN) = 0.5V • 0.985 • 1 + 8 0.99 = 4.354V 1.01 and VUV(MAX) = 0.5V • 1.015 • 1 + 8 1.01 = 4.650V 0.99 Glitch Immunity In any supervisory application, noise riding on the monitored DC voltage causes spurious resets. To solve this problem without adding hysteresis, which causes a new error term in the trip voltage, the LTC2912 lowpass filters the output of the first stage comparator at each input. This filter integrates the output of the comparator before asserting the UV or OV logic. A transient at the input of the comparator of sufficient magnitude and duration triggers the output logic. The Typical Performance Characteristics show a graph of the Transient Duration vs Comparator Overdrive. UV/OV Timing The LTC2912 has an adjustable timeout period (tUOTO) that holds OV, OV or UV asserted after each fault has cleared. This delay assures a minimum reset pulse width allowing settling time for the monitored voltage after it has entered the “valid” region of operation. The two extreme conditions, with a relative accuracy of 1.5% and resistance accuracy of 1%, result in: VUV(MIN) = 0.5V • 0.985 • 1 + and VUV(MAX) = 0.5V • 1.015 • 1 + For a desired trip point of 4.5V, RC • 1.01 (RA + RB ) • 0.99 RC =8 RA + RB RC • 0.99 (RA + RB ) • 1.01 2912fa 8 LTC2912 APPLICATIONS INFORMATION When the VH input drops below its designed threshold, the UV pin asserts low. When the input recovers above its designed threshold, the UV output timer starts. If the input remains above the designed threshold when the timer finishes, the UV pin weakly pulls high. However, if the input falls below its designed threshold during this timeout period, the timer resets and restarts when the input is above the designed threshold. The OV and OV outputs behave as the UV output when LATCH is high (LTC2912-1, LTC2912-3). Selecting the UV/OV Timing Capacitor The UV and OV timeout period (tUOTO) for the LTC2912 is adjustable to accommodate a variety of applications. Connecting a capacitor, CTMR, between the TMR pin and ground sets the timeout period. The value of capacitor needed for a particular timeout period is: CTMR = tUOTO • 115 • 10–9 [F/s] The Reset Timeout Period vs Capacitance graph found in the Typical Performance Characteristics shows the desired delay time as a function of the value of the timer capacitor that must be used. The TMR pin must have a minimum 10pF load or be tied to VCC. For long timeout periods, the only limitation is the availability of a large value capacitor with low leakage. Capacitor leakage current must not exceed the minimum TMR charging current of 1.3μA.Tying the TMR pin to VCC bypasses the timeout period. Undervoltage Lockout When VCC falls below 2V, the LTC2912 asserts an undervoltage lockout (UVLO) condition. During UVLO, UV is asserted and pulled low while OV and OV are cleared and blocked from asserting. When VCC rises above 2V, UV follows the same timing procedure as an undervoltage condition on the VH input. Shunt Regulator The LTC2912 has an internal shunt regulator. The VCC pin operates as a direct supply input for voltages up to 6V. Under this condition, the quiescent current of the device remains below a maximum of 70μA. For VCC voltages higher than 6V, the device operates as a shunt regulator and should have a resistance RZ between the supply and the VCC pin to limit the current to no greater than 10mA. When choosing this resistance value, select an appropriate location on the I-V curve shown in the Typical Performance Characteristics to accommodate any variations in VCC due to changes in current through RZ. UV, OV and OV Output Characteristics The DC characteristics of the UV, OV and 0V pull-up and pull-down strength are shown in the Typical Performance Characteristics. Each pin has a weak internal pull-up to VCC and a strong pull-down to ground. This arrangement allows these pins to have open-drain behavior while possessing several other beneficial characteristics. The weak pull-up eliminates the need for an external pull-up resistor when the rise time on the pin is not critical. On the other hand, the open-drain configuration allows for wired-OR connections, and is useful when more than one signal needs to pull down on the output. VCC of 1V guarantees a maximum VOL = 0.15V at UV. At VCC = 1V, the weak pull-up current on OV is barely turned on. Therefore, an external pull-up resistor of no more than 100k is recommended on the OV pin if the state and pull-up strength of the OV pin is crucial at very low VCC. Note however, by adding an external pull-up resistor, the pull-up strength on the OV pin is increased. Therefore, if it is connected in a wired-OR connection, the pull-down strength of any single device must accommodate this additional pull-up strength. Output Rise and Fall Time Estimation The UV, OV and OV outputs have strong pull-down capability. The following formula estimates the output fall time (90% to 10%) for a particular external load capacitance (CLOAD): tFALL ≈ 2.2 • RPD • CLOAD where RPD is the on-resistance of the internal pull-down transistor, typically 50Ω at VCC > 1V and at room temperature (25°C). CLOAD is the external load capacitance on the pin. Assuming a 150pF load capacitance, the fall time is 16.5ns. 2912fa 9 LTC2912 APPLICATIONS INFORMATION The rise time on the UV, OV and 0V pins is limited by a 400k pull-up resistance to VCC. A similar formula estimates the output rise time (10% to 90%) at the UV, OV and OV pins: tRISE ≈ 2.2 • RPU • CLOAD where RPU is the pull-up resistance. OV/OV Latch (LTC2912-1, LTC2912-3) With the LATCH pin held low, the OV pin latches low (LTC2912-1) and the OV pin latches high (LTC2912-3) when an OV condition is detected. The latch is cleared by raising the LATCH pin high. If an OV condition clears while LATCH is held high, the latch is bypassed and the OV and OV pins behave the same as the UV pin with a similar timeout period at the output. If LATCH is pulled low while the timeout period is active, the OV and OV pins latch as before. Disable (LTC2912-2) The LTC2912-2 allows disabling the UV and OV outputs via the DIS pin. Pulling DIS high forces both outputs to remain weakly pulled high, regardless of any faults that occur on the inputs. However, if a UVLO condition occurs, UV asserts and pulls low, but the timeout function is bypassed. UV pulls high as soon as the UVLO condition is cleared. DIS has a weak 2μA (typical) internal pull-down current guaranteeing normal operation with the pin left open. TYPICAL APPLICATIONS Dual UV/OV Supply Monitor, 3.3V ±10% Tolerance POWER SUPPLY 3.3V CBYP 0.1μF 1 VCC VH LTC2912-1 VL UV LATCH TMR 4 OV 6 7 8 2912 TA02 48V Supply Monitor (