LTC3405AES6-1.375

LTC3405A-1.375 1.375V, 1.5MHz, 300mA Synchronous Step-Down Regulators in ThinSOT FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO High Efficiency: Up to 90% Very Low Quiescent Current: Only 20µA During Operation 300mA Output Current at VIN = 3V 2.5V to 5.5V Input Voltage Range 1.5MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle Stable with Ceramic Capacitors Shutdown Mode Draws < 1µA Supply Current ± 3% Output Voltage Accuracy Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected Low Profile (1mm) ThinSOTTM Package The LTC ®3405A-1.375 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. Supply current during operation is only 20µA and drops to 1.5V). In this mode, the efficiency is lower at light loads, but becomes comparable to Burst Mode operation when the output load exceeds 25mA. The advantage of pulse skipping mode is lower output ripple and less interference to audio circuitry. 6 + – W 0.65V 4 VIN – + U U U – + 0.4V – + EN SLEEP – BURST Q Q SWITCHING LOGIC AND BLANKING CIRCUIT ICOMP + 5Ω S R RS LATCH ANTISHOOTTHRU 3 SW OV 2 GND 3405A1375 BD 3405a1375f LTC3405A-1.375 OPERATIO When the converter is in Burst Mode operation, the peak current of the inductor is set to approximately 100mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 20µA. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA amplifier’s output rises above the sleep threshold signaling the BURST comparator to trip and turn the top MOSFET on. This process repeats at a rate that is dependent on the load demand. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 210kHz, 1/7 the nominal APPLICATIO S I FOR ATIO The basic LTC3405A-1.375 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the inductor value will fall in the range of 2.2µH to 10µH. Its value is determined by the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in equation 1. A reasonable starting point for setting ripple current is ∆IL = 120mA (40% of 300mA). ∆IL = ( )( ) ⎛V⎞ VOUT ⎜ 1 − OUT ⎟ VIN ⎠ ⎝ fL 1 The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 360mA rated inductor should be enough for most applications (300mA + 60mA). For better efficiency, choose a low DC-resistance inductor. U W UU U (Refer to Functional Diagram) frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 1.5MHz when VOUT rises above 0V. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3405A-1.375 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 100mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3405A-1.375 requires to operate. (1) 3405a1375f 7 LTC3405A-1.375 APPLICATIO S I FOR ATIO Table 1 shows some typical surface mount inductors that work well in LTC3405A-1.375 applications. Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER Taiyo Yuden LB2016T2R2M LB2012T2R2M LB2016T3R3M ELT5KT4R7M LB2016T4R7M ELT5KT6R8M ELT5KT100M MAX DC VALUE CURRENT DCR HEIGHT 2.2µH 2.2µH 3.3µH 4.7µH 4.7µH 6.8µH 10µH 315mA 240mA 280mA 950mA 450mA 210mA 760mA 680mA 620mA 0.13Ω 1.6mm 0.23Ω 1.25mm 0.2Ω 1.6mm 0.2Ω 1.2mm 0.2Ω 2mm 0.25Ω 1.6mm 0.3Ω 1.2mm 0.36Ω 1.2mm 0.23Ω 1.2mm Panasonic Murata Taiyo Yuden Panasonic Panasonic Sumida LQH32CN2R2M33 4.7µH CMD4D116R8MC 6.8µH CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: CIN required IRMS ≅ IOMAX [V (V OUT IN − VOUT VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆VOUT is determined by: 8 U ⎛ 1⎞ ∆VOUT ≅ ∆IL ⎜ ESR + ⎟ 8 fCOUT ⎠ ⎝ where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3405A-1.375’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. Care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. W UU )] 1/ 2 3405a1375f LTC3405A-1.375 APPLICATIO S I FOR ATIO Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3405A-1.375 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 2. 1 VIN = 3.6V 0.1 POWER LOST (W) 0.01 0.001 0.0001 0.1 1 100 10 LOAD CURRENT (mA) 1000 3405A1375 F02 Figure 2. Power Lost vs Load Current 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than U the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In most applications, the LTC3405A-1.375 does not dissipate much heat due to its high efficiency. But, in applications where they run at high ambient temperature with low supply voltage, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To keep the LTC3405A-1.375 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(θJA) 3405a1375f W UU 9 LTC3405A-1.375 APPLICATIO S I FOR ATIO where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3405A-1.375 with an input voltage of 2.7V, a load current of 300mA and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the Pchannel switch at 70°C is approximately 0.94Ω and the RDS(ON) of the N-channel synchronous switch is approximately 0.75Ω. The series resistance looking into the SW pin is: RSW = 0.95Ω (0.51) + 0.75Ω (0.49) = 0.85Ω Therefore, power dissipated by the part is: PD = ILOAD2 • RSW = 76.5mW For the SOT-23 package, the θJA is 250°C/ W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.0765)(250) = 89.1°C which is well below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. 10 U PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3405A-1.375. These items are also illustrated graphically in Figures 3 and 4. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 3. Keep the (–) plates of CIN and COUT as close as possible. 1 RUN MODE 6 LTC3405A-1.375 2 W UU – VOUT COUT GND VOUT VIN CIN 5 + 3 L1 SW 4 VIN 3405A1375 F03 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 3. LTC3405A-1.375 Layout Diagram Design Example As a design example, assume the LTC3405A-1.375 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.15A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 1.375V. With this information we can calculate L using equation (1), L= ( )( ) ⎛V⎞ VOUT ⎜ 1 − OUT ⎟ VIN ⎠ ⎝ f ∆IL 1 (3) 3405a1375f LTC3405A-1.375 APPLICATIO S I FOR ATIO Substituting VOUT = 1.375V, VIN = 4.2V, ∆IL = 60mA and f = 1.5MHz in equation (3) gives: L= EFFICIENCY (%) ⎛ 1.375V ⎞ 1.375V ⎜1 − ⎟ ≅ 10µH 1.5MHz(60mA) ⎝ 4.2V ⎠ VIA TO VIN VOUT PIN 1 LTC3405A-1.375 L1 SW VIN COUT GND CIN 3405A1518 F04 Figure 4. LTC3405A-1.375 Suggested Layout For best efficiency choose a 200mA or greater inductor with less than 0.3Ω series resistance. CIN will require an RMS current rating of at least 0.125A ≅ ILOAD(MAX)/2 at temperature and COUT will require an ESR of less than 0.5Ω. In most cases, a ceramic capacitor will satisfy this requirement. Figure 5 shows the complete circuit along with its efficiency curve. VIN 2.7V TO 4.2V 4 CIN*** 2.2µF CER VIN RUN MODE GND 2 VOUT 5 SW 3 10µH* VOUT 1.375V COUT** 10µF CER LTC3405A-1.375 1 6 * MURATA LQHMCN10002 ** MURATA 0603 GRM188R60G106ME47B *** MURATA 0603 GRM188R61A225KE34B 3405A1375 F05a Figure 5a. Small Footprint Application Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U 100 90 80 70 60 50 40 30 20 10 0 0.1 1 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 100 LOAD CURRENT (mA) 1000 3405A1375 F05b W UU Figure 5b. LTC3405A-1.375 Small Footprint Efficiency VOUT 100mV/DIV AC COUPLED IL 200mA/DIV ILOAD 200mA/DIV VIN = 3.6V 20µs/DIV ILOAD = 100mA TO 300mA Burst Mode OPERATION 3405A1375 F05c Figure 5c. 3405a1375f 11 LTC3405A-1.375 PACKAGE DESCRIPTIO 0.754 0.854 ± 0.127 0.20 BSC DATUM ‘A’ 3.254 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID 0.95 BSC 0.80 – 0.90 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.9 BSC RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 RELATED PARTS PART NUMBER LT1616 LT1676 LT1765 LT1776 LTC1878 LTC1879 LTC3404 LTC3405/LTC3405A LTC3405A-1.5 LTC3405A-1.8 LTC3406/LTC3406B LTC3411 LTC3412 LTC3413 LT3430 LTC3440 DESCRIPTION 500mA (IOUT), 1.4MHz, High Efficiency Step-Down DC/DC Converter 450mA (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter 25V, 2.75A (IOUT), 1.25MHz, High Efficiency Step-Down DC/DC Converter 500mA (IOUT), 200kHz, High Efficiency Step-Down DC/DC Converter 600mA (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 1.20A (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.4MHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 600mA (IOUT) 1.5MHz, Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 3A (IOUT), Sink/Source, 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 60V, 2.75A (IOUT), 200kHz, High Efficiency Step-Down DC/DC Converter 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter COMMENTS 90% Efficiency, VIN = 3.6V to 25V, VOUT = 1.25V, IQ = 1.9mA ISD =