LTC3408

LTC3408 1.5MHz, 600mA Synchronous Step-Down Regulator with Bypass Transistor FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Dynamically Adjustable Output from 0.3V to 3.5V 600mA Output Current Internal 0.08Ω P-Channel MOSFET Bypass Transistor High Efficiency: Up to 96% 1.5MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 2.5V to 5V Input Voltage Range Shutdown Mode Draws < 1µA Supply Current Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected Available in 8-Lead 3mm × 3mm DFN Package The LTC ®3408 is a high efficiency monolithic synchronous buck regulator optimized for WCDMA power amplifier applications. The output voltage can be dynamically programmed from 0.3V to 3.5V. At VOUT > 3.6V an internal 0.08Ω bypass P-channel MOSFET connects VOUT directly to VIN, eliminating power loss through the inductor. The input voltage range is 2.5V to 5V making the LTC3408 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Switching frequency is internally set at 1.5MHz, allowing the use of small surface mount inductors and capacitors. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. The LTC3408 is available in a low profile (0.75mm) 8-lead 3mm × 3mm DFN package. , LTC and LT are registered trademarks of Linear Technology Corporation. U.S. Patent Numbers: 5481178, 6580258, 6304066, 6127815, 6498466, 6611131 APPLICATIO S ■ ■ WCDMA Cell Phone Power Amplifiers Wireless Modems TYPICAL APPLICATIO WCDMA Transmitter Power Supply VIN 2.7V TO 5V 4.7µH* CIN† 10µF CER VIN SW VOUT 3 × VREF COUT** 600mA 4.7µF CER Efficiency Power Lost vs Load Current 1 100 90 80 POWER LOST (W) LTC3408 RUN REF VOUT 0.1 OUTPUT PROGRAMMING DAC GND WCDMA RF PA 0.01 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 1 10 100 LOAD CURRENT (mA) *MURATA LQH32CN4R7M11 **TAIYO YUDEN JMK212BJ475MG † TAIYO YUDEN JMK212BJ106MN 3403 TA01 0.01 U 70 60 50 40 30 20 10 0 1000 U U EFFICIENCY (%) 3408 F04 3408f 1 LTC3408 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW VOUT VIN GND SW 1 2 3 4 9 8 7 6 5 VOUT VIN REF RUN Input Supply Voltage (< 300µs) .................. – 0.3V to 6V Input Supply Voltage (DC) ....................... – 0.3V to 5.5V RUN, REF, VOUT Voltages .......................... – 0.3V to VIN SW Voltage (DC) ......................... – 0.3V to (VIN + 0.3V) P-Channel Switch Source Current (DC) ............. 800mA N-Channel Switch Sink Current (DC) ................. 800mA Peak SW Sink and Source Current ........................ 1.3A Bypass P-Channel FET Source Current (DC) .............. 1A Operating Temperature Range (Note 2) .. – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................ – 65°C to 125°C ORDER PART NUMBER LTC3408EDD DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN EXPOSED PAD IS GND (PIN 9) MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 43°C/ W, θJC = 3°C/ W DD PART MARKING LAEA Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 3.6V unless otherwise specified. SYMBOL VOUT ∆VOUT IPK VLOADREG VIN IS fOSC VREF RPFET RNFET RBYPASS ILSW ILBYP VRUN IRUN IREF PARAMETER Regulated Output Voltage Output Voltage Line Regulation Peak Inductor Current Output Voltage Load Regulation Input Voltage Range Input Current Shutdown Current Oscillator Frequency Bypass PFET Turn-Off Threshold Bypass PFET Turn-On Threshold RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET RDS(ON) of Bypass P-Channel FET SW Leakage Bypass PFET Leakage RUN Threshold RUN Input Current REF Input Current VRUN = 0V or 2.5V VRUN = 1.2V, SW = Open VRUN = 0V, SW = Open VREF ≥ 0.25V VREF ≤ 0.1V VREF = VREF = ISW = 160mA, Wafer Level ISW = 160mA, DD Package ISW = – 160mA, Wafer Level ISW = – 160mA, DD Package IOUT = 100mA, VIN = 3V, Wafer Level IOUT = 100mA, VIN = 3V, DD Package (Note 4) VRUN = 0V, VSW = 0V or 5V, VIN = 5V VOUT = 0V, VIN = 5V, VREF = 0V ● ● ● ● ● CONDITIONS VREF = 1.1V VREF = 0.1V VIN = 2.5V to 5V, VREF = 0.6V VIN = 3V, VREF = 0.9V ● ● ● MIN 3.23 0.25 0.70 2.5 TYP 3.3 0.3 0.1 1 0.7 MAX 3.37 0.35 0.4 1.25 5 UNITS V V %/V A % V mA µA MHz kHz V V Ω Ω Ω Ω Ω Ω µA µA V µA µA 1.5 0.1 1.2 550 1.167 1.5 700 1.2 1.21 0.3 0.4 0.3 0.4 0.05 0.08 ± 0.01 ±0.01 0.3 1 ± 0.01 ±0.01 2.5 1 1.8 850 1.26 0.4 0.4 0.08 ±1 ±1 1.5 ±1 ±1 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3408E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3408: TJ = TA + (PD)(43°C/W) 3408f 2 U W U U WW W LTC3408 ELECTRICAL CHARACTERISTICS Note 4: When VREF > 1.2V and VREF x3 > VIN, the P-channel FET will be on in parallel with the bypass PFET reducing the overall RDS(ON). Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs VOUT 110 100 100mA TA = 25°C VIN = 3.6V 100 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) 90 600mA 80 70 60 50 0 1 2 VOUT (V) 3 Efficiency vs Output Current 100 90 80 TA = 25°C VOUT = 2.5V 1.70 1.65 1.60 FREQUENCY (MHz) 70 EFFICIENCY (%) OSCILLATOR FREQUENCY (MHz) 60 50 40 30 20 10 0 0.1 VIN = 3.6V VIN = 4.2V 10 100 1 OUTPUT CURRENT (mA) UW 4 3408 G02 3408 G05 (From Figure 1) Efficiency vs Output Current 100 90 80 70 TA = 25°C VOUT = 1.5V Efficiency vs Output Current TA = 25°C 90 VOUT = 1.2V 80 70 60 50 40 30 20 10 0 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 3408 G03 VIN = 3.6V VIN = 4.2V 60 50 40 30 20 10 0 0.1 VIN = 3.6V VIN = 4.2V 1 10 100 OUTPUT CURRENT (mA) 1000 3408 G04 Oscillator Frequency vs Temperature 1.8 VIN = 3.6V 1.7 1.6 1.5 1.4 1.3 1.2 Oscillator Frequency vs Supply Voltage TA = 25°C 1.55 1.50 1.45 1.40 1.35 1.30 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1000 2 3 4 5 SUPPLY VOLTAGE (V) 6 3408 G07 3408 G06 3408f 3 LTC3408 TYPICAL PERFOR A CE CHARACTERISTICS Frequency vs VOUT 1600 1400 TA = 25°C VIN = 3.6V OUTPUT VOLTAGE (V) FREQUENCY (kHz) 1200 1000 800 600 400 1.814 1.804 1.794 1.784 1.774 0 100 200 300 400 500 600 700 800 900 1000 LOAD CURRENT (mA) 3408 G09 RDS(ON) (Ω) 0 0.2 0.4 0.6 0.8 VOUT (V) RDS(ON) vs Temperature 0.7 VIN = 2.7V DYNAMIC SUPPLY CURRENT (µA) 0.6 0.5 RDS(ON) (Ω) VIN = 3.6V MAIN SWITCH VIN = 4.2V 3000 2500 2000 1500 1000 FORCED CONTINUOUS MODE SWITCH LEAKAGE (nA) 0.4 0.3 0.2 0.1 0 –50 –25 BYPASS SWITCH VIN = 3V VIN = 4.2V 50 25 75 0 TEMPERATURE (°C) 100 125 SYNCHRONOUS SWITCH Switch Leakage vs Input Voltage 120 100 SWITCH LEAKAGE (pA) 80 60 40 20 0 SYNCHRONOUS SWITCH TA = 25°C RUN = 0V RUN 2V/DIV VOUT 1V/DIV 0 1 4 UW 1.0 3408 G08 (From Figure 1) Output Voltage vs Load Current 1.844 T = 25°C A VIN = 3.6V 1.834 1.824 RDS(ON) vs Input Voltage 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 4 3 5 2 INPUT VOTLAGE (V) 6 7 BYPASS SWITCH SYNCHRONOUS SWITCH MAIN SWITCH TA = 25°C 1.2 3408 G10 Dynamic Supply Current vs Supply Voltage TA = 25°C 4000 VOUT = 1.8V ILOAD = 0A 3500 4500 300 Switch Leakage vs Temperature VIN = 5.5V RUN = 0V 250 200 150 100 50 MAIN SWITCH SYNCHRONOUS SWITCH 500 0 2 3 4 SUPPLY VOLTAGE (V) 3408 G11 3408 G12 5 6 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3408 G13 Start-Up from Shutdown MAIN SWITCH IL 500mA/DIV VIN = 3.6V VREF = 0.6V RLOAD = 3Ω 40µs/DIV 3408 G15 2 3 4 INPUT VOLTAGE (V) 5 6 3408 G14 3408f LTC3408 TYPICAL PERFOR A CE CHARACTERISTICS (From Figure 1) Output Ripple Waveform VOUT 100mV/DIV IL 500mA/DIV IL 100mA/DIV ILOAD 500mA/DIV VOUT 10mV/DIV VIN = 3.6V VREF = 0.6V ILOAD = 0A REF Transient 4.5 VREF 0.5V/DIV VOUT (V) VOUT 1V/DIV VIN = 4.2V 40µs/DIV VREF = 0V TO 1.4V RLOAD = 5Ω PI FU CTIO S VOUT (Pins 1, 8): Output Voltage Feedback Pin. An internal resistive divider divides the output voltage down by 3 for comparison to the external reference voltage. The drain of the P-channel bypass MOSFET is connected to this pin. VIN (Pins 2, 7): Main Supply Pin. Must be closely decoupled to GND, Pin 3, with a 10µF or greater ceramic capacitor. GND (Pin 3): Ground Pin. SW (Pin 4): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. RUN (Pin 5): Run Control Input. Forcing this pin above 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing 1.2V. Exposed Pad (Pin 9): Connect to GND, Pin 3. UW Load Step Response 200ns/DIV 3408 G16 VIN = 3.6V 20µs/DIV VREF = 0.6V ILOAD = 0mA TO 600mA 3408 G17 VOUT vs VREF VIN = 4.2V IL = 100mA IL = 600mA 4.0 3.5 3.0 2.5 2.0 1.5 1.0 3408 G18 0.5 0 0 0.5 VREF (V) 3408 G19 1.0 1.5 U U U 3408f 5 LTC3408 FU CTIO AL DIAGRA OSC REF 6 VOUT 8 VOUT 1 180k 360k FREQ ÷2 – BCMP 5 IRCMP OPERATIO VIN 2.7V TO 5V CIN 10µF CER REF † (Refer to Functional Diagram) 4.7µH* VIN SW LTC3408 VOUT RUN REF GND 3403 F01 VOUT 3 × VREF COUT** 600mA 4.7µF CER output voltage can respond quickly to the external reference voltage by sourcing or sinking current as needed. Controlling the Output Voltage *MURATA LQH32CN4R7M11 **TAIYO YUDEN JMK212BJ475MG † TAIYO YUDEN JMK212BJ106MN Figure 1. Typical Application Main Control Loop The LTC3408 uses a constant frequency, current mode stepdown architecture. The main (P-channel MOSFET), synchronous (N-channel MOSFET) and bypass (P-channel MOSFET) switches are internal. During normal operation, the internal main switch is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, FB, relative to the external reference, which in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new load current. While the main switch is off, the synchronous switch is turned on until the beginning of the next clock cycle. The LTC3408 operates in forced continuous mode where the inductor current is constantly cycled. In this mode, the The output voltage can be dynamically programmed from 0.3V to 3.5V using the REF input. Because the gain to VOUT from REF is internally set to 3, the corresponding input range at REF is 0.1V to 1.167V. VOUT can be modulated during operation by driving REF with an external DAC. When REF exceeds 1.2V, a 0.08Ω internal bypass P-channel MOSFET connects VIN to VOUT, dramatically reducing the drop across the inductor and the main switch. Short-Circuit Protection A current sense comparator monitors the current across the bypass P-channel MOSFET with a trip current of about 2.5A. When this current is exceeded during a VOUT short to ground, the bypass P-channel MOSFET is immediately turned off. The propagation delay of the current sensing comparator, IBCMP, detecting an overcurrent condition to turning off the bypass P-channel MOSFET is approxmately 100ns. Once the bypass P-channel MOSFET is off for about 10µs to 20µs, it is allowed to turn back on. The initial current limit is then lowered to about 1.6A after the first current limit trip. If the short to ground persists, the current comparator will trip at the lower current limit, turning 3408f 6 + RUN 1.2V + – – IBCMP + – FB W SLOPE COMP OSC 2 VIN + U U U – + EA 0.85V – + BURST S R P-CHANNEL VIN Q Q SLEEP – ICOMP + 5Ω 7 VIN RS LATCH SWITCHING LOGIC AND BLANKING CIRCUIT ANTISHOOTTHRU 4 SW 9 3 GND 3408 BD LTC3408 OPERATIO off and on the bypass P-channel MOSFET with a frequency of approximately 50kHz to 100kHz at 1.6A peak current. This will continue until the short is removed. While the bypass P-channel MOSFET is pulsing intermittently, the inherent current limit of the step-down regulator limits its peak current to about 1A. Dropout Operation If the reference voltage would cause VOUT to exceed VIN, the LTC3408 enters dropout operation. During dropout, the main switch remains on continuously and operates at 100% duty cycle. If the voltage at REF is less than 1.2V, the bypass P-channel MOSFET will stay off even in dropout operation. The output voltage is then determined by the input voltage minus the voltage drop across the main switch and the inductor. If the voltage at REF is greater than 1.2V, 1200 MAXIMUM OUTPUT CURRENT (mA) 1000 800 600 400 200 0 VOUT = 1.8V VOUT = 2.5V VOUT = 1.5V 2.5 Figure 2. Maximum Output Current vs Input Voltage APPLICATIO S I FOR ATIO The basic LTC3408 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 4µH to 6µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple U W UU U 3.0 (Refer to Functional Diagram) but less than VIN/3, the bypass P-channel MOSFET will be on, but the main switch will be off. For best performance and lowest voltage drop from VIN to VOUT, always ensure that the REF voltage is greater than both 1.2V and VIN/3. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3408 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). Low Supply Operation The LTC3408 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 2 shows the reduction in the maximum output current as a function of input voltage for various output voltages. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3408 uses a patent-pending scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 3408 F02 currents. As Equation 1 shows, a greater difference between VIN and VOUT produces a larger ripple current. Where these voltages are subject to change, the highest VIN and lowest VOUT will determine the maximum ripple current. A reasonable starting point for setting ripple current is IL = 120mA (20% of the maximum load, 600mA). ∆IL = V 1 VOUT  1 – OUT  (f)(L) VIN   (1) 3408f 7 LTC3408 APPLICATIO S I FOR ATIO At output voltages below 0.6V, the switching frequency decreases linearly to a minimum of approximately 700kHz. This places the maximum ripple current (in forced continuous mode) at the highest input voltage and the lowest output voltage. In practice, the resulting ouput ripple voltage is 10mV to 15mV using the components specified in Figure 1. The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 660mA rated inductor should be enough for most applications (600mA + 60mA). For better efficiency, choose a low DC-resistance inductor. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price versus size requirements and any radiated field/EMI requirements than on what the LTC3408 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3408 applications. Table 1. Representative Surface Mount Inductors PART NUMBER Sumida CDRH2D11 Sumida CDRH2D18/LD Sumida CMD4D06 Murata LQH32C Taiyo Yuden LBLQ2016 Toko D312C VALUE (µH) 4.7 4.7 4.7 4.7 4.7 4.7 DCR (ΩMAX) 0.135 0.078 0.216 0.150 0.250 0.20 MAX DC CURRENT (A) 0.5 0.63 0.75 0.65 0.210 0.79 SIZE WxLxH (mm3) 3.2 x 3.2 x 1.2 3.2 x 3.2 x 2.0 3.5 x 4.1 x 0.8 2.5 x 3.2 x 2.0 1.6 x 2.0 x 1.6 3.6 x 3.6 x 1.2 CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the 8 U maximum RMS current must be used. The maximum RMS capacitor current is given by: [VOUT (VIN – VOUT )]1/ 2 VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. CIN required IRMS ≅ IOMAX W UU The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple VOUT is determined by:  1 ∆VOUT ≅ ∆IL  ESR + 8f C OUT    where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. The bulk capacitance values in Figure 1(a) (CIN = 10µF, COUT = 4.7µF) are tailored to mobile phone applications, in which the output voltage is expected to slew quickly according to the needs of the power amplifier. Holding the output capacitor to 4.7µF facilitates rapid charging and discharging. When the output voltage descends quickly in 3408f LTC3408 APPLICATIO S I FOR ATIO forced continuous mode, the LTC3408 will actually pull current from the output until the command from VREF is satisfied. On alternate half cyles, this current actually exits the VIN terminal, potentially causing a rise in VIN and forcing current into the battery. To prevent deterioration of the battery, use sufficient bulk capacitance with low ESR; at least 10µF is recommended. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3408’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Ceramic capacitors of Y5V material are not recommended because normal operating voltages cause their bulk capacitance to become much less than the nominal value. Programming the Output Voltage With a DAC The output voltage can be dynamically programmed to any voltage from 0.3V to 3.5V with an external DAC driving the REF pin. When the output is commanded low, the output voltage descends quickly in forced continuous mode pulling current from the output and transferring it to the input. If the input is not connected to a low impedance source capable of absorbing the energy, the input voltage could rise above the absolute maximum voltage of the part DAC 1000pF U and get damaged. The faster VOUT is commanded low, the higher is the voltage spike at the input. For best results, ramp the REF pin from high to low as slow as the application will allow. Avoid abrupt changes in voltage of >0.2V/µs. If ramp control is unavailable, an RC filter with a time constant of 10µs can be inserted between the REF pin and the DAC as shown in Figure 3. 10k LTC3408 REF GND 3408 F03 W UU Figure 3. Filtering the REF Pin Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3408 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at low load currents can be misleading since the actual power lost is of little consequence as illustrated in Figure 4. 1. The VIN quiescent current consists of two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is typically larger than the DC bias current. In continuous mode, 3408f 9 LTC3408 APPLICATIO S I FOR ATIO 1 100 90 80 POWER LOST (W) 0.1 70 60 50 40 0.01 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 1 10 100 LOAD CURRENT (mA) 30 20 10 0 1000 0.01 3408 F04 Figure 4. Power Lost vs Load Current IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN, thus, their effects will be more pronounced at higher supply voltages. (The gate charge of the bypass FET is, of course, negligible because it is infrequently cycled.) 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Hence, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In most applications the LTC3408 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3408 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum 10 U junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To prevent the LTC3408 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(θJA) where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3408 in dropout at an input voltage of 2.7V, a load current of 600mA (0.9V ≤ VREF < 1.2V) and an ambient temperature of 70°C. With VREF < 1.2V, the entire 600mA flows through the main P-channel FET. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is approximately 0.52Ω. Therefore, power dissipated by the part is: PD = (ILOAD2) • RDS(ON) = 187.2mW For the 8L DFN package, the θJA is 43°C/W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.1872)(43) = 78°C which is below the maximum junction temperature of 125°C. Modifying this example, suppose that VREF is raised to 1.2V or higher. This turns on the bypass P-channel FET as well as the main P-channel FET. Assume that the inductor’s DC resistance is 0.1Ω, the RDS(ON) of the main P-channel switch is 0.52Ω, and the RDS(ON) of the bypass P-channel switch is 0.08Ω. The current through the P-channel switch and the inductor will be 69mA, causing power dissipation of (0.069A)2 • 0.62Ω = 2.9mW. The bypass FET will 3408f W UU EFFICIENCY (%) LTC3408 APPLICATIO S I FOR ATIO dissipate (0.531A)2 • 0.08Ω = 22.6mW. Thus, TJ = 70°C + (0.0143 + 0.0425)(43) = 71.1°C. Reductions in power dissipation occur at higher supply voltages, where the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD • ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. VOUT COUT 1 VIN CIN VOUT VOUT VIN REF RUN 8 7 6 5 RREF DAC CREF VIA TO PIN 7 CIN VOUT VIN GND SW 1 2 LTC3408 3 4 6 5 8 7 VOUT VIN REF RUN CREF VIA TO PIN 2 2 VIN 3 4 GND SW LTC3408 3403 F05 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 5. Layout Diagram Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3408. These items are also illustrated graphically in Figures 5 and 6. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC drive to the internal power MOSFETs. 3. Keep the (–) plates of CIN and COUT as close as possible. Design Example As a design example, assume the LTC3408 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.6A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using Equation (1), L= V 1 VOUT  1 – OUT  VIN  (f)(∆IL )  W UU (2) TO DAC RREF VIA TO REF COUT VIA TO PIN 8 VIA TO PIN 1 L1 VIA TO VIN VIA TO GND 3408 F06 Figure 6. Suggested Layout 3408f 11 LTC3408 APPLICATIO S I FOR ATIO Substituting VOUT = 2.5V, VIN = 4.2V, IL = 120mA and f = 1.5MHz in Equation (2) gives: L= 2.5V  2.5V   1–  = 5.6µH 1.5MHz (120mA)  4.2V  A 4.7µH inductor works well for this application. For best efficiency choose a 660mA or greater inductor with less than 0.2Ω series resistance. CIN will require an RMS current rating of at least 0.3A ≅ LOAD(MAX)/2 at temperature and COUT will require an PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.675 ± 0.05 0.38 ± 0.10 8 3.5 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE PIN 1 TOP MARK (NOTE 6) RELATED PARTS PART NUMBER LTC3403 DESCRIPTION COMMENTS 1.5MHz, 600mA Synchronous Step-Down Regulator with Bypass Transistor LTC3405/LTC3405A-1.5/ 1.5MHz, 300mA (IOUT) Synchronous LTC3405A-1.8 Monolithic Step-Down Regulators LTC3406B/LTC3406B-1.5/ 1.5MHz, 600mA, (IOUT) Synchronous Monolithic LTC3406B-1.8 Step-Down Regulators with Burst Mode Defeat LTC3407/LTC3407-2 1.5MHz/2.25MHz, 600mA/800mA Dual (IOUT) Synchronous Monolithic Step-Down Regulator LTC5505 ThinSOT RF Power Detector with Buffered Output and >40dB Dynamic Range Up to 96% Efficiency, VIN: 2.5V to 5V, VOUT: 0.3V to 3.5V, IQ = 20µA, ISD < 1µA, DFN Package Up to 95% Efficiency, VIN: 2.5V to 5.5V, IQ = 20µA, Fixed Output Voltages Available, ThinSOTTM Package Up to 95% Efficiency, with Pulse Skipping Mode Enabled, Fixed Output Voltages Available, ThinSOT Package Up to 91% Efficiency, VIN: 2.5V to 5.5V, IQ = 4µA, MS10 Package 300MHz to 3GHz, Temperatrue Compensated, LTC5505-1: –28dBm to 18dBm, LTC5505-2: –32dBm to 12dBm, VCC = 2.7V to 6V Burst Mode is a registered trademark of Linear Technology Corporaton. ThinSOT is a trademark of Linear Technology Corporation. 3408f 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com U ESR of less than 0.25Ω. In most cases, a ceramic capacitor will satisfy this requirement. VIN 2.7V TO 5V 2, 7 CIN† 10µF CER 10k DAC 1000pF VIN SW 4 4.7µH* VOUT COUT** 4.7µF CER 3403 F07 U W UU LTC3408 5 6 RUN REF GND 3, 9 VOUT 1, 8 * MURATA LQH32CN4R7M11 ** TAIYO YUDEN JMK212BJ475MG † TAIYO YUDEN JMK212BJ106MN Figure 7 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD8) DFN 1203 0.200 REF 0.75 ± 0.05 4 0.25 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE LT/TP 0504 1K • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2003