LTC3417EFE

LTC3417 Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO High Efficiency: Up to 95% 1.4A/800mA Guaranteed Minimum Output Current No Schottky Diodes Required Programmable Frequency Operation: 1.5MHz or Adjustable From 0.6MHz to 4MHz Low RDS(ON) Internal Switches Short-Circuit Protected VIN: 2.25V to 5.5V Current Mode Operation for Excellent Line and Load Transient Response 125µA Quiescent Current in Sleep Mode Ultralow Shutdown Current: IQ < 1µA Low Dropout Operation: 100% Duty Cycle Power Good Output Phase Pin Selects 2nd Channel Phase Relationship with Respect to 1st Channel Internal Soft-Start with Individual Run Pin Control Available in Small Thermally Enhanced (5mm × 3mm) DFN and 20-Lead TSSOP Packages The LTC®3417 is a dual constant frequency, synchronous step-down DC/DC converter. Intended for medium power applications, it operates from a 2.25V to 5.5V input voltage range and has a constant programmable switching frequency, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. Each output voltage is adjustable from 0.8V to 5V. Internal synchronous low RDS(ON) power switches provide high efficiency without the need for external Schottky diodes. A user selectable mode input allows the user to trade off ripple voltage for light load efficiency. Burst Mode® operation provides high efficiency at light loads, while Pulse Skip mode provides low ripple noise at light loads. A phase mode pin allows the second channel to operate in-phase or 180° out-of-phase with respect to channel 1. Out-ofphase operation produces lower RMS current on VIN and thus lower RMS derating on the input capacitor. To further maximize battery life, the P-channel MOSFETs are turned on continuously in dropout (100% duty cycle) and both channels draw a total quiescent current of only 125µA. In shutdown, the device draws (VIN – 0.5V), Burst Mode operation is selected. When the voltage on the MODE pin is VOUT2: IRMS = 2 • I1 • I2 • D2(1 – D1) + I22 (D2 – D22 ) + I12 (D1 – D12 ) W U U VOUT2 > VOUT1: IRMS = 2 • I1 • I2 • D1(1 – D2) + I22 (D2 – D22 ) + I12 (D1 – D12 ) where: D1 = VOUT1 V and D2 = OUT2 VIN VIN DCR 0.014 0.018 0.06 0.031 0.035 0.033 0.027 0.07 0.047 0.035 0.047 DIMENSIONS L × W × H (mm) 6 × 6 × 2.5 6×6×2 6.6 × 4.5 × 2.9 5 × 5 × 2.4 3.2 × 3.2 × 2 4.3 × 4.8 × 3.5 5×5×3 6.6 × 4.5 × 2.9 4 × 4 × 1.8 3.2 × 3.2 × 2 4.3 × 4.8 × 3.5 3417fb MAX DC CURRENT (A) 2.8 2.9 2.6 3.9 1.8 5.5 3.9 2.3 1.75 1.6 3.9 LTC3417 APPLICATIO S I FOR ATIO When D1 = D2 then the equation simplifies to: IRMS = (I1 + I2 ) D(1– D) or IRMS = (I1 + I2 ) VOUT ( VIN – VOUT ) VIN where the maximum average output currents I1 and I2 equal the respective peak currents minus half the peak-topeak ripple currents: ∆IL1 2 ∆IL2 I2 = ILIM2 – 2 I1 = ILIM1 – These formula have a maximum at VIN = 2VOUT, where IRMS = (I1 + I2)/2. This simple worst case is commonly used to determine the highest IRMS. For “out of phase” operation, the ripple current can be lower than the “in phase” current. In the “out of phase” case, the maximum IRMS does not occur when VOUT1 = VOUT2. The maximum typically occurs when VOUT1 – VIN/2 = VOUT2 or when VOUT2 – VIN/2 = VOUT1. As a good rule of thumb, the amount of worst case ripple is about 75% of the worst case ripple in the “in phase” mode. Also note that when VOUT1 = VOUT2 = VIN/2 and I1 = I2, the ripple is zero. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1µF to 1µF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. U Output Capacitor (COUT1 and COUT2) Selection The selection of COUT1 and COUT2 is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is determined by: ⎛ ⎞ 1 ∆VOUT ≈ ∆IL ⎜ ESRCOUT + ⎟ ⎝ 8 • fO • COUT ⎠ W U U where fO = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage, since ∆IL increases with input voltage. With ∆IL = 0.35ILOAD(MAX), the output ripple will be less than 100mV at maximum VIN and fO = 1MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and are often used in extremely cost-sensitive applications provided that consideration is 3417fb 11 LTC3417 APPLICATIO S I FOR ATIO given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, high voltage and temperature coefficient and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. In most cases, 0.1µF to 1µF of ceramic capacitors should also be placed close to the LTC3417 in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective. Also, ceramic capacitors are prone to temperature effects which require the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must fulfill a charge storage requirement. During a load step, the output capacitor must 12 U instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear droop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: W U U COUT ≈ 2.5 ∆IOUT fO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10µF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3417 develops a 0.8V reference voltage between the feedback pins, VFB1 and VFB2, and the signal ground as shown in Figure 4. The output voltages are set by two resistive dividers according to the following formulas: ⎛ R1⎞ VOUT1 ≈ 0.8 V⎜ 1 + ⎟ ⎝ R2 ⎠ ⎛ R3 ⎞ VOUT2 ≈ 0.8 V⎜ 1 + ⎟ ⎝ R4 ⎠ Keeping the current small (1µF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this prob- 14 U lem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot SwapTM controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and softstarting. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (P1+ P2 + P3 +…) where P1, P2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3417 circuits: 1) LTC3417 IS current, 2) switching losses, 3) I2R losses, 4) other losses. 1) The IS current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. IS current results in a small (< 0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge moves from VIN to ground. The resulting charge over the switching period is a current out of VIN that is typically much larger than the DC bias current. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. Hot Swap is a trademark of Linear Technology Corporation. 3417fb W U U LTC3417 APPLICATIO S I FOR ATIO 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and the external inductor, RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) where RL is the resistance of the inductor. 4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESRCOUT at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations The LTC3417 requires the package Exposed Pad (PGND2/ GNDD pin) to be well soldered to the PC board. This gives the DFN and TSSOP packages exceptional thermal properties, compared to similar packages of this size, making it difficult in normal operation to exceed the maximum junction temperature of the part. In a majority of applications, the LTC3417 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3417 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both switches in both regulators will be turned off and the SW nodes will become high impedance. U To prevent the LTC3417 from exceeding its maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3417 is in dropout in both regulators at an input voltage of 3.3V with load currents of 1.4A and 800mA. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the 1.4A P-channel switch is 0.09Ω and the RDS(ON) of the 800mA P-channel switch is 0.163Ω. The power dissipated by the part is: PD = I12 • RDS(ON)1 + I22 • RDS(ON)2 PD = 1.42 • 0.09 + 0.82 • 0.163 PD = 281mW The DFN package junction-to-ambient thermal resistance, θJA, is about 43°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: TJ = 0.281 • 43 + 70 TJ = 82.1°C Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125°C. 3417fb W U U 15 LTC3417 APPLICATIO S I FOR ATIO Design Example As a design example, consider using the LTC3417 in a portable application with a Li-Ion battery. The battery provides a VIN from 2.5V to 4.2V. One output requires 1.8V at 1.3A in active mode, and 1mA in standby mode. The other output requires 2.5V at 700mA in active mode, and 500µA in standby mode. Since both loads still need power in standby, Burst Mode operation is selected for good low load efficiency (MODE = VIN). First, determine what frequency should be used. Higher frequency results in a lower inductor value for a given ∆IL (∆IL is estimated as 0.35ILOAD(MAX)). Reasonable values for wire wound surface mount inductors are usually in the range of 1µH to 10µH. CONVERTER OUTPUT SW1 SW2 ILOAD(MAX) 1.4A 800mA ∆ IL 490mA 280mA Using the 1.5MHz frequency setting (FREQ = VIN), we get the following equations for L1 and L2: L1 = 1 . 8V ⎛ 1 . 8V ⎞ 1– = 1 . 4 µH ⎠ ⎝ 1 . 5MHz • 490mA ⎜ 4 . 2V ⎟ Use 1 . 5 µH. L2 = 2 . 5V ⎛ 2 . 5V ⎞ 1– = 2 . 4 µH ⎠ ⎝ 1 . 5MHz • 280mA ⎜ 4 . 2V ⎟ Use 2 . 2 µH. 16 U COUT selection is based on load step droop instead of ESR requirements. For a 5% output droop: W U U COUT1 = 2 . 5 • COUT 2 = 2 . 5 • 1 . 3A = 24µ F 1 . 5MHz ( 5 % • 1 . 8V ) 0 . 7A = 9 . 3µ F 1 . 5MHz ( 5 % • 2 . 5V ) The closest standard values are 22µF and 10µF. The output voltages can now be programmed by choosing the values of R1, R2, R3, and R4. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2µA with the 0.8V feedback voltages makes R2 and R4 equal to 400k. A close standard 1% resistor is 412k. This then makes R1 = 515k. A close standard 1% is 511k. Similarily, with R4 at 412k, R3 is equal to 875k. A close 1% resistor is 866k. The compensation should be optimized for these components by examining the load step response, but a good place to start for the LTC3417 is with a 5.9kΩ and 2200pF filter on ITH1 and 2.87k and 6800pF on ITH2. The output capacitor may need to be increased depending on the actual undershoot during a load step. The PGOOD pin is a common drain output and requires a pull-up resistor. A 100k resistor is used for adequate speed. Figure 4 shows a complete schematic for this design. 3417fb LTC3417 APPLICATIO S I FOR ATIO VIN 2.25V TO 5.5V CIN 10µF VOUT1 1.8V 1.4A L1 1.5µH C1 22pF VIN R1 511k COUT1 22µF R2 412k R5 5.9k C3 2200pF L1: MIDCOM DUS-5121-1R5R COUT1: KEMET C1210C226K8PAC OUT1 Efficiency vs Load Current 100 VIN = 3.6V VOUT = 1.8V 95 FREQ = 1MHz REFER TO FIGURE 4 90 85 80 75 70 0.001 0.001 10 3417 F04a EFFICIENCY (%) Figure 4. 1.8V at 1.4A/2.5V at 800mA Step-Down Regulators U CIN1 0.1µF CIN2 0.1µF R7 100k VIN1 VIN2 MODE SW1 RUN1 LTC3417 VFB1 PHASE ITH1 VFB2 FREQ VIN R6 2.87k C4 6800pF 3417 F04 W U U PGOOD SW2 RUN2 VIN L2 2.2µH C2 22pF VOUT2 2.5V 800mA R3 866k R4 412k COUT2 10µF ITH2 EXPOSED GNDA PAD GNDD L2: MIDCOM DUS-5121-2R2R COUT2, CIN: KEMET C1206C106K4PAC 10 1 POWER LOSS (W) EFFICIENCY 0.1 POWER LOSS 0.01 0.01 0.1 1 LOAD CURRENT (A) 3417fb 17 LTC3417 APPLICATIO S I FOR ATIO Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3417. These items are also illustrated graphically in the layout diagram of Figure 5. Check the following in your layout. 1. Does the capacitor CIN connect to the power VIN1 (Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as close as possible (DFN package)? It may be necessary to split CIN into two capacitors. This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT1, L1 and COUT2, L2 closely connected? The (–) plate of COUT1 returns current to PGND1, and the (–) plate of COUT2 returns current to the PGND2/GNDD and the (–) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT1 and a ground line terminated near GNDA. The resistor divider, R3 and R4, VIN CIN 10µF CIN2 0.1µF VIN2 PGND2/ EXPOSED PAD GNDA L2 VOUT2 CC2 R3 VFB2 R4 STAR TO GNDA CITH2 VIN RITH2 R8 PGOOD RUN2 PHASE GNDD SW2 COUT2 18 U must be connected between the (+) plate of COUT2 and a ground line terminated near GNDA. The feedback signals VFB1 and VFB2 should be routed away from noise components and traces, such as the SW lines, and its trace should be minimized. 4. Keep sensitive components away from the SW pins. The input capacitor CIN, the compensation capacitors CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3, R4, RITH1 and RITH2 should be routed away from the SW traces and the inductors L1 and L2. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GNDA pin at one point which is then connected to the PGND2/GNDD pin. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to one of the input supplies. VIN1 PGND1 COUT1 L1 SW1 CC1 R1 VFB1 R2 RITH1 R7 FREQ RUN1 MODE VIN CITH1 STAR TO GNDA VOUT1 CIN1 0.1µF LTC3417 ITH2 ITH1 W U U Figure 5 3417fb LTC3417 PACKAGE DESCRIPTIO 3.50 ± 0.05 1.65 ± 0.05 2.20 ± 0.05 (2 SIDES) 0.25 ± 0.05 0.50 BSC 4.40 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 6.60 ± 0.10 4.50 ± 0.10 SEE NOTE 4 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) R = 0.115 TYP R = 0.20 TYP 3.00 ± 0.10 (2 SIDES) 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH (DHC16) DFN 1103 5.00 ± 0.10 (2 SIDES) 0.65 ± 0.05 0.40 ± 0.10 16 9 PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 8 0.75 ± 0.05 4.40 ± 0.10 (2 SIDES) 1 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE BOTTOM VIEW—EXPOSED PAD FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation CA 4.95 (.195) 6.40 – 6.60* (.252 – .260) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 2.74 (.108) 0.45 ± 0.05 1.05 ± 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 6.40 2.74 (.252) (.108) BSC 0.25 REF 1.20 (.047) MAX 0° – 8° 0.50 – 0.75 (.020 – .030) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3417fb 19 LTC3417 RELATED PARTS PART NUMBER LTC3404 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3407-2 LTC3409 LTC3411 LTC3412 LTC3413 LTC3414 LTC3416 LTC3418 LTC3440 LTC3441 LTC3443 LTC3448 LTC3548 DESCRIPTION 600mA (IOUT), 1.4MHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters COMMENTS 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10µA, ISD < 1µA, MS8 Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20µA, ISD < 1µA, ThinSOTTM Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, ISD < 1µA, ThinSOT Package Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, Converter ISD < 1µA, MSE/DFN Packages Dual 800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 600mA, Low VIN (1.6V to 5.5V), Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA, MSE/DFN Packages 95% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65µA, ISD < 1µA, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, MS Package 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD < 1µA, TSSOP16E Package 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter with Tracking 8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 1.2A (IOUT), 600kHz, Synchronous Buck-Boost DC/DC Converter 1.5MHz/2.25MHz, 600mA Synchronous Step-Down DC/DC Converter with LDO Mode Dual 800mA and 400mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF/2, IQ = 280µA, ISD < 1µA, TSSOP16E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64µA, ISD < 1µA, TSSOP20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64µA, ISD < 1µA, TSSOP20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 380µA, ISD < 1µA, QFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.4V, IQ = 25µA, ISD < 1µA, MS/DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.4V, IQ = 25µA, ISD < 1µA, DFN Package 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN) = 2.4V, IQ = 28µA, ISD < 1µA, MS Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 32µA, ISD < 1µA, DFN/MS8E 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD < 1µA, MSE/DFN Packages ThinSOT is a trademark of Linear Technology Corporation. 3417fb 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0506 REV B • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005