LTC3441EDE

LTC3441 High Current Micropower Synchronous Buck-Boost DC/DC Converter FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Regulated Output with Input Above, Below or Equal to the Output Single Inductor, No Schottky Diodes High Efficiency: Up to 95% 25μA Quiescent Current in Burst Mode® Operation Up to 1.2A Continuous Output Current from a Single Lithium-Ion True Output Disconnect in Shutdown 2.4V to 5.5V Input Range 2.4V to 5.25V Output Range 1MHz Fixed Frequency Operation Synchronizable Oscillator Selectable Burst Mode or Fixed Frequency Operation 1.4V to enable the IC and >2.4V to ensure the error amp is not clamped from soft-start. An RC from the shutdown command signal to this pin will provide a soft-start function by limiting the rise time of the VC pin. GND (Pin 2): Signal Ground for the IC. PGND (Pins 3, 6, 13 Exposed Pad): Power Ground for the Internal NMOS Power Switches SW1 (Pin 4): Switch pin where the internal switches A and B are connected. Connect inductor from SW1 to SW2. An optional Schottky diode can be connected from this SW1 to ground. Minimize trace length to keep EMI down. SW2 (Pin 5): Switch pin where the internal switches C and D are connected. An optional Schottky diode can be connected from SW2 to VOUT (it is required where VOUT > 4.3V). Minimize trace length to keep EMI down. MODE/SYNC (Pin 7): Burst Mode Select and Oscillator Synchronization. MODE/SYNC = High: Enable Burst Mode Operation. During the period where the IC is supplying energy to the output, the inductor peak inductor current will reach 0.8A and return to zero current on each cycle. In Burst Mode operation the operation is variable frequency, which provides a significant efficiency improvement at light loads. The Burst Mode operation will continue until the pin is driven low. MODE/SYNC = Low: Disable Burst Mode operation and maintain low noise, constant frequency operation . MODE/SYNC = External CLK : Synchronization of the internal oscillator and Burst Mode operation disable. A clock pulse width between 100ns and 2μs and a clock frequency between 2.3MHz and 3.4MHz (twice the desired frequency) is required to synchronize the IC. fOSC = fSYNC/2 VOUT (Pin 8): Output of the Synchronous Rectifier. A filter capacitor is placed from VOUT to GND. A ceramic bypass capacitor is recommended as close to the VOUT and GND pins as possible. PVIN (Pin 9): Power VIN Supply Pin. A 10μF ceramic capacitor is recommended as close to the PVIN and PGND pins as possible VIN (Pin 10): Input Supply Pin. Internal VCC for the IC. VC (Pin 11): Error Amp Output. A frequency compensation network is connected from this pin to the FB pin to compensate the loop. See the section “Compensating the Feedback Loop” for guidelines. FB (Pin 12): Feedback Pin. Connect resistor divider tap here. The output voltage can be adjusted from 2.4V to 5.25V. The feedback reference voltage is typically 1.22V. 3441fa UW PMOS RDS(ON) 2.30 VIN = VOUT = 3.6V SWITCHES A AND D 2.25 Minimum Start Voltage 2.20 2.15 0.05 –50 –25 35 65 5 TEMPERATURE (°C) 95 125 3441 G15 2.10 –55 –25 5 35 65 TEMPERATURE (°C) 95 125 3441 G16 U U U 5 LTC3441 BLOCK DIAGRA VIN 2.4V TO 5.5V 9 PVIN VIN SW B + 10 ISENSE AMP + gm = 1 k 100 3.2A PGND – AVERAGE CURRENT LIMIT THERMAL SHUTDOWN SUPPLY CURRENT LIMIT + 4A VCC INTERNAL – UVLO + 2.4V – 1MHz OSC SYNC SLEEP ÷2 5μs DELAY 7 MODE/SYNC 2 GND 6 PGND Burst Mode OPERATION CONTROL SHUTDOWN 1 = Burst Mode OPERATION 0 = FIXED FREQUENCY 6 – PWM LOGIC AND OUTPUT PHASING PWM COMPARATORS CLAMP + – – + + W SW1 SW A GATE DRIVERS AND ANTICROSS CONDUCTION 4 5 SW2 SW D VOUT VOUT 2.4V TO 5.25V 8 –0.8A SW C REVERSE CURRENT LIMIT ERROR AMP + – 1.22V R1 FB 12 VC 11 R2 SHDN/SS RSS 1 VIN CSS 3440 BD 3441fa LTC3441 OPERATIO The LTC3441 provides high efficiency, low noise power for applications such as portable instrumentation. The LTC proprietary topology allows input voltages above, below or equal to the output voltage by properly phasing the output switches. The error amp output voltage on the VC pin determines the output duty cycle of the switches. Since the VC pin is a filtered signal, it provides rejection of frequencies from well below the switching frequency. The low RDS(ON), low gate charge synchronous switches provide high frequency pulse width modulation control at high efficiency. Schottky diodes across the synchronous switch D and synchronous switch B are not required, but provide a lower drop during the break-before-make time (typically 15ns). The addition of the Schottky diodes will improve peak efficiency by typically 1% to 2%. High efficiency is achieved at light loads when Burst Mode operation is entered and when the IC’s quiescent current is a low 25μA. LOW NOISE FIXED FREQUENCY OPERATION Oscillator The frequency of operation is factory trimmed to 1MHz. The oscillator can be synchronized with an external clock applied to the MODE/SYNC pin. A clock frequency of twice the desired switching frequency and with a pulse width of at least 100ns is applied. The oscillator sync range is 1.15MHz to 1.7MHz (2.3MHz to 3.4MHz sync frequency). Error Amp The error amplifier is a voltage mode amplifier. The loop compensation components are configured around the amplifier to obtain stability of the converter. The SHDN/SS pin will clamp the error amp output, VC, to provide a softstart function. Supply Current Limit The current limit amplifier will shut PMOS switch A off once the current exceeds 4A typical. Before the switch current limit, the average current limit amp (3.2A typical) will source current into the FB pin to drop the output voltage. The current amplifier delay to output is typically 50ns. U Reverse Current Limit The reverse current limit amplifier monitors the inductor current from the output through switch D. Once a negative inductor current exceeds – 800mA typical, the IC will shut off switch D. Output Switch Control Figure 1 shows a simplified diagram of how the four internal switches are connected to the inductor, VIN, VOUT and GND. Figure 2 shows the regions of operation for the LTC3441 as a function of the internal control voltage, VCI. The VCI voltage is a level shifted voltage from the output of the error amp (VC pin) (see Figure 5). The output switches are properly phased so the transfer between operation modes is continuous, filtered and transparent to the user. When VIN approaches VOUT the Buck/Boost region is reached where the conduction time of the four switch region is typically 150ns. Referring to Figures 1 and 2, the various regions of operation will now be described. PVIN 9 PMOS A SW1 4 NMOS B SW2 5 NMOS C VOUT 8 VOUT PMOS D 3441 F01 Figure 1. Simplified Diagram of Output Switches 75% DMAX BOOST A ON, B OFF BOOST REGION PWM CD SWITCHES DMIN BOOST DMAX BUCK FOUR SWITCH PWM BUCK/BOOST REGION V2 (≈ 1.55V) D ON, C OFF PWM AB SWITCHES BUCK REGION 0% DUTY CYCLE V1 (≈ 0.9V) INTERNAL CONTROL VOLTAGE, VCI V3 (≈ 1.65V) V4 (≈ 2.05V) 3441 F02 Figure 2. Switch Control vs Internal Control Voltage, VCI 3441fa 7 LTC3441 OPERATIO Buck Region (VIN > VOUT) Switch D is always on and switch C is always off during this mode. When the internal control voltage, VCI, is above voltage V1, output A begins to switch. During the off time of switch A, synchronous switch B turns on for the remainder of the time. Switches A and B will alternate similar to a typical synchronous buck regulator. As the control voltage increases, the duty cycle of switch A increases until the maximum duty cycle of the converter in Buck mode reaches DMAX_BUCK, given by: DMAX_BUCK = 100 – D4SW % where D4SW = duty cycle % of the four switch range. D4SW = (150ns • f) • 100 % where f = operating frequency, Hz. Beyond this point the “four switch,” or Buck/Boost region is reached. Buck/Boost or Four Switch (VIN ~ VOUT) When the internal control voltage, VCI, is above voltage V2, switch pair AD remain on for duty cycle DMAX_BUCK, and the switch pair AC begins to phase in. As switch pair AC phases in, switch pair BD phases out accordingly. When the VCI voltage reaches the edge of the Buck/Boost range, at voltage V3, the AC switch pair completely phase out the BD pair, and the boost phase begins at duty cycle D4SW. The input voltage, VIN, where the four switch region begins is given by: VIN = VOUT V 1 – (150ns • f) The point at which the four switch region ends is given by: VIN = VOUT(1 – D) = VOUT(1 – 150ns • f) V Boost Region (VIN < VOUT) Switch A is always on and switch B is always off during this mode. When the internal control voltage, VCI, is above 8 U voltage V3, switch pair CD will alternately switch to provide a boosted output voltage. This operation is typical to a synchronous boost regulator. The maximum duty cycle of the converter is limited to 88% typical and is reached when VCI is above V4. Burst Mode OPERATION Burst Mode operation is when the IC delivers energy to the output until it is regulated and then goes into a sleep mode where the outputs are off and the IC is consuming only 25μA. In this mode the output ripple has a variable frequency component that depends upon load current. During the period where the device is delivering energy to the output, the peak current will be equal to 800mA typical and the inductor current will terminate at zero current for each cycle. In this mode the typical maximum average output current is given by: IOUT(MAX)BURST ≈ 0.2 • VIN A VOUT + VIN Burst Mode operation is user controlled, by driving the MODE/SYNC pin high to enable and low to disable. The peak efficiency during Burst Mode operation is less than the peak efficiency during fixed frequency because the part enters full-time 4-switch mode (when servicing the output) with discontinuous inductor current as illustrated in Figures 3 and 4. During Burst Mode operation, the control loop is nonlinear and cannot utilize the control voltage from the error amp to determine the control mode, therefore full-time 4-switch mode is required to maintain the Buck/Boost function. The efficiency below 1mA becomes dominated primarily by the quiescent current and not the peak efficiency. The equation is given by: Efficiency Burst ≈ ( ηbm) • ILOAD 25μA + ILOAD where (ηbm) is typically 75% during Burst Mode operation. 3441fa LTC3441 OPERATIO Burst Mode Operation to Fixed Frequency Transient Response When transitioning from Burst Mode operation to fixed frequency, the system exhibits a transient since the modes of operation have changed. For most systems this transient is acceptable, but the application may have stringent input current and/or output voltage requirements that dictate a broad-band voltage loop to minimize the transient. Lowering the DC gain of the loop will facilitate the task (5M from FB to VC) at the expense of DC load regulation. Type 3 compensation is also recommended to broad band the loop and roll off past the two pole response of the LC of the converter (see Closing the Feedback Loop). PVIN 9 A 4 SW1 B dI ≈ VIN L dt L D VOUT 8 A + – IINDUCTOR SW2 C SW1 B 0mA T1 3441 F03 L SW2 C IINDUCTOR 6 GND Figure 3. Inductor Charge Cycle During Burst Mode Operation TO PWM COMPARATORS U SOFT-START The soft-start function is combined with shutdown. When the SHDN/SS pin is brought above typically 1V, the IC is enabled but the EA duty cycle is clamped from the VC pin. A detailed diagram of this function is shown in Figure 5. The components RSS and CSS provide a slow ramping voltage on the SHDN/SS pin to provide a soft-start function. PVIN 9 dI ≈ – VOUT L dt D 5 800mA VOUT 8 5 800mA 4 – + 0mA T2 3441 F04 6 GND Figure 4. Inductor Discharge Cycle During Burst Mode Operation VIN 14μA ERROR AMP VOUT FB R1 + – SOFT-START CLAMP VCI 1.22V 12 VC 11 CP1 R2 SHDN/SS 1 CSS RSS ENABLE SIGNAL 3441 F05 + CHIP ENABLE – 1V Figure 5. Soft-Start Circuitry 3441fa 9 LTC3441 APPLICATIO S I FOR ATIO COMPONENT SELECTION 1 SHDN/SS 2 GND 3 PGND 4 SW1 5 SW2 6 PGND FB 12 VC 11 VIN 10 PVIN 9 VOUT 8 MODE 7 VOUT VIN GND MULTIPLE VIAS Figure 6. Recommended Component Placement. Traces Carrying High Current are Direct. Trace Area at FB and VC Pins are Kept Low. Lead Length to Battery Should be Kept Short. VOUT and VIN Ceramic Capacitors Close to the IC Pins Inductor Selection The high frequency operation of the LTC3441 allows the use of small surface mount inductors. The inductor current ripple is typically set to 20% to 40% of the maximum inductor current. For a given ripple the inductance terms are given as follows: L> L> VIN(MIN) • VOUT – VIN(MIN) • 100 f • IOUT(MAX) • %Ripple • VOUT VOUT • VIN(MAX) – VOUT • 100 f • IOUT(MAX) • %Ripple • VIN(MAX) ( ) H, ( ) H where f = operating frequency, Hz %Ripple = allowable inductor current ripple, % VIN(MIN) = minimum input voltage, V VIN(MAX) = maximum input voltage, V VOUT = output voltage, V IOUT(MAX) = maximum output load current For high efficiency, choose an inductor with a high frequency core material, such as ferrite, to reduce core loses. The inductor should have low ESR (equivalent series resistance) to reduce the I2R losses, and must be able to 10 U handle the peak inductor current without saturating. Molded chokes or chip inductors usually do not have enough core to support the peak inductor currents in the 1A to 2A region. To minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. See Table 1 for suggested components and Table 2 for a list of component suppliers. Table 1. Inductor Vendor Information SUPPLIER Coilcraft Coiltronics Murata 3441 F06 W UU PHONE (847) 639-6400 (561) 241-7876 USA: (814) 237-1431 (800) 831-9172 FAX (847) 639-1469 (561) 241-9339 USA: (814) 238-0490 WEB SITE www.coilcraft.com www.coiltronics.com www.murata.com Sumida USA: www.japanlink.com/ (847) 956-0666 (847) 956-0702 sumida Japan: 81(3) 3607-5111 81(3) 3607-5144 Output Capacitor Selection The bulk value of the capacitor is set to reduce the ripple due to charge into the capacitor each cycle. The steady state ripple due to charge is given by: %Ripple _ Boost = %Ripple _ Buck = IOUT(MAX) • VOUT – VIN(MIN) • 100 COUT • VOUT • f 2 ( ) % % IOUT(MAX) • VIN(MAX) – VOUT • 100 COUT • VIN(MAX) • VOUT • f ( ) where COUT = output filter capacitor, F The output capacitance is usually many times larger in order to handle the transient response of the converter. For a rule of thumb, the ratio of the operating frequency to the unity-gain bandwidth of the converter is the amount the output capacitance will have to increase from the above calculations in order to maintain the desired transient response. The other component of ripple is due to the ESR (equivalent series resistance) of the output capacitor. Low ESR capacitors should be used to minimize output voltage ripple. For surface mount applications, Taiyo Yuden ceramic capacitors, AVX TPS series tantalum capacitors or Sanyo POSCAP are recommended. 3441fa LTC3441 APPLICATIO S I FOR ATIO Input Capacitor Selection Since the VIN pin is the supply voltage for the IC it is recommended to place at least a 4.7μF, low ESR bypass capacitor. Table 2. Capacitor Vendor Information SUPPLIER AVX Sanyo PHONE (803) 448-9411 (619) 661-6322 FAX (803) 448-1943 (619) 661-1055 (408) 573-4159 WEB SITE www.avxcorp.com www.sanyovideo.com www.t-yuden.com Taiyo Yuden (408) 573-4150 Optional Schottky Diodes The Schottky diodes across the synchronous switches B and D are not required (VOUT < 4.3V), but provide a lower drop during the break-before-make time (typically 15ns) of the NMOS to PMOS transition, improving efficiency. Use a Schottky diode such as an MBRM120T3 or equivalent. Do not use ordinary rectifier diodes, since the slow recovery times will compromise efficiency. For applications with an output voltage above 4.3V, a Schottky diode is required from SW2 to VOUT. Output Voltage < 2.4V The LTC3441 can operate as a buck converter with output voltages as low as 0.4V. The part is specified at 2.4V minimum to allow operation without the requirement of a Schottky diode. Synchronous switch D is powered from VOUT and the RDS(ON) will increase at low output voltages, therefore a Schottky diode is required from SW2 to VOUT to provide the conduction path to the output. Output Voltage > 4.3V A Schottky diode from SW to VOUT is required for output voltages over 4.3V. The diode must be located as close to the pins as possible in order to reduce the peak voltage on SW2 due to the parasitic lead and trace inductance. Input Voltage > 4.5V For applications with input voltages above 4.5V which could exhibit an overload or short-circuit condition, a 2Ω/1nF series snubber is required between the SW1 pin and GND. A Schottky diode from SW1 to VIN should also be added as close to the pins as possible. For the higher U input voltages, VIN bypassing becomes more critical; therefore, a ceramic bypass capacitor as close to the VIN and GND pins as possible is also required. Operating Frequency Selection Additional quiescent current due to the output switches GATE charge is given by: Buck: 800e–12 • VIN • f Boost: 400e–12 • (VIN + VOUT) • f Buck/Boost: f • (1200e–12 • VIN + 400e–12 • VOUT) where f = switching frequency Closing the Feedback Loop The LTC3441 incorporates voltage mode PWM control. The control to output gain varies with operation region (Buck, Boost, Buck/Boost), but is usually no greater than 15. The output filter exhibits a double pole response is given by: fFILTER _ POLE = 1 Hz 2 • π • L • COUT W UU where COUT is the output filter capacitor. The output filter zero is given by: fFILTER _ ZERO = 1 2 • π • RESR • COUT Hz where RESR is the capacitor equivalent series resistance. A troublesome feature in Boost mode is the right-half plane zero (RHP), and is given by: fRHPZ VIN = Hz 2 • π • IOUT • L • VOUT 2 The loop gain is typically rolled off before the RHP zero frequency. A simple Type I compensation network can be incorporated to stabilize the loop but at a cost of reduced bandwidth and slower transient response. To ensure proper phase margin, the loop requires to be crossed over a decade before the LC double pole. 3441fa 11 LTC3441 APPLICATIO S I FOR ATIO 1 fUG = Hz 2 • π • R1 • CP1 Most applications demand an improved transient response to allow a smaller output filter capacitor. To achieve a higher bandwidth, Type III compensation is required. Two zeros are required to compensate for the double-pole response. 1 Hz 2 • π • 32 e3 • R1 • CP1 Which is extremely close to DC 1 fZERO1 = Hz 2 • π • RZ • CP1 1 fZERO2 = Hz 2 • π •R1 • CZ 1 fPOLE1 ≈ 1 fPOLE2 = Hz 2 • π • RZ • CP 2 The unity-gain frequency of the error amplifier with the Type I compensation is given by: L1 4.7μH 4 9 2.5V TO 4.2V 10 5 8 R1 348k R3 15k C4 220pF 5M R2 200k 220pF 2.2k SW1 PVIN SW2 Li-Ion * C1 10μF VOUT 12 LTC3441 VIN FB 1 11 SHDN/SS VC 7 2 MODE/SYNC GND 3 6 PGND PGND *1 = Burst Mode OPERATION 0 = FIXED FREQUENCY C1: TAIYO YUDEN JMK212BJ106MG C2: TAIYO YUDEN JMK325BJ476MM L1: TOKO A916CY-4R7M Figure 9. Fast Transient Response Compensation for Step Load or Mode Change 12 U VOUT W UU + ERROR AMP 1.22V FB 12 VC 11 CP1 R2 3441 F07 R1 – Figure 7. Error Amplifier with Type I Compensation VOUT + ERROR AMP 1.22V FB 12 VC 11 CP2 3441 F08 R1 CZ1 – RZ CP1 R2 Figure 8. Error Amplifier with Type III Compensation VOUT 3.3V 1A Load Transient Response, 100mA to 1A C2 47μF VOUT 100mV/DIV 1A 100mA 3441 F09 100μs/DIV 3441 G01 3441fa LTC3441 TYPICAL APPLICATIO S Li-Ion to 3.3V at 1.2A Converter L1 4.7μH 4 9 2.8V TO 4.2V 10 5 8 R1 340k R3 15k C4 1.5nF D1 VOUT 3.3V 1.2A C2 22μF R2 200k Li-Ion *1 = Burst Mode OPERATION 0 = FIXED FREQUENCY EFFICIENCY (%) U SW1 PVIN SW2 D2 C1 10μF * VOUT 12 LTC3441 VIN FB 1 11 VC SHDN/SS 7 2 MODE/SYNC GND 3 6 PGND PGND C1: TAIYO YUDEN JMK212BJ106MG C2: TAIYO YUDEN JMK325BJ226MM D1, D2: ON SEMICONDUCTOR MBRM120LT3 L1: TOKO A916CY-3R3M 3441 TA03a Efficiency 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 IOUT (mA) 1000 10000 2.8VIN PWM 4.2VIN PWM 3.6VIN PWM 4.2VIN BURST 3441 TA03b 3441fa 13 LTC3441 TYPICAL APPLICATIO S Li-Ion to 5V at 600mA Boost Converter with Output Disconnect L1 4.7μH 4 9 2.5V TO 4.2V 1M Li-Ion 0.047μF C1 10μF * 10 5 8 D1 VOUT 5V 600mA R1 619k R3 15k C4 1.5nF COUT 22μF R2 200k *1 = Burst Mode OPERATION 0 = FIXED FREQUENCY EFFICIENCY (%) 14 U SW1 PVIN VIN SW2 VOUT 12 LTC3441 FB 1 11 VC SHDN/SS 7 2 MODE/SYNC GND 3 6 PGND PGND C1: TAIYO YUDEN JMK212BJ106MG C2: TAIYO YUDEN JMK325BJ226MM D1: MBRM120LT3 L1: TOKO A916CY-4R7M 3441 TA04a Efficiency 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 3441 TA04b VIN = 4.2V Burst Mode OPERATION VIN = 3.6 V VIN = 2.7V 3441fa LTC3441 PACKAGE DESCRIPTIO 3.60 ± 0.05 2.20 ± 0.05 3.30 ± 0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) R = 0.05 TYP 3.00 ± 0.10 (2 SIDES) 3.30 ± 0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 1 0.50 BSC 2.50 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD (UE12/DE12) DFN 0806 REV D PIN 1 TOP MARK (NOTE 6) 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695) 0.70 ± 0.05 7 R = 0.115 TYP 0.40 ± 0.10 12 0.75 ± 0.05 6 0.25 ± 0.05 3441fa 15 LTC3441 TYPICAL APPLICATIO VIN 2.5V TO 5.5V 1A MAX RS 0.05Ω R4 1k AVERAGE INPUT CURRENT CONTROL RELATED PARTS PART NUMBER LT 1613 LT1615/LT1615-1 LT1616 LTC1776 LTC1877 LTC1878 LTC1879 LT1930/LT1930A ® DESCRIPTION 550mA (ISW) 1.4MHz High Efficiency Step-Up DC/DC Converter 300mA/80mA (ISW) Constant Off-Time, High Efficiency Step-Up DC/DC Converter 500mA (IOUT) 1.4MHz High Efficiency Step-Down DC/DC Converter 500mA (IOUT) 200kHz High Efficiency Step-Down DC/DC Converter 600mA (IOUT) 550kHz Synchronous Step-Down DC/DC Converter 600mA (IOUT) 550kHz Synchronous Step-Down DC/DC Converter 1.2A (IOUT) 550kHz Synchronous Step-Down DC/DC Converter 1A (ISW) 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX): 34V, IQ: 5.5mA, ISD: ≤ 1μA, ThinSOT 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN): 0.8V, IQ: 20μA, ISD: ≤ 1μA, ThinSOT 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 20μA, ISD: ≤ 1μA, ThinSOT 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 40μA, ISD: ≤ 1μA, 10-Lead MS 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60μA, ISD: ≤ 1μA, 10-Lead MS 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60μA, ISD: ≤ 1μA, TSSOP16E 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 2.5V, IQ: 25μA, ISD: ≤ 1μA, 10-Lead MS 3441fa LTC3405/LTC3405A 300mA (IOUT) 1.5MHz Synchronous Step-Down DC/DC Converter LTC3406/LTC3406B 600mA (IOUT) 1.5MHz Synchronous Step-Down DC/DC Converter LTC3407 LTC3411 LTC3412 LTC3440 600mA (IOUT) ×2 1.5MHz Dual Synchronous Step-Down DC/DC Converter 1.25A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 2.5A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 600mA (IOUT) 2MHz Synchronous Buck-Boost DC/DC Converter ThinSOT is a trademark of Linear Technology Corporation. 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U PCMCIA Powered GSM Modem L1 10μH 4 9 10 5 8 R6 24k 1N914 R1 392k VOUT 3.6V 2A (PULSED) SW1 PVIN VIN SW2 C1 10μF VOUT 12 LTC3441 FB 1 11 VC SHDN/SS 7 2 MODE/SYNC GND 3 6 PGND PGND + 1/2 LT1490A – C4 10nF R5 24k R2 200k COUT 2200μF 3441 TA05 + 1/2 LT1490A 2N3906 ICURRENTLIMIT = 1.22 • R4 R5 • RS – C1: TAIYO YUDEN JMK212BJ106MG C2: SANYO MV-AX SERIES L1: TOKO A916CY-4R7M COMMENTS VIN: 0.9V to 10V, VOUT(MAX): 34V, IQ: 3mA, ISD: ≤ 1μA, ThinSOTTM VIN: 1.2V to 15V, VOUT(MAX): 34V, IQ: 20μA, ISD: ≤ 1μA, ThinSOT High Efficiency, VIN: 3.6V to 25V, VOUT(MIN): 1.25V, IQ: 1.9mA, ISD: ≤ 1μA, ThinSOT High Efficiency, VIN: 7.4V to 40V, VOUT(MIN): 1.24V, IQ: 3.2mA, ISD: 30μA, N8, S8 95% Efficiency, VIN: 2.7V to 10V, VOUT(MIN): 0.8V, IQ: 10μA, ISD: ≤ 1μA, MS8 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN): 0.8V, IQ: 10μA, ISD: ≤ 1μA, MS8 95% Efficiency, VIN: 2.7V to 10V, VOUT(MIN): 0.8V, IQ: 15μA, ISD: ≤ 1μA, TSSOP16 LT 0507 REV A • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003