LTC3445EUF

LTC3445 I2C Controllable Buck Regulator with Two LDOs in a 4mm × 4mm QFN FEATURES Buck Regulator ■ High Efficiency: Up to 93% ■ 600mA Output Current (V CC1 = 3V, VOUT = 1.3V) ■ Programmable Output Voltage: 0.85V to 1.55V ■ 2.5V to 5.5V Input Voltage Range ■ 1.5MHz Constant Frequency or Spread Spectrum Option ■ Soft-Start LDOs ■ Two LDO Regulators: 0.3V Dropout at 50mA PowerPath Controller ■ Dynamically Regulates V CC BATT 2C I ■ Standard (100kHz) or Fast Mode (400kHz) ■ 24-Lead (4mm × 4mm) QFN Package DESCRIPTIO The LTC®3445 contains a high efficiency monolithic synchronous current mode buck regulator, two LDO regulators, a PowerPathTM controller and an I2CTM interface. The buck regulator has a 6-bit programmable output range of 0.85V to 1.55V. Also, the buck regulator uses either a constant (1.5MHz) or a spread spectrum switching frequency. Using the spread spectrum option allows for a lower noise regulated output as well as low noise at the input. In addition, the regulated output voltage slew rate is programmable via the I2C interface. The LTC3445 contains two LDO voltage regulators. The regulator output voltages are externally resistor programmable. Each LDO is capable of delivering up to 50mA. The LTC3445 contains control circuitry (PowerPath) for automatic back-up battery selection. VBACKUP is typically a coin cell. Typical supply current during operation is only 360µA and drops to 27µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3445 ideal for single Li-Ion battery-powered applications. Automatic Burst Mode ® operation increases efficiency at light loads, further extending battery life. APPLICATIO S ■ ■ Intel’s Microprocessor Supply (PXA27X) Portable Instruments , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. PowerPath is a trademark of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, Spread Spectrum patent pending. TYPICAL APPLICATIO VCC 4.7µF CER VBACKUP VCC1 VTRACK VBACKUP VBACKUP VCC2 VCC1 VCC BATT 2.2µH PWR_EN I2C BUS VCC 20k nVCC_FAULT VCC1 OR GND VCC1 OR GND ADD7 ADD6 PGOOD GND LDO1FB LDO2 503k LDO2FB 3445 TA01 20k nBATT_FAULT 4.7µF CER 4.7µF CER 705k 604k 10µF CER 3VTYP BATTFAULT 3V COIN CELL + RUN SDA SCL LTC3445 SW FB LDO1 EFFICIENCY (%) 0.85V TO 1.55V 1.3V 604k 10µF CER 1.1V U Efficiency and Power Loss vs Load Current, VCC1 = 3.6V 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 0.1 1000 3445 TA01b U U 1000 EFFICIENCY DAC MAX DAC MIN 100 POWER LOSS (mW) DAC MAX 10 DAC MIN 1.0 POWER LOSS 3445fa 1 LTC3445 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO BATTFAULT VCC1, VCC2, SDA, SCL Voltages .................. – 0.3V to 6V RUN, VTRACK, VBACKUP, PGOOD, ADD7, ADD6, FB, VCC BATT, BATTFAULT Voltages .............................. – 0.3V to VCC1 SW Voltage ................................ – 0.3V to (VCC1 + 0.3V) LDO1FB, LDO2FB Voltages ..................... – 0.3V to VCC2 LDO1, LDO2 Voltages ................ – 0.3V to (VCC2 + 0.3V) LDO1, LDO2 Source Current ............................... 50mA VCC BATT Source Current ...................................... 8mA P-Channel Switch Source Current (DC) ............. 800mA N-Channel Switch Sink Current (DC) ................. 800mA Peak SW Sink and Source Current ........................ 1.3A LDO1, LDO2, VCC BATT Output Short-Circuit Duration .......................................................... Indefinite Operating Temperature Range (Note 2) ...–40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. –65°C to 125°C TOP VIEW LDO2FB LDO1FB LDO2 LDO1 VCC2 24 23 22 21 20 19 VTRACK 1 VBACKUP 2 VCC1 3 PGOOD 4 ADD7 5 SDA 6 7 NC 18 VCC BATT 17 FB 16 NC 25 15 RUN 14 SW 13 NC 8 SCL 9 10 11 12 ADD6 GND VCC1 NC UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER PART NUMBER LTC3445EUF UF PART MARKING 3445 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VCC1, VCC2 RUN PGOOD IS PARAMETER Input Voltage Range Run Threshold Reports Undervoltage of any Regulator DC Bias Current (Shutdown) DC Bias Current (Buck, LDO1, LDO2 Disabled) Buck Regulator RFB VOUT(MIN) VOUT(MAX) VOUT(STEP) Feedback Resistance Regulated Output Voltage Regulated Output Voltage Output Voltage Step Size (0 to 48) Output Voltage Slew Rate = 00 Output Voltage Slew Rate = 01 Output Voltage Slew Rate = 10 Output Voltage Slew Rate = 11 IPK VLOADREG Peak Inductor Current Output Voltage Load Regulation The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = VCC2 = 3.6V, unless otherwise noted. CONDITIONS ● ● MIN 2.5 0.3 3 TYP 1 27 105 340 MAX 5.5 1.5 50 150 UNITS V V mA µA µA kΩ PGOOD = 0.4V RUN = 0 RUN = VCC1 ● IOUT = 100mA, Burst Mode Operation Disabled IOUT = 100mA, Burst Mode Operation Disabled IOUT = 100mA IOUT = 100mA, VOUT = 0.85V to 1.55V IOUT = 100mA, VOUT = 0.85V to 1.55V IOUT = 100mA, VOUT = 0.85V to 1.55V IOUT = 100mA, VOUT = 0.85V to 1.55V VCC1 = 3V, VFB = 0.5V or VOUT = 90%, Duty Cycle < 35% ● ● ● 0.824 1.504 13.1 0.850 1.55 14.7 11.3 7.5 3.8 0.9 0.875 1.597 16.1 mV/µs mV/µs mV/µs mV/µs 1.25 A % 3445fa 0.75 1 0.5 2 U V V mV W U U WW W LTC3445 ELECTRICAL CHARACTERISTICS SYMBOL IS PARAMETER The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = VCC2 = 3.6V, unless otherwise noted. CONDITIONS MIN TYP 220 6 ● MAX UNITS µA µA Additional Input DC Bias Current For Buck (Note 4) Active Mode VOUT = 90%, ILOAD = 0A Sleep Mode VOUT = 103%, ILOAD = 0A Nominal Oscillator Frequency RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET SW Leakage Additional DC Bias for LDO1 Regulated Output Voltage Line Regulation Load Regulation Dropout Voltage 2.5V < VIN < 5.5V, 1mA < ILOAD < 50mA ∆VCC2 = 2.5V to 5.5V, ILOAD = 1mA, VOUT = 1.2V VCC2 = 2.5V, ∆ILOAD = 1mA to 50mA, VOUT = 1.2V ILOAD = 50mA ILOAD = 0mA ● fOSC RPFET RNFET ILSW LDO1 IS VOUT VOUT = 100% VOUT = 0V ISW = 100mA ISW = –100mA VRUN = 0V, VSW = 0V or 5V, VCC1 = 5V 1.2 1.5 300 0.45 0.325 1 23 1.8 MHz kHz Ω Ω µA 30 VCC2 – 0.3 µA V mV mV V V µA V mV mV V V V V V µA V mA V V V 0.582 1 0.3 0.582 0.6 23 5 15 0.618 30 VCC2 – 0.3 VFB LDO2 IS VOUT LDO Feedback Voltage Additional DC Bias for LDO2 Regulated Output Voltage Line Regulation Load Regulation Dropout Voltage 2.5V < VIN < 5.5V, 1mA < ILOAD < 50mA ∆VCC2 = 2.5V to 5.5V, ILOAD = 1mA, VOUT = 1.2V VCC2 = 2.5V, ∆ILOAD = 1mA to 50mA, VOUT = 1.2V ILOAD = 50mA ILOAD = 0mA ● 0.582 1 0.3 0.582 3 0.6 5 15 0.618 VCC1 – 0.2 VFB VTRACK VTRACK – VCC BATT VBACKUP IBACKUP VCC BATT IVCCBATT LDO Feedback Voltage Tracked Input Voltage Tracked Output Voltage at VCC BATT Backup Battery Voltage Backup Battery Bias Current VCC BATT Output Max VCC BATT Output Current VCC1 Low Level (Bad) Hysteresis PowerPath Controller 3V < VTRACK < VCC1 – 0.2V –0.2 2 0 0.2 5.5 VCC1 = VTRACK = 0V, VBACKUP = 2.5V VTRACK = 0V, VCC1 = 4V, IVCCBAT = 8mA VCC1 = 2.5V Where BATTFAULT Goes High Where BATTFAULT Goes Low VCC1 = 0V to 4.2V, 4.2 to 0V (Note 5) (Note 5) (Note 5) 2.65 2.4 2.85 4 3 8 2.8 2.5 0.3 6.5 3.1 2.9 2.6 BATTFAULT VCC1 High Level (Good) I2C Interface fI2C(MAX) tBUF tHD(RSTA) Maximum I2C Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition 400 1.3 600 kHz µs ns 3445fa 3 LTC3445 ELECTRICAL CHARACTERISTICS SYMBOL tSU(RSTA) tSU(STOP) tHD(DIN) tSU(DAT) VTHR VHYS ILVTRACK ILVBACKUP ILADD7 ILADD6 ILSCL ILSDA ILLDO1 ILLDO2 ILLDO1FB ILLDO2FB ILBATTFAULT IFB1,2 PARAMETER Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time, Input Data Setup Time SCL and SDA Logic Input Threshold SCL and SDA Logic Input Hysteresis VTRACK Leakage VBACKUP Leakage ADD7 Leakage ADD6 Leakage SCL Leakage SCL Leakage LDO1 Leakage LDO2 Leakage LDO1FB Leakage LDO2FB Leakage BATTFAULT Leakage LDO Feedback Input Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = VCC2 = 3.6V, unless otherwise noted. CONDITIONS (Note 5) (Note 5) (Note 5) (Note 5) 1.8 (Note 5) VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V, RUN = 0 VCC = 3.6V, RUN = 0 VCC = 3.6V, RUN = 0 VCC = 3.6V, RUN = 0 VCC = 3.6V VFB1 = 0.6V ● ● ● ● ● ● ● ● ● ● ● MIN TYP MAX 600 600 0 100 UNITS ns ns ns ns V mV 50 1.44 2.2 1 1 1 1 1 1 1 1 1 1 1 µA µA µA µA µA µA µA µA µA µA µA µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3445EUF is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: TJ = TA + PD • 37°C/W Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 5: Determined by design, not production tested. TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 500 1.6 1.5 400 SUPPLY CURRENT (µA) 1.4 VOUT (V) VOUT(N) – VOUT(N–1) (V) ALL ON BUCK ONE LDO TWO LDOs RUN = HIGH RUN = LOW 2.8 4.4 4.8 3.2 3.6 4 SUPPLY VOLTAGE (V) 5.2 5.6 3445 G01 300 200 100 0 2.4 4 UW VOUT vs DAC 0mA 600mA VOUT Step Size vs DAC 0.016 0.014 100mA 0.012 0.010 0.008 0.006 0.004 0.002 0 –0.002 1.3 1.2 1.1 1.0 0.9 0.8 0 10 20 30 40 50 DAC VALUE 60 70 80 0 10 20 30 40 50 DAC VALUE 60 70 80 3445 G02 3445 G03 3445fa LTC3445 TYPICAL PERFOR A CE CHARACTERISTICS Buck Efficiency and Power Loss vs Load Current, VCC1 = 2.5V 100 90 80 70 DAC MIN DAC MAX 100 EFFICIENCY 1000 100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 0.1 1000 3445 G04 60 50 40 30 20 10 0 0.1 1 DAC MAX DAC MIN 10 100 LOAD CURRENT (mA) 0.1 1000 3445 G05 DAC MAX POWER LOSS 10 BUCK OUTPUT (V) EFFICIENCY (%) DAC MIN Buck Output Voltage vs Load Current 1.580 1.560 DAC = MAX VCC2 LEAKAGE CURRENT (µA) 1.2 1.0 0.8 0.6 0.4 0.2 1.540 1.520 1.500 1.480 1.460 –100 VCC2 LEAKAGE CURRENT (µA) BUCK OUTPUT (V) 100 500 700 300 LOAD CURRENT (mA) RDS(ON) vs Input Voltage 600 550 500 RDS(ON) (mΩ) RDS(ON) (mΩ) 450 400 350 300 250 2.2 2.6 3 3.4 3.8 4.2 4.6 INPUT VOLTAGE (V) 5 5.4 5.8 3445 G10 500 RDS(ON) (mΩ) MAIN SWITCH SYNCHRONOUS SWITCH UW 900 Buck Efficiency and Power Loss vs Load Current, VCC1 = 4.2V 1000 EFFICIENCY DAC MAX DAC MIN 100 POWER LOSS (mW) Buck Output Voltage vs Load Current 0.900 DAC = MIN 0.850 POWER LOSS (mW) 10 0.800 1.0 POWER LOSS 1.0 0.750 0.700 –100 100 500 700 300 LOAD CURRENT (mA) 900 3445 G06 IVCC2 vs Temperature (RUN = VCC1) VCC2 = 2.5V VCC2 = 3.6V VCC2 = 4.2V VCC2 = 5.5V 1.2 1.0 0.8 0.6 0.4 0.2 IVCC2 vs Temperature (RUN = 0V) VCC2 = 2.5V VCC2 = 3.6V VCC2 = 4.2V VCC2 = 5.5V 0 –50 –10 30 70 110 TEMPERATURE (°C) 150 3445 G08 0 –50 –10 30 70 110 TEMPERATURE (°C) 150 3445 G09 3445 G07 Synchronous Switch RDS(ON) vs Temperature 700 VCC1 = 2.5V VCC1 = 3.6V VCC1 = 4.2V VCC1 = 5.5V 800 Main Switch RDS(ON) vs Temperature VCC1 = 2.5V VCC1 = 3.6V VCC1 = 4.2V VCC1 = 5.5V 600 700 600 400 500 300 400 200 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 3445 G11 300 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 3445 G12 3445fa 5 LTC3445 TYPICAL PERFOR A CE CHARACTERISTICS Slew Rates DAC Min to DAC Max Buck (DAC = Min) 100mA to 300mA Load Step BUCK VOLTAGE 50mV/DIV 200mV/DIV 100µs/DIV Buck Switching Frequency vs VCC1 1.60 SWITCHING FREQUENCY (MHz) 1.560 SWITCHING FREQUENCY (MHz) 1.56 1.52 1.48 1.44 1.40 2.5 3.5 VCC1 (V) 4.5 VCC BATT vs VCC1 6 5 4 3 2 VCC1 1 0 0 VCC1 RAMP (V) 3445 G19 VTRACK = VBACKUP = 2V VOLTAGE (V) VCC BATT VOLTAGE (V) 6 UW Buck (DAC = Max) 100mA to 400mA Load Step BUCK VOLTAGE 50mV/DIV LOAD CURRENT 100mA/DIV 20µs/DIV LOAD CURRENT 100mA/DIV 3445 G13 3445 G14 20µs/DIV 3445 G15 Buck Switching Frequency vs Temperature Soft-Start (DAC = Min and Max) 4.7Ω Load 1.540 1.520 1.500 1.480 1.460 1.440 –50 –25 BUCK OUTPUTS 500mV/DIV 200µs/DIV 3445 G18 5.5 3445 G16 0 25 50 75 100 125 150 TEMPERATURE (°C) 3445 G17 VCC BATT vs VTRACK 6 5 4 3 2 VTRACK PowerPath LDO Load Step 1mA to 5.5mA VCC BATT 0mA 5mA VCC BATT 20mV/DIV VCC1 = 5.5V VBACKUP = 2V LOAD CURRENT 10mA/DIV 1 0 0 VTRACK RAMP (V) 3445 G20 200µs/DIV 3445 G21 3445fa LTC3445 TYPICAL PERFOR A CE CHARACTERISTICS LDO Reference Voltage vs Temperature 0.604 0.602 LDO REFERENCE VOLTAGE (V) LDO REFERENCE VOLTAGE (V) LDO OUTPUT VOLTAGE (V) 0.600 0.598 0.596 0.594 0.592 0.590 0.498 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3445 G22 0mA LDO Output Voltage vs Load Current 2.590 2.588 1.204 LDO OUTPUT VOLTAGE (V) 2.586 2.584 2.582 VCC2 = 5.5V 2.580 VCC2 = 3.6V 2.578 2.576 2.574 0 10 20 30 40 50 60 LOAD CURRENT (mA) 70 80 LDO OUTPUT VOLTAGE (V) LDO Dropout Voltage vs Load Current 200 –50°C 25°C 150°C LDO DROPOUT VOLTAGE (mV) 160 120 80 40 0 0 10 30 40 20 LOAD CURRENT (mA) UW LDO Reference Voltage vs Load Current 0.608 0.606 0.604 0.602 VCC2 = 5.5V VCC2 = 2.5V 1.202 1.201 1.200 1.199 1.198 1.197 1.196 1.195 LDO Output Voltage vs VCC2 10mA 50mA 0.600 0.598 0.596 0 10 20 30 40 50 60 LOAD CURRENT (mA) 70 80 1.194 2.5 3.1 3.7 4.3 VCC2 (V) 4.9 5.5 3445 G24 3445 G23 LDO Output Voltage vs Load Current 1.202 1.200 VCC2 = 5.5V 1.198 VCC2 = 2.5V 1.196 1.194 0 10 20 30 40 LOAD CURRENT (mA) 50 60 3445 G26 3445 G25 LDO Load Step (10mA to 40mA) LDO OUTPUT 20mV/DIV LOAD CURRENT 20mA/DIV 40µs/DIV 3445 G29 50 3445 G28 3445fa 7 LTC3445 PI FU CTIO S VTRACK (Pin 1): Supply Sense that VCC BATT Tracks when above 3V. Must be ≤ VCC1. VBACKUP (Pin 2): Back-Up Battery Input. VCC1 (Pins 3, 10): Power Supply (2.5V to 5.5V). Both VCC1 pins must be connected externally to the 2.5V to 5.5V supply. PGOOD (Pin 4): Fault Report (Undervoltage). Open-drain driver sinks current whenever LDO1, LDO2 or buck outputs are low. ADD7 (Pin 5): I2C Strappable Address (Bit 7)—VCC1 or ground. SDA (Pin 6): I2C Data Input. NC (Pin 7): Not Connected. SCL (Pin 8): I2C Clock Input. ADD6 (Pin 9): I2C Strappable Address (Bit 6)—VCC1 or ground. GND (Pin 11): Buck NFET Ground. NC (Pin 12): Not Connected. NC (Pin 13): Not Connected. SW (Pin 14): Buck Regulator Switch. RUN (Pin 15): Chip Enable. 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled, drawing 40%. However, the LTC3445 uses a patent-pending scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. 12 U (refer to Figure 1) 1400 1300 1200 1100 1000 900 800 700 600 500 400 2.5 3 3.5 4.5 4 VCC1 (V) 5 5.5 3445 F03 DAC (MIN) DAC (MAX) Figure 3. Buck Maximum Peak Current vs VCC1 Spread Spectrum The LTC3445 has a spread spectrum mode that can be enabled via two register bits. In the spread spectrum mode, the switching frequency is dithered about a center frequency of 1.5MHz. Spread spectrum lowers noise at the regulated output and at the input. Figure 4 shows the noise reduction capabilities of the LTC3445 in spread spectrum mode. The percent spread of the frequency is controlled by two bits in register 5. 00 = 0% Spread 01 = 7.4% Spread 10 = 14.8% Spread 11 = 22.4% Spread DAC The buck output voltage is controlled by programming a 6-bit DAC register (REG0[5:0]) and GO bit (REG2[0]). The output voltage range is 0.85V to 1.55V in ~15mV steps. The DAC setting range is from 0 to 48. Any settings above 48 will default to the 48 settings value. When the desired DAC setting is loaded, the GO bit needs to be changed from 0 to 1. Once the GO bit transition occurs, VOUT will begin to change to the DAC setting loaded at that instant. Slew Rate A 2-bit register is used to control the rate of change of VOUT between DAC settings. The slew rate is controlled by stepping VOUT to its new setting using a series of 3445fa LTC3445 OPERATIO SPR = 00 (Spread Spectrum OFF) NOISE 10dBm/DIV START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz NOISE 10dBm/DIV START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz micro-steps. The table below shows the register settings and corresponding slew rates. REG1 [1:0] 00 01 10 11 SLEW RATE (mV/µs) 11.3 7.5 3.8 0.9 It should be noted that during DAC transistions, PGOOD fault reporting is disabled. LDO OPERATION Adjustable Operation The LTC3445 contains two 50mA LDOs with an output voltage range of 0.6V to (VCC2 – 0.3V). The output voltage is set by the ratio of two external resistors as shown in Figure 1. Each LDO servos the output voltage (Pin LDOx) in order to maintain a feedback voltage (Pin LDOxFB) of U (refer to Figure 1) SPR = 10 NOISE 10dBm/DIV START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz SPR = 01 SPR = 11 NOISE 10dBm/DIV START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz Figure 4. LTC3445 Output Noise Spectrum 0.6V. The current in R1 and R2 is then equal to 0.6V/R2. The regulated voltage is equal to: VOUT = (0.6V/R2) • (R1+R2) Frequency Compensation The LT3445 is frequency compensated by an internal dominant pole. An output capacitor of 2µF to 10µF is usually large enough to provide good stability. In order to insure stability, a feedforward capacitor may be needed between the output pin and the feedback pin. This cancels the pole formed by the stray capacitance in large value feedback resistors. Also, a feedback capacitor minimizes noise pickup and improves ripple rejection. PowerPath OPERATION The output of the PowerPath (VCC BATT) is controlled by a combination of three inputs: main battery (VCC1), VTRACK, and VBACKUP. 3445fa 13 LTC3445 OPERATIO When VCC1 rises above 2.8V, the PowerPath’s LDO is enabled and set to the lesser of 3V or VCC1. Once VTRACK is 3V or higher, it controls the PowerPath’s LDO output (VCC BATT) voltage to within 200mV of VTRACK. Note that VTRACK needs to be less than or equal to VCC1. When VTRACK falls below 3V, VCC1 is used to regulate the PowerPath’s LDO (VCC BATT) to 3V. When VCC1 falls below 2.4V, the PowerPath LDO is disconnected and VBACKUP is connected to VCC BATT. The PowerPath’s fault detection circuit uses an open-drain driver (BATTFAULT) to report when the main battery is disconnected. Figure 5 shows the different states of the PowerPath circuits. Typically, VBACKUP is a coin cell; however, other types of back up power supplies may be used. BATTFAULT = 1 4.2V 3.6V 3V 2.8V VBACKUP 2.4V VCC1 0V VTRACK 3445 F05 I2C OPERATION • • • • • • Simple 2-wire interface Multiple devices on same bus Idle bus must have SDA and SCL lines high LTC3445 is read/write Master controls bus Devices listen for unique address that precedes data SDA SCL S START CONDITION 1-7 ADDRESS 8 R/W 9 ACK 1-7 DATA 8 9 ACK 1-7 DATA 8 9 ACK P STOP CONDITION 3445 F06 14 U (refer to Figure 1) General I2C Bus/SMBus Description I2C Bus and SMBus are reasonably similar examples of 2-wire, bidirectional, serial communications busses. Calling them 2-wire is not strictly accurate, as there is an implied third wire, which is the ground line. Large ground drops or spikes between the grounds of different parts on the bus can interrupt or disrupt communications, as the signals on the two wires are both inherently referenced to a ground which is expected to be common to all parts on the bus. Both bus types have one data line and one clock line which are externally pulled to a high voltage when they are not being controlled by a device on the bus. The devices on the bus can only pull the data and clock lines low, which makes it simple to detect if more than one device is trying to control the bus; eventually, a device will release a line and it will not pull high because another device is still holding it low. Pull-ups for the data and clock lines are usually provided by external discrete resistors, but external current sources can also be used. Since there are no dedicated lines to use to tell a given device if another device is trying to communicate with it, each device must have a unique address to which it will respond. The first part of any communication is to send out an address on the bus and wait to see if another device responds to it. After a response is detected, meaningful data can be exchanged between the parts. Typically, one device will control the clock line at least most of the time and will normally be sending data to the other parts and polling them to send data back to it, and this device is called the master. There can certainly be more than one master, since there is an effective protocol to resolve bus contentions, and non-master (slave) devices can also control the clock to delay rising edges and give themselves more time to complete calculations or communications (clock stretching). Slave devices need to Figure 5 Figure 6. Typical 2-Wire Serial I2C Waveforms 3445fa LTC3445 OPERATIO be able to control the data line to acknowledge communications from the master, and some devices will need to able to send data back to the master; they will be in control of the data line while they are doing so. Many slave devices will have no need to stretch the clock signal and will have no ability to pull the clock line low, which is the case with the LTC3445. Data is exchanged in the form of bytes, which are 8-bit packets. Any byte needs to be acknowledged by the slave (data line pulled low) or not acknowledged by the master (data line left high), so communications are broken up into 9-bit segments, one byte followed by one bit for acknowledging. For example, sending out an address consists of 7 bits of device address, 1 bit that signals whether a read or write operation will be performed, and then 1 more bit to allow the slave to acknowledge. There is no theoretical limit to how many total bytes can be exchanged in a given transmission. I2C and SMBus are very similar specifications, SMBus having been derived from I2C. In general, SMBus is targeted to low power devices (particularly battery-powered ones) and emphasizes low power consumption, while I2C is targeted to higher speed systems where the power consumption of the bus is not so critical. I2C has three different specifications for three different maximum speeds, these being standard mode (100kHz max), fast mode (400kHz max) and HS mode (3.4MHz max). Standard and fast mode are not radically different, but HS mode is very different from a hardware and software perspective and requires an initiating command at standard or fast speed before data can start transferring at HS speed. SMBus simply specifies a 100kHz maximum speed. WRITE BYTE PROTOCOL 1 START 7 AA01011 SLAVE ADDRESS 0 READ BYTE PROTOCOL 1 START 7 AA01011 SLAVE ADDRESS 0 1 WR S 0 1 ACK 8 XXXXXAAA REGISTER ADDRESS S 0 1 ACK 1 START 1 WR S 0 1 ACK 8 XXXXXAAA REGISTER ADDRESS S 0 1 ACK 8 U (refer to Figure 1) The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Acknowledge The acknowledge signal is used for handshaking between the master and the slave. An acknowledge signal (LOW active) as generated by the slave lets the master know that the latest byte of information was received. The acknowledge-related clock pulse is generated by the master. The transmitter master releases the SDA line (HIGH) during the acknowledge clock pulse. The slave receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave receiver doesn’t acknowledge the slave address (for example, it’s unable to receive because it’s performing some real-time function), the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If a slave receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. The 1 ACK S 0 1 STOP DDDDDDDD DATA BYTE 7 AA01011 1 RD 1 ACK S 0 8 DDDDDDDD DATA BYTE 1 ACK M 1 1 STOP 3445 G07 SLAVE ADDRESS 1 Figure 7 3445fa 15 LTC3445 OPERATIO data line is also left high by the slave and master after a slave has transmitted a byte of data to the master in a read operation, but this is a not-acknowledge that indicates that the data transfer is successful. 12C Register Definitions (POR = 00 for all registers) REG 0 7 6 5 4 3 2 1 0 REG 2 7 6 5 4 3 2 1 0 0 (Logic Low) 0 (Logic Low) 0 (Logic Low) STATUS—Buck Thermal Shutdown STATUS—Buck PGOODb STATUS—LDO2 PGOODb STATUS—LDO1 PGOODb Buck Update (GO Bit) 0 (Logic Low) 0 (Logic Low) Buck DAC5 Buck DAC4 Buck DAC3 Buck DAC2 Buck DAC1 Buck DAC0 REG 1 7 6 5 4 3 2 1 0 REG 3 7 6 5 4 3 2 1 0 PGOOD Blank Disable 0 (Logic Low) 0 (Logic Low) 0 (Logic Low) BURST Mode LDO2 Disable LDO1 Disable Buck Disable 0 (Logic Low) 0 (Logic Low) 0 (Logic Low) 0 (Logic Low) 0 (Logic Low) 0 (Logic Low) Slew Rate 1 Slew Rate 0 16 U (refer to Figure 1) Commands Supported The LTC3445 supports read byte and write byte commands. For the ACK bits, an S indicates that the slave is pulling the data line low and an M indicates that the master is effectively acknowledging by leaving the data line high. Data Transfer Timing for Write Commands In order to help assure that bad data is not written into the part, data from a write command is only stored after a valid acknowledge has been performed. The part will detect that SDA is low on the rising edge of SCL that marks the end of the period in which the LTC3445 acknowledges the data write and then latch the data during the following SCL low period. REG 5 7 6 5 4 3 2 1 0 0 (Logic Low) % SPR1 % SPR0 (Logic Low) (Logic Low) (Logic Low) (Logic Low) (Logic Low) 3445fa LTC3445 APPLICATIO S I FOR ATIO BUCK REGULATOR The basic LTC3445 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1µH to 4.7µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VCC1 or lower VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current is ∆IL = 240mA (40% of 600mA). ⎛V⎞ 1 VOUT ⎜ 1 – OUT ⎟ ∆IL = ( f)(L) ⎝ VCC1 ⎠ The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 720mA rated inductor should be enough for most applications (600mA + 120mA). For better efficiency, choose a low DC-resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 200mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size U requirements and any radiated field/EMI requirements than on what the LTC3445 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3445 applications. Table 1 MANUFACTURER PART NUMBER Sumida CDRH3D16/ HP2R2 Sumida CR434R7 TDK TDK7030T2R2M5R4 Coilcraft D03316P-222 VALUE DCR MAX DC SIZE (µH) (mΩ MAX) (A) L × W × H (mm3) 2.2 4.7 2.2 2.2 72 109 12 12 1.2 1.15 5.5 7 4.0 × 4.0 × 1.8 4.0 × 4.5 × 3.5 7.3 × 6.8 × 3.2 12.45 × 9.4 × 5.21 W UU CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VCC1. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: (1) [VOUT (VCC1 – VOUT )]1/2 CIN required IRMS ≅ IOMAX VCC1 (2) This formula has a maximum at VCC1 = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆VOUT is determined by: ⎛ 1⎞ ∆VOUT ≅ ∆IL ⎜ ESR + ⎟ ⎝ 8 fCOUT ⎠ (3) 3445fa 17 LTC3445 APPLICATIO S I FOR ATIO where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3445’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VCC1. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VCC1, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Buck Output Voltage Programming The LTC3445 has an internal resistor divider network tied to the FB pin. The output voltage is controlled by a DAC (6-bit register) whose setting is controlled by the I2C interface. The effective DAC bit range is from 0 to 48. Note 18 U that any DAC settings above 48 defaults to the 48 setting. The DAC controls the VOUT range of 0.85V to 1.55V in ~15mV steps. The default value for VOUT is 1.35V and is reset to this value whenever VCC1 comes up. When the DAC’s value is changed, LTC3445 controls VOUT’s slew rate via a 2-bit RATE register. The RATE register can be updated via the I2C interface. The slew rate can be set to approximately 0.9mV/µs, 3.8mV/µs, 7.5mV/µs or 11.3mV/µs. The default value for RATE is 10mV/µs and is reset to this value whenever VCC1 comes up. The DAC and RATE values are not lost whenever the RUN pin is deasserted. Once the DAC and RATE registers are programmed, a GO bit transition is required for the buck to update. This is accomplished by changing the GO bit (REG2[0]) from logic low to a logic high. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3445 buck regulator circuits: VCC1 quiescent current and I2R losses. The VCC1 quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 8. 1. The VCC1 quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the 3445fa W UU LTC3445 APPLICATIO S I FOR ATIO 1000 100 POWER LOSS (mW) 10 DAC MAX DAC MIN 1 0.1 0.1 1 10 100 LOAD CURRENT (mA) 1000 3445 F08 Figure 8. Power Loss vs Load Current, VCC1 = 3.6V internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VCC1 to ground. The resulting dQ/dt is the current out of VCC1 that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VCC1 and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. U Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. LDO REGULATORS The LDOs in the LTC3445 are 50mA low dropout regulators with low quiescent and shutdown currents. Each device is capable of supplying 50mA at a dropout voltage of 300mV. The LDOs are current limited to greater than 50mA but less than 75mA. The output voltages of the LDOs are set with external resistive dividers according to the following formula: VLDOOUT1 = 0.6(1 + R1/R2) VLDOOUT2 = 0.6(1 + R3/R4) Output Capacitance and Transient Response The LTC3445 LDOs are designed to be stable with a wide range of output capacitors. A minimum output capacitor of 2.2µF with an ESR of 3Ω or less is recommended to 3445fa W UU (4) (5) 19 LTC3445 APPLICATIO S I FOR ATIO prevent oscillations. The LTC3445 LDOs are micropower devices and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. PowerPath CONTROLLER The PowerPath circuitry in the LTC3445 is used to provide backup power from VBACKUP to the VCC BATT pin when VCC1 is low or disconnected. When VCC1 is below 2.8V, the PowerPath routes VBACKUP, typically a coin cell, to the VCC BATT pin. While VBACKUP is selected there is no current limiting except for a small (