LTC3615IUF-PBF

FeaTures n n n n n n n n n n n n LTC3615 Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter DescripTion The LTC®3615 is a dual 3A synchronous step-down regulator using a current mode, constant-frequency architecture. The DC supply current is only 130µA (Burst Mode operation at no-load) while maintaining the output voltages, dropping to zero current in shutdown. The 2.25V to 5.5V input supply range makes the LTC3615 ideally suited for single Li-Ion applications. 100% duty cycle capability provides low dropout operation, which extends operating time in battery-operated systems. The operating frequency is externally programmable up to 4MHz, allowing the use of small surface mount inductors. 0°, 90°, or 180° of phase shift between the two channels can be selected to minimize input current ripple and output voltage ripple in a single 6A output configuration. Programmable slew rate limiting reduces EMI, and external synchronization can be applied up to 4MHz. The internal synchronous switches increase efficiency and eliminate the need for external catch diodes, saving external components and board space. The LTC3615 is offered in leadless 24-pin 4mm × 4mm QFN and thermally enhanced 24-pin TSSOP packages. L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5994885, 6304066, 6498466, 6580258, 6611131. n n n n n n High Efficiency: Up to 94% Dual Outputs with 2 × 3A Output Current Capability Low Output Ripple Burst Mode® Operation: IQ = 130µA 2.25V to 5.5V Input Voltage Range ±1% Output Voltage Accuracy Output Voltages Down to 0.6V Programmable Slew Rate at Switch Pins Low Dropout Operation: 100% Duty Cycle Shutdown Current ≤1µA Adjustable Switching Frequency Up to 4MHz Internal or External Compensation Selectable Pulse-Skipping/Forced Continuous/ Burst Mode Operation with Adjustable Burst Clamp Optional Active Voltage Positioning (AVP) with Internal Compensation Selectable 0°/90°/180° Phase Shift Between Channels Fixed Internal and Programmable External Soft-Start Accurate Start-Up Tracking Capability DDR Memory Mode IOUT = ±1.5A Available in 4mm × 4mm QFN-24 and TSSOP-24 Packages applicaTions n n n n n Point-of-Load Supplies Distributed Power Supplies Portable Computer Systems DDR Memory Termination Handheld Devices Typical applicaTion VIN 100µF SVIN PVIN1 RUN1 TRACK/SS1 PGOOD1 LTC3615 ITH1 SRLIM RT /SYNC MODE PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND PVIN2 SW1 0.47µH 422k FB1 210k SW2 0.47µH 665k FB2 PGND 3615 TA01a Efficiency and Power Loss vs Load Current 100 90 VOUT1 1.8V/3A 47µF 80 EFFICIENCY (%) 70 60 50 40 30 20 0.01 0.1 1 POWER LOSS (W) 10 VOUT2 2.5V/3A 47µF 210k 0.001 VIN = 3.3V VIN = 4V 10 2.25MHz VIN = 5V VOUT = 2.5V 0 0.0001 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 3615 TA01b 3615f  LTC3615 absoluTe MaxiMuM raTings (Note 1) PVIN1, PVIN2 Voltages..................... –0.3V to SVIN + 0.3V SVIN Voltage................................................. –0.3V to 6V SW1 Voltage ............................. –0.3V to (PVIN1 + 0.3V) SW2 Voltage .............................. –0.3V to (PVIN2 + 0.3V) PGOOD1, PGOOD2 Voltages ........................ –0.3V to 6V All Other Pins .............................. –0.3V to (SVIN + 0.3V) Operating Junction Temperature Range (Note 2)....................................... –40°C to 125°C Storage Temperature.............................. –65°C to 150°C Lead Soldering Temperature (TSSOP) .................. 300°C Reflow Peak Body Temperature (QFN) .................. 260°C pin conFiguraTion PVIN1 PVIN1 PHASE FB2 ITH2 TRACK/SS2 SGND PVIN2 PVIN2 SW2 SW2 1 2 3 4 5 6 7 8 9 25 PGND 24 MODE 23 FB1 22 ITH1 21 TRACK/SS1 20 SVIN 19 PVIN1 18 PVIN1 17 SW1 16 SW1 15 PGOOD1 14 SRLIM 13 PGOOD2 ITH1 1 FB1 2 MODE 3 PHASE 4 FB2 5 ITH2 6 7 TRACK/SS2 8 SGND 9 10 11 12 PVIN2 PVIN2 SW2 SW2 25 PGND TRACK/SS1 TOP VIEW TOP VIEW SW1 SW1 18 PGOOD1 17 SRLIM 16 PGOOD2 15 RT/SYNC 14 RUN1 13 RUN2 SVIN 24 23 22 21 20 19 RUN2 10 RUN1 11 RT /SYNC 12 FE PACKAGE 24-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 33°C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB UF PACKAGE 24-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH LTC3615EFE#PBF LTC3615IFE#PBF LTC3615EUF#PBF LTC3615IUF#PBF TAPE AND REEL LTC3615EFE#TRPBF LTC3615IFE#TRPBF LTC3615EUF#TRPBF LTC3615IUF#TRPBF PART MARKING* LTC3615FE LTC3615FE 3615 3615 PACKAGE DESCRIPTION 24-Lead Plastic TSSOP 24-Lead Plastic TSSOP 24-Lead (4mm × 4mm) Plastic QFN 24-Lead (4mm × 4mm) Plastic QFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3615f  LTC3615 elecTrical characTerisTics SYMBOL VIN VUVLO VFB PARAMETER Operating Voltage Range Undervoltage Lockout Threshold Feedback Voltage Internal Reference SVIN Ramping Down SVIN Ramping Up (Note 3) VTRACK = SVIN, VSRLIM = 0V 0°C < TJ < 85°C –40°C < TJ < 125°C (Note 3) VTRACK = 0.3V, VSRLIM = SVIN (Note 3) VTRACK = 0.5V, VSRLIM = SVIN VFBx = 0.6V SVIN = PVINx = 2.25V to 5.5V (Note 4) VITHx from 0.5V to 0.9V (Note 4) VITHx = SVIN, VFBx = 0.6V (Note 5) VFB1 = 0.5V, VMODE = SVIN, VRUN2 = 0V (Note 6) VFBx = 0.5V, VMODE = SVIN, VRUNx = SVIN (Note 6) Sleep Mode VFB1 = 0.7V, VRUN1 = SVIN, VRUN2 = 0V, VMODE = 0V, VITH1 = SVIN (Note 5) VFBx = 0.7V, VRUN1 = SVIN, VRUN2 = 0V, VMODE = 0V (Note 4) VFBx = 0.7V, VRUNx = SVIN, VMODE =0V, VITHx = SVIN (Note 5) VFBx = 0.7V, VRUNx = SVIN, VMODE =0V, ITH = (Note 4) Shutdown RDS(ON) ILIM Top Switch On-Resistance Bottom Switch On-Resistance Top Switch Current Limit SVIN = PVIN = 5.5V, VRUNx = 0V PVINx = 3.3V (Note 10) PVINx = 3.3V (Note 10) Sourcing (Note 8), VFB = 0.5V Duty Cycle 30ns l l l l The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, RSRLIM = 40.2k, unless otherwise specified (Notes 1, 2, 11). CONDITIONS l l MIN 2.25 1.7 TYP MAX 5.5 2.25 UNITS V V V V V V V nA %/ V % % µA µA l 0.592 0.590 0.289 0.489 0.6 0.3 0.5 0 0.608 0.610 0.311 0.511 ±30 0.2 0.2 2 Feedback Voltage External Reference (Note 7) IFB ∆VLINEREG ∆VLOADREG IS Feedback Input Current Line Regulation Load Regulation Active Mode 130 220 200 360 1 µA µA µA µA µA mΩ mΩ 7.5 –5 1 A A A µA µmho µA ms Ω µs Bottom Switch Current Limit ISW(LKG) gm(EA) IEAO tSOFT-START Switch Leakage Current Error Amplifier Transconductance Error Amplifier Output Current Internal Soft-Start Time RON(TRACK/SS_DIS) TRACK/SS Pull-Down Resistance at Start-Up tTRACK/SS_DIS fOSC Soft-Start Discharge Time at Start-Up Internal Oscillator Frequency 1.85 1.8 0.4 1.2 2.25 2.25 2.65 2.7 4 0.3 MHz MHz MHz V V 3615f  LTC3615 The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, RSRLIM = 40.2k, unless otherwise specified (Notes 1, 2, 11). SYMBOL jSW1–SW2 PARAMETER Output Phase Shift Between SW1 and SW2 CONDITIONS VPHASE < 0.15 • SVIN 0.35 • SVIN < VPHASE < 0.65 • SVIN VPHASE > 0.85 • SVIN (Note 9) SVIN – 0.3 0.3 SVIN – 0.3 1.1 0.5 TRACK/SSx = SVIN, Entering Window VFBx Ramping Up VFBx Ramping Down TRACK/SSx = SVIN , Leaving Window VFBx Ramping Up VFBx Ramping Down tPGOOD RPGOOD VRUN Power Good Blanking Time Enable Pin Entering/Leaving Window Input High Input Low Pull-Down Resistance Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3615 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3615E is guaranteed to meet performance specifications over the 0°C to 85°C operating junction temperature range. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3615I is guaranteed to meet specifications over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedence. l l elecTrical characTerisTics MIN TYP 0 90 180 MAX UNITS Deg Deg Deg V V V V V % % VSRLIM VMODE (Note 9) Voltage at SRLIM to Enable DDR Mode Internal Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode External Burst Mode Operation SVIN • 0.58 0.85 –6 6 9 –9 11 –11 140 30 0.4 4 PGOOD Power Good Voltage Windows –3.5 3.5 % % µs Ω V V MΩ 70 8 1 105 12 Power Good Pull-Down On-Resistance I = 10mA Note 3: This parameter is tested in a feedback loop which servos VFB1,2 to the midpoint for the error amplifier (VITH1,2 = 0.75V). Note 4: External compensation on ITH pin. Note 5: Tying the ITH pin to SVIN enables internal compensation and AVP mode for the selected channel. Note 6: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 7: See description of the TRACK/SS pin in the Pin Functions section. Note 8: When sourcing current, the average output current is defined as flowing out of the SW pin. When sinking current, the average output current is defined as flowing into the SW pin. Sinking mode requires the use of forced continuous mode. Note 9: See description of the MODE pin in the Pin Functions section. Note 10: Guaranteed by design and correlation to wafer level measurements for QFN packages. Note 11: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. 3615f  LTC3615 Typical perForMance characTerisTics 100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001 VIN = 2.5V VIN = 3.3V VIN = 5V 0.01 0.1 1 OUTPUT CURRENT (A) 10 3615 G01 VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. Efficiency vs Load Current (VMODE = 0V) VOUT = 2.5V Efficiency vs Load Current (VMODE = 0V) VOUT = 1.8V 100 90 80 Efficiency vs Load Current (VMODE = 0V) VOUT = 1.2V 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 10 3615 G02 70 60 50 40 30 20 10 0 0.001 VIN = 2.5V VIN = 3.3V VIN = 5V 0.01 0.1 1 OUTPUT CURRENT (A) 0 0.001 VIN = 3.3V VIN = 4V VIN = 5V 0.01 0.1 1 OUTPUT CURRENT (A) 10 3615 G03 Efficiency vs Load Current (VMODE = 0.55 • SVIN) 100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001 VIN = 2.25V VIN = 3.3V VIN = 5V 0.01 0.1 1 OUTPUT CURRENT (A) 10 3615 G04 Efficiency vs Load Current (VMODE = 0.55 • SVIN) 100 90 80 70 60 50 40 30 20 10 0 0.001 VIN = 2.25V VIN = 3.3V VIN = 5V 0.01 0.1 1 OUTPUT CURRENT (A) 10 3615 G05 Efficiency vs Input Voltage (VMODE = 0V) 95 90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 2.25 2.75 IOUT = 3A IOUT = 2A IOUT = 1A IOUT = 0.3A IOUT = 0.2A 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25 3615 G06 VOUT = 1.8V VOUT = 1.2V VOUT = 1.8V Load Regulation 0.5 0.4 0.3 VOUT ERROR (%) 0.2 0.1 EXTERNAL –0.1 COMPENSATION –0.2 –0.3 –0.4 0 0.5 1 1.5 2 2.5 3 3615 G07 Line Regulation 0.20 0.15 0.10 VOUT ERROR (%) 0.05 0 –0.05 –0.10 –0.15 –0.20 2.25 2.75 3.25 3.75 4.25 4.75 5.25 3615 G08 VMODE = 1.5V INTERNAL COMPENSATION (ITH = SVIN ) 0 OUTPUT CURRENT (A) INPUT VOLTAGE (V) 3615f  LTC3615 Typical perForMance characTerisTics Forced Continuous Mode Operation (FCM) VOUT 20mV/DIV VOUT 20mV/DIV VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. Pulse-Skipping Mode Operation VOUT 20mV/DIV Burst Mode Operation IL 200mA/DIV IL 500mA/DIV VOUT = 1.8V IOUT = 100mA VMODE = 1.5V 1µs/DIV 3615 G09 IL 500mA/DIV VOUT = 1.8V IOUT = 75mA VMODE = 3.3V 20µs/DIV 3615 G10 VOUT = 1.8V IOUT = 75mA VMODE = 0V 20µs/DIV 3615 G11 Load Step Transient in FCM External Compensation VOUT 200mV/DIV VOUT 200mV/DIV IL 1A/DIV Load Step Transient in Pulse-Skipping Mode VOUT 200mV/DIV IL 1A/DIV Load Step Transient in Burst Mode Operation IL 1A/DIV VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 1.5V COMPENSATION FIGURE 1 3615 G12 VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 3.3V COMPENSATION FIGURE 1 3615 G13 VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 0V COMPENSATION FIGURE 1 3615 G14 Load Step Transient in FCM with AVP Mode VOUT 100mV/DIV IL 1A/DIV IL 2A/DIV 0A VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 1.5V VITH = 3.3V OUTPUT CAPACITOR VALUE FIGURE 1 3615 G15 Load Step Transient in Forced Continuous Mode Sourcing and Sinking Current VOUT 200mV/DIV RUN 1V/DIV VOUT 500mV/DIV IL 1A/DIV PGOOD 2V/DIV VOUT = 1.8V 50µs/DIV ILOAD = –1.5A TO 3A VMODE = 1.5V COMPENSATION FIGURE 1 3615 G16 Internal Start-Up in Forced Continuous Mode VOUT = 1.8V IOUT = 3A VMODE = 1.5V 500µs/DIV 3615 G17 3615f  LTC3615 Typical perForMance characTerisTics Reference Voltage vs Temperature 0.606 0.604 REFERENCE VOLTAGE (V) 0.602 0.600 0.598 0.596 0.594 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) RDS(ON) ( ) 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 2.25 3.25 4.25 VIN (V) 5.25 3615 G19 VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. Switch On-Resistance vs Input Voltage MAIN SWITCH SYNCHRONOUS SWITCH 3615 G18 Switch On-Resistance vs Temperature 100 90 80 70 RDS(ON) (µA) fOSC (MHz) 3615 G20 4.0 3.6 MAIN SWITCH 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 Frequency vs RT/SYNC 60 50 40 30 20 10 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) SYNCHRONOUS SWITCH 0 100 200 300 400 500 600 700 800 900 1000 RT/SYNC (k ) 3615 G22 Frequency vs Temperature 2.7 2.6 2.5 2.4 fOSC (MHz) 2.3 2.2 2.1 2.0 1.9 1.8 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3615 G23 Frequency vs Input Voltage 2.60 2.50 2.40 2.30 RT/SYNC = SVIN RT /SYNC = SVIN RT = 178k fOSC (MHz) 2.20 2.10 2.00 1.90 1.80 1.70 1.60 2.25 3.00 3.75 VIN (V) 4.50 5.25 3615 G24 RT/SYNC = 200k 3615f  LTC3615 Typical perForMance characTerisTics Switch Leakage vs Temperature 2.0 1.8 1.6 SWITCH LEAKAGE (µA) SUPPLY CURRENT (µA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 SYNCHRONOUS SWITCH MAIN SWITCH VIN = 5.5V 180 VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. No Load Supply Current vs Temperature 180 MODE = 0V 160 RUNx = ITHx = SVIN 140 SUPPLY CURRENT (µA) 120 100 80 60 40 20 No Load Supply Current vs Input Voltage MODE = 0V 160 RUNx = ITHx = SVIN 140 120 100 80 60 40 20 0 2.25 2.75 3.25 3.75 4.25 VIN (V) 4.75 5.25 3615 G26 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3615 G25 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3615 G27 Slew Rate of Falling Edge at SW1/2 vs SRLIM Resistor VIN = 3.3V VOUT = 1.8V IOUT = 1A Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor VIN = 3.3V VOUT = 1.8V IOUT = 1A VOUT 20mV/DIV SRLIM = SGND OR SVIN 40.2k 1V/DIV OPEN 100k SW 2V/DIV IL 500mA/DIV Sinking Current SRLIM = SGND OR SVIN 40.2k OPEN 100k 1V/DIV VOUT = 1.2V IOUT = –1A VMODE = 1.5V 1µs/DIV 3615 G30 2ns/DIV 3615 G28 2ns/DIV 3615 G29 Tracking Up/Down in Forced Continuous Mode, SRLIM Pin Tied to 0V VOUT1 1V/DIV VTRACK/SS 500mV/DIV PGOOD 2V/DIV 2ms/DIV VOUT = 0V TO 1.8V IOUT = 3A VTRACK/SS = 0V TO 0.7V VMODE = 1.5V VSRLIM = 0V 3615 G31 Tracking Up/Down in Forced Continuous Mode, SRLIM Pin Tied to SVIN VOUT1 500mV/DIV VTRACK/SS 200mV/DIV PGOOD 2V/DIV 2ms/DIV VOUT = 0V TO 1.2V IOUT = 3A VTRACK/SS = 0V TO 0.4V VMODE = 1.5V VSRLIM = 3.3V 3615 G32 3615f  LTC3615 pin FuncTions (FE/UF) PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied to SGND, the phase between SW1 and SW2 will be 0°. Tying PHASE to SVIN will select 180° of phase shift. With the PHASE pin tied to half of the SVIN voltage, 90° of phase shift will be selected. VFB2 (Pin 2/Pin 5): Voltage Feedback Input Pin for Channel 2. See VFB1. ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of Channel 2. See ITH1. TRACK/SS2 (Pin 4 /Pin 7): Internal, External Soft-Start, External Reference Input for Channel 2. See TRACK/SS1. SGND (Pin 5/Pin 8): Signal Ground. All small-signal and compensation components should connect to this ground pin which, in turn, should be connected to PGND at one point. PVIN2 (Pins 6, 7/Pins 9, 10) Channel 2 Power Supply Input. See PVIN1. SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node. See SW1. RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See RUN1. RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forcing RUN1 above the input threshold enables the output SW1 of channel 1. Forcing both RUNx pins to ground shuts down the LTC3615. In shutdown, all functions are disabled and the LTC3615 draws 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. More output capacitance may be required depending on the duty cycle and load step requirements. If the ITH pin is tied to SVIN, the active voltage positioning (AVP) mode and the internal compensation is selected. In AVP mode, the load regulation performance is intentionally reduced, setting the output voltage at a point that is dependent on the load current. When the load current suddenly increases, the output voltage starts from a level slightly higher than nominal so the output voltage can droop more and stay within the specified voltage range. When the load current suddenly decreases, the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. This behavior is demonstrated in Figure 6. The benefit is a lower peak-to-peak output voltage deviation for a given load step without having to increase the output filter capacitance. Alternatively, the output voltage filter capacitance can be reduced while maintaining the same peak-to-peak transient response. For this operation mode, the loop gain is reduced and no external compensation is required. Programmable Switch Pin Slew Rate As switching frequencies rise, it is desirable to minimize the transition time required when switching to minimize power losses and blanking time for the switch to settle. However, fast slewing of the switch node results in relatively high external radiated EMI and high on-chip supply transients, which can cause problems for some applications. VOUT 100mV/DIV VOUT 200mV/DIV 3A IL 1A/DIV 100mA 3615 F05 50µs/DIV VOUT = 1.8V ILOAD = 100mA TO 3A VMODE = 1.5V COMPENSATION AND OUTPUT CAPACITOR VALUES OF FIGURE 3 IL 1A/DIV 50µs/DIV VOUT = 1.8V ILOAD = 100mA TO 3A VMODE = 1.5V VIN = VITH = 3.3V OUTPUT CAPACITOR VALUE FIGURE 3 3615 F06 Figure 5. Load Step Transient in FCM with External Compensation Figure 6. Load Step Transient in FCM in AVP Mode 3615f 0 LTC3615 applicaTions inForMaTion The LTC3615 allows the user to control the slew rate of the switching node SW by using the SRLIM pin. Tying this pin to ground selects the fastest slew rate. The slowest slew rate is selected when the pin is open. Connecting a resistor (between 10k to 100k) from SRLIM pin to ground adjusts the slew rate between the maximum and minimum values. The reduced dV/dt of the switch node results in a significant reduction of the supply and ground ringing, as well as lower radiated EMI. See Figure 7a and the Typical Performance Characteristics section for examples. Reducing the slew rate causes a trade-off between efficiency and low EMI (see Figure 7b). Particular attention should be used with very high switching frequencies. Using the slowest slew rate (SRLIM open) can reduce the minimum duty cycle capability. Soft-Start The RUNx pins provide a means to shut down each channel of the LTC3615. Pulling both pins below 0.3V places the LTC3615 in a low quiescent current shutdown state (IQ < 1µA). After enabling the LTC3615 by bringing either one or both RUNx pins above the threshold, the enabled channels enter a soft-start-up state. The type of soft-start behavior is set by the TRACK/SSx pins. The soft-start cycle begins with an initial discharge pulse pulling down the TRACK/SSx pin to SGND and discharging the external capacitor CSS (see Figure 3). The initial discharge is adequate to discharge capacitors up to 33nF If a larger capacitor is required, connect the . external soft-start resistor RSS to the RUN pin to fully discharge the capacitor. 1. Tying this pin to SVIN selects the internal soft-start circuit. This circuit ramps the output voltage to the final value within 1ms. 2. If a longer soft-start period is desired, it can be set externally with a resistor and capacitor on the TRACK/SSx pins as shown in Figure 3. The voltage applied at the TRACK/SSx pins sets the value of the internal reference at VFB until TRACK/SSx is pulled above 0.6V. The external soft-start duration can be calculated by using the following equation:   SVIN tSS = RSS • CSS • I n   SV – 0.6 V   IN 3. The TRACK/SSx pin can be used to track the output voltage of another supply. Regardless of either the internal or external soft-start state, the MODE pin is ignored during start-up and the regulator defaults to pulse-skipping mode. In addition, the PGOODx pin is kept low, and the frequency foldback function is disabled. VIN = 3.3V VOUT = 1.8V IOUT = 1A 92 91 SRLIM = SGND OR SVIN EFFICIENCY (%) 40.2k 90 89 88 87 86 85 84 83 2ns/DIV 3615 F07a VOUT = 1.8V IOUT = 1A FCM GND OR SVIN 20k OPEN 40.2k 1V/DIV OPEN 100k 82 2.25 3.06 3.88 VIN (V) 4.69 5.50 3615 07b (7a) Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor (7b) Efficiency vs SRLIM Resistor Programming Figure 7. Slew Rate and the SRLIM Resistor 3615f  LTC3615 applicaTions inForMaTion Output Voltage Tracking Input If SRLIM is low, once VTRACK/SS reaches or exceeds 0.6V the run state is entered, and the MODE selection, power good and current foldback circuits are enabled. In the run state, the TRACK/SS pin can be used to track down/up the output voltage of another supply. If the VTRACK/SS again drops below 0.6V, the LTC3615 enters the down-tracking state and the VOUT is referenced to the TRACK/SS voltage. If VTRACK/SS reaches 0.1V value the switching frequency is reduced by 4x to ensure that the minimum duty cycle limit does not prevent the output from following the TRACK/SS pin. The run state will resume if the VTRACK/SS again exceeds 0.6V and the VOUT is referenced to the internal reference. VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE Through the TRACK/SS pin, the output voltage can be set up to either coincidental or ratiometric tracking, as shown in Figures 8 and 9. To implement the coincidental tracking waveform in Figure 8, connect an extra resistive divider to the output of the master channel and connect its midpoint to the TRACK/SS pin for the slave channel. The ratio of this divider should be selected the same as that of the slave channel’s feedback divider (Figure 10). In this tracking mode, the master channel’s output must be set higher than slave channel’s output. To implement the ratiometric start-up in Figure 9, no extra divider is needed; simply connect the TRACK/SS pin to the other channel’s VFB pin (Figure 12). VOUT1 VOUT2 VOUT2 TIME 3615 F08 TIME 3615 F09 Figure 8. Coincident Start-Up Tracking Figure 9. Ratiometric Start-Up Tracking VOUT1 VOUT1 R3 R1 R1 R2 VOUT1 LTC3615 FB1 R3 TRACK/SS2 VOUT2 R5 FB2 R6 3615 F10 LTC3615 FB1 R1 LTC3615 FB1 R4 R2 R2 TRACK/SS2 TRACK/SS2 VOUT2 R3 FB2 FB2 R4 3615 F11 3615 F12 VOUT2 R4 R5 Figure 10. Set for Coincidentally Tracking (R3 = R5, R4 = R6) Figure 11. Alternative Set-Up for Coincident Start-Up Tracking (R1 = R3, R2 = R3 = R5) Figure 12. Set-Up for Ratiometric Tracking 3615f  LTC3615 applicaTions inForMaTion External Reference Input (DDR Mode) If SRLIM is tied to SVIN, the TRACK/SS pin can be used as an external reference input between 0.3V and 0.5V, if desired (see Figure 13). VFB PIN 0.6V VOLTAGE 0V In DDR mode, the maximum slew rate is selected. If VTRACK/SS is within 0.3V and 0.5V, the PGOOD function is enabled. If VTRACK/SS is less than 0.3V, the output current foldback is disabled and the PGOOD pin is always pulled down. 0.6V TRACK/SS PIN VOLTAGE 0.1V 0V RUN PIN VOLTAGE VIN 0V VIN 0V RUN STATE REDUCED SWITCHING FREQUENCY SVIN PIN VOLTAGE TIME RUN STATE 3615 F13 SHUTDOWN SOFT-START STATE STATE tSS > 1ms DOWNTRACKING STATE UPTRACKING STATE Figure 13. Tracking if VSRLIM Is Low 0.45V VFB PIN 0.3V VOLTAGE 0V 0.45V TRACK/SS 0.3V PIN VOLTAGE 0.1V 0V RUN PIN VOLTAGE VIN 0V VIN 0V EXTERNAL VOLTAGE REFERENCE 0.45V SVIN PIN VOLTAGE TIME RUN STATE REDUCED SWITCHING FREQUENCY RUN STATE 3615 F14 SHUTDOWN SOFT-START STATE STATE tSS > 1ms DOWNTRACKING STATE UPTRACKING STATE Figure 14. Tracking if VSRLIM Is Tied to SVIN 3615f  LTC3615 applicaTions inForMaTion DDR Application The LTC3615 can be used in DDR memory power supply applications by tying the SRLIM pin to SVIN. In DDR mode, the maximum slew rate is selected. The output can both source and sink current. Current sinking is typically limited to 1.5A, for 1MHz frequency and 1µH inductance, but can be lower at higher frequencies and low output voltages. If higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. See the Typical Performance Characteristics curves for more information. In addition, in DDR mode, lower external reference voltages and tracking output voltages between channels are possible. See the Output Voltage Tracking Input section. Single, Low Ripple 6A Output Application The LT3615 can generate a single, low ripple 6A output if the outputs of the two switching regulators are tied together and share a single output capacitor (see Figure 15 on back of data sheet). In order to evenly share the current between the two regulators, it is needed to connect pins FB1 to FB2, ITH1 to ITH2 and to select forced continuous mode at the MODE pin. To achieve lowest ripple, 90°, or better, 180°, antiphase is selected by connecting the PHASE pin to midrail or SVIN. There are several advantages to this 2-phase buck regulator. Ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive capacitors. Although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. This may be important when there are tight height restrictions on the circuit. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of little consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN due to gate charge, and it is typically larger than the DC bias current. Both the DC bias and gate charge losses are proportional to VIN , thus, their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC), as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% of the total loss. 3615f  LTC3615 applicaTions inForMaTion Thermal Considerations In most applications, the LTC3615 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3615 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160°C, all four power switches will be turned off and the SW node will become high impedance. To prevent the LTC3615 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. To determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator, and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TRISE where TA is the ambient temperature. As an example, consider this case: the LTC3615 is in dropout at an input voltage of 3.3V with a load current for each channel of 2A at an ambient temperature of 70°C. Assuming a 20°C rise in junction temperature, to 90°C, results in an RDS(ON) of 0.086mΩ (see the graph in the Typical Performance Characteristics section). Therefore, the power dissipated by the part is: PD = (I12 + I22) • RDS(ON) = 0.69W For the QFN package, the θJA is 37°C/W. Therefore, the junction temperature of the regulator operating at 70°C ambient temperature is approximately: TJ = 0.69W • 37°C/W + 70°C = 95°C Note that for very low input voltage, the junction temperature will be higher due to increased switch resistance RDS(ON). It is not recommended to use full load current at high ambient temperature and low input voltage. To maximize the thermal performance of the LTC3615, the Exposed Pad should be soldered to a ground plane. See the PC Board Layout Checklist. Design Example As a design example, consider using the LTC3615 in an application with the following specifications: VIN = 3.3V to 5.5V VOUT1 = 2.5V VOUT2 = 1.2V IOUT1(MAX) = 1A IOUT2(MAX) = 3A IOUT(MIN) = 100mA f = 2.25MHz Because efficiency is important at both high and low load current, Burst Mode operation will be selected by connecting the MODE pin to SGND. First, calculate the timing resistor: R RT / SYNC = 4E11 Ω • Hz = 178 k 2.25MHz Next, calculate the inductor values for about 1A ripple current at maximum VIN :   2.5V L1 =   2.25MHz • 1A     1.2V L2 =   2.25MHz • 1A    2.5V  •  1– = 0.6µH  5.5V    1.2V  •  1– = 0.42µH  5.5V   Using a standard value of 0.56µH and 0.47µH inductors results in maximum ripple currents of:   2.5V ∆ I L1 =   2.25MHz • 0.56µH    1.2V ∆ I L2 =   2.25MHz • 0.47µH   2.5V  •  1– = 1.08 A  5.5V    1.2V  •  1– = 0.89 A  5.5V   3615f  LTC3615 applicaTions inForMaTion COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, 47µF ceramic capacitors will be used with X5R or X7R dielectric. CIN should be sized for a maximum current rating of: IOUT1 I OUT 2 + = 2A RMS 2 2 Decoupling the PVIN with two 47µF capacitors is adequate for most applications. IRMS(MAX ) = Finally, it is possible to define the soft-start up time choosing the proper value for the capacitor and the resistor connected to TRACK/SS pin. If one sets minimum TSS = 5ms and a resistor of 4.7M, the following equation can be solved with the maximum SVIN = 5.5V: CSS = 5ms = 9.2nF   5.5V 4.7M • In   5.5V – 0.6 V   PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3615: 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the SGND pin at one point which is then connected to the PGND node at the exposed pad close to the LTC3615 2. Connect the (+) terminal of the input capacitors, CIN, as close as possible to the PVINx pins, and the (–) terminal as close as possible to the exposed pad PGND. This capacitor provides the AC current into the internal power MOSFETs. 3. Keep the switching nodes, SWx, away from all sensitive small signal nodes FBx, ITHx, RTSYNC, SRLIM. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to PGND (exposed pad) for best performance. 5. Connect the VFBx pins directly to the feedback resistors. The resistor divider must be connected between VOUTx and SGND. The standard value of 10nF and 4.7M guarantees the minimum soft-start time of 5ms. In Figure 3, channel 1 shows the schematic for this design example. 3615f  LTC3615 Typical applicaTions External Compensation, Forced Continuous Operation, In-Phase Switching, Slew Rate Limit, Common PGOOD Output VIN 3.3V 47µF 47µF 1µF SVIN RUN RUN1 TRACK/SS1 RT 178k R5 40.2k PGOOD1 ITH1 RT /SYNC SRLIM MODE PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND RC2 43k CC2 220pF 10pF (2 ) SW2 0.47µH R3 665k R4 210k 47µF VOUT2 2.5V/3A FB1 MODE (2 ) PVIN1 (2 ) PVIN2 (2 ) SW1 0.47µH R1 412k R2 205k 47µF VOUT1 1.8V/3A RC1 43k CC1 220pF 10pF LTC3615 R6 226k R7 174k FB2 100k PGOOD PGND 3615 TA02 VOUT1 Waveform VOUT2 Waveform VOUT1 100mV/DIV VOUT2 100mV/DIV IOUT1 1A/DIV 20µs/DIV 3615 TA02b IOUT2 1A/DIV 20µs/DIV 3615 TA02c 3615f  LTC3615 Typical applicaTions DDR Memory Termination VIN 3.3V CIN1 47µF CIN2 47µF CIN3 1µF SVIN (2 ) PVIN1 (2 ) PVIN2 RUN1 TRACK/SS1 PGOOD1 ITH1 RT /SYNC SRLIM MODE LTC3615 (2 ) SW1 L1 0.47µH R1 121k R3 150k R4 49.9k VDDQ 1.8V/3A COUT1 47µF R10 15k C2 1000pF C1 10pF FB1 R2 60.4k L2 0.47µH (2 ) SW2 R5 49.9k FB2 R6 49.9k 3615 TA03a R8 174k R9 226k PHASE RUN2 TRACK/SS2 PGOOD2 COUT2 47µF VTT 0.9V 3A/–1.5A R7 15k C4 1000pF C3 10pF ITH2 SGND PGND Ratiometric Start-Up VDD 500mV/ DIV VTT 500µs/DIV 3615 TA03b 3615f  LTC3615 Typical applicaTions Master and Slave for Coincident Tracking Outputs Using a 2MHz External Clock RF1 24 CF1 1µF VIN 3.3V C1 47µF C2 47µF L1 0.47µH R1 715k R2 357k C3 22pF R3 453k R4 453k CO11 47µF 4.7M SVIN (2 ) PVIN1 (2 ) PVIN2 (2 ) SW1 RUN1 TRACK/SS1 FB1 LTC3615 PGOOD1 RT /SYNC ITH1 SRLIM MODE VOUT1 1.8V/3A CO12 22µF CSYNC 15pF PGOOD1 2MHz CLOCK RT 200k R5 100k 10nF RC1 15k CC1 1000pF CC2 10pF R9 226k R8 174k (2 ) SW2 PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND PGND FB2 L2 0.47µH R5 294k CO21 47µF CO22 22µF VOUT2 1.2V/3A PGOOD2 R7 100k CC4 10pF C7 22pF R6 294k RC2 15k CC3 470pF 3615 TA04a Coincident Start-Up Coincident Tracking Up/Down VOUT1 500mV/ DIV VOUT2 VOUT1 500mV/ DIV VOUT2 2ms/DIV 3615 TA04b 200ms/DIV 3615 TA04c 3615f  LTC3615 package DescripTion FE Package 24-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation AA 3.25 (.128) 7.70 – 7.90* (.303 – .311) 3.25 (.128) 24 23 22 21 20 19 18 17 16 15 14 13 6.60 0.10 4.50 0.10 SEE NOTE 4 2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 6.40 2.74 (.252) (.108) BSC 1 2 3 4 5 6 7 8 9 10 11 12 1.20 (.047) MAX 0 –8 4.30 – 4.50* (.169 – .177) 0.25 REF 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE24 (AA) TSSOP 0208 REV Ø 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3615f 0 LTC3615 package DescripTion UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ± 0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ± 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 4.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 23 24 0.40 ± 0.10 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 3615f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LTC3615 Typical applicaTion VIN 3.3V 47µF 1µF SVIN RUN1 (2 ) (2 ) PVIN1 PVIN2 (2 ) SW1 FB1 L2 0.47µH VSW1 L1 0.47µH R1 102k R2 102k VOUT 1.2V/6A 47µF TRACK/SS1 PGOOD1 ITH1 20pF RC 7.5k CC 2000pF R8 226k LTC3615 RT / SYNC SRLIM MODE R9 174k PHASE RUN2 2V/DIV, 1A/DIV VSW2 IL1 IL2 (2 ) SW2 FB2 IL1 + IL2 MODE = FCM 200ns/DIV 3615 F16 TRACK/SS2 PGOOD2 ITH2 SGND PGND 3615 F15 Figure 16. Reduced Ripple Current (Waveform IL1 + IL2) and Ripple Voltage (Not Shown) Through 180° Phase Shift Between SW1 and SW2 100 VOUT = 1.2V 90 MODE = FCM 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 VIN = 2.5V VIN = 3.3V VIN = 5V 0.1 1 OUTPUT CURRENT (A) 10 3615 F17 Figure 15. Single, Low Ripple 6A Output Figure 17. Efficiency vs Load Current for VOUT = 1.2V and IOUT Up to 6A relaTeD parTs PART NUMBER LTC3633 LTC3546 LTC3417A-2 LTC3612 LTC3614 LTC3616 DESCRIPTION 15V, Dual 3A, 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, Dual 3A/1A, 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, Dual 1.5A/1A, 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 95% Efficiency, VIN: 3.60V to 15V, VOUT(MIN) = 0.6V, IQ = 500µA, ISD < 13µA, 4mm × 5mm QFN-28 and TSSOP-28E Packages 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 160µA, ISD < 1µA, 4mm × 5mm QFN-28 Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 125µA, ISD < 1µA, TSSOP-16E and 3mm × 5mm DFN-16 Packages 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 3mm × 4mm QFN-20 and TSSOP-20E Packages 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 3mm × 4mm QFN-20 and TSSOP-20E Packages 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 3mm × 5mm QFN-24 Package 3615f  Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0410 • PRINTED IN USA www.linear.com  LINEAR TECHNOLOGY CORPORATION 2010