LTC3727LXEUH-1

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LTC3727LX-1 High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator DESCRIPTIO The LTC®3727LX-1 is a high performance dual step-down switching regulator controller that drives all N-channel synchronous power MOSFET stages. A constant-frequency current mode architecture allows phase-lockable frequency of up to 550kHz. Power loss and noise due to the ESR of the input capacitors are minimized by operating the two controller output stages out of phase. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. There is a precision 0.8V reference and a power good output indicator. A wide 4V to 28V (32V maximum) input supply range encompasses all battery chemistries. Table 1 PART NUMBER LTC3727 LTC3727-1 LTC3727A-1 VIN RANGE 4V to 36V 4V to 36V 4V to 36V VREF ACCURACY OVERTEMPERATURE ±1.5% ±1% ±1% ±1% LATCHOFF No Yes No No MINIMUM ON-TIME 120ns 180ns 180ns 120ns Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 14V Out-of-Phase Controllers Reduce Required Input Capacitance and Power Supply Induced Noise OPTI-LOOP® Compensation Minimizes COUT ±1.5% Output Voltage Accuracy Power Good Output Voltage Monitor Phase-Lockable Fixed Frequency 250kHz to 550kHz Dual N-Channel MOSFET Synchronous Drive Wide VIN Range: 4V to 32V Operation Very Low Dropout Operation: 99% Duty Cycle Adjustable Soft-Start Current Ramping Foldback Output Current Limiting Output Overvoltage Protection Low Shutdown IQ: 20µA Selectable Constant-Frequency or Burst Mode® Operation Small 28-Lead SSOP and 5mm × 5mm QFN Packages LTC3727LX-1 4V to 32V APPLICATIO S ■ ■ ■ Telecom Systems Automotive Systems Distributed DC Power Systems , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919. TYPICAL APPLICATIO + M1 8µH 4.7µF VIN PGOOD INTVCC TG1 0.1µF BOOST1 SW1 BG1 PLLIN SENSE1+ LTC3727LX-1 TG2 BOOST2 SW2 BG2 PGND SENSE2 + 1µF CERAMIC M3 0.1µF M2 0.015Ω VOUT1 5V 5A 1000pF SENSE1– VOSENSE1 105k 1% ITH1 20k 1% 220pF 15k SENSE2 – VOSENSE2 ITH2 1000pF + 47µF 6V SP M1, M2, M3, M4: FDS6680A RUN/SS1 SGND RUN/SS2 0.1µF 0.1µF 220pF 15k Figure 1. High Efficiency Dual 12V/5V Step-Down Converter 3727lx1fa U U U VIN 18V TO 28V 22µF 50V CERAMIC 15µH M4 0.015Ω VOUT2 12V 4A 280k 1% 20k 1% + 56µF 15V SP 3727LX1 F01 1 LTC3727LX-1 ABSOLUTE AXI U RATI GS (Note 1) ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ...2.7V to – 0.3V Peak Output Current < 10µs (TG1, TG2, BG1, BG2) .... 3A INTVCC Peak Output Current ................................ 50mA Operating Temperature Range (Note 2)..... – 40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range ................. – 65°C to 125°C Lead Temperature (Soldering, 10 sec, G Package)............................. 300°C Solder Reflow Temperature (UH Package) ........... 265°C Input Supply Voltage (VIN).........................32V to – 0.3V Top Side Driver Voltages (BOOST1, BOOST2) ...................................40V to – 0.3V Switch Voltage (SW1, SW2) .........................32V to – 5V INTVCC, EXTVCC, (BOOST1-SW1), (BOOST2-SW2) ........................................8.5V to – 0.3V RUN/SS1, RUN/SS2, PGOOD ..................... 7V to – 0.3V SENSE1+, SENSE2 +, SENSE1–, SENSE2 – Voltages .....................................14V to – 0.3V PLLIN, PLLFLTR, FCB Voltages ........... INTVCC to – 0.3V PACKAGE/ORDER I FOR ATIO TOP VIEW RUN/SS1 SENSE1 + SENSE1 – VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 1 2 3 4 5 6 7 8 9 28 PGOOD 27 TG1 26 SW1 25 BOOST1 24 VIN 23 BG1 22 EXTVCC 21 INTVCC 20 PGND 19 BG2 18 BOOST2 17 SW2 16 TG2 15 RUN/SS2 RUN/SS1 SENSE1– SENSE1+ PGOOD LTC3727LXEG-1 VOSENSE1 1 PLLFLTR 2 PLLIN 3 FCB 4 ITH1 5 SGND 6 3.3VOUT 7 ITH2 8 SW1 ORDER PART NUMBER NC TG1 NC 3.3VOUT 10 ITH2 11 VOSENSE2 12 SENSE2 – 13 SENSE2 + 14 VOSENSE2 NC TG2 SENSE2– SENSE2+ G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) IS SGND (MUST BE SOLDERED TO PCB) Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted. SYMBOL VOSENSE1, 2 IVOSENSE1, 2 VREFLNREG PARAMETER Regulated Feedback Voltage Feedback Current Reference Voltage Line Regulation CONDITIONS (Note 4); ITH1, 2 Voltage = 1.2V (Note 4) VIN = 3.6V to 30V (Note 4) ● ELECTRICAL CHARACTERISTICS RUN/SS2 SW2 NC Main Control Loops 0.788 0.800 –5 0.002 0.812 – 50 0.02 V nA %/V 3727lx1fa 2 U U W WW U W TOP VIEW ORDER PART NUMBER LTC3727LXEUH-1 24 BOOST1 23 VIN 22 BG1 21 EXTVCC 20 INTVCC 19 PGND 18 BG2 17 BOOST2 32 31 30 29 28 27 26 25 33 UH PART MARKING 727LX1 9 10 11 12 13 14 15 16 MIN TYP MAX UNITS LTC3727LX-1 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted. SYMBOL VLOADREG PARAMETER Output Voltage Load Regulation CONDITIONS (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 2.0V ITH1, 2 = 1.2V; Sink/Source 5µA (Note 4) ITH1, 2 = 1.2V (Note 4) (Note 5) VIN = 15V, EXTVCC Tied to VOUT1, VOUT1 = 8.5V VRUN/SS1, 2 = 0V ● ● ● ELECTRICAL CHARACTERISTICS MIN TYP 0.1 – 0.1 1.3 3 1 20 MAX 0.5 – 0.5 UNITS % % mmho MHz mA µA V µA V V V µA % µA gm1, 2 gmGBW1, 2 IQ Transconductance Amplifier gm Transconductance Amplifier GBW Input DC Supply Current Normal Mode Shutdown Forced Continuous Threshold Forced Continuous Pin Current Burst Inhibit (Constant-Frequency) Threshold Undervoltage Lockout Feedback Overvoltage Lockout Sense Pins Total Source Current Maximum Duty Factor Soft-Start Charge Current Maximum Current Sense Threshold TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation EXTVCC Voltage Drop EXTVCC Switchover Voltage EXTVCC Hysteresis Nominal Frequency Lowest Frequency Highest Frequency PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability 35 0.84 – 0.05 7.3 4 0.88 VFCB IFCB VBINHIBIT UVLO VOVL ISENSE DFMAX IRUN/SS1, 2 VSENSE(MAX) TG1, 2 tr TG1, 2 tf BG1, 2 tr BG1, 2 tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCC VLDO INT VLDO EXT VEXTVCC VLDOHYS fNOM fLOW fHIGH RPLLIN IPLLFLTR 0.76 – 0.30 0.800 – 0.18 6.8 VFCB = 0.85V Measured at FCB pin VIN Ramping Down Measured at VOSENSE1, 2 (Each Channel) VSENSE1–, 2 – = VSENSE1+, 2+ = 0V In Dropout VRUN/SS1, 2 = 1.9V VRUN/SS1, VRUN/SS2 Rising VOSENSE1, 2 = 0.7V,VSENSE1–, 2 – = 12V (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF Each Driver CLOAD = 3300pF Each Driver ● ● ● 3.5 0.84 – 85 98 0.5 1.0 105 0.86 – 60 99.4 1.2 1.5 135 50 50 40 40 90 90 120 VRUN/SS1, 2 ON RUN/SS Pin ON Threshold 1.9 165 90 90 90 80 V mV ns ns ns ns ns ns ns INTVCC Linear Regulator 8.5V < VIN < 30V, VEXTVCC = 6V ICC = 0mA to 20mA, VEXTVCC = 6V ICC = 20mA, VEXTVCC = 8.5V ICC = 20mA, EXTVCC Ramping Positive ● 7.2 7.5 0.2 70 7.8 1.0 160 V % mV V V 6.9 7.3 0.3 Oscillator and Phase-Locked Loop VPLLFLTR = 1.2V VPLLFLTR = 0V VPLLFLTR ≥ 2.4V 350 220 460 380 255 530 100 fPLLIN < fOSC fPLLIN > fOSC –15 15 430 290 580 kHz kHz kHz kΩ µA µA 3727lx1fa 3 LTC3727LX-1 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted. SYMBOL V3.3OUT V3.3IL V3.3VL PGOOD Output VPGL IPGOOD VPG PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level, Either Controller IPGOOD = 2mA VPGOOD = 5V VOSENSE with Respect to Set Output Voltage VOSENSE Ramping Negative VOSENSE Ramping Positive –6 6 –7.5 7.5 0.1 0.3 ±1 – 9.5 9.5 V µA % % PARAMETER 3.3V Regulator Output Voltage 3.3V Regulator Load Regulation 3.3V Regulator Line Regulation CONDITIONS No Load I3.3 = 0mA to 10mA 6V < VIN < 30V ● ELECTRICAL CHARACTERISTICS 3.3V Linear Regulator MIN 3.25 TYP 3.35 0.5 0.05 MAX 3.45 2.5 0.3 UNITS V % % Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3727LX-1 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3727LXEG-1: TJ = TA + (PD • 95 °C/W) LTC3727LXEUH-1: TJ = TA + (PD • 34 °C/W) Note 4: The LTC3727LX-1 is tested in a feedback loop that servos VITH1, 2 to a specified voltage and measures the resultant VOSENSE1, 2. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Output Current and Mode (Figure 13) 100 90 80 Burst Mode OPERATION FORCED CONTINUOUS MODE EFFICIENCY (%) 60 50 40 30 20 10 0 0.001 VIN = 15V VOUT = 8.5V 0.1 0.01 1 OUTPUT CURRENT (A) 10 3727LX1 G01 EFFICIENCY (%) EFFICIENCY (%) 70 CONSTANTFREQUENCY (BURST DISABLE) 4 UW Efficiency vs Output Current (Figure 13) 100 VIN = 7V 90 VIN = 10V VIN = 15V VIN = 20V 70 90 100 Efficiency vs Input Voltage (Figure 13) VOUT = 5V IOUT = 3A 80 80 70 60 VOUT = 5V 0.1 0.01 1 OUTPUT CURRENT (A) 10 3727LX1 G02 60 50 0.001 50 5 25 15 INPUT VOLTAGE (V) 32 3727LX1 G03 3727lx1fa LTC3727LX-1 TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Input Voltage and Mode (Figure 13) 1000 EXTVCC VOLTAGE DROP (mV) 800 SUPPLY CURRENT (µA) INTVCC VOLTAGE (V) BOTH CONTROLLERS ON 600 400 200 SHUTDOWN 0 0 20 10 INPUT VOLTAGE (V) 30 32 3727LX1 G04 Maximum Current Sense Threshold vs Duty Factor 150 125 100 VSENSE (mV) 75 50 25 0 0 20 40 60 DUTY FACTOR (%) 80 100 3727LX1 G07 VSENSE (mV) 90 75 60 45 30 15 0 VSENSE (mV) Current Sense Threshold vs ITH Voltage 150 125 0.0 VSENSE (mV) 75 50 25 0 –25 –50 0 0.5 1.0 1.5 VITH (V) 2.0 2.5 NORMALIZED VOUT (%) 100 –0.2 VITH (V) UW 3727LX1 G10 EXTVCC Voltage Drop 160 140 120 100 80 60 40 20 0 0 Internal 7.5V LDO Line Regulation 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 6.9 ILOAD = 1mA VEXTVCC = 8.5V 10 30 CURRENT (mA) 20 40 50 3727LX1 G05 6.8 0 5 10 15 20 25 INPUT VOLTAGE (V) 30 32 3727LX1 G06 Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) 150 135 120 105 Maximum Current Sense Threshold vs VRUN/SS (Soft-Start) 150 VSENSE(CM) = 1.6V 125 100 75 50 20 60 80 0 100 40 PERCENT OF NOMINAL OUTPUT VOLTAGE (%) 3727LX1 G08 0 1 2 3 4 VRUN/SS (V) 5 6 3727LX1 G09 Load Regulation FCB = 0V VIN = 15V FIGURE 1 VITH vs VRUN/SS 2.5 VOSENSE = 0.7V –0.1 2.0 1.5 1.0 –0.3 0.5 –0.4 0 1 3 2 LOAD CURRENT (A) 0 4 5 3727LX1 G11 0 1 2 3 4 VRUN/SS (V) 5 6 3727LX1 G12 3727lx1fa 5 LTC3727LX-1 TYPICAL PERFOR A CE CHARACTERISTICS SENSE Pins Total Source Current 100 50 0 1.4 1.2 DROPOUT VOLTAGE (V) –50 1.0 RSENSE = 0.015Ω 0.8 0.6 0.4 0.2 0 RSENSE = 0.010Ω 0 1 2 3 4 5 3727LX1 G14 RUN/SS CURRENT (µA) ISENSE (µA) –100 –150 –200 –250 –300 –350 –400 0 10 5 VSENSE COMMON MODE VOLTAGE (V) 15 Soft-Start Up (Figure 12) IL 5A/DIV VOUT 5V/DIV IL 2A/DIV IL 2A/DIV VRUN/SS 5V/DIV VIN = 20V VOUT = 12V 50ms/DIV Input Source/Capacitor Instantaneous Current (Figure 12) IIN 1A/DIV VSW1 20V/DIV VSW2 20V/DIV VIN = 15V VOUT1 = 12V VOUT2 = 5V IOUT1 = IOUT2 = 2A 1µs/DIV 6 UW 3727LX1 G16 Dropout Voltage vs Output Current (Figure 13) VOUT = 5V 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 RUN/SS Current vs Temperature 0 –50 –25 OUTPUT CURRENT (A) 0 25 50 75 TEMPERATURE (°C) 100 125 3727LX1 G13 3727LX1 G15 Load Step (Figure 12) Load Step (Figure 12) VOUT 200mV/DIV VOUT 200mV/DIV VIN = 15V 50µs/DIV VOUT = 12V LOAD STEP = 0A TO 3A Burst Mode OPERATION 3727LX1 G17 VIN = 15V 50µs/DIV VOUT = 12V LOAD STEP = 0A TO 3A CONTINUOUS MODE 3727LX1 G18 Burst Mode Operation (Figure 12) Constant Frequency (Burst Inhibit) Operation (Figure 12) VOUT 20mV/DIV VOUT 20mV/DIV IL 0.5A/DIV 3727LX1 G19 IL 0.5A/DIV VIN = 15V VOUT = 12V VFCB = OPEN IOUT = 20mA 50µs/DIV VIN = 15V VOUT = 12V VFCB = 7.5V IOUT = 20mA 5µs/DIV 3727LX1 G20 3727LX1 G21 3727lx1fa LTC3727LX-1 TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Pin Input Current vs Temperature 35 10 VOUT = 5V EXTVCC SWITCH RESISTANCE (Ω) CURRENT SENSE INPUT CURRENT (µA) 33 31 29 27 25 –50 –25 Oscillator Frequency vs Temperature 700 UNDERVOLTAGE LOCKOUT (V) 600 FREQUENCY (kHz) 500 400 300 200 100 0 – 50 – 25 VPLLFLTR = 1.2V UW EXTVCC Switch Resistance vs Temperature 8 6 4 2 50 25 0 75 TEMPERATURE (°C) 100 125 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3727LX1 G22 3727LX1 G23 Undervoltage Lockout vs Temperature 3.50 VPLLFLTR = 5V 3.45 3.40 3.35 3.30 3.25 3.20 –50 –25 VPLLFLTR = 0V 50 25 75 0 TEMPERATURE (°C) 100 125 50 25 75 0 TEMPERATURE (°C) 100 125 3727LX1 G24 3727LX1 G25 3727lx1fa 7 LTC3727LX-1 PI FU CTIO S RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combination of Soft-Start and Run Control Inputs. A capacitor to ground at each of these pins sets the ramp time to full output current. Forcing either of these pins back below 1.0V causes the IC to shut down the circuitry required for that particular controller. SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+) Input to the Differential Current Comparators. The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11): The (–) Input to the Differential Current Comparators. VOSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9): Receives the remotely-sensed feedback voltage for each controller from an external resistive divider across the output. PLLFLTR (Pin 5/Pin 2): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. PLLIN (Pin 6/Pin 3): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. FCB (Pin 7/Pin 4): Forced Continuous Control Input. This input acts on both controllers and is normally used to regulate a secondary winding. Pulling this pin below 0.8V will force continuous synchronous operation. Do not leave this pin floating. ITH1, ITH2 (Pins 8, 11/Pins 5, 8): Error Amplifier Outputs and Switching Regulator Compensation Points. Each associated channels’ current comparator trip point increases with this control voltage. SGND (Pin 9/Pin 6): Small Signal Ground. Common to both controllers; must be routed separately from high current grounds to the common (–) terminals of the COUT capacitors. 3.3VOUT (Pin 10/Pin 7): Linear Regulator Output. Capable of supplying 10mA DC with peak currents as high as 50mA. 8 U U U G Package/UH Package PGND (Pin 20/Pin 19): Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs, anodes of the Schottky rectifiers and the (–) terminal(s) of CIN. INTVCC (Pin 21/Pin 20): Output of the Internal 7.5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7µF tantalum or other low ESR capacitor. EXTVCC (Pin 22/Pin 21): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies VCC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 7.3V. See EXTVCC connection in Applications section. Do not exceed 8.5V on this pin. BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTVCC. VIN (Pin 24/Pin 23): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the boost and switch pins and Schottky diodes are tied between the boost and INTVCC pins. Voltage swing at the boost pins is from INTVCC to (VIN + INTVCC). SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC – 0.5V superimposed on the switch node voltage SW. PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on either VOSENSE pin is not within ±7.5% of its set point. Exposed Pad (Pin 33, UH Package): Signal Ground. Must be soldered to the PCB ground for electrical contact and optimum thermal performance. 3727lx1fa LTC3727LX-1 FU CTIO AL DIAGRA PLLIN FIN 100k PLLFLTR RLP CLP CLK1 OSCILLATOR CLK2 – + PGOOD VOSENSE1 – + – + VOSENSE2 – VSEC 0.18µA R6 FCB + R5 – FCB 1.5V 7V – + BINH + 0.74V 0.74V 0.86V 0.86V PHASE DET – 0.86V 4(VFB) SLOPE COMP + + 50k SENSE – 50k SENSE DSEC 3mV 25k 25k 2.4V VFB 0.80V VOSENSE R2 3.3VOUT + – 0.8V VREF – EA + OV + – R1 VIN VIN 7.3V EXTVCC + – 7.5V LDO REG 1.2µA SHDN RST 4(VFB) 0.86V ITH CC + 7.5V INTVCC 6V RUN SOFT START RUN/SS CC2 RC SGND INTERNAL SUPPLY CSS 3727LX1 F02 Figure 2 OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC3727LX-1 uses a constant-frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VOSENSE pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VOSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. 3727lx1fa + W INTVCC DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST DB VIN DROP OUT DET S R Q Q TOP BOT FCB SW SWITCH LOGIC BOT B SHDN INTVCC BG PGND TG CB D1 U U U + CIN TOP ON COUT + 0.55V + – VOUT RSENSE INTVCC CSEC I1 + – ++ – – I2 9 LTC3727LX-1 OPERATIO The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 400ns every tenth cycle to allow CB to recharge. The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, the ITH pin voltage is gradually released allowing normal, full-current operation. When both RUN/SS1 and RUN/SS2 are low, all LTC3727LX-1 controller functions are shut down, including the 7.5V and 3.3V regulators. Low Current Operation The FCB pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by temporarily forcing continuous PWM operation on both controllers; and 2) to select between two modes of low current operation. When the FCB pin voltage is below 0.8V, the controller forces continuous PWM current mode operation. In this mode, the top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VINTVCC – 1V but greater than 0.8V, the controller enters Burst Mode operation. Burst Mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will temporarily inhibit turn-on of both output MOSFETs until the output voltage drops. There is 60mV of hysteresis in the burst comparator B tied to the ITH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by 10 U (Refer to Functional Diagram) having the hysteretic comparator follow the error amplifier gain block. Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 250kHz to 550kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFLTR pin goes low, forcing the oscillator to its minimum frequency. Continuous Current (PWM) Operation Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 7.5V low dropout linear regulator supplies INTVCC power. If EXTVCC is taken above 7.3V, the 7.5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. 3727lx1fa LTC3727LX-1 OPERATIO Power Good (PGOOD) Pin The PGOOD pin is connected to an open drain of an internal MOSFET. The MOSFET turns on and pulls the pin low when either output is not within ± 7.5% of the nominal output level as determined by the resistive feedback divider. When both outputs meet the ± 7.5% requirement, the MOSFET is turned off within 10µs and the pin is allowed to be pulled up by an external resistor to a source of up to 7V. THEORY AND BENEFITS OF 2-PHASE OPERATION The LTC3727LX-1 dual high efficiency DC/DC controller brings the considerable benefits of 2-phase operation to portable applications. Notebook computers, PDAs, handheld terminals and automotive electronics will all benefit from the lower input filtering requirement, reduced electromagnetic interference (EMI) and increased efficiency associated with 2-phase operation. When constant-frequency dual switching regulators operate both channels in phase (i.e., single-phase operation), both switches turn on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses increased the total RMS current flowing from the input capacitor, requiring U (Refer to Functional Diagram) the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and battery. With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 3 compares the input waveforms for a representative single-phase dual switching regulator to the new LTC3727LX-1 2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input current from 2.53ARMS to 1.55ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to IRMS2, meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV IIN(MEAS) = 2.53ARMS 3727LX1 F03a IIN(MEAS) = 1.55ARMS 3727LX1 F03b (a) (b) Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC3727LX-1 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency 3727lx1fa 11 LTC3727LX-1 OPERATIO Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative duty cycles which, in turn, are dependent upon the input voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how the RMS input current varies for single-phase and 2-phase operation for 3.3V and 5V regulators over a wide input voltage range. It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. INPUT RMS CURRENT (A) APPLICATIO S I FOR ATIO Figure 1 on the first page is a basic LTC3727LX-1 application circuit. External component selection is driven by the load requirement, and begins with the selection of RSENSE and the inductor value. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC3727LX-1 current comparator has a maximum threshold of 135mV/RSENSE and an input common mode range of SGND to 14V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Allowing a margin for variations in the LTC3727LX-1 and external component values yields: R SENSE = 90mV IMAX When using the controller in very low dropout conditions, the maximum output current level will be reduced due to 12 U W UU U (Refer to Functional Diagram) 3.0 2.5 2.0 1.5 1.0 0.5 0 2-PHASE DUAL CONTROLLER SINGLE PHASE DUAL CONTROLLER VO1 = 5V/3A VO2 = 3.3V/3A 0 10 20 30 INPUT VOLTAGE (V) 40 3727LX1 F04 Figure 4. RMS Input Current Comparison the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. Operating Frequency The LTC3727LX-1 uses a constant-frequency phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to PhaseLocked Loop and Frequency Synchronization in the Applications Information section for additional information. A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure 5. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 550kHz. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. However, a 3727lx1fa LTC3727LX-1 2.5 Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper (I2R) losses will increase. 250 300 350 400 450 500 OPERATING FREQUENCY (kHz) 550 PLLFLTR PIN VOLTAGE (V) 2.0 1.5 1.0 0.5 0 200 3727LX1 F05 Figure 5. PLLFLTR Pin Voltage vs Frequency higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN: Ferrite designs have very low core loss and are preferred at high switching frequencies, so designers can concentrate on reducing I2R loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. New designs for high current surface mount inductors are available from numerous manufacturers, including Coiltronics, Vishay, TDK, Pulse, Panasonic, Wuerth, Coilcraft, Toko and Sumida. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for each controller in the LTC3727LX-1: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 7.5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the 3727lx1fa ∆ IL = ⎛V ⎞ 1 VOUT ⎜ 1 – OUT ⎟ ( f)(L) VIN ⎠ ⎝ Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. 13 LTC3727LX-1 APPLICATIO S I FOR ATIO BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC3727LX-1 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN VIN – VOUT VIN Synchronous Switch Duty Cycle = The MOSFET power dissipations at maximum output current are given by: V 2 PMAIN = OUT (IMAX ) (1 + δ )RDS(ON) + VIN k ( VIN ) (IMAX )(CRSS )( f ) 2 PSYNC = VIN – VOUT (IMAX )2 (1+ δ )RDS(ON) VIN where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to 14 U estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diode D1 shown in Figure 2 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the deadtime and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. Schottky diodes should be placed in parallel with the synchronous MOSFETs when operating in pulse-skip mode or in Burst Mode operation. CIN and COUT Selection The selection of CIN is simplified by the multiphase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS current requirement. Increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input RMS ripple current from this maximum value (see Figure 4). The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. The type of input capacitor, value and ESR rating have efficiency effects that need to be considered in the selection process. The capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 22µF to 47µF is usually sufficient for a 25W output supply operating at 250kHz. The ESR of the capacitor is important for capacitor power dissipation as well as overall battery efficiency. All of the power (RMS ripple current • ESR) not only heats up the capacitor but wastes power from the battery. Medium voltage (20V to 35V) ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage 3727lx1fa W UU LTC3727LX-1 APPLICATIO S I FOR ATIO coefficients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics’ higher ESR and dryout possibility require several to be used. Multiphase systems allow the lowest amount of capacitance overall. As little as one 22µF or two to three 10µF ceramic capacitors are an ideal choice in a 20W to 35W power supply due to their extremely low ESR. Even though the capacitance at 20V is substantially below their rating at zero-bias, very low ESR loss makes ceramics an ideal candidate for highest efficiency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk capacitance goals. In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Re quired IRMS ≅ IMAX ⎡ VOUT ( VIN − VOUT ) ⎤ ⎣ ⎦ VIN 1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The benefit of the LTC3727LX-1 multiphase can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switch on at the same time. The total RMS power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the U worst-case controller is adequate for the dual controller design. Remember that input protection fuse resistance, battery resistance and PC board trace resistance losses are also reduced due to the reduced peak currents in a multiphase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The drains of the two top MOSFETS should be placed within 1cm of each other and share a common CIN(s). Separating the drains and CIN may produce undesirable voltage and current resonances at VIN. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The output ripple (∆VOUT) is determined by: W UU ⎛ 1⎞ ∆ VOUT ≅ ∆ IL ⎜ ESR + 8 fCOUT ⎟ ⎠ ⎝ Where f = operating frequency, COUT = output capacitance, and ∆IL= ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. With ∆IL = 0.3IOUT(MAX) the output ripple will typically be less than 50mV at max V IN assuming: COUT Recommended ESR < 2 RSENSE and COUT > 1/(8fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric 3727lx1fa 15 LTC3727LX-1 APPLICATIO S I FOR ATIO capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have lower storage capacity per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPS Series III or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 1.2mm to 4.1mm. Aluminum electrolytic capacitors can be used in costdriven applications providing that consideration is given to ripple current ratings, temperature and long term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Cornell Dubilier ESRE and Sprague 595D series. Consult manufacturers for other specific recommendations. INTVCC Regulator An internal P-channel low dropout regulator produces 7.5V at the INTVCC pin from the VIN supply pin. INTVCC powers the drivers and internal circuitry within the LTC3727LX-1. The INTVCC pin regulator can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7µF tantalum, 10µF special polymer, or low ESR type electrolytic capacitor. A 1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly recommended. Good bypassing is necessary to supply the high transient currents required 16 U by the MOSFET gate drivers and to prevent interaction between channels. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3727LX-1 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional external loading of the INTVCC and 3.3V linear regulators also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 7.5V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 7.3V, all of the INTVCC current is supplied by the internal 7.5V linear regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC), and overall efficiency is lowered. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3727LX-1 VIN current is limited to less than 24mA from a 24V supply when not using the EXTVCC pin as follows: TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70°C + (24mA)(7.5V)(95°C/W) = 87°C Dissipation should be calculated to also include any added current drawn from the internal 3.3V linear regulator. To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. EXTVCC Connection The LTC3727LX-1 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 7.3V, the internal regulator is turned off and the switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal power. The switch remains closed as long as the voltage applied to EXTVCC remains above 7.0V. This allows the MOSFET driver and control power to be derived from the output during normal opera3727lx1fa W UU LTC3727LX-1 APPLICATIO S I FOR ATIO tion (7.2V < VOUT < 8.5V) and from the internal regulator when the output is out of regulation (start-up, shortcircuit). If more current is required through the EXTVCC switch than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply greater than 8.5V to the EXTVCC pin and ensure that EXTVCC < VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 7.5V regulators this supply means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 7.5V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected directly to VOUT. This is the normal connection for a 7.5V regulator and provides the highest efficiency. 3. EXTVCC Connected to an External supply. If an external supply is available in the 7.5V to 8.5V range, it may be VIN OPTIONAL EXTVCC CONNECTION 7.5V < VSEC < 8.5V VIN LTC3727LX-1 TG1 RSENSE VOUT EXTVCC R6 FCB R5 SGND PGND 3727LX1 F06 + CIN VSEC N-CH SW T1 1:N BG1 N-CH Figure 6. Secondary Output Loop & EXTVCC Connection U used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 7.5V. This can be done with the inductive boost winding as shown in Figure 6. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the functional diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Output Voltage + 1µF W UU + COUT The LTC3727LX-1 output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor. The resultant feedback signal is compared with the internal precision 0.800V voltage reference by the error amplifier. The output voltage is given by the equation: ⎛ R2 ⎞ VOUT = 0 . 8 V ⎜ 1 + ⎟ ⎝ R1⎠ where R1 and R2 are defined in Figure 2. 3727lx1fa 17 LTC3727LX-1 APPLICATIO S I FOR ATIO SENSE+/SENSE– Pins The common mode input range of the current comparator sense pins is from 0V to 14V. Continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8V to 14V. A differential NPN input stage is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This requires that current either be sourced or sunk from the SENSE pins depending on the output voltage. If the output voltage is below 2.4V current will flow out of both SENSE pins to the main output. The output can be easily preloaded by the VOUT resistive divider to compensate for the current comparator’s negative input bias current. The maximum current flowing out of each pair of SENSE pins is: ISENSE+ + ISENSE– = (2.4V – VOUT)/24k Since VOSENSE is servoed to the 0.8V reference voltage, we can choose R1 in Figure 2 to have a maximum value to absorb this current. ⎛ 0 . 8V R1(MAX ) = 24k ⎜ ⎝ 2 . 4V – V for VOUT < 2.4V OUT ⎞ ⎟ ⎠ (7a) Regulating an output voltage of 1.8V, the maximum value of R1 should be 32K. Note that for an output voltage above 2.4V, R1 has no maximum value necessary to absorb the sense currents; however, R1 is still bounded by the VOSENSE feedback current. Soft-Start/Run Function The RUN/SS1 and RUN/SS2 pins are multipurpose pins that provide a soft-start function and a means to shut down the LTC3727LX-1. Soft-start reduces the input power source’s surge currents by gradually increasing the controller’s current limit (proportional to VITH). This pin can also be used for power supply sequencing. An internal 1.2µA current source charges up the CSS capacitor. When the voltage on RUN/SS1 (RUN/SS2) reaches 1.5V, the particular controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 45mV/ RSENSE to 135mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.25s/µF to reach full 18 U current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: t DELAY = tIRAMP = 1 . 5V C SS = (1 . 25s / µ F ) C SS 1 . 2µ A 3V − 1 . 5V C SS = (1 . 25s / µ F ) C SS 1 . 2µ A W UU By pulling both RUN/SS pins below 1V, the LTC3727LX-1 is put into low current shutdown (IQ = 20µA). The RUN/SS pins can be driven directly from logic as shown in Figure 7. Diode D1 in Figure 7 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. Each RUN/SS pin has an internal 6V zener clamp (See Functional Diagram). 3.3V OR 5V D1 CSS CSS 3727LX1 F07 RUN/SS RUN/SS (7b) Figure 7. RUN/SS Pin Interfacing Fault Conditions: Current Limit and Current Foldback The LTC3727LX-1 current comparator has a maximum sense voltage of 135mV resulting in a maximum MOSFET current of 135mV/RSENSE. The maximum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the highest power dissipation in the top MOSFET. The LTC3727LX-1 includes current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is overridden. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 135mV to 45mV. Under short-circuit conditions with very low duty cycles, the LTC3727LX-1 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short3727lx1fa LTC3727LX-1 APPLICATIO S I FOR ATIO circuit ripple current is determined by the minimum ontime tON(MIN) of the LTC3727LX-1 (less than 200ns), the input voltage and inductor value: ∆IL(SC) = tON(MIN) (VIN/L) The resulting short-circuit current is: ISC = 45mV 1 + ∆ IL(SC) R SENSE 2 Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor PC layout to function while the design is being debugged. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Phase-Locked Loop and Frequency Synchronization The LTC3727LX-1 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ± 50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 380kHz. The nominal operating frequency range of the LTC3727LX-1 is 250kHz to 550kHz. U The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC: ∆fH = ∆fC = ± 0.5 fO (250kHz-550kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC3727LX-1 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple LTC3727LX-1s for a phaselocked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A DC voltage of 0.7V to 1.7V applied to the master oscillator’s PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency can range from 310kHz to 470kHz. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to 0.1µF. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3727LX-1 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty 3727lx1fa W UU 19 LTC3727LX-1 APPLICATIO S I FOR ATIO cycle applications may approach this minimum on-time limit and care should be taken to ensure that V t ON(MIN) < OUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3727LX-1 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3727LX-1 is generally less than 200ns. However, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger inductor current and output voltage ripple. FCB Pin Operation The FCB pin can be used to regulate a secondary winding or as a logic level input. Continuous operation is forced on both controllers when the FCB pin drops below 0.8V. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom, synchronous switch is on. When primary load currents are low and/or the VIN/VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in Figure 6 by the turns ratio N of the transformer: VSEC ≅ (N + 1) VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from 20 U VSEC to the FCB pin sets a minimum voltage VSEC(MIN): W UU ⎛ R6 ⎞ VSEC(MIN) ≅ 0 . 8 V ⎜ 1 + ⎟ ⎝ R5 ⎠ where R5 and R6 are shown in Figure 2. If VSEC drops below this level, the FCB voltage forces temporary continuous switching operation until VSEC is again above its minimum. In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.18µA internal current source pulling the pin high. Include this current when choosing resistor values R5 and R6. The following table summarizes the possible states available on the FCB pin: Table 2 FCB PIN 0V to 0.75V CONDITION Forced Continuous Both Controllers (Current Reversal Allowed— Burst Inhibited) Minimum Peak Current Induces Burst Mode Operation No Current Reversal Allowed Regulating a Secondary Winding Burst Mode Operation Disabled Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current 0.85V < VFCB < 6.0V Feedback Resistors >7.3V Voltage Positioning Voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step specifications. Voltage positioning can easily be added to the LTC3727LX-1 by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage range of the error amplifier, or 1.2V (see Figure 8). The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A 3727lx1fa LTC3727LX-1 APPLICATIO S I FOR ATIO complete explanation is included in Design Solutions 10 (see www.linear.com). INTVCC RT2 ITH RT1 RC CC 3727LX1 F08 LTC3727LX-1 Figure 8. Active Voltage Positioning Applied to the LTC3727LX-1 Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3727LX-1 circuits: 1) LTC3727LX-1 VIN current (including loading on the 3.3V internal regulator), 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the 3.3V linear regulator output. VIN current typically results in a small (1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from Hell. The main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator 3727lx1fa W UU LTC3727LX-1 APPLICATIO S I FOR ATIO can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 9 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC3727LX-1 has a maximum input voltage of 32V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V VIN LTC3727LX-1 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 3727LX1 F09 Figure 9. Automotive Application Protection Design Example As a design example for one channel, assume VIN = 24V(nominal), VIN = 30V(max), VOUT = 12V, IMAX = 5A and f = 250kHz. The inductance value is chosen first based on a 40% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFLTR pin to the SGND pin for 250kHz operation. The minimum inductance for 40% ripple current is: ∆ IL = ⎞ VOUT ⎛ V 1 – OUT ⎟ ( f)(L) ⎜ VIN ⎠ ⎝ A 14µH inductor will result in 40% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 6A, for the 14µH value. U The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: W UU R SENSE ≤ 90mV ≈ 0 . 015Ω 6A Choosing 1% resistors; R1 = 20k and R2 = 280k yields an output voltage of 12V. The power dissipation on the top side MOSFET can be easily estimated. Choosing a Siliconix Si4412DY results in: RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input voltage with T(estimated) = 50°C: 12V 2 (5) [1+ (0 . 005)(50 °C – 25 °C)] 30 V PMAIN = (0 . 042Ω) + 1 . 7 (30V )2 (5A )(100pF )(250kHz ) = 664mW A short-circuit to ground will result in a folded back current of: ISC = 45mV 1 ⎛ 200ns(30 V) ⎞ = 3 . 2A +⎜ ⎠ 0 . 015Ω 2 ⎝ 14µ H ⎟ with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is: PSYNC = 30 V – 12V (3 . 2A )2 (1 . 1) (0 . 042Ω) 30 V = 284mW which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) = 0.02Ω(2A) = 40mVP–P 3727lx1fa 23 LTC3727LX-1 APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3727LX-1. These items are also illustrated graphically in the layout diagram of Figure 10; Figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. Are the signal and power grounds kept separate? The combined LTC3727LX-1 signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output 1 2 3 4 5 fIN 6 7 RUN/SS1 SENSE1 + SENSE1 – VOSENSE1 PLLFLTR PLLIN FCB PGOOD TG1 SW1 BOOST1 VIN BG1 R2 R1 INTVCC + 22 EXTVCC LTC3727LX-1 21 8 ITH1 INTVCC 9 10 11 12 SGND 3.3VOUT ITH2 VOSENSE2 SENSE2 – SENSE2 + PGND BG2 BOOST2 SW2 TG2 RUN/SS2 20 19 18 17 16 15 + 3.3V R3 R4 13 14 Figure 10. LTC3727LX-1 Recommended Printed Circuit Layout Diagram 3727lx1fa 24 U capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Do the LTC3727LX-1 VOSENSE pins resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The R2 and R4 connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE – should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current RPU 28 27 26 25 24 23 RIN CIN CVIN VIN GND COUT1 CB1 M1 M2 D1 PGOOD L1 VOUT1 RSENSE VPULL-UP (