LTC3785EUF-1-TRPBF

FEATURES n n n n n n n n n n n n n LTC3785-1 10V, High Efficiency, Buck-Boost Controller with Power Good DESCRIPTION The LTC®3785-1 is a high power synchronous buck-boost controller that drives all N-channel power MOSFETs from input voltages above, below and equal to the output voltage. With an input range of 2.7V to 10V, the LTC3785-1 is well suited for a wide variety of single or dual cell Li-Ion or multi-cell alkaline/NiMH applications. The operating frequency can be programmed from 100kHz to 1MHz. The soft-start time and current limit are also programmable. The soft-start capacitor doubles as the fault timer which can program the IC to latch off or recycle after a determined off time. Burst Mode operation is user controlled and can be enabled by driving the MODE pin high. The LTC3785-1 includes a Power Good output that indicates when the output voltage is within 7.5% of its designed setpoint. Protection features include foldback current limit, short-circuit and overvoltage protection. , LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Single Inductor Architecture Allows VIN Above, Below or Equal to VOUT Power Good Output Indicator 2.7V to 10V Input and Output Range Up to 96% Efficiency Up to 10A of Output Current All N-Channel MOSFETs, No RSENSETM True Output Disconnect During Shutdown Programmable Current Limit and Soft-Start Optional Short-Circuit Shutdown Timer Output Overvoltage and Undervoltage Protection Programmable Frequency: 100kHz to 1MHz Selectable Burst Mode® Operation Available in 24-Lead (4mm × 4mm) Exposed Pad QFN Package APPLICATIONS n n n n Palmtop Computers Handheld Instruments Wireless Modems Cellular Telephones TYPICAL APPLICATION VOUT VIN VCC 215k 1.3k 270pF FB 127k 1nF VC RT 49.9k MODE PGOOD RUN/SS ILSET 2.2nF 42.2k CCM GND TG2 D VBST2 SW2 ISSW2 BG2 C 37851 TA01a 4.7μF VIN 2.7V TO 10V 100 22μF Efficiency vs Input Voltage VOUT = 3.3V FOSC = 500kHz ISVIN VSENSE TG1 A 0.22μF SW1 ISSW1 VDRV BG1 LTC3785-1 ISVOUT EFFICIENCY (%) VBST1 95 215k 127k ILOAD = 2A ILOAD = 1A 90 12k 4.7μH B VOUT 3.3V 5A 85 2.5 4 5.5 VIN (V) 7 8.5 10 37851 TA01b 0.22μF 100μF 37851f 1 LTC3785-1 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW VBST1 ISVIN SW1 18 ISSW1 17 BG1 25 16 VDRV 15 BG2 14 ISSW2 13 SW2 7 RT 8 MODE 9 10 11 12 ISVOUT VBST2 PGOOD TG2 TG1 VCC VIN RUN/SS 1 VC 2 FB 3 VSENSE 4 ILSET 5 CCM 6 Input Supply Voltage (VIN) ......................... –0.3V to 11V ISVOUT, ISVIN .............................................. –0.3V to 11V SW1, SW2, ISSW1, ISSW2 Voltage: DC............................................................. –1V to 11V Pulsed, 2V ISSW2 to ISVOUT, CCM < 0.4V ISVIN ISVOUT ISSW1, ISSW2 l MIN TYP 800 0.7 1.9 –1 1 60 105 –110 –15 80 10 0.1 MAX UNITS μA V V μA μA mV mV mV mV μA μA μA V V μA V μA μs kHz % % Ω Ω ns ns ns ns ns ns 0.35 1.1 5 100 155 –170 –35 150 20 5 0.4 1 2.2 1 l l l l 20 55 –50 CCM Input Threshold (High) CCM Input Threshold (Low) CCM Input Current Burst Mode Operation Mode Threshold Mode Input Current tON Time Oscillator Frequency Accuracy Switching Characteristics Maximum Duty Cycle TG1, TG2 Driver Impedance BG1, BG2 Driver Impedance TG1, TG2 Rise Time BG1, BG2 Rise Time TG1, TG2 Fall Time BG1, BG2 Fall Time Buck Driver Nonoverlap Time Boost Driver Nonoverlap Time Power Good Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold Overvoltage Hysteresis PGOOD Output Low PGOOD Leakage VSENSE Input Current l l 2.2 0.01 l 0.8 1.5 0.01 1.4 509 90 99 2 2 20 20 20 20 100 100 –7.5 1.5 7.5 –2 200 1 l 370 80 650 Boost (% Switch BG2 On) Buck (% Switch TG1 On) l CLOAD = 3300pF (Note 3) CLOAD = 3300pF (Note 3) CLOAD = 3300pF (Note 3) CLOAD = 3300pF (Note 3) TG1 to BG1 TG2 to BG2 VSENSE Falling, % Below FB Regulation Voltage VSENSE Rising % Above FB Regulation Voltage, MODE = 0V IPGOOD = 500μA VPGOOD = 5.5V VSENSE = Measured FB Voltage –5 5 –10.5 10.5 % % % % mV μA nA 500 5 500 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3785E-1 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Specification is guaranteed by design and not 100% tested in production. Note 4: Current measurements are performed when the outputs are not switching. Note 5: The IC is tested in a feedback loop to make the measurement. 37851f 3 LTC3785-1 TYPICAL PERFORMANCE CHARACTERISTICS Li-Ion to 3.3V Efficiency vs Load Current 100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.0001 0.001 VIN = 4.2V VIN = 3.6V VIN = 3V MOSFET Si7940 L = 4.7μH WURTH WE-PD fOSC = 500kHz 0.1 0.01 LOAD CURRENT (A) 1 10 37851 G01 Two Li-Ion to 7V Efficiency vs Load Current 100 100 Burst Mode OPERATION 90 80 FIXED FREQUENCY EFFICIENCY (%) 70 60 50 40 30 20 10 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 VIN = 8.4V VIN = 7.2V VIN = 5.4V MOSFET Si7940 L = 5.6μH MSS1260 fOSC = 430kHz 0.01 0.1 LOAD CURRENT (A) 1 10 37851 G02 Li-Ion/9V to 5V VOUT Efficiency vs Load Current Burst Mode OPERATION Burst Mode OPERATION FIXED FREQUENCY FIXED FREQUENCY VIN = 9V VIN = 4.2V VIN = 3.6V VIN = 2.7V MOSFET Si7940 L = 5.6μH MSS1260 fOSC = 430kHz 0.001 0.01 0.1 LOAD CURRENT (A) 1 10 37851 G03 0 0.0001 Burst Mode Ripple VOUT 500mV/ DIV VIN 3V TO 8.5V Line Transient Response VOUT 200mV/ DIV VOUT Load Transient VOUT 50mV/DIV AC COUPLED INDUCTOR CURRENT 1A/DIV VOUT = 3.3V COUT = 100μF 5μs/DIV 37851 G04 ILOAD = 300μA VOUT = 5V COUT = 100μF 500μs/DIV 37851 G05 ILOAD 10mA TO 2A VIN = 3.6V VOUT = 3.3V COUT = 100μF 100μs/DIV 37851 G06 VFB vs Temperature 1.2255 1.2250 CHANGE FROM 25°C (%) 1.2245 1.2240 VFB (V) 1.2235 1.2230 1.2225 1.2220 1.2215 1.2210 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 37851 G07 Normalized Oscillator Frequency vs Temperature 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –50 0 –25 25 50 0 TEMPERATURE (°C) 75 100 OSCILLATOR FREQUENCY (kHz) 1000 800 600 400 200 1200 Oscillator Frequency vs RT 20 40 60 RT (kΩ) 80 100 37851 G09 37851 G08 37851f 4 LTC3785-1 TYPICAL PERFORMANCE CHARACTERISTICS VIN Start-Up Voltage vs Temperature 2.490 100 VIN Burst Quiescent Current vs Temperature 8 6 OV and UV Thresholds vs Temperature OV THRESHOLD VIN START-UP VOLTAGE (V) 2.485 VIN CURRENT (mA) 95 THRESHOLD (%) 4 2 0 –2 –4 –6 UV THRESHOLD –25 25 50 0 TEMPERATURE (°C) 75 100 2.480 90 2.475 85 2.470 2.465 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 80 –50 –25 25 50 0 TEMPERATURE (°C) 75 100 –8 –50 37851 G10 37851 G11 37851 G12 PIN FUNCTIONS RUN/SS (Pin 1): Run Control and Soft-Start Input. An internal 1μA charges the soft-start capacitor and will charge to approximately 2.5V. During a current limit fault, the soft-start capacitor will incrementally discharge. Once the pin drops below 1.225V the IC will enter fault mode, turning off the outputs for 32 times the soft-start time. If >5μA (at RUN/SS = 1.225V) is applied externally, the part will latch off after a fault is detected. If >40μA (at RUN/SS = 1.225V) is applied externally, current limit faults will not discharge the SS capacitor. VC (Pin 2): Error Amp Output. A frequency compensation network is connected from this pin to the FB pin to compensate the loop. See the section “Closing the Feedback Loop” for guidelines. FB (Pin 3): Feedback Pin. Connect resistor divider tap here. The feedback reference voltage is typically 1.225V The output voltage can be adjusted from 2.7V to 10V according to the following formula: VOUT = 1.225V • R1+ R2 R2 VSENSE (Pin 4): Overvoltage and Undervoltage Sense. The overvoltage threshold is internally set 7.5% above the regulated FB voltage and the undervoltage threshold is internally set 7.5% below the FB regulated voltage. This pin can be tied to FB but to optimize the response time it is recommended that a separate voltage divider from VOUT be applied. The divider can be skewed from the feedback value to achieve the desired UV or OV threshold. ILSET (Pin 5): Current Limit Set. A resistor from this pin to ground sets the current limit threshold from the ISVIN and ISSW1 pins. CCM (Pin 6): Continuous Conduction Mode Control Pin. When set low, the inductor current is allowed to go slightly negative (–15mV referenced to the ISVOUT – ISSW2 pins). When driven high, the reverse current limit is set to the similar value of the forward current limit set by the ILSET pin. RT (Pin 7): Oscillator Programming Pin. A resistor from this pin to GND sets the free-running frequency of the IC. fOSC ≅ 2.5e10/RT. 37851f 5 LTC3785-1 PIN FUNCTIONS MODE (Pin 8): Burst Mode Control Pin. • MODE = High: Enable Burst Mode Operation. In Burst Mode operation the operation is variable frequency, which provides a significant efficiency improvement at light loads. The Burst Mode operation will continue until the pin is driven low. • MODE = Low: Disable Burst Mode operation and maintain low noise, constant frequency operation. PGOOD (Pin 9): Open drain output. PGOOD is pulled to ground when the voltage on VSENSE is not within ±7.5% of its setpoint. PGOOD will also be pulled low when the part is in shutdown or input UVLO. ISVOUT (Pin 10): Reverse Current Limit Comparator Noninverting Input. This pin is normally connected to the drain of the N-channel MOSFET D (TG2 driven). VBST2 (Pin 11): Boosted Floating Driver Supply for Boost Switch D. This pin will swing from a diode below VCC up to VOUT + VCC – VDIODE. SW2 (Pin 13): Ground Reference for Driver D. Gate drive from TG2 will reference to the common point of output switches C and D. ISSW2 (Pin 14): Reverse Current Limit Comparator Inverting Input. This pin is normally connected to the source of the N-channel MOSFET D (TG2 driven). VDRV (Pin 16): Driver Supply for Ground Referenced Switches. Connect this pin to VCC potential. BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive the ground referenced N-channel MOSFET switches B and C. ISSW1 (Pin 18): Forward Current Limit Comparator Noninverting Input. This pin is normally connected to the source of the N-channel MOSFET A (TG1 driven). SW1 (Pin 19): Ground Reference for Driver A. Gate drive from TG1 will reference to the common point of output switches A and B. TG1, TG2 (Pins 20, 12): Top gate drive pins drive the top N-channel MOSFET switches A and D with a voltage swing equal to VCC – VDIODE superimposed on the SW1 and SW2 nodes respectively. VBST1 (Pin 21): Boosted Floating Driver Supply for the Buck Switch A. This pin will swing from a diode below VCC up to VIN + VCC – VDIODE. ISVIN (Pin 22): Forward Current Limit Comparator Inverting Input. This pin is normally connected to the drain of N-channel MOSFET A (TG1 driven). VCC (Pin 23): Internal 4.5V LDO Regulator Output. The driver and control circuits are powered from this voltage to limit the maximum VGS drive voltage. Decouple this pin to power ground with at least a 4.7μF ceramic capacitor. For low VIN applications, VCC can be bootstrapped from VOUT through a Schottky diode. VIN (Pin 24): Input Supply Pin for the VCC Regulator. A ceramic capacitor of at least 10μF is recommended close to the VIN and GND pins. Exposed Pad (Pin 25): The GND and PGND pins are connected to the Exposed Pad which must be connected to the PCB ground for electrical contact and rated thermal performance. 37851f 6 LTC3785-1 BLOCK DIAGRAM VIN 2.7V TO 10V 24 1.225V VIN TSD 1.225V VREF 4.5V REG IDEAL DIODE 2.4V ILIMIT 1/25k 100% DUTY CHARGE PUMP VCC ISVIN 23 22 CVCC + – + – 1μA 2μA OSC FAULT LOGIC VBE RUN UVLO + – CSS 1 gm RUN/SS + – V = 60k/RILSET ADRV ILIM(OUT) ILIM(OUT) 10μA MAX IMAX TG1 20 21 CA 19 18 16 17 MB D1 OPT MA CIN + – V = 90k/RILSET BBM SW1 DELAY TG1 BG1 + X10 – SAMPLED VBST1 SW1 ISSW1 VDRV BG1 SW1 –7.5% VOUT 7.5% 4 VOUT R1 R2 CP1 3 2 RT 7 1.225V FB VC VSENSE + – – + UV SW1 PULSE UV BDRV OV SW2 PULSE REVERSE LIMIT RT REVERSE CURRENT LIMIT (ZERO LIMIT FOR BURST) DDRV 1 = Burst Mode OPERATION 0 = FIXED FREQUENCY BURST LOGIC BURST SAMPLED VDRV SS 1.5V 8 MODE RILSET 5 ILSET ILIMIT SET ILIM COMP IMAX COMP UV OV SD UVLO CDRV PGND VREV PGOOD 9 GND/PGND 25 0 = 15mV 1 = ILIMIT 1/2 LIMIT AT VOUT < 1V – + + – BBM SW2 DELAY TG2 BG2 DISABLE 15mV OR 1X ILIMIT VREV TG2 VBST2 11 SW2 ISSW2 CB 13 14 SW2 + – OV VOUT LOW 1.8V PGND 100% DUTY CHARGE PUMP L1 ISVOUT 10 D2 OPT 12 MD VOUT + – BG2 15 MC COUT CCM 6 37851 BD 37851f 7 LTC3785-1 OPERATION MAIN CONTROL LOOP The LTC3785-1 is a buck-boost voltage mode controller that provides an output voltage above, equal to or below the input voltage. The LTC proprietary topology and control architecture also employs drain-to-source sensing (No RSENSE) for forward and reverse current limiting. The controller provides all N-channel MOSFET output switch drive, facilitating single package multiple power switch technology along with lower RDS(ON). The error amp output voltage (VC) determines the output duty cycle of the switches. Since the VC pin is a filtered signal, it provides rejection of high frequency noise. The FB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the error amplifier. The top MOSFET drivers are biased from a floating bootstrap capacitor, which is normally recharged during each off cycle through an external diode when the top MOSFET turns off. Optional Schottky diodes can be connected across synchronous switch B and D to provide a lower drop during the dead time and eliminate efficiency loss due to body diode reverse recovery. The main control loop is shut down by pulling the RUN/ SS pin low. An internal 1μA current source charges the RUN/SS pin and when the pin voltage is higher than 0.7V the IC is enabled. The VC voltage is then clamped to the RUN/SS voltage minus 0.7V while CSS is slowly charged during start-up. This “soft-start” clamping prevents inrush current draw from the input power supply. POWER SWITCH CONTROL Figure 1 shows a simplified diagram of how the four power switches are connected to the inductor, VIN, VOUT and GND. Figure 2 shows the regions of operation for the LTC3785-1 as a function of duty cycle D. The power switches are properly controlled so that the transfer between modes is continuous. Buck Region (VIN > VOUT) Switch D is always on and switch C is always off during buck mode. When the error amp output voltage, VC, is approximately above 0.1V, output A begins to switch. During the off time of switch A, synchronous switch B turns on for TG1 VIN VOUT A SW1 BG1 B L SW2 C 37851 F01 D TG2 BG2 Figure 1. Response Time Test Circuit 90% DMAX BOOST A ON, B OFF PWM C, D SWITCHES DMIN BOOST DMAX BUCK FOUR SWITCH PWM D ON, C OFF PWM A, B SWITCHES DMIN BUCK BUCK/BOOST REGION BOOST REGION BUCK REGION 37851 F02 Figure 1. Response Time Test Circuit the remainder of the switching period. Switches A and B will alternate similar to a typical synchronous buck regulator. As the control voltage increases, the duty cycle of switch A increases until the max duty cycle of the converter in buck mode reaches DMAX_BUCK, given by: DMAX_BUCK = 100 – D4(SW)% where D4(SW) = duty cycle % of the four switch range. D4(SW) = (300ns • f) • 100% where f = operating frequency, Hz. Beyond this point the “four switch” or buck-boost region is reached. Buck-Boost or Four Switch (VIN ~ VOUT) When the error amp output voltage, VC, is above approximately 0.65V, switch pair AD remain on for duty cycle DMAX_BUCK, and the switch pair AC begin to phase in. As switch pair AC phases in, switch pair BD phases out accordingly. When the VC voltage reaches the edge of the buck-boost range, approximately 0.7V, the AC switch pair completely phase out the BD pair, and the boost phase begins at duty cycle, D4(SW). 37851f 8 LTC3785-1 OPERATION The input voltage, VIN, where the four switch region begins is given by: VIN = VOUT V 1 – 300ns • f In Burst Mode operation the maximum output current is given by: IOUT(MAX,BURST ) ≈ 1.2 • VIN  A f • L • VOUT + VIN ( ) ( ) the point at which the four switch region ends is given by: VIN = VOUT(1 – D) = VOUT(1 – 300ns • f) V Boost Region (VIN < VOUT) Switch A is always on and switch B is always off during boost mode. When the error amp output voltage, VC, is approximately above 0.7V, switch pair C and D will alternately switch to provide a boosted output voltage. This operation is typical to a synchronous boost regulator. The maximum duty cycle of the converter is limited to 90% typical. Burst Mode OPERATION During Burst Mode operation, the LTC3785-1 delivers energy to the output until it is regulated and then goes into a sleep state where the outputs are off and the IC is consuming only 86μA. In Burst Mode operation, the output ripple has a variable frequency component, which is dependent upon load current During the period where the converter is delivering energy to the output, the inductor will reach a peak current determined by an on time, tON, and will terminate at zero current for each cycle. The on time is given by: tON = 2.4 VIN • f Burst Mode operation is user-controlled by driving the MODE pin high to enable and low to disable. VCC REGULATOR An internal P-channel low dropout regulator produces 4.35V at the VCC pin from the VIN supply pin. VCC powers the drivers and internal circuitry of the LTC3785-1. The VCC pin regulator can supply a peak current of 100mA and must be bypassed to ground with a minimum of 4.7μF placed directly adjacent to the VCC and GND pins. Good bypassing is necessary to supply the high transient current required by the MOSFET gate drivers and to prevent interaction between channels. If desired, the VCC regulator can be connected to VOUT through a Schottky diode to provide higher gate drive in low input voltage applications. The VCC regulator can also be driven with an external 5V source directly (without a Schottky diode). TOPSIDE MOSFET DRIVER SUPPLY (VBST1, VBST2) The external bootstrap capacitors connected to the VBST1 and VBST2 pins supply the gate drive voltage for the topside MOSFET switches A and D. When the top MOSFET switch A turns on, the switch node SW1 rises to VIN and the VBST2 pin rises to approximately VIN + VCC. When the bottom MOSFET switch B turns on, the switch node SW1 drops low and the boost capacitor is charged through the diode connected to VCC. When the top MOSFET switch D turns on, the switch node SW2 rises to VOUT and the VBST2 pin rises to approximately VOUT + VCC. When the bottom MOSFET switch C turns on, the switch node SW2 drops low and the boost capacitor is charged through the diode connected to VCC. The boost capacitors need to store about 100 times the gate charge required by the top MOSFET switch A and D. In most applications a 0.1μF to 0.47μF , X5R or X7R dielectric capacitor is adequate. where f is the oscillator frequency. The peak current is given by: IPEAK = IPEAK = VIN • tON L 2.4 f •L So the peak current is independent of VIN and inversely proportional to the f • L product optimizing the energy transfer for various applications. 37851f 9 LTC3785-1 OPERATION RUN/SOFT-START (RUN/SS) The RUN/SS pin serves as the enable to the LTC3785-1, soft-start function, and fault programming. A 1μA current source charges the external capacitor. Once the RUN/SS voltage is above a diode drop(~0.7V) the IC is enabled. Once the IC is enabled, the RUN/SS voltage minus a diode drop (RUN/SS – 0.7V) clamps the output of the error amp (VC) to limit duty cycle. The range of the duty cycle clamping is approximately 0.7V to 1.7V. The RUN/SS pin is clamped to approximately 2.2V. If current limit is reached the pin will begin to discharge with a current determined by the magnitude of inductor current overcurrent limit, but not to exceed 10μA. This function will be described in more detail in the “Forward Current Limit” section. OSCILLATOR The frequency of operation is set through a resistor from the RT pin to ground where f ≅ (2.5e10/RT)Hz. ERROR AMP The error amplifier is a voltage mode amplifier with a reference voltage of 1.225V internally connected to the non-inverting input. The loop compensation components are configured around the amplifier to provide loop compensation for the converter. The RUN/SS pin will clamp the error amp output, VC, to provide a soft-start function. UNDERVOLTAGE AND OVERVOLTAGE PROTECTION The LTC3785-1 incorporates overvoltage (OV) and undervoltage (UV) functions for fault protection and transient limitation. Both comparators are connected to the VSENSE pin, which usually has a similar voltage divider as the error amplifier without the compensation. The overvoltage threshold is 7.5% above the reference. The undervoltage threshold is 7.5% below the reference with both comparators having 1% hysteresis. During an overvoltage fault, all output switching stops until the fault ceases. During an undervoltage fault, the IC is commanded to run fixed frequency only (disabled Burst Mode operation). If the design requires a tightened threshold to one of the comparator thresholds the voltage divider on the VSENSE pin can be skewed to achieve the threshold. Since the range is a constant, tightening the UV threshold will loosen the OV threshold and vice versa. POWER GOOD COMPARATOR The PGOOD pin is an open-drain output which indicates the status of the buck-boost converter output. The output voltage is monitored at VSENSE via a resistor divider tap from VOUT to GND. The values used for this resistor divider are typically selected to be the same as those used in the error amplifier feedback divider. If the voltage on VSENSE either falls 7.5% below (UV condition) or rises 7.5% above (OV condition) the regulation voltage, the PGOOD open-drain output will pull low signaling the output is out of regulation. Once an out of regulation condition is triggered, the voltage on VSENSE must rise 1.5% above the UV threshold or fall 2% below the OV threshold before the pull-down will turn off. In addition, there is a 15μs deglitch delay to help prevent false trips due to voltage transients caused by line or load steps. Depending upon the application, this delay may be insufficient. A capacitor can be placed from VSENSE to GND to add additional deglitch filtering, ensuring PGOOD doesn’t trip during a transient. The PGOOD output will also pull low during shutdown and input undervoltage lockout to indicate these fault conditions. FORWARD CURRENT LIMIT The LTC3785-1 is designed to sense the input current by sampling the voltage across MOSFET A during the on time of the switch (TG1 = High). The sense pins are ISVIN and ISSW1. A current sense resistor can be used if increased accuracy is required. The current limit threshold can be programmed with a resistor on the ILSET pin. Once the desired current limit has been chosen, RILSET can be determined by the following formula: 6000 RILSET =  Ω RDS(ON)A • ILIMIT where RDS(ON)A = RDS(ON) of N-channel MOSFET switch A and ILIMIT = current limit in Amps. Once the voltage between ISVIN and ISSW1 exceeds the threshold, current will be sourced out of FB to take control 37851f 10 LTC3785-1 OPERATION of the voltage loop, resulting in a lower output voltage to regulate the input current. This fault condition causes the RUN/SS capacitor to begin discharging. The level of the discharge current depends on how much the current exceeds the programmed threshold. Figure 3 is a simplified diagram of the current sense and fault circuitry. If the current limit fault duration is long enough to discharge the RUN/SS capacitor below 1.225V, the fault latch is set and will cycle the RUN/SS capacitor 16 times (1μA charging and 1μA discharging of the RUN/SS capacitor) to create an off time of 32 times the soft-start time before the outputs are allowed to switch to restart the output voltage. If the current limit fault level exceeds 150% of the programmed ILIMIT level at any time, the IMAX comparator is tripped and output switches B and D are turned on to discharge the inductor current for the remainder of the cycle. To have the power converter latch-off on a fault, a pull-up current between 4μA and 7μA on the RUN/SS pin will allow the RUN/SS capacitor to discharge during an extended fault, but will prevent cycling of the fault which will cause the converter to stay off. One method to implement this is by THERMAL SD 1.225V placing a diode (anode tied to VOUT) and a resistor from VOUT to the RUN/SS pin. The current sourced into RUN/SS will be VOUT – 0.7 divided by the resistor value. To ignore all faults source greater than 40μA into the RUN/SS pin (At 1.225V on the RUN/SS pin). Since the maximum fault current is limited, this will prevent any discharging of the RUN/SS capacitor, the soft-start capacitor will need to be sized accordingly to accommodate the extra charging current at start-up. During an output short-circuit or if VOUT is less than 1.8V, the current limit folds back to 50% of the programmed level. REVERSE CURRENT LIMIT The LTC3785-1 can be programmed to provide full class D operation or allowed to source and sink current equal to the current limit set value. This is achieved by asserting a high level on the CCM pin. To minimize the reverse output current, the CCM pin should be driven low or strapped to ground. During this mode only, –15mV typical is allowed across output switch D and is sensed with the ISVOUT and ISSW2 pins. + – + – S FAULT S LOGIC ILIMIT COMP gm = 1/20k 0.7V RUN V = 60k/RILSET (15k/RILSET WHEN VOUT < 1.8V) IMAX COMP TURN SWITCHES B AND D ON + gm – ISVIN VIN 22 A TG1 20 1μA 1 CSS RUN/SS 2.2V 2μA 1/3 • ILIM(OUT) 10μA MAX SW1 19 + – V = 90k/RILSET + X10 – SAMPLED ISSW1 18 BG1 17 CCM = HIGH = 6k/RILSET CCM 6 CCM = LOW = 15mV B L1 4 VOUT R1 CP1 3 2 R2 FB VC 1.225V ILIM(OUT) 30μA MAX SWITCH D OFF – + ISVOUT + – ERROR AMP REVERSE CURRENT LIMIT 5 RILSET ILSET ILIMIT SET ILIM COMP IMAX COMP Figure 3. Block Diagram of Current Limit Fault Circuitry 37851f – + 10 D VOUT COUT TG2 12 SW2 13 SAMPLED ISSW2 14 C 37851 F03 BG2 15 11 LTC3785-1 APPLICATIONS INFORMATION INDUCTOR SELECTION The high frequency operation of the LTC3785-1 allows the use of small surface mount inductors. The inductor current ripple is typically set 20% to 40% of the maximum inductor current. For a given ripple the inductance terms are given as follows: L> VIN(MIN)2 • VOUT – VIN(MIN) • 100 f • IOUT(MAX ) • %Ripple • VOUT2 VOUT • VIN(MAX ) – VOUT • 100 f • IOUT(MAX ) • %Ripple • VIN(MAX ) This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. In boost mode, the discontinuous current shifts from the input to the output, so COUT must be capable of reducing the output voltage ripple. The effects of ESR (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The steady ripple due to charging and discharging the bulk capacitance is given by: VRIPPLE _ BOOST = IOUT(MAX ) • VOUT – VIN(MIN) COUT • VOUT • f VOUT • VIN(MAX ) – VOUT ( ) , (Boost  Mode) L> ( ) , (Buck  Mode) where: f = Operating frequency, Hz %Ripple = Allowable inductor current ripple, % VIN(MIN) = Minimum input voltage (limit to VOUT/2 minimum for worst case), V VIN(MAX) = Maximum input voltage, V VOUT = Output voltage, V IOUT(MAX) = Maximum output load current, A For high efficiency choose an inductor with a high frequency core material, such as ferrite, to reduce core loses. The inductor should have low ESR (equivalent series resistance) to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. Molded chokes or chip inductors usually do not have enough core to support the peak inductor currents in the 3A to 6A region. To minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. CIN AND COUT SELECTION In boost mode, input current is continuous. In buck mode, input current is discontinuous. In buck mode, the selection of input capacitor, CIN, is driven by the need to filter the input square wave current. Use a low ESR capacitor, sized to handle the maximum RMS current. For buck operation, the maximum RMS capacitor current is given by: IRMS ~ IOUT(MAX ) • VOUT VIN ⎛V⎞ • ⎜ 1 – OUT ⎟ VIN ⎠ ⎝ ( ) VRIPPLE _ BUCK = 8 • L • COUT • VIN(MAX ) • f2 ( ) where COUT= output filter capacitor, F The steady ripple due to the voltage drop across the ESR is given by: ΔVBOOST,ESR = IL(MAX,BOOST) • ESR ΔVBUCK,ESR = L • f • VIN ( VIN(MAX) – VOUT ) • VOUT • ESR Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient. Capacitors are now available with low ESR and high ripple current ratings such as OS-CON and POSCAP . POWER N-CHANNEL MOSFET SELECTION AND EFFICIENCY CONSIDERATIONS The LTC3785-1 requires four external N-channel power MOSFETs, two for the top switches (switches A and D, shown in Figure 1) and two for the bottom switches 37851f 12 LTC3785-1 APPLICATIONS INFORMATION (switches B and C shown in Figure 1). Important parameters for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The drive voltage is set by the 4.35V VCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3785-1 applications. If the input voltage is expected to drop below 5V, then sub-logic threshold MOSFETs should be considered. In order to select the power MOSFETs, the power dissipated by the device must be known. For switch A, the maximum power dissipation happens in boost mode, when it remains on all the time. Its maximum power dissipation at maximum output current is given by: ⎛V ⎞ PA(BOOST) = ⎜ OUT • IOUT(MAX )⎟ • ρT • RDS(ON) ⎝V ⎠ IN 2 Switch C operates in boost mode as the control switch. Its power dissipation at maximum current is given by: PC(BOOST) = ( VOUT – VIN) • VOUT • I VIN2 2 OUT(MAX ) • ρT • RDS(ON) + k • VOUT 3 • IOUT(MAX ) VIN • CRSS • f where CRSS is usually specified by the MOSFET manufacturers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.0. For switch D, the maximum power dissipation happens in boost mode when its duty cycle is higher than 50%. Its maximum power dissipation at maximum output current is given by: V PD (BOOST ) = OUT • IOUT(MAX )2 • ρT • RDS(ON) VIN Typically, switch A has the highest power dissipation and switch B has the lowest power dissipation unless a short occurs at the output. From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + P • RTH(JA) The RTH(JA) to be used in the equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(CA)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. SCHOTTKY DIODE (D1, D2) SELECTION where ρT is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C as shown in Figure 4. For a maximum junction temperature of 125°C, using a value ρT = 1.5 is reasonable. Switch B operates in buck mode as the synchronous rectifier. Its power dissipation at maximum output current is given by: PB(BUCK) = 2.0 T NORMALIZED ON-RESISTANCE VIN – VOUT • IOUT(MAX )2 • ρT • RDS(ON) VIN 1.5 1.0 0.5 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 37851 F04 Figure 4. Normalized RDS(ON) vs Temperature Optional Schottky diodes D1 and D2 shown in the Block Diagram conduct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diode of synchronous switches B and D from turning on and storing charge during the dead time. In particular, D2 significantly reduces reverse recovery current between switch D turn off and switch C turn on, which improves converter efficiency and reduces switch C voltage stress. In order for D2 to be effective, it must be located in very close proximity to SWD. 37851f 13 LTC3785-1 APPLICATIONS INFORMATION CLOSING THE FEEDBACK LOOP The LTC3785-1 incorporates voltage mode control. The control to output gain is given by: GBuck = 1.6 • VIN, Buck  Mode GBOOST = 1.6 • VOUT 2 , Boost  Mode VIN The unity gain frequency of the error amplifier with the type 1 compensation is given by: fUG = 1 2 • π • R1 • CP1 The output filter exhibits a double-pole response and is given by: fFILTER _ POLE = 1 2 • π • L • COUT Most applications demand an improved transient response to allow a smaller output filter capacitor. To achieve a higher bandwidth, type III compensation is required as shown in Figure 6. Two zeros are required to compensate for the double pole response. fPOLE1 ≈ f ZERO1 = f ZERO2 = fPOLE2 ≈ 1  (a   very  low   frequency) 2 • π • 32e3 • CP1 • R1 1 2 • π • RZ • CP1 1 2 • π • R1 • C Z1 1 2 • π • RZ • C P2 VOUT where COUT is the output filter capacitor. The output filter zero is given by: fFILTER _ ZERO = 1 2 • π • RESR • COUT where RESR is the capacitor equivalent series resistance. A troublesome feature in boost mode is the right half plane zero (RHP), and is given by: VIN2 fRHPZ = 2 • π • IOUT • L • VOUT The loop gain is typically rolled off before the RHP zero frequency. A simple type I compensation network (Figure 5) can be incorporated to stabilize the loop but at a cost of reduced bandwidth and slower transient response. To ensure proper phase margin, the loop must cross over almost a decade before the L-C double pole. + ERROR AMP 1.225V FB CP1 VOUT R1 + ERROR AMP 1.225V R1 FB CP1 CP2 37851 F06 CZ1 – VC RZ R2 Figure 6. Error Amplifier with Type III Compensation EFFICIENCY CONSIDERATIONS The percentage efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuits produce losses, four main sources account for most of the losses in LTC3785-1 application circuits: 37851f – VC R2 37851 F05 Figure 5. Error Amplifier with Type I Compensation 14 LTC3785-1 APPLICATIONS INFORMATION 1. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor (if used), inductor and PC board traces and cause the efficiency to drop at high output currents. 2. Transition loss. This loss arises from the brief voltage transition time of switch A or switch C. It depends upon the switch voltage, inductor current, driver strength and MOSFET capacitance, among other factors. Transition Loss ~ VSW2 • IL • CRSS • f where CRSS is the reverse transfer capacitance. 3. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator in buck mode. The output capacitor has the more difficult job of filtering the large RMS output current in boost mode. Both CIN and COUT are required to have low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 4. Other losses. Optional Schottky diodes D1 and D2 are responsible for conduction losses during dead time and light load conduction periods. Core loss is the predominant inductor loss at light loads. Turning on switch C causes reverse recovery current loss in boost mode. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. 5. VCC regulator loss. In applications where the input voltage is above 5V, such as two Li-Ion cells, the VCC regulator will dissipate some power due the differential voltage and the average output current to the drive the gates of the output switches. The VCC pin can be driven directly from a high efficiency external 5V source if desired to incrementally improve overall efficiency at lighter loads. DESIGN EXAMPLE As a design example, assume VIN = 2.7V to 10V (3.6V nominal Li-Ion with 9V adapter), VOUT = 3.3V (5%), IOUT(MAX) = 3A and f = 500kHz. Determine the Inductor Value Setting the Inductor Ripple to 40% and using the equations in the Inductor Selection section gives: 500 • 103 • 3 • 40 • 10 So the worst-case ripple for this application is during buck mode so a standard inductor value of 3.3μH is chosen. Determine the Proper Inductor Type Selection The highest inductor current is during boost mode and is given by: IL(MAX _ AV ) = VOUT • IOUT VIN • η (2.7)2 • (3.3 – 2.7) • 100 = 0.67μH L> 2 500 • 103 • 3 • 40 • ( 3.3) 3.3 • (10 – 3.3) • 100 L> = 3.7μH where η = estimated efficiency in this mode (use 80%). IL(MAX _ AV ) = 3.3 • 3 = 4.6 A 2.7 • 0.8 To limit the maximum efficiency loss of the inductor ESR to below 5% the equation is: ESRL(MAX ) ~ VOUT • IOUT • %Loss IL(MAX _ AV )2 • 100 = 24mΩ A suitable inductor for this application could be a Coiltronics CD1-3R8 which has a rating DC current of 6A and ESR of 13mΩ. Choose a Proper MOSFET Switch Using the same guidelines for ESR of the inductor, one suitable MOSFET could be the Siliconix Si7940DP which is a dual MOSFET in a surface mount package with 25mΩ at 2.5V and a total gate charge of 12nC. Checking the power dissipation of each switch will ensure reliable operation since the thermal resistance of the package is 60°C/W. 37851f 15 LTC3785-1 APPLICATIONS INFORMATION The maximum power dissipation of switch A and C occurs in boost mode. Assuming a junction temperature of TJ = 100°C with ρ100C = 1.3, the power dissipation at VIN = 2.7, and using the equations from the Efficiency Considerations section: ⎛ 3.3 ⎞ PA(BOOST) = ⎜ • 3  • 1.3 • 0.025 = 0.43W ⎝ 2.7 ⎟ ⎠ PC(BOOST) = 2 The maximum current is set 25% above IL(PEAK) to account for worst-case variation at 100°C = 6A. RILSET = 6000 = 42k 0.025 • 6 Choose the Input and Output Capacitance The input capacitance should filter current ripple which is worst case in buck mode. Since the input current could reach 6A, a capacitor ESR of 10mΩ or less will yield an input ripple of 60mV. The output capacitance should filter current ripple which is worst in boost mode, but is usually dictated by the loop response, the maximum load transient and the allowable transient response. PC BOARD LAYOUT CHECKLIST The basic PC board layout requires a dedicated ground plane layer. Also, for high current, a multilayer board provides heat sinking for power components. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Place CIN, switch A, switch B and D1 in one compact area. Place COUT, switch C, switch D and D2 in one compact area. • Use immediate vias to connect the components (including the LTC3785-1’s GND/PGND pin) to the ground plane. Use several large vias for each power component. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (VIN or GND). When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3785-1. (3.3 – 2.7) • 3.3 • 32 • 1.3 • 0.025 2 . 72 +  1 • 3.33 • = 0.09 W 3 • 0.45 – 9 • 500 • 103 2.7 The maximum power dissipation of switch B and D occurs in buck mode and is given by: 10 – 3.3 2 PB(BUCK) = • 3 • 1.3 • 0.025 = 0.20 W 10 PD(BOOST) = 3.3 2 • 3 • 1.3 • 0.025 = 0.10 W 10 Now to double check the TJ of the package with 50°C ambient. Since this is a dual NMOS package we can add switches A + B and C + D worst case. For applications where the MOSFETs are in separate packages each device’s maximum TJ would have to be calculated. TJ(PKG1) = TA + θJA(PA + PB) = 50 + 60 • (0.43 + 0.20) = 88°C TJ(PKG2) = TA + θJA(PC + PD) = 50 + 60 • (0.09 + 0.10) = 60°C Set The Maximum Current Limit The equation for setting the maximum current limit of the IC is given by: RILSET = 6000  Ω RDS(ON)A • ILIMIT 37851f 16 LTC3785-1 APPLICATIONS INFORMATION • Segregate the signal and power grounds. All small-signal components should return to the GND pin at one point. The sources of switch B and switch C should also connect to one point at the GND of the IC. • Place switch B and switch C as close to the controller as possible, keeping the PGND, BG and SW traces short. • Keep the high dV/dT SW1, SW2, VBST1, VBST2, TG1 and TG2 nodes away from sensitive small-signal nodes. • The path formed by switch A, switch B, D1 and the CIN capacitor should have short leads and PC trace lengths. The path formed by switch C, switch D, D2 and the COUT capacitor also should have short leads and PC trace lengths. • The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor. • Connect the VCC decoupling capacitor CVCC closely to the VCC and PGND pins. • Connect the top driver boost capacitor CA closely to the VBST1 and SW1 pins. Connect the top driver boost capacitor CB closely to the VBST2 and SW2 pins. • Connect the input capacitors CIN and output capacitors COUT close to the power MOSFETs. These capacitors carry the MOSFET AC current in boost and buck mode. • Connect FB and VSENSE pin resistive dividers to the (+) terminals of COUT and signal ground. If a small VSENSE decoupling capacitor is used, it should be as close as possible to the LTC3785-1 GND pin. • Route ISVIN and ISSW1 leads together with minimum PC trace spacing. Ensure accurate current sensing with Kelvin connections across MOSFET A or sense resistor. • Route ISVOUT and ISSW2 leads together with minimum PC trace spacing. Ensure accurate current sensing with Kelvin connections across MOSFET D or sense resistor. • Connect the feedback network close to IC, between the VC and FB pins. 37851f 17 LTC3785-1 TYPICAL APPLICATION VIN 2.7V TO 10V CVCC 4.7μF VCC ISVIN VSENSE 270pF R1 205k R2 124k 1.3k TG1 CMDSH-3 VBST1 SW1 ISSW1 VDRV FB BG1 LTC3785-1 VC RT RT 59k VOUT RILSET 42.2k ILSET CCM GND 100k PGOOD MODE VBST2 SW2 ISSW2 BG2 CMDSH-3 CB 0.22μF COUT 100μF D2 ISVOUT TG2 MD OPTIONAL VOUT 3.3V 3A CA 0.22μF OPTIONAL MB D1 MA CIN 22μF MA = MB = MC = MD = 1/2 Si7940DY L1 = WÜRTH ELECTRONICS 744311470 D1 = D2 = PMEG2020EJ 9V REGULATED WALL ADAPTER + 1nF VIN RUN/SS Li-Ion 2.7V TO 4.2V 124k 205k 12k 1nF L1 4.7μH MC 37851 TA02 37851f 18 LTC3785-1 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 0.05 4.50 0.05 3.10 2.45 0.05 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD 0.75 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 45° CHAMFER 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 23 24 0.40 1 2 0.10 2.45 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 37851f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3785-1 TYPICAL APPLICATION Li-Ion/9V Wall Adapter to 5V/2A VIN 2.7V TO 10V CVCC 4.7μF VCC ISVIN VSENSE 270pF 205k 1.3k TG1 CMDSH-3 VBST1 SW1 ISSW1 VDRV FB BG1 LTC3785-1 VC 59k 100k PGOOD CMDSH-3 MODE 42.2k ILSET CCM GND VBST2 SW2 ISSW2 BG2 MC CB 0.22μF COUT 100μF D2 RT ISVOUT TG2 MD OPTIONAL VOUT 5V 2A CA 0.22μF OPTIONAL MB D1 L1 3.3μH MA CIN 22μF MA = MB = MC = MD = 1/2 Si7940DY L1 = RLF7030T-3R3M4R1 D1 = D2 = PMEG2020EJ 9V REGULATED WALL ADAPTER + 1nF VIN RUN/SS Li-Ion 2.7V TO 4.2V 66.5k 205k 66.5k 12k 1nF VOUT 37851 TA03 RELATED PARTS PART NUMBER LTC3443 LTC3444 LTC3531 LTC3531-3 LTC3531-3.3 LTC3532 LTC3533 LTC3780 LTC3785 LTM4605 LTM4607 DESCRIPTION 1.2A IOUT, 600kHz, Synchronous Buck-Boost DC/DC Converter 500mA IOUT, 1.5MHz Synchronous Buck-Boost DC/DC Converter 200mA IOUT, Synchronous Buck-Boost DC/DC Converter COMMENTS VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 28μA, ISD < 1μA, MS Package VIN: 2.7V to 5.5V, VOUT: 0.5V to 5.25V, Optimized for WCDMA RF Amplifier Bias VIN: 1.8V to 5.5V, VOUT: 2V to 5V, IQ = 35μA, ISD < 1μA, MS, DFN Packages VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 35μA, ISD < 1μA, MS, DFN Packages 500mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter 2A Wide Input Voltage Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40μA, ISD < 1μA, DFN Package High Efficiency, Synchronous, 4-Switch Buck-Boost Controller 10V, High Efficiency, Synchronous, No RSENSE, Buck-Boost Controller 5A to 12A Buck-Boost μModule 5A to 12A Buck-Boost μModule VIN: 4V to 36V, VOUT: 0.8V to 30V, IQ = 1.5mA, ISD < 55μA, SSOP-24, QFN-32 Packages VIN: 2.7V to 10V, VOUT: 2.7V to 10V, IQ = 86mA, ISD < 15μA, QFN-24 Package 4.5V ≤ VIN ≤ 20V, 0.8V ≤ VOUT ≤ 16V, 15mm × 15mm × 2.8mm LGA Package 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 24V, 15mm × 15mm × 2.8mm LGA Package 37851f LT 0908 • PRINTED IN USA 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008