LTC3809EDD-TRPBF

FEATURES n n n n n n n n n n n n n n LTC3809 No RSENSE™, Low EMI, Synchronous DC/DC Controller DESCRIPTION The LTC®3809 is a synchronous step-down switching regulator controller that drives external complementary power MOSFETs using few external components. The constant frequency current mode architecture with MOSFET VDS sensing eliminates the need for a current sense resistor and improves efficiency. For noise sensitive applications, the LTC3809 can be externally synchronized from 250kHz to 750kHz. Burst Mode is inhibited during synchronization or when the SYNC/MODE pin is pulled low to reduce noise and RF interference. To further reduce EMI, the LTC3809 incorporates a novel spread spectrum frequency modulation technique. Burst Mode operation provides high efficiency operation at light loads. 100% duty cycle provides low dropout operation, extending operating time in battery-powered systems. The switching frequency can be programmed up to 750kHz, allowing the use of small surface mount inductors and capacitors. The LTC3809 is available in tiny footprint thermally enhanced DFN and 10-lead MSOP packages. L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6580258, 6304066, 5847554, 6611131, 6498466. Other Patents pending. No Current Sense Resistor Required Selectable Spread Spectrum Frequency Modulation for Low Noise Operation Constant Frequency Current Mode Operation for Excellent Line and Load Transient Response True PLL for Frequency Locking or Adjustment (Frequency Range: 250kHz to 750kHz) Wide VIN Range: 2.75V to 9.8V Wide VOUT Range: 0.6V to VIN 0.6V ±1.5% Reference Low Dropout Operation: 100% Duty Cycle Selectable Burst Mode®/Pulse-Skipping/Forced Continuous Operation Auxiliary Winding Regulation Internal Soft-Start Circuitry Output Overvoltage Protection Micropower Shutdown: IQ = 9μA Tiny Thermally Enhanced Leadless (3mm × 3mm) DFN and 10-lead MSOP Packages APPLICATIONS n n n 1- or 2-Cell Lithium-Ion Powered Devices Portable Instruments Distributed DC Power Systems TYPICAL APPLICATION High Efficiency, 550kHz Step-Down Converter 10μF VIN TG 2.2μH 15k 187k 470pF VFB ITH RUN GND SW BG IPRG 47μF VOUT 2.5V 2A VIN 2.75V TO 9.8V Efficiency and Power Loss vs Load Current 100 EFFICIENCY 90 EFFICIENCY (%) VIN = 3.3V VIN = 5V 80 POWER LOSS VIN = 4.2V VIN = 4.2V 100 1k POWER LOSS (mW) 10k LTC3809 PLLLPF SYNC/MODE 59k 70 10 60 FIGURE 10 CIRCUIT VOUT = 2.5V 1 10 100 1000 LOAD CURRENT (mA) 1 50 0.1 10000 3809 TA01 3809 TA01b 3809fc 1 LTC3809 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN) ........................ –0.3V to 10V PLLLPF, RUN, SYNC/MODE, IPRG Voltages ............................... –0.3V to (VIN + 0.3V) VFB , ITH Voltages ...................................... –0.3V to 2.4V SW Voltage ......................... –2V to VIN + 1V (10V Max) TG, BG Peak Output Current ( fSYNC/MODE fOSC < fSYNC/MODE Minimum Switching Frequency Maximum Switching Frequency SYNC/MODE = 2.2V 480 260 650 550 300 750 200 1000 –3 3 460 635 2.6 600 340 825 250 kHz kHz kHz kHz kHz μA μA kHz kHz μA CL = 3000pF CL = 3000pF CL = 3000pF CL = 3000pF IPRG = Floating (Note 6) IPRG = 0V (Note 6) IPRG = VIN (Note 6) Time for VFB to Ramp from 0.05V to 0.55V l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted. CONDITIONS (Note 4) RUN = 0V VIN = UVLO Threshold – 200mV VIN Falling VIN Rising (Note 5) 2.75V < VIN < 9.8V (Note 5) ITH = 0.9V (Note 5) ITH = 1.7V (Note 5) Measured at VFB 0.66 0.325 l l l MIN TYP MAX UNITS 350 105 9 3 1.95 2.15 0.8 0.591 2.25 2.45 1.1 0.6 0.01 0.1 –0.1 9 0.68 20 0.4 40 40 50 40 110 70 185 0.5 125 85 204 0.74 500 150 20 10 2.55 2.75 1.4 0.609 0.04 0.5 –0.5 50 0.7 0.475 μA μA μA μA V V V V %/V % % nA V mV V ns ns ns ns 140 100 223 0.9 mV mV mV ms Phase-Locked Loop Lock Range 750 Phase Detector Output Current Sinking Sourcing Spread Spectrum Frequency Range SYNC/MODE Pull-Down Current Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3809E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 85°C operating range are assured by design characterization, and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA °C/W) Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: The LTC3809 is tested in a feedback loop that servos ITH to a specified voltage and measures the resultant VFB voltage. Note 6: Peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in Figure 1. 3809fc 3 LTC3809 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted. Efficiency vs Load Current 100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 1 SYNC/MODE = VIN VIN = 5V 10 100 1k LOAD CURRENT (mA) 10k 3809 G01 Efficiency vs Load Current 100 FIGURE 10 CIRCUIT 95 VIN = 5V, VOUT = 2.5V 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 1 10 100 1k LOAD CURRENT (mA) 10k 3809 G02 Maximum Current Sense Voltage vs ITH Pin Voltage 100 80 CURRENT LIMIT (%) 60 40 20 0 –20 Burst Mode OPERATION (ITH RISING) Burst Mode OPERATION (ITH FALLING) FORCED CONTINUOUS MODE PULSE SKIPPING MODE FIGURE 10 CIRCUIT VOUT = 3.3V VOUT = 2.5V VOUT = 1.2V VOUT = 1.8V BURST MODE (SYNC/MODE = VIN) FORCED CONTINUOUS (SYNC/MODE = 0V) PULSE SKIPPING (SYNC/MODE = 0.6V) 0.5 1 1.5 ITH VOLTAGE (V) 2 3809 G03 Load Step (Burst Mode Operation) VOUT 200mV/DIV AC COUPLED VOUT 200mV/DIV AC COUPLED Load Step (Forced Continuous Mode) IL 2A/DIV IL 2A/DIV 100μs/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 300mA TO 3A SYNC/MODE = VIN FIGURE 10 CIRCUIT 3809 G04 100μs/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 300mA TO 3A SYNC/MODE = 0V FIGURE 10 CIRCUIT 3809 G05 Load Step (Pulse-Skipping Mode) VOUT 200mV/DIV AC COUPLED Start-Up with Internal Soft-Start VOUT 1.8V 500mV/DIV IL 2A/DIV 100μs/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 300mA TO 3A SYNC/MODE = VFB FIGURE 10 CIRCUIT 3809 G06 200μs/DIV VIN = 4.2V RLOAD = 1Ω FIGURE 10 CIRCUIT 3809 G07 3809fc 4 LTC3809 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted. Regulated Feedback Voltage vs Temperature 0.606 0.604 FEEDBACK VOLTAGE (V) INPUT VOLTAGE (V) 0.602 0.600 0.598 0.596 0.594 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 2.55 2.50 2.45 2.40 2.35 2.30 VIN FALLING 2.25 2.20 80 100 2.15 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 1.00 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 RUN VOLTAGE (V) VIN RISING 1.15 Undervoltage Lockout Threshold vs Temperature 1.20 Shutdown (RUN) Threshold vs Temperature 1.10 1.05 3809 G08 3809 G09 3809 G10 Maximum Current Sense Threshold vs Temperature MAXIMUM CURRENT SENSE THRESHOLD (mV) 135 SYNC/MODE PULL-DOWN CURRENT (μA) IPRG = FLOAT 2.80 2.75 SYNC/MODE Pull-Down Current vs Temperature 10 8 NORMALIZED FREQUENCY (%) 100 6 4 2 0 –2 –4 –6 –8 80 Oscillator Frequency vs Temperature 130 2.70 2.65 2.60 2.55 2.50 2.45 2.40 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 125 120 115 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 –10 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 3809 G11 3809 G12 3809 G13 Oscillator Frequency vs Input Voltage 5 NORMALIZED FREQUENCY SHIFT (%) 4 SHUTDOWN CURRENT (μA) 3 2 1 0 –1 –2 –3 –4 –5 2 3 4 7 8 5 6 INPUT VOLTAGE (V) 9 10 18 16 Shutdown Quiescent Current vs Input Voltage 130 120 14 12 10 8 6 4 80 2 0 2 3 4 8 7 6 5 INPUT VOLTAGE (V) 70 9 10 SLEEP CURRENT (μA) 110 100 90 Sleep Current vs Input Voltage 2 3 4 7 8 5 6 INPUT VOLTAGE (V) 9 10 3809 G14 3809 G15 3809 G16 3809fc 5 LTC3809 PIN FUNCTIONS PLLLPF (Pin 1): Frequency Set/PLL Lowpass Filter. When synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. Normally, a series RC is connected between this pin and ground. When not synchronizing to an external clock, this pin serves as the frequency select input. Tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. Connect a 2.2nF capacitor between this pin and GND, and a 1000pF capacitor between this pin and the SYNC/MODE when using spread spectrum modulation operation. SYNC/MODE (Pin 2): This pin performs four functions: 1) auxiliary winding feedback input, 2) external clock synchronization input for phase-locked loop, 3) Burst Mode, pulse-skipping or forced continuous mode select, and 4) enable spread spectrum modulation operation in pulse-skipping mode. Applying a clock with frequency between 250kHz to 750kHz causes the internal oscillator to phase-lock to the external clock and disables Burst Mode operation but allows pulse-skipping at low load currents. To select Burst Mode operation at light loads, tie this pin to VIN . Grounding this pin selects forced continuous operation, which allows the inductor current to reverse. Tying this pin to VFB selects pulse-skipping mode. In these cases, the frequency of the internal oscillator is set by the voltage on the PLLLPF pin. Tying to a voltage between 1.35V to VIN – 0.5V enables spread spectrum modulation operation. In this case, an internal 2.6μA pull-down current source helps to set the voltage at this pin by tying a resistor with appropriate value between this pin and VIN. Do not leave this pin floating. VFB (Pin 3): Feedback Pin. This pin receives the remotely sensed feedback voltage for the controller from an external resistor divider across the output. ITH (Pin 4): Current Threshold and Error Amplifier Compensation Point. Nominal operating range on this pin is from 0.7V to 2V. The voltage on this pin determines the threshold of the main current comparator. RUN (Pin 5): Run Control Input. Forcing this pin below 1.1V shuts down the chip. Driving this pin to VIN or releasing this pin enables the chip to start-up with the internal soft-start. IPRG (Pin 6): Three-State Pin to Select Maximum Peak Sense Voltage Threshold. This pin selects the maximum allowed voltage drop between the VIN and SW pins (i.e., the maximum allowed drop across the external P-channel MOSFET). Tie to VIN, GND or float to select 204mV, 85mV or 125mV respectively. BG (Pin 7): Bottom (NMOS) Gate Drive Output. This pin drives the gate of the external N-channel MOSFET. This pin has an output swing from PGND to VIN. TG (Pin 8): Top (PMOS) Gate Drive Output. This pin drives the gate of the external P-channel MOSFET. This pin has an output swing from PGND to VIN. VIN (Pin 9): Chip Signal Power Supply. This pin powers the entire chip, the gate drivers and serves as the positive input to the differential current comparator. SW (Pin 10): Switch Node Connection to Inductor. This pin is also the negative input to the differential current comparator and an input to the reverse current comparator. Normally this pin is connected to the drain of the external P-channel MOSFET, the drain of the external N-channel MOSFET and the inductor. GND (Pin 11): Exposed Pad. The Exposed Pad is ground and must be soldered to the PCB ground for electrical contact and optimum thermal performance. 3809fc 6 LTC3809 FUNCTIONAL DIAGRAM VIN CIN 9 VIN VOLTAGE REFERENCE VREF 0.6V SLOPE 6 IPRG + UNDERVOLTAGE LOCKOUT VIN VIN 0.7μA 5 RUN VIN t = 1ms INTERNAL SOFT-START 11 GND 0.3V SYNC/MODE BURST DEFEAT 2 0.4V 2.6μA CLOCK DETECT BURSTDIS FCB PHASE DETECTOR 0.15V UVSD SENSE+ ICMP CLK S Q R SWITCHING LOGIC AND BLANKING CIRCUIT GND ANTI-SHOOTTHROUGH PVIN 8 TG MP – 10 SW L VOUT COUT 7 BG MN + – FCB SLEEP OV IREV BURSTDIS + – + UV 0.68V RB 0.54V SS – + – + EAMP + – VFB 4 VREF 0.6V SS 3 VFB RA ITH RC CC 1 PLLLPF VCO CLK 3809 FD + IREV RICMP SW – GND 3809fc 7 LTC3809 OPERATION (Refer to Functional Diagram) Main Control Loop The LTC3809 uses a constant frequency, current mode architecture. During normal operation, the top external P-channel power MOSFET is turned on when the clock sets the RS latch, and is turned off when the current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is determined by the voltage on the ITH pin, which is driven by the output of the error amplifier (EAMP). The VFB pin receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to the internal 0.6V reference voltage by the EAMP. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top P-channel MOSFET is off, the bottom N-channel MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next cycle. Shutdown and Soft-Start (RUN Pin) The LTC3809 is shut down by pulling the RUN pin low. In shutdown, all controller functions are disabled and the chip draws only 9μA. The TG output is held high (off) and the BG output low (off) in shutdown. Releasing the RUN pin allows an internal 0.7μA current source to pull up the RUN pin to VIN. The controller is enabled when the RUN pin reaches 1.1V. The start-up of VOUT is controlled by the LTC3809’s internal soft-start. During soft-start, the error amplifier EAMP compares the feedback signal VFB to the internal soft-start ramp (instead of the 0.6V reference), which rises linearly from 0V to 0.6V in about 1ms. This allows the output voltage to rise smoothly from 0V to its final value while maintaining control of the inductor current. Light Load Operation (Burst Mode Operation, Continuous Conduction or Pulse-Skipping Mode) (SYNC/MODE Pin) The LTC3809 can be programmed for either high efficiency Burst Mode operation, forced continuous conduction mode or pulse-skipping mode at low load currents. To select Burst Mode operation, tie the SYNC/MODE pin to VIN. To select forced continuous operation, tie the SYNC/MODE pin to a DC voltage below 0.4V (e.g., GND). Tying the SYNC/MODE to a DC voltage above 0.4V and below 1.2V (e.g., VFB) enables pulse-skipping mode. The 0.4V threshold between forced continuous operation and pulse-skipping mode can be used in secondary winding regulation as described in the Auxiliary Winding Control Using SYNC/MODE Pin discussion in the Applications Information section. When the LTC3809 is in Burst Mode operation, the peak current in the inductor is set to approximately one-fourth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the EAMP will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.85V, the internal SLEEP signal goes high and the external MOSFET is turned off. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3809 draws. The load current is supplied by the output capacitor. As the output voltage decreases, the EAMP increases the ITH voltage. When the ITH voltage reaches 0.925V, the SLEEP signal goes low and the controller resumes normal operation by turning on the external P-channel MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode or pulseskipping operation, the inductor current is not allowed to reverse. Hence, the controller operates discontinuously. 3809fc 8 LTC3809 OPERATION (Refer to Functional Diagram) The reverse current comparator RICMP senses the drain-tosource voltage of the bottom external N-channel MOSFET. This MOSFET is turned off just before the inductor current reaches zero, preventing it from going negative. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. The P-channel MOSFET is turned on every cycle (constant frequency) regardless of the ITH pin voltage. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and no noise at audio frequencies. When the SYNC/MODE pin is clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop), or is set to a DC voltage between 0.4V and several hundred mV below VIN, the LTC3809 operates in PWM pulse-skipping mode at light loads. In this mode, the current comparator ICMP may remain tripped for several cycles and force the external P-channel MOSFET to stay off for the same number of cycles. The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. However, it provides low current efficiency higher than forced continuous mode, but not nearly as high as Burst Mode operation. During start-up or an undervoltage condition (VFB ≤ 0.54V), the LTC3809 operates in pulse-skipping mode (no current reversal allowed), regardless of the state of the SYNC/MODE pin. Short-Circuit and Current Limit Protection The LTC3809 monitors the voltage drop ΔVSC (between the GND and SW pins) across the external N-channel MOSFET with the short-circuit current limit comparator. The allowed voltage is determined by: ΔVSC(MAX) = A • 90mV where A is a constant determined by the state of the IPRG pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN selects A = 5/3; tying IPRG to GND selects A = 2/3. The inductor current limit for short-circuit protection is determined by ΔVSC(MAX) and the on-resistance of the external N-channel MOSFET: ISC = ΔVSC(MAX) RDS(ON) Once the inductor current exceeds ISC, the short current comparator will shut off the external P-channel MOSFET until the inductor current drops below ISC. Output Overvoltage Protection As further protection, the overvoltage comparator (OVP) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. When the feedback voltage on the VFB pin has risen 13.33% above the reference voltage of 0.6V, the external P-channel MOSFET is turned off and the N-channel MOSFET is turned on until the overvoltage is cleared. 3809fc 9 LTC3809 OPERATION (Refer to Functional Diagram) Frequency Selection and Phase-Locked Loop (PLLLPF and SYNC/MODE Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3809’s controllers can be selected using the PLLLPF pin. If the SYNC/MODE is not being driven by an external clock source, the PLLLPF can be floated, tied to VIN or tied to GND to select 550kHz, 750kHz or 300kHz, respectively. A phase-locked loop (PLL) is available on the LTC3809 to synchronize the internal oscillator to an external clock source that connects to the SYNC/MODE pin. In this case, a series RC should be connected between the PLLLPF pin and GND to serve as the PLL’s loop filter. The LTC3809 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of the external P-channel MOSFET to the rising edge of the synchronizing signal. The typical capture range of the LTC3809’s phase-locked loop is from approximately 200kHz to 1MHz. Spread Spectrum Modulation (SYNC/MODE and PLLLPF Pins) Connecting the SYNC/MODE pin to a DC voltage above 1.35V and several hundred mV below VIN enables spread spectrum modulation (SSM) operation. An internal 2.6μA pull-down current source at SYNC/MODE helps to set the voltage at the SYNC/MODE pin for this operation by tying a resistor with appropriate value between SYNC/MODE and VIN. This mode of operation spreads the internal oscillator frequency fOSC (= 550kHz) over a wider range (460kHz to 635kHz), reducing the peaks of the harmonic output on a spectral analysis of the output noise. In this case, a 2.2nF filter cap should be connected between the PLLLPF pin and GND and another 1000pF cap should be connected between PLLLPF and the SYNC/MODE pin. The controller operates in PWM pulse-skipping mode at light loads when spread spectrum modulation is selected. See the discussion of Spread Spectrum Modulation with SYNC/MODE and PLLLPF Pins in the Applications Information section. Dropout Operation When the input supply voltage (VIN) approaches the output voltage, the rate of change of the inductor current while the external P-channel MOSFET is on (ON cycle) decreases. This reduction means that the P-channel MOSFET will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the EAMP on the ITH pin. Further reduction in the input supply voltage will eventually cause the P-channel MOSFET to be turned on 100%; i.e., DC. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. Undervoltage Lockout To prevent operation of the P-channel MOSFET below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3809. When the input supply voltage (VIN) drops below 2.25V, the external P- and N-channel MOSFETs and all internal circuits are turned off except for the undervoltage block, which draws only a few microamperes. 3809fc 10 LTC3809 OPERATION (Refer to Functional Diagram) Peak Current Sense Voltage Selection and Slope Compensation (IPRG Pin) When the LTC3809 controller is operating below 20% duty cycle, the peak current sense voltage (between the VIN and SW pins) allowed across the external P-channel MOSFET is determined by: ΔVSENSE(MAX) = A • VITH – 0.7 V 10 maximum sense voltage allowed across the external Pchannel MOSFET is 125mV, 85mV or 204mV for the three respective states of the IPRG pin. However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor (SF) given by the curve in Figure 1. The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel MOSFET: IPK = ΔVSENSE(MAX) RDS(ON) where A is a constant determined by the state of the IPRG pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN selects A = 5/3; tying IPRG to GND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the 110 100 90 80 SF = I/IMAX (%) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3809 F01 Figure 1. Maximum Peak Current vs Duty Cycle 3809fc 11 LTC3809 APPLICATIONS INFORMATION The typical LTC3809 application circuit is shown in Figure 10. External component selection for the controller is driven by the load requirement and begins with the selection of the inductor and the power MOSFETs. Power MOSFET Selection The LTC3809’s controller requires two external power MOSFETs: a P-channel MOSFET for the topside (main) switch and a N-channel MOSFET for the bottom (synchronous) switch. The main selection criteria for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS, turn-off delay tD(OFF) and the total gate charge QG. The gate drive voltage is the input supply voltage. Since the LTC3809 is designed for operation down to low input voltages, a sublogic level MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required for applications that work close to this voltage. When these MOSFETs are used, make sure that the input supply to the LTC3809 is less than the absolute maximum MOSFET VGS rating, which is typically 8V. The P-channel MOSFET’s on-resistance is chosen based on the required load current. The maximum average load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE. The LTC3809’s current comparator monitors the drain-tosource voltage VDS of the top P-channel MOSFET, which is sensed between the VIN and SW pins. The peak inductor current is limited by the current threshold, set by the voltage on the ITH pin, of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ΔVSENSE(MAX) to approximately 125mV when IPRG is floating (85mV when IPRG is tied low; 204mV when IPRG is tied high). The output current that the LTC3809 can provide is given by: IOUT(MAX) = ΔVSENSE(MAX) IRIPPLE – RDS(ON) 2 where IRIPPLE is the inductor peak-to-peak ripple current (see Inductor Value Calculation). A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: RDS(ON)MAX = 5 ΔVSENSE(MAX) • for Duty Cycle < 20% 6 IOUT(MAX) However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current: RDS(ON)MAX = ΔVSENSE(MAX) 5 • SF • 6 IOUT(MAX) where SF is a scale factor whose value is obtained from the curve in Figure 1. These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3809 and external component values: RDS(ON)MAX = ΔVSENSE(MAX) 5 • 0.9 • SF • 6 IOUT(MAX) • ρT The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 2. Junction-to-case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in the above equation is a reasonable choice. The N-channel MOSFET’s on resistance is chosen based on the short-circuit current limit (ISC). The LTC3809’s short-circuit current limit comparator monitors the drainto-source voltage VDS of the bottom N-channel MOSFET, which is sensed between the GND and SW pins. The 3809fc 12 LTC3809 APPLICATIONS INFORMATION 2.0 T NORMALIZED ON RESISTANCE 1.5 VOUT VIN V –V Bottom N-Channel Duty Cycle = IN OUT VIN Top P-Channel Duty Cycle = The MOSFET power dissipations at maximum output current are: PTOP = VOUT • IOUT (MAX)2 • ρT • RDS(ON) + 2 • VIN2 VIN • IOUT (MAX) • C RSS • f VIN – VOUT • IOUT (MAX)2 • ρT • RDS(ON) VIN 1.0 0.5 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3809 F02 Figure 2. RDS(ON) vs Temperature PBOT = short-circuit current sense threshold ΔVSC is set approximately 90mV when IPRG is floating (60mV when IPRG is tied low; 150mV when IPRG is tied high). The on-resistance of N-channel MOSFET is determined by: RDS(ON)MAX = ΔVSC ISC(PEAK) Both MOSFETs have I2R losses and the PTOP equation includes an additional term for transition losses, which are largest at high input voltages. The bottom MOSFET losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is 100%. The LTC3809 utilizes a non-overlapping, anti-shootthrough gate drive control scheme to ensure that the P- and N-channel MOSFETs are not turned on at the same time. To function properly, the control scheme requires that the MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs, particularly P-channel MOSFETs, are intended to be used as static switches and therefore are slow to turn on or off. Reasonable starting criteria for selecting the P-channel MOSFET are that it must typically have a gate charge (QG) less than 25nC to 30nC (at 4.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns. However, due to differences in test and specification methods of various MOSFET manufacturers, and in the variations in QG and tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET ultimately should be evaluated in the actual LTC3809 application circuit to ensure proper operation. Shoot-through between the P-channel and N-channel MOSFETs can most easily be spotted by monitoring the input supply current. As the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shoot-through. Note that some MOSFETs The short-circuit current limit (ISC(PEAK)) should be larger than the IOUT(MAX) with some margin to avoid interfering with the peak current sensing loop. On the other hand, in order to prevent the MOSFETs from excessive heating and the inductor from saturation, ISC(PEAK) should be smaller than the minimum value of their current ratings. A reasonable range is: IOUT(MAX) < ISC(PEAK) < IRATING(MIN) Therefore, the on-resistance of N-channel MOSFET should be chosen within the following range: ΔVSC IRATING(MIN) < RDS(ON) < ΔVSC IOUT(MAX) where ΔVSC is 90mV, 60mV or 150mV with IPRG being floated, tied to GND or VIN respectively. The power dissipated in the MOSFET strongly depends on its respective duty cycles and load current. When the LTC3809 is operating in continuous mode, the duty cycles for the MOSFETs are: 3809fc 13 LTC3809 APPLICATIONS INFORMATION that do not work well at high input voltages (e.g., VIN > 5V) may work fine at lower voltages (e.g., 3.3V). Selecting the N-channel MOSFET is typically easier, since for a given RDS(ON), the gate charge and turn-on and turn-off delays are much smaller than for a P-channel MOSFET. Operating Frequency and Synchronization The choice of operating frequency, fOSC, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The internal oscillator for the LTC3809’s controller runs at a nominal 550kHz frequency when the PLLLPF pin is left floating and the SYNC/MODE pin is not configured for spread spectrum operation. Pulling the PLLLPF to VIN selects 750kHz operation; pulling the PLLLPF to GND selects 300kHz operation. Alternatively, the LTC3809 will phase-lock to a clock signal applied to the SYNC/MODE pin with a frequency between 250kHz and 750kHz (see Phase-Locked Loop and Frequency Synchronization). To further reduce EMI, the nominal 550kHz frequency will be spread over a range with frequencies between 460kHz and 635kHz when spread spectrum modulation is enabled (see Spread Spectrum Modulation with SYNC/MODE and PLLLPF Pins). Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency, fOSC , directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN – VOUT • VIN fOSC • L A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC • IRIPPLE VIN Burst Mode Operation Considerations The choice of RDS(ON) and inductor value also determines the load current at which the LTC3809 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately: IBURST(PEAK) = 1 ΔVSENSE(MAX) • 4 RDS(ON) The corresponding average current depends on the amount of ripple current. Lower inductor values (higher IRIPPLE) will reduce the load current at which Burst Mode operation begins. The ripple current is normally set so that the inductor current is continuous during the burst periods. Therefore, IRIPPLE ≤ IBURST(PEAK) This implies a minimum inductance of: LMIN ≤ VIN – VOUT V • OUT fOSC • IBURST(PEAK) VIN A smaller value than L MIN could be used in the circuit, although the inductor current will not be continuous during burst periods, which will result in slightly lower efficiency. In general, though, it is a good idea to keep IRIPPLE comparable to IBURST(PEAK). Inductor Core Selection Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mμ® cores. Actual core loss is independent of core Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. 3809fc 14 LTC3809 APPLICATIONS INFORMATION size for a fixed inductor value, but is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. Core saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mμ. Toroids are very space efficient, especially when several layers of wire can be used, while inductors wound on bobbins are generally easier to surface mount. However, designs for surface mount that do not increase the height significantly are available from Coiltronics, Coilcraft, Dale and Sumida. Schottky Diode Selection (Optional) The schottky diode D in Figure 11 conducts current during the dead time between the conduction of the power MOSFETs. This prevents the body diode of the bottom N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. A 1A Schottky diode is generally a good size for most LTC3809 applications, since it conducts a relatively small average current. Larger diode results in additional transition losses due to its larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. CIN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle (VOUT/VIN). To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: VOUT • ( VIN – VOUT ) CIN Re quiredIRMS ≈ IMAX • VIN 1/ 2 This formula has a maximum value at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet the size or height requirements in the design. Due to the high operating frequency of the LTC3809, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is approximated by: ⎛ ⎞ 1 ΔVOUT ≈ IRIPPLE • ⎜ ESR + ⎟ ⎝ 8 • f • C OUT ⎠ where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increase with input voltage. Setting Output Voltage The LTC3809 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 3. The regulated output voltage is determined by: ⎛ R⎞ VOUT = 0.6 V • ⎜ 1 + B ⎟ ⎝ RA ⎠ 3809fc 15 LTC3809 APPLICATIONS INFORMATION VOUT LTC3809 VFB RA 3809 F03 RB CFF is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to SYNC/ MODE, is shown in Figure 5 and specified in the electrical characteristics table. Note that the LTC3809 can only be synchronized to an external clock whose frequency is within range of the LTC3809’s internal VCO, which is nominally 200kHz to 1MHz. This is guaranteed, over temperature and process variations, to be between 250kHz and 750kHz. A simplified block diagram is shown in Figure 6. 1200 1000 FREQUENCY (kHz) 800 600 400 200 0 0.2 0.7 1.2 1.7 PLLLPF PIN VOLTAGE (V) 2.2 3809 F05 Figure 3. Settling Output Voltage For most applications, a 59k resistor is suggested for RA. In applications where minimizing the quiescent current is critical, RA should be made bigger to limit the feedback divider current. If RB then results in very high impedance, it may be beneficial to bypass RB with a 50pF to 100pF capacitor CFF . Run and Soft-Start Functions The LTC3809 has a low power shutdown mode which is controlled by the RUN pin. Pulling the RUN pin below 1.1V puts the LTC3809 into a low quiescent current shutdown mode (IQ = 9μA). Releasing the RUN pin, an internal 0.7μA (at VIN = 4.2V) current source will pull the RUN pin up to VIN, which enables the controller. The RUN pin can be driven directly from logic as showed in Figure 4. Once the controller is enabled, the start-up of VOUT is controlled by the internal soft-start, which slowly ramps the positive reference to the error amplifier from 0V to 0.6V, allowing VOUT to rise smoothly from 0V to its final value. The default internal soft-start time is around 1ms. 3.3V OR 5V LTC3809 RUN LTC3809 RUN 3809 F04 Figure 5. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock 2.4V RLP CLP SYNC/ MODE EXTERNAL OSCILLATOR PLLLPF DIGITAL PHASE/ FREQUENCY DETECTOR Figure 4. RUN Pin Interfacing Phase-Locked Loop and Frequency Synchronization The LTC3809 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the external P-channel MOSFET to be locked to the rising edge of an external clock signal applied to the SYNC/MODE pin. The phase detector OSCILLATOR 3809 F06 Figure 6. Phase-Locked Loop Block Diagram 3809fc 16 LTC3809 APPLICATIONS INFORMATION If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01μF. Typically, the external clock (on SYNC/MODE pin) input high level is 1.6V, while the input low level is 1.2V. Table 1 summarizes the different states in which the PLLLPF pin can be used. Table 1. The States of the PLLLPF Pin PLLLPF PIN 0V Floating VIN RC Loop Filter Filter Caps SYNC/MODE PIN DC Voltage (