LTC3812EFE-5-TRPBF

FEATURES n n n n n n n n n n n n n n n LTC3812-5 60V Current Mode Synchronous Switching Regulator Controller DESCRIPTION The LTC3812-5 is a synchronous step-down switching regulator controller that can directly step down voltages from up to 60V input, making it ideal for telecom and automotive applications. The LTC3812-5 uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifier provides very fast line and load transient response. Large 1Ω gate drivers allow the LTC3812-5 to drive large power MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN. A shutdown pin allows the LTC3812-5 to be turned off reducing the supply current to 1.5V (Notes 4, 5) RUN/SS = 0V RUN/SS > 1.5V (Note 5) RUN/SS = 0V (Note 4) 0°C to 85°C –40°C to 85°C –40°C to 125°C (I-grade) 5V < INTVCC < 14V (Note 4) VRNG = 2V, VFB = 0.76V VRNG = 0V, VFB = 0.76V VRNG = INTVCC, VFB = 0.76V VRNG = 2V, VFB = 0.84V VRNG = 0V, VFB = 0.84V VRNG = INTVCC, VFB = 0.84V VFB = 0.8V 65 (Note 6) VFCB Rising FCB = 5V 1.2 RUN/SS = 0V INTVCC Rising, INDRV = 100μA INTVCC Rising, NDRV = INTVCC = EXTVCC INTVCC Rising, NDRV = INTVCC, EXTVCC = 0 INTVCC Falling ION = 100μA ION = 300μA ION = 2500μA 250 VBG = 0V VTG – VSW = 0V 0.7 0.7 1 1 1 1 VFB Rising VFB Falling VFB Returning IPGOOD = 5mA 7.5 –7.5 10 –10 1.5 0.3 1.5 12.5 –12.5 3 0.6 1.5 l l l l l l l l ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN 4.35 TYP MAX 14 UNITS V mA μA μA μA V V V V %/V mV mV mV mV mV mV 3 224 240 0 0.796 0.794 0.792 0.792 256 70 170 0.800 0.800 0.800 0.800 0.002 320 95 215 –300 –85 –200 20 100 25 0.75 0.8 0 1.5 1.4 4.2 4.2 9.0 3.7 1.85 605 0.7 4.05 4.05 8.70 6 600 400 5 0.804 0.806 0.806 0.808 0.02 384 120 260 ΔVFB,LINE VSENSE(MAX) Feedback Voltage Line Regulation Maximum Current Sense Threshold VSENSE(MIN) Minimum Current Sense Threshold IVFB AVOL(EA) fU VFCB IFCB VRUN/SS IRUN/SS VVCCUV Feedback Current Error Amplifier DC Open-Loop Gain Error Amp Unity Gain Crossover Frequency FCB Threshold FCB Current Shutdown Threshold RUN/SS Source Current INTVCC Undervoltage Lockout Linear Regulator Mode External Supply Mode Trickle-Charge Mode 150 nA dB MHz 0.85 1 2 2.5 4.35 4.35 9.30 V μA V μA V V V V μs ns ns ns A Ω A Ω % % % V 38125fb Oscillator tON tON(MIN) tOFF(MIN) Driver IBG,PEAK RBG,SINK ITG,PEAK RTG,SINK PGOOD Output ΔVFBOV ΔVFB,HYST VPGOOD PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysterisis PGOOD Low Voltage BG Driver Peak Source Current BG Driver Pull-Down RDS(ON) TG Driver Peak Source Current TG Driver Pull-Down RDS(ON) On-Time Minimum On-Time Minimum Off-Time 1.55 515 2.15 695 100 350 3 LTC3812-5 The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, INTVCC = VBOOST = VRNG = VEXTVCC = VNDRV = 5V, VFCB = VSW = 0V, unless otherwise specified. SYMBOL IPGOOD PG Delay VCC Regulators VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising EXTVCC Hysterisis INTVCC Voltage from EXTVCC VEXTVCC - VINTVCC at Dropout INTVCC Load Regulation from EXTVCC INTVCC Voltage from NDRV Regulator INTVCC Load Regulation from NDRV Current into NDRV Pin Linear Regulator Timeout Enable Threshold Maximum Supply Voltage Maximum Current into NDRV/INTVCC Trickle Charger Shunt Regulator Trickle Charger Shunt Regulator, INTVCC ≤ 16.7V (Note 8) 10 6V < VEXTVCC < 15V ICC = 20mA, VEXTVCC = 5V ICC = 0mA to 20mA, VEXTVCC = 10V Linear Regulator in Operation ICC = 0mA to 20mA, VEXTVCC = 0 VNDRV – VINTVCC = 3V 20 210 5.2 l ELECTRICAL CHARACTERISTICS PARAMETER PGOOD Leakage Current PGOOD Delay CONDITIONS VPGOOD = 5V VFB Falling MIN TYP 0 120 MAX 2 UNITS μA μs 4.5 0.1 5.2 4.7 0.25 5.5 75 0.01 5.5 0.01 40 270 15 0.4 5.8 150 5.8 60 350 V V V mV % V % μA μA V mA VINTVCC,1 ΔVEXTVCC,1 ΔVLOADREG,1 VINTVCC,2 ΔVLOADREG,2 INDRV INDRVTO VCCSR ICCSR Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3812E-5 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3812I-5 is guaranteed to meet performance specifications over the full –40°C to 125°C operating temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3812-5: TJ = TA + (PD • 38°C/W) PARAMETER Maximum VIN MOSFET Gate Drive INTVCC UV+ INTVCC UV– LTC3810 100V 6.35V to 14V 6.2V 6V Note 4: The LTC3812-5 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 1V and 2V. Note 5: The dynamic input supply current is higher due to the power MOSFET gate charging being delivered at the switching frequency (QG • fOSC). Note 6: Guaranteed by design. Not subject to test. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: ICC is the sum of current into NDRV and INTVCC. LTC3810-5 60V 4.5V to 14V 4.2V 4V LTC3812-5 60V 4.5V to 14V 4.2V 4V 38125fb 4 LTC3812-5 TYPICAL PERFORMANCE CHARACTERISTICS Load Transient Response VIN 20V/DIV VOUT 50mV/DIV IOUT 5A/DIV INTVCC, VOUT 2V/DIV IL 2A/DIV 10μs/DIV FRONT PAGE CIRCUIT VIN = 25V 0A TO 5A LOAD STEP 38125 G01 Start-Up VOUT 5V/DIV INTVCC VOUT SS/TRACK 2V/DIV IL 5A/DIV Short-Circuit/Fault Timeout Operation 2ms/DIV FRONT PAGE CIRCUIT VIN = 30V ILOAD = 0.5A FCB = 0V 38125 G02 5ms/DIV FRONT PAGE CIRCUIT VIN = 25V RSHORT = 0.1Ω 38125 G03 Short-Circuit/Foldback Operation VOUT 5V/DIV IL 5A/DIV VOUT 100mV/DIV Pulse Skip Mode Operation 100 Efficiency vs Input Voltage FRONT PAGE CIRCUIT f = 250kHz ILOAD = 5A FORCED CONTINUOUS ILOAD = 0.5A FORCED CONTINUOUS ILOAD = 0.5A PULSE SKIP IL 2A/DIV EFFICIENCY (%) ITH 0.5A/DIV 95 90 200μs/DIV FRONT PAGE CIRCUIT VIN = 25V 38125 G04 20μs/DIV FRONT PAGE CIRCUIT VIN = 25V IOUT = 100mA FCB = INTVCC 38125 G05 85 80 0 10 20 30 40 INPUT VOLTAGE (V) 50 60 38125 G06 Efficiency vs Load Current 100 VIN = 24V EFFICIENCY (%) 95 FREQUENCY (kHz) 300 290 280 270 260 250 240 230 220 210 5 6 38125 G07 Frequency vs Input Voltage 350 FRONT PAGE CIRCUIT FCB = 0V LOAD = 5A FREQUENCY (kHz) 300 250 200 Frequency vs Load Current FRONT PAGE CIRCUIT FORCED CONTINUOUS VIN = 42V PULSE SKIP 150 100 50 0 LOAD = 0A 90 VOUT = 12V FCB = INTVCC f = 250kHz 85 0 1 2 3 4 LOAD CURRENT (A) 200 0 10 30 40 20 INPUT VOLTAGE (V) 50 60 0 1 2 3 4 5 38125 G09 LOAD CURRENT (A) LT1108 • TPC12 38125fb 5 LTC3812-5 TYPICAL PERFORMANCE CHARACTERISTICS ITH Voltage vs Load Current 3.0 2.5 ITH VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0 1 CURRENT SENSE THRESHOLD (mV) VRNG = 1V FRONT PAGE CIRCUIT 400 VRNG = 2V 300 200 100 0 –100 –200 –300 –400 0 0.5 1 1.5 2 ITH VOLTAGE (V) 2.5 3 10 10 100 1000 ION CURRENT (μA) 10000 38125 G12 Current Sense Threshold vs ITH Voltage 10000 On-Time vs ION Current VON = INTVCC 1.4V ON-TIME (ns) 1V 0.7V 0.5V 1000 100 4 3 2 5 LOAD CURRENT (A) 6 7 38125 G10 38125 G11 On-Time vs Temperature MAXIMUM CURRENT SENSE THRESHOLD (mV) 680 660 640 620 600 580 560 –50 –25 ION = 300μA 250 Current Limit Foldback VRNG = INTVCC MAXIMUM CURRENT SENSE THRESHOLD (mV) 400 Maximum Current Sense Threshold vs VRNG Voltage 200 300 ON-TIME (ns) 150 200 100 100 50 50 25 75 0 TEMPERATURE (°C) 100 125 0 0 0.2 0.4 VFB (V) 0.6 0.8 38125 G14 0 0.5 1 1.5 2 38125 G15 VRNG VOLTAGE (V) 38125 G13 Maximum Current Sense Threshold vs Temperature MAXIMUM CURRENT SENSE THRESHOLD (mV) 230 VRNG = INTVCC 220 0.803 0.802 REFERENCE VOLTAGE (V) 0.801 0.800 0.799 0.798 Reference Voltage vs Temperature 1.5 Driver Peak Source Current vs Temperature VBOOST = VINTVCC = 5V 210 PEAK SOURCE CURRENT (A) 1.0 200 190 180 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0.797 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0.5 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 38125 G16 38125 G17 38125 G18 38125fb 6 LTC3812-5 TYPICAL PERFORMANCE CHARACTERISTICS Driver Pull-Down RDS(ON) vs Temperature 1.75 1.50 1.25 RDS(ON) (Ω) 1.00 0.75 0.50 0.25 –50 –25 VBOOST = VINTVCC = 5V PEAK SOURCE CURRENT (A) 3.0 2.5 2.0 RDS(ON) (Ω) 0.9 1.5 1.0 0.5 0 0.7 Driver Peak Source Current vs Supply Voltage 1.1 Driver Pull-Down RDS(ON) vs Supply Voltage 1.0 0.8 50 25 75 0 TEMPERATURE (°C) 100 125 0.6 4 5 6 7 8 9 10 11 12 13 14 DRVCC/BOOST VOLTAGE (V) 38125 G20 4 5 6 7 8 9 10 11 12 13 14 DRVCC/BOOST VOLTAGE (V) 38125 G21 38125 G19 EXTVCC Switch Resistance vs Temperature 7 6 4 RESISTANCE (Ω) 5 4 3 2 1 0 –50 –25 INTVCC CURRENT (mA) 5 INTVCC Current vs Temperature 400 INTVCC = 5V 300 INTVCC Shutdown Current vs Temperature INTVCC = 5V 3 INTVCC CURRENT (μA) 200 2 100 1 50 25 75 0 TEMPERATURE (°C) 100 125 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 38125 G22 38125 G23 38125 G24 INTVCC Current vs INTVCC Voltage 3.5 3.0 INTVCC CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 0 0 2 8 6 10 4 INTVCC VOLTAGE (V) 12 14 INTVCC CURRENT (μA) 350 300 250 200 150 100 50 0 INTVCC Shutdown Current vs INTVCC Voltage 0 2 8 6 10 4 INTVCC VOLTAGE (V) 12 14 38125 G25 38125 G26 38125fb 7 LTC3812-5 TYPICAL PERFORMANCE CHARACTERISTICS RUN/SS Pull-Up Current vs Temperature 3 2.2 RUN/SS = 0V 2.0 SHUTDOWN THRESHOLD (V) SS/TRACK CURRENT (μA) 1.8 1.6 1.4 1.2 1.0 0.8 0 –50 –25 0.6 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 Shutdown Threshold vs Temperature 2 1 50 25 75 0 TEMPERATURE (°C) 100 125 38125 G27 38125 G28 PIN FUNCTIONS ION (Pin 1): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. VRNG (Pin 2): Sense Voltage Limit Set. The voltage at this pin sets the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 95mV when this pin is tied to ground, and 215mV when tied to INTVCC. PGOOD (Pin 3): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not between ±10% of the regulation point. The output voltage must be out of regulation for at least 120μs before the power good output is pulled to ground. FCB (Pin 4): Pulse Skip Mode Enable Pin. This pin provides pulse skip mode enable/disable control. Pulling this pin below 0.8V disables pulse skip mode operation and forces continuous operation. Pulling this pin above 0.8V enables pulse skip mode operation. This pin can also be connected to a feedback resistor divider from a secondary winding on the inductor to regulate a second output voltage. ITH (Pin 5): Error Amplifier Compensation Point and Current Control Threshold. The current comparator threshold increases with control voltage. The voltage ranges from 0V to 2.6V with 1.2V corresponding to zero sense voltage (zero current). VFB (Pin 6): Feedback Input. Connect VFB through a resistor divider network to VOUT to set the output voltage. RUN/SS (Pin 7): RUN/Soft-Start Input. For soft-start, a capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.6s/μF). Pulling this pin below 1.5V will shut down the LTC3812-5, turn off both of the external MOSFET switches and reduce the quiescent supply current to 224μA. SGND (Pin 8): Signal Ground. All small-signal components should connect to this ground and eventually connect to PGND at one point. NDRV (Pin 9): Drive Output for External Pass Device of the Linear Regulator for INTVCC. Connect to the gate of an external NMOS pass device and a pull-up resistor to the input voltage VIN. 38125fb 8 LTC3812-5 PIN FUNCTIONS EXTVCC (Pin 10): External Driver Supply Voltage. When this voltage exceeds 4.2V, an internal switch connects this pin to INTVCC through an LDO and turns off the external MOSFET connected to NDRV, so that controller and gate drive are drawn from EXTVCC. INTVCC (Pin 11): Main Supply and Driver Supply Pin. All internal circuits and bottom gate output driver are powered from this pin. INTVCC should be bypassed to SGND and PGND with a low ESR (X5R or better) 1μF capacitor in close proximity to the LTC3812-5. BG (Pin 12): Bottom Gate Drive. The BG pin drives the gate of the bottom N-channel synchronous switch MOSFET. This pin swings from PGND to INTVCC. PGND (Pin 13): Bottom Gate Return. This pin connects to the source of the pull-down MOSFET in the BG driver and is normally connected to ground. SW (Pin 14): Switch Node Connection to Inductor and Bootstrap Capacitor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. TG (Pin 15): Top Gate Drive. The TG pin drives the gate of the top N-channel synchronous switch MOSFET. The TG driver draws power from the BOOST pin and returns to the SW pin, providing true floating drive to the top MOSFET. BOOST (Pin 16): Top Gate Driver Supply. The BOOST pin supplies power to the floating TG driver. BOOST should be bypassed to SW with a low ESR (X5R or better) 0.1μF capacitor. An additional fast recovery Schottky diode from INTVCC to the BOOST pin will create a complete floating charge-pumped supply at BOOST. Exposed Pad (Pin 17): Ground. The Exposed Pad must be soldered to PCB ground. 38125fb 9 LTC3812-5 FUNCTIONAL DIAGRAM INTVCC EXTVCC NDRV INTVCC VIN INTVCC MODE LOGIC 5.5V 5V REG 0.8V REF + – OFF NDRV 9 M3 9V 0.8V FCB 4 + F UV + INTVCC 4.2V INTVCC 11 EXTVCC 10 – – + 270μA – 1.4μA + – ON 5.5V + + – 4.7V BOOST 16 TG CB M1 DB VIN 100nA RON VIN ION 1 tON = 2.4V (76pF) IION TIMEOUT LOGIC DRV OFF FCNT ON + CIN R S Q 15 SW 14 + ICMP 20k + IREV SWITCH LOGIC L1 VOUT INTVCC BG 12 PGND CVCC M2 – – SHDN OV + COUT × 1.4V VRNG 2 ITH FOLDBACK FB ITH 5 CC2 RC CC1 2.6V 0.7V 13 OVERTEMP SENSE 5V PGOOD 3 RFB1 1.5V FAULT EA 1.5V – + 7 0.8V RUN/SS 10 – UV OV RUN SHDN + – + –++ 0.72V VFB 6 + – SGND 8 0.88V RFB2 38125 FD 38125fb LTC3812-5 OPERATION Main Control Loop The LTC3812-5 is a current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer (OST). When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the PGND and SW pins using the bottom MOSFET on-resistance. The voltage on the ITH pin sets the comparator threshold corresponding to the inductor valley current. The fast 25MHz error amplifier EA adjusts this voltage by comparing the feedback signal VFB to the internal 0.8V reference voltage. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an on time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Forcing a voltage above 1.5V will turn on the device. PULSE SKIP MODE Pulse Skip Mode The LTC3812-5 can operate in one of two modes selectable with the FCB pin—pulse skip mode or forced continuous mode (see Figure 1). Pulse skip mode is selected when increased efficiency at light loads is desired (see Figure 2). In this mode, the bottom MOSFET is turned off when inductor current reverses to minimize efficiency loss due to reverse current flow and gate charge switching. At low load currents, ITH will drop below the zero current level (1.2V) shutting off both switches. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 LOAD (A) 38125 F02 PULSE SKIP FORCED CONTINUOUS VIN = 12V VIN = 42V 1 10 Figure 2. Efficiency in Pulse Skip/Forced Continuous Modes FORCED CONTINUOUS 0A DECREASING LOAD CURRENT 0A 0A 0A 0A 0A 38125 F01 Figure 1. Comparison of Inductor Current Waveforms for Pulse Skip Mode and Forced Continuous Operation 38125fb 11 LTC3812-5 OPERATION level to initiate another cycle. In this mode, frequency is proportional to load current at light loads. Pulse skip mode operation is disabled by comparator F when the FCB pin is brought below 0.8V, forcing continuous synchronous operation. Forced continuous mode is less efficient due to resistive losses, but has the advantage of better transient response at low currents, approximately constant frequency operation, and the ability to maintain regulation when sinking current. Fault Monitoring/Protection Constant on-time current mode architecture provides accurate cycle-by-cycle current limit protection—a feature that is very important for protecting the high voltage power supply from output short-circuits. The cycle-by-cycle current monitor guarantees that the inductor current will never exceed the value programmed on the VRNG pin. Foldback current limiting provides further protection if the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down and clamped to 1V. This reduces the inductor valley current level to one-sixth of its maximum value as VFB approaches 0V. Foldback current limiting is disabled at start-up. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point after the internal 120μs power bad mask timer expires. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on immediately and held on until the overvoltage condition clears. The LTC3812-5 provides an undervoltage lockout comparator for the INTVCC supply. The INTVCC UV threshold is 4.2V to guarantee that the MOSFETs have sufficient gate drive voltage before turning on. If INTVCC is under the UV threshold, the LTC3812-5 is shut down and the drivers are turned off. Strong Gate Drivers The LTC3812-5 contains very low impedance drivers capable of supplying amps of current to slew large MOSFET gates quickly. This minimizes transition losses and allows paralleling MOSFETs for higher current applications. A 60V floating high side driver drives the topside MOSFET and a low side driver drives the bottom side MOSFET (see Figure 3). The bottom side driver is supplied directly from the INTVCC pin. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode from INTVCC when the top MOSFET turns off. In pulse skip mode operation, where it is possible that the bottom MOSFET will be off for an extended period of time, an internal timeout guarantees that the bottom MOSFET is turned on at least once every 25μs for one on-time period to refresh the bootstrap capacitor. INTVCC VIN LTC3812-5 INTVCC DB BOOST TG SW CB M1 + CIN L VOUT BG PGND M2 + COUT 38125 F03 Figure 3. Floating TG Driver Supply and Negative BG Return IC/Driver Supply Power The LTC3812-5’s internal control circuitry and top and bottom MOSFET drivers operate from a supply voltage (INTVCC pin) in the range of 4.2V to 14V. The LTC3812-5 has two integrated linear regulator controllers to easily generate this IC/driver supply from either the high voltage input or from the output voltage. For best efficiency the supply is derived from the input voltage during start-up and then derived from the lower voltage output as soon as the output is higher than 4.7V. Alternatively, the supply can be derived from the input continuously if the output is 270μA I < 270μA driver shutdown/restart for VOUT < 4.7V is disabled. This scheme is less efficient but may be necessary if VOUT < 4.7V and a boost network is not desired. 3. Trickle charge mode provides an even simpler approach by eliminating the external NMOS. The IC/driver supply capacitors are charged through a single high valued resistor connected to the input supply. When the INTVCC voltage reaches the turn-on threshold of 9V (automatically raised from 4.2V to provide extra headroom for start-up), the drivers turn on and begin charging up the output capacitor. When the output reaches 4.7V, IC/driver power is derived from the output. In trickle-charge mode, the supply capacitors must have sufficient capacitance such that they are not discharged below the 4V INTVCC UV threshold before the output is high enough to take over or else the power supply will not start. 4. Low voltage supply available. The simplest approach is if a low voltage supply (between 4.2V and 14V) is available and connected directly to the IC/driver supply pins. Mode 2: MOSFET for Continuous Use VIN NDRV INTVCC LTC3812-5 NDRV + 5.5V INTVCC LTC3812-5 + 5.5V EXTVCC VOUT (> 4.7V) EXTVCC Mode 3: Trickle Charge Mode VIN Mode 4: External Supply NDRV INTVCC LTC3812-5 NDRV + 5.5V INTVCC LTC3812-5 + + – 4.2V TO 14V 38125 F04 EXTVCC VOUT EXTVCC Figure 4. Operating Modes for IC/Driver Supply 38125fb 13 LTC3812-5 APPLICATIONS INFORMATION The basic LTC3812-5 application circuit is shown on the first page of this data sheet. External component selection is primarily determined by the maximum input voltage and load current and begins with the selection of the power MOSFET switches. The LTC3812-5 uses the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Next, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Finally, loop compensation components are selected to meet the required transient/ phase margin specifications. MAXIMUM SENSE VOLTAGE AND VRNG PIN Inductor current is determined by measuring the voltage across a sense resistance (the on-resistance of the bottom MOSFET) that appears between the PGND and SW pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately: VSENSE(MAX) = 0.173VRNG – 0.026 The current mode control loop will not allow the inductor current valleys to exceed VSENSE(MAX)/RSENSE. In practice, one should allow some margin for variations in the LTC3812-5 and external component values and a good guide for selecting the sense resistance is: RSENSE = VSENSE(MAX) 1.3 •IOUT(MAX ) POWER MOSFET SELECTION The LTC3812-5 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage BVDSS, threshold voltage V(GS)TH, on-resistance RDS(ON), input capacitance and maximum current IDS(MAX). Since the bottom MOSFET is used as the current sense element, particular attention must be paid to its on-resistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX) = RSENSE T The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature (see Figure 5) and typically varies from 0.4%/°C to 1.0%/°C depending on the particular MOSFET used. 2.0 ρT NORMALIZED ON-RESISTANCE 1.5 1.0 An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 60mV to 320mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 95mV or 215mV, respectively. 0.5 0 –50 50 100 0 JUNCTION TEMPERATURE (°C) 150 38125 F05 Figure 5. RDS(ON) vs Temperature 38125fb 14 LTC3812-5 APPLICATIONS INFORMATION The most important parameter in high voltage applications is breakdown voltage BVDSS. Both the top and bottom MOSFETs will see full input voltage plus any additional ringing on the switch node across its drain-to-source during its off-time and must be chosen with the appropriate breakdown specification. The LTC3812-5 is designed to be used with a 4.5V to 14V gate drive supply (INTVCC pin) for driving logic-level MOSFETs (VGS(MIN) ≥ 4.5V). For maximum efficiency, on-resistance RDS(ON) and input capacitance should be minimized. Low RDS(ON) minimizes conduction losses and low input capacitance minimizes transition losses. MOSFET input capacitance is a combination of several components but can be taken from the typical “gate charge” curve included on most data sheets (Figure 6). VIN MILLER EFFECT a QIN CMILLER = (QB – QA)/VDS b VGS V voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN VIN – VOUT VIN Synchronous Switch Duty Cycle = VGS + +V DS – 38125 F06 The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PTOP = VOUT (IMAX )2 ( T )RDS(ON) + VIN I VIN2 MAX (RDR )(CMILLER ) • 2 1 1 ( f) + VCC – VTH(IL) VTH(IL ) PBOT = VIN – VOUT (IMAX )2( VIN T )RDS(0N) – Figure 6. Gate Charge Characteristic The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain where ρT is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified 38125fb 15 LTC3812-5 APPLICATIONS INFORMATION drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the topside N-channel equation incudes an additional term for transition losses, which peak at the highest input voltage. For high input voltage low duty cycle applications that are typical for the LTC3812-5, transition losses are the dominate loss term and therefore using higher RDS(ON) device with lower CMILLER usually provides the highest efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. Since there is no transition loss term in the synchronous MOSFET, optimal efficiency is obtained by minimizing RDS(ON) —by using larger MOSFETs or paralleling multiple MOSFETS. Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. The LTC3812-5 contains large low impedance drivers capable of driving large gate capacitances without significantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (10Ω or less) to reduce noise and EMI caused by the fast transitions. 1000 OPERATING FREQUENCY The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC3812-5 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is set by the current out of the ION pin and the voltage at the VON pin according to: tON = 2.4V (76pF) IION Tying a resistor RON from VIN to the ION pin yields an on-time inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT [Hz] 2.4V • RON(76pF ) Figure 7 shows how RON relates to switching frequency for several common output voltages. SWITCHING FREQUENCY (kHz) VOUT = 12V VOUT = 3.3V VOUT = 5V 100 10 100 RON (kΩ) 1000 38112 F07 Figure 7. Switching Frequency vs RON 38125fb 16 LTC3812-5 APPLICATIONS INFORMATION MINIMUM OFF-TIME AND DROPOUT OPERATION The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3812-5 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: L= VOUT f IL(MAX ) 1 VOUT VIN(MAX ) A plot of maximum duty cycle vs frequency is shown in Figure 8. INDUCTOR SELECTION Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V IL = OUT fL V 1 OUT VIN Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mμ® cores. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. SCHOTTKY DIODE D1 SELECTION The Schottky diode D1 shown in the front page schematic conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving 2.0 SWITCHING FREQUENCY (MHz) 1.5 DROPOUT REGION 1.0 0.5 0 0 0.25 0.50 0.75 DUTY CYCLE (VOUT/VIN) 1.0 38125 F08 Figure 8. Maximum Switching Frequency vs Duty Cycle 38125fb 17 LTC3812-5 APPLICATIONS INFORMATION it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. INPUT CAPACITOR SELECTION In continuous mode, the drain current of the top MOSFET is approximately a square wave of duty cycle VOUT/VIN which must be supplied by the input capacitor. To prevent large input transients, a low ESR input capacitor sized for the maximum RMS current is given by: ICIN(RMS) V VIN IO(MAX) OUT –1 VIN VOUT 1/2 A good approach is to use a combination of aluminum electrolytics for bulk capacitance and ceramics for low ESR and RMS current. If the RMS current cannot be handled by the aluminum capacitors alone, when used together, the percentage of RMS current that will be supplied by the aluminum capacitor is reduced to approximately: % IRMS,ALUM 1 1+ (8fCRESR )2 • 100% where RESR is the ESR of the aluminum capacitor and C is the overall capacitance of the ceramic capacitors. Using an aluminum electrolytic with a ceramic also helps damp the high Q of the ceramic, minimizing ringing. OUTPUT CAPACITOR SELECTION The selection of COUT is primarily determined by the ESR required to minimize voltage ripple. The output ripple (ΔVOUT) is approximately equal to: VOUT IL ESR + 1 8fCOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. Because tantalum and OS-CON capacitors are not available in voltages above 30V, ceramics or aluminum electrolytics must be used for regulators with input supplies above 30V. Ceramic capacitors have the advantage of very low ESR and can handle high RMS current, but ceramics with high voltage ratings (> 50V) are not available with more than a few microfarads of capacitance. Furthermore, ceramics have high voltage coefficients which means that the capacitance values decrease even more when used at the rated voltage. X5R and X7R type ceramics are recommended for their lower voltage and temperature coefficients. Another consideration when using ceramics is their high Q which, if not properly damped, may result in excessive voltage stress on the power MOSFETs. Aluminum electrolytics have much higher bulk capacitance, but they have higher ESR and lower RMS current ratings. Since ΔIL increases with input voltage, the output ripple is highest at maximum input voltage. ESR also has a significant effect on the load transient response. Fast load transitions at the output will appear as voltage across the ESR of COUT until the feedback loop in the LTC3812-5 can change the inductor current to match the new load current value. Typically, once the ESR requirement is satisfied the capacitance is adequate for filtering and has the required RMS current rating. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance throughhole capacitors. The OS-CON (organic semiconductor dielectric) capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the effect of their lead inductance. In surface mount applications, multiple capacitors placed in parallel may be required to meet the ESR, RMS current 38125fb 18 LTC3812-5 APPLICATIONS INFORMATION handling and load step requirements. Dry tantalum, special polymer and aluminum electrolytic capacitors are available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Several excellent surge-tested choices are the AVX TPS and TPSV or the KEMET T510 series. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-driven applications providing that consideration is given to ripple current ratings and long term reliability. Other capacitor types include Panasonic SP and Sanyo POSCAPs. OUTPUT VOLTAGE The LTC3812-5 output voltage is set by a resistor divider according to the following formula: VOUT = 0.8V 1+ RFB1 RFB2 The reverse breakdown of the external diode, DB, must be greater than VIN(MAX). Another important consideration for the external diode is the reverse recovery and reverse leakage, either of which may cause excessive reverse current to flow at full reverse voltage. If the reverse current times reverse voltage exceeds the maximum allowable power dissipation, the diode may be damaged. For best results, use an ultrafast recovery diode such as the MMDL770T1. IC/MOSFET DRIVER SUPPLY (INTVCC) The LTC3812-5 drivers are supplied from the INTVCC and BOOST pins (see Figure 3), which have an absolute maximum voltage of 14V. Since the main supply voltage, VIN is typically much higher than 14V a separate supply for the IC and driver power (INTVCC) must be used. The LTC3812-5 has integrated bias supply control circuitry that allows the IC/driver supply to be easily generated from VIN and/or VOUT with minimal external components. There are four ways to do this as shown in the simplified schematics of Figure 4 and explained in the following sections. Using the Linear Regulator for INTVCC Supply In Mode 1, a small external SOT-23 MOSFET, controlled by the NDRV pin, is used to generate a 5.5V start-up supply from VIN. The small SOT-23 package can be used because the NMOS is on continuously only during the brief start-up period. As soon as the output voltage reaches 4.7V, the LTC3812-5 turns off the external NMOS and the LTC3812-5 regulates the 5.5V supply from the EXTVCC pin (connected to VOUT or a VOUT derived boost network) through an internal low dropout regulator. For this mode to work properly, EXTVCC must be in the range 4.7V < EXTVCC < 15V. If VOUT < 4.7V, a charge pump or extra winding can be used to raise EXTVCC to the proper voltage, or alternatively, Mode 2 should be used as explained later in this section. If VOUT is shorted or otherwise goes below the minimum 4.5V threshold, the MOSFET connected to VIN is turned back on to maintain the 5.5V supply. However if the output cannot be brought up within a timeout period, The external resistor divider is connected to the output as shown in the Functional Diagram, allowing remote voltage sensing. The resultant feedback signal is compared with the internal precision 800mV voltage reference by the error amplifier. The internal reference has a guaranteed tolerance of less than ±1%. Tolerance of the feedback resistors will add additional error to the output voltage. 0.1% to 1% resistors are recommended. TOP MOSFET DRIVER SUPPLY (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1μF to 0.47μF X5R , or X7R dielectric capacitor is adequate. 38125fb 19 LTC3812-5 APPLICATIONS INFORMATION the drivers are turned off to prevent the SOT-23 MOSFET from overheating. Soft-start cycles are then attempted at low duty cycle intervals to try to bring the output back up (see Figure 9). This fault timeout operation is enabled by choosing the choosing RNDRV such that the resistor current INDRV is greater than 270μA by using the following formulas: RNDRV where ICC = (f)(QG(TOP) + QG(BOTTOM)) + 3mA and VT is the threshold voltage of the MOSFET. The value of RNDRV also affects the VIN(MIN) as follows: VIN(MIN) = VINTVCC(MIN) + (40μA) RNDRV + VT (1) where VINTVCC(MIN) is normally 4.5V for driving logic level MOSFETs. If minimum VIN is not low enough, consider reducing RNDRV and/or using a darlington NPN instead of an NMOS to reduce VT to ~1.4V. When using RNDRV equal to the computed value, the LTC3812-5 will enable the low duty cycle soft-start retries only when the desired maximum power dissipation, PMOSFET(MAX), in the MOSFET is exceeded and leave the drivers on continuously otherwise. The shutoff/restart times are a function of the RUN/SS capacitor value. FAULT TIMEOUT ENABLED DRIVER POWER FROM VOUT RUN/SS DRIVER POWER FROM VIN START-UP VOUT SHORT-CIRCUIT EVENT START-UP INTO SHORT CIRCUIT DRIVER POWER FROM VIN EXTVCC UV THRESHOLD The external NMOS for the linear regulator should be a standard 3V threshold type (i.e., not a logic level threshold). The rate of charge of VCC from 0V to 5.5V is controlled by the LTC3812-5 to be approximately 75μs regardless of the size of the capacitor connected to the INTVCC pin. The charging current for this capacitor is approximately: IC = 5.5V C 75μs INTVCC PMOSFET(MAX) /ICC VT 270μA The safe operating area (SOA) for the external NMOS should be chosen so that capacitor charging does not damage the NMOS. Excessive values of capacitor are unnecessary and should be avoided. Typically values in the 1μF to 10μF work well. One more design requirement for this mode is the minimum soft-start capacitor value. The fault timeout is enabled when RUN/SS voltage is greater than 4V. This gives the power supply time to bring the output up before it starts the timeout sequence. To prevent timeout sequence from starting prematurely during start-up, a minimum CSS value is necessary to ensure that VRUN/SS < 4V until VEXTVCC > 4.7V. To ensure this, choose: CSS > COUT • (2.3 • 10-6)/IOUT(MAX) Mode 2 should be used if VOUT is outside of the 4.7V < EXTVCC < 15V operating range and the extra complexity of a charge pump or extra inductor winding is not wanted DRIVER OFF THRESHOLD ISS/TRACK = 1.4μA (SOURCE) ISS/TRACK = 0.1μA (SINK) TG/BG 38125 F09 Figure 9. Fault Timeout Operation 38125fb 20 LTC3812-5 APPLICATIONS INFORMATION to boost this voltage above 4.7V. In this mode, EXTVCC is grounded and the NMOS is chosen to handle the worstcase power dissipation: PMOSFET = (VIN(MAX))[(f)(QG(TOP) + QG(BOTTOM) + 3mA] To operate properly, the fault timeout operation must be disabled by choosing RNDRV > (VIN(MAX) – 5.5V – VT)/270μA If the required RNDRV value results in an unacceptable value for VIN(MIN) (see Equation 1), fault timeout operation can also be disabled by connecting a 500k to 1M resistor from RUN/SS to INTVCC. Using Trickle Charge Mode Trickle charge mode is selected by shorting NDRV and INTVCC and connecting EXTVCC to VOUT. Trickle charge mode has the advantage of not requiring an external MOSFET but takes longer to start up due to slow charge up of CINTVCC through RPULLUP (tDELAY = 0.77 • RPULLUP • CINTVCC) and usually requires a larger INTVCC capacitor value to hold up the supply voltage during start-up. Once the INTVCC voltage reaches the trickle charge UV threshold of 9V, the drivers will turn on and start discharging CINTVCC at a rate determined by the driver current IG. In order to ensure proper start-up, CINTVCC must be chosen large enough so that the EXTVCC voltage reaches the switchover threshold of 4.7V before CINTVCC discharges below the falling UV threshold of 4V. This is ensured if: CINTVCC > IG • Larger of COUT 5.5 • 105 • CSS or IMAX VOUT(REG) In this mode, INTVCC, EXTVCC and NDRV must be shorted together. INTVCC Supply and the EXTVCC Connection The LTC3812-5 contains an internal low dropout regulator to produce the 5.5V INTVCC supply from the EXTVCC pin voltage. This regulator turns on when the EXTVCC pin is above 4.7V and remains on until EXTVCC drops below 4.45V. This allows the IC/MOSFET power to be derived from the output or an output derived boost network during normal operation and from the external NMOS from VIN during start-up or short-circuit. Using the EXTVCC pin in this way results in significant efficiency gains compared to what would be possible when deriving this power continuously from the typically much higher VIN voltage. The EXTVCC connection also allows the power supply to be configured in trickle charge mode in which it starts up with a high-valued “bleed” resistor connected from VIN to INTVCC to charge up the INTVCC capacitor. As soon as the output rises above 4.7V the internal EXTVCC regulator takes over before the INTVCC capacitor discharges below the UV threshold. When the EXTVCC regulator is active, the EXTVCC pin can supply up to 50mA RMS. Do not apply more than 15V to the EXTVCC pin. The following list summarizes the possible connections for EXTVCC: 1. EXTVCC grounded. This connection will require INTVCC to be powered continuously from an external NMOS from VIN resulting in an efficiency penalty as high as 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for 4.7V < VOUT < 15V and provides the highest efficiency. The power supply will start up using an external NMOS or a bleed resistor until the output supply is available. 3. EXTVCC connected to an output-derived boost network. If VOUT < 4.7V. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. 4. EXTVCC connected to INTVCC. This is the required connection for EXTVCC if INTVCC is connected to an external supply where the external supply is 4.2V < VEXT < 14V. 38125fb where IG is the gate drive current = (f)(QG(TOP) + QG(BOTTOM)) and IMAX is the maximum inductor current selected by VRNG. For RPULLUP, the value should fall in the following range to ensure proper start-up: Min RPULLUP > (VIN(MAX) – 14V)/ICCSR Max RPULLUP < (VIN(MIN) – 9V)/IQ,SHUTDOWN Using an External Supply Connected to the INTVCC If an external supply is available between 4.2V and 14V, the supply can be connected directly to the INTVCC pins. 21 LTC3812-5 APPLICATIONS INFORMATION Applications using large MOSFETs with a high input voltage and high frequency of operation may result in a large EXTVCC pin current. Due to the LTC3812-5 thermally enhanced package, maximum junction temperature will rarely be exceeded, however, it is good design practice to verify that the maximum junction temperature rating and RMS current rating are within the maximum limits. Typically, most of the EXTVCC current consists of the MOSFET gates current. In continuous mode operation, this EXTVCC current is: IEXTVCC = f(QG(TOP) + QG(BOTTOM)) + 3mA < 50mA The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics as follows: TJ = TA + IEXTVCC • (VEXTVCC – VINTVCC)(38°C/W) < 125°C If absolute maximum ratings are exceeded, consider using an external supply connected directly to the INTVCC pin. FEEDBACK LOOP/COMPENSATION Feedback Loop Types In a typical LTC3812-5 circuit, the feedback loop consists of the modulator, the output filter and load, and the feedback amplifier with its compensation network. All of these components affect loop behavior and must be accounted for in the loop compensation. The modulator and output filter consists of the internal current comparator, the output MOSFET drivers and the external MOSFETs, inductor and output capacitor. Current mode control eliminates the effect of the inductor by moving it to the inner loop, reducing it to a first order system. From a feedback loop point of view, it looks like a linear voltage controlled current source from ITH to VOUT and has a gain equal to (IMAXROUT)/1.2V. It has fairly benign AC behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. The external output capacitor and load cause a first order roll off at the output at the ROUTCOUT pole frequency, with the attendant 90° phase shift. This roll off is what filters the PWM waveform, resulting in the desired DC output voltage. The output capacitor also contributes a zero at the COUTRESR frequency which adds back the 90° phase and cancels the first order roll off. So far, the AC response of the loop is pretty well out of the user’s control. The modulator is a fundamental piece of the LTC3812-5 design and the external output capacitor is usually chosen based on the regulation and load current requirements without considering the AC loop response. The feedback amplifier, on the other hand, gives us a handle with which to adjust the AC response. The goal is to have 180° phase shift at DC (so the loop regulates), and something less than 360° phase shift (preferably about 300°) at the point that the loop gain falls to 0dB, i.e., the crossover frequency, with as much gain as possible at frequencies below the crossover frequency. Since the modulator/output filter is a first order system with maximum of 90° phase shift (at frequencies below fSW/4) and the feedback amplifier adds another 90° of phase shift, some phase boost is required at the crossover frequency to achieve good phase margin. If the ESR zero is below the crossover frequency, this zero may provide enough phase boost to achieve the desired phase margin and the only requirement of the compensation will be to guarantee that the gain is below zero at frequencies above fSW/4. If the ESR zero is above the crossover frequency, the feedback amplifier will probably be required to provide phase boost. For most LTC3810 applications, Type 2 compensation will provide enough phase boost; however some applications where high bandwidth is required with low ESR ceramics and lots of bulk capacitance, Type 3 compensation may be necessary to provide additional phase boost. The two types of compensation networks, “Type 2” and “Type 3” are shown in Figures 10 and 11. When component values are chosen properly, these networks provide C2 IN R1 FB RB VREF R2 C1 GAIN (dB) PHASE (DEG) –6dB/OCT GAIN –6dB/OCT – OUT 0 FREQ –90 PHASE –180 –270 –360 38125 F10 + Figure 10. Type 2 Schematic and Transfer Function 38125fb 22 LTC3812-5 APPLICATIONS INFORMATION IN C3 R1 R3 FB R2 C2 C1 GAIN (dB) –6dB/OCT – OUT 0 GAIN +6dB/OCT –6dB/OCT FREQ –90 RB VREF + PHASE –180 –270 –360 38125 F11 Figure 11. Type 3 Schematic and Transfer Function a “phase bump” at the crossover frequency. Type 2 uses a single pole-zero pair to provide up to about 60° of phase boost while Type 3 uses two poles and two zeros to provide up to 150° of phase boost. Feedback Component Selection Selecting the R and C values for a typical Type 2 or Type 3 loop is a nontrivial task. The applications shown in this data sheet show typical values, optimized for the power components shown. They should give acceptable performance with similar power components, but can be way off if even one major power component is changed significantly. Applications that require optimized transient response will require recalculation of the compensation values specifically for the circuit in question. The underlying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. Modulator gain and phase can be obtained in one of three ways: measured directly from a breadboard, or if the appropriate parasitic values are known, simulated or generated from the modulator transfer function. Measurement will give more accurate results, but simulation or transfer function can often get close enough to give a working system. To measure the modulator gain and phase directly, wire up a breadboard with an LTC3812-5 and the actual MOSFETs, inductor and input and output capacitors that the final design will use. This breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the LTC3812-5, no long wires connecting components, appropriately sized ground returns, etc. Wire the feedback amplifier with a 0.1μF feedback capacitor from ITH to FB and a 10k to 100k resistor from VOUT to FB. Choose the bias resistor (RB) as required to set the desired output voltage. Disconnect RB from ground and connect it to a signal generator or to the source output of a network analyzer to inject a test signal into the loop. Measure the gain and phase from the ITH pin to the output node at the positive terminal of the output capacitor. Make sure the analyzer’s input is AC coupled so that the DC voltages present at both the ITH and VOUT nodes don’t corrupt the measurements or damage the analyzer. If breadboard measurement is not practical, a SPICE simulation can be used to generate approximate gain/phase curves. Plug the expected capacitor, inductor and MOSFET values into the following SPICE deck and generate an AC plot of VOUT/VITH with gain in dB and phase in degrees. Refer to your SPICE manual for details of how to generate this plot. *3810 modulator gain/phase *2006 Linear Technology *this file simulates a simplified model of *the LTC3810 for generating a v(out)/v(ith) *bode plot .param rdson=.0135 ;MOSFET rdson .param Vrng=2 ;use 1.4 for INTVCC and 0.7 for ground .param vsnsmax={0.173*Vrng-0.026} .param Imax={vsnsmax/rdson} .param DL=4 ;inductor ripple current *inductor current gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2} *output cap cout out out2 270u ;capacitor value resr out2 0 0.018 ;capacitor ESR *load Rout out 0 2 ; load resistor vstim ith 0 0 ac 1 ;ac stimulus .ac dec 100 100 10meg .probe .end 38125fb PHASE (DEG) 23 LTC3812-5 APPLICATIONS INFORMATION Mathematical software such as MATHCAD or MATLAB can also be used to generate plots using the following transfer function of the modulator: H(s) = VSENSE(MAX) 1.2 • RDS(ON) s = j2 f With the gain/phase plot in hand, a loop crossover frequency can be chosen. Usually the curves look something like Figure 12. Choose the crossover frequency about 25% of the switching frequency for maximum bandwidth. Although it may be tempting to go beyond fSW/4, remember that significant phase shift occurs at half the switching frequency that isn’t modeled in the above H(s) equation and PSPICE code. Note the gain (GAIN, in dB) and phase (PHASE, in degrees) at this point. The desired feedback amplifier gain will be –GAIN to make the loop gain at 0dB at this frequency. Now calculate the needed phase boost, assuming 60° as a target phase margin: BOOST = – (PHASE + 30°) If the required BOOST is less than 60°, a Type 2 loop can be used successfully, saving two external components. BOOST values greater than 60° usually require Type 3 loops for satisfactory performance. Finally, choose a convenient resistor value for R1 (10k is usually a good value). Now calculate the remaining values: • 1+ s • RESR • COUT • RL (2) 1+ s • RL • COUT (K is a constant used in the calculations) f = chosen crossover frequency G = 10(GAIN/20) (this converts GAIN in dB to G in absolute gain) TYPE 2 Loop: BOOST + 45° 2 1 C2 = 2 • f • G • K • R1 K = tan C1= C2 K 2 1 R2 = ( ) K 2 • f • C1 V (R1) RB = REF VOUT VREF TYPE 3 Loop: BOOST + 45° 4 1 C2 = 2 • f • G • R1 C1= C2 (K 1) K = tan2 K 2 • f • C1 R1 R3 = K1 1 C3 = 2 f K • R3 V (R1) RB = REF VOUT VREF R2 = SPICE or mathematical software can be used to generate the gain/phase plots for the compensated power supply to do a sanity check on the component values before trying them out on the actual hardware. For software, use the following transfer function: T(s) = A(s)H(s) 38125fb PHASE (DEG) GAIN (dB) GAIN 0 0 PHASE –90 –180 FREQUENCY (Hz) 38125 F12 Figure 12. Transfer Function of Buck Modulator 24 LTC3812-5 APPLICATIONS INFORMATION where H(s) was given in equation 2 and A(s) depends on compensation circuit used: Type 2: A (s) = 1+ s • R3 • C2 s • RFB1 • (C2 + C3) • 1+ s • R3 • C2 • C3 C2 + C3 threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. To prevent forcing current back into the main power supply, potentially boosting the input supply to a dangerous voltage level, forced continuous mode of operation is disabled when the RUN/SS voltage is below 2.5V during soft-start or tracking. During these two periods, the PGOOD signal is forced low. In addition to providing a logic input to force continuous operation, the FCB pin provides a mean to maintain a flyback winding output when the primary is operating in pulse skip mode. The secondary output VOUT2 is normally set as shown in Figure 13 by the turns ratio N of the transformer. However, if the controller goes into pulse skip mode and halts switching due to a light primary load current, then VOUT2 will droop. An external resistor divider from VOUT2 to the FCB pin sets a minimum voltage VOUT2(MIN) below which continuous operation is forced until VOUT2 has risen above its minimum. VOUT2(MIN) = 0.8V 1+ Table 1 FCB PIN DC Voltage: 0V to 0.75V DC Voltage: ≥0.85V Feedback Resistors CONDITION Forced Continuous Current Reversal Enabled Pulse Skip Mode Operation No Current Reversal Regulating a Secondary Winding Type 3: A (s) = 1 • s • R1• (C2 + C3) (1+ s • (R1+ R3) • C3) • (1+ s • R2 • C1) (1+ s • R3 • C3) • 1+ s • R2 • C1• C2 C1+ C2 For SPICE, replace VSTIM line in the previous PSPICE code with following code and generate a gain/phase plot of V(out)/V(outin): rfb1 outin vfb 52.5k rfb2 vfb 0 10k eithx ithx 0 laplace {0.8-v(vfb)} = {1/(1+s/1000)} eith ith 0 value={limit(1e6*v(ithx),0,2.4)} cc1 ith vfb 4p cc2 ith x1 8p rc x1 vfb 210k rf outin x2 11k ;delete this line for Type 2 cf x2 vfb 120p ;delete this line for Type 2 vstim out outin dc=0 ac=1m R4 R3 + VIN VIN CIN 1N4148 PULSE SKIP MODE OPERATION AND FCB PIN The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.8V threshold enables pulse skip mode operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in VIN. Tying the FCB pin below the 0.8V LTC3812-5 R4 FCB R3 SGND BG PGND SW Figure 13. Secondary Output Loop • T1 1:N TG + • + VOUT2 COUT2 1μF VOUT1 COUT 38125 F13 38125fb 25 LTC3812-5 APPLICATIONS INFORMATION FAULT CONDITIONS: CURRENT LIMIT AND FOLDBACK The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3812-5, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX) RDS(ON) T RUN/SOFT-START FUNCTION The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC3812-5. Soft-start reduces the input supply’s surge current by controlling the ramp rate of the output voltage, eliminates output overshoot and can also be used for power supply sequencing. Pulling RUN/SS below 1.5V puts the LTC3812-5 into a low quiescent current shutdown (IQ = 224μA). This pin can be driven directly from logic as shown in Figure 14. Releasing the RUN/SS pin allows an internal 1.4μA current source to charge up the soft-start capacitor, CSS. When the voltage on RUN/SS reaches 1.5V, the LTC3812-5 turns on and begins regulating the output to VFB = VSS – 1.5V. As the RUN/SS voltage increases from 1.5V to 2.3V, the output voltage is raised from 0% to 100% of its regulated value. Current foldback, forced continuous mode and fault timeout are disabled during this soft-start phase and PGOOD signal is forced low. The RUN/SS voltage continues to charge until it reaches its internally clamped value of 4V. If RUN/SS starts at 0V, the delay before starting is approximately: tDELAY,START = 1.5V C = (1.1s/µF ) CSS 1.4µA SS + 1 I 2L The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same percentage below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. To further limit current in the event of a short-circuit to ground, the LTC3812-5 includes foldback current limiting. If the output falls by more than 60%, then the maximum sense voltage is progressively lowered to about one tenth of its full value. Be aware also that when the fault timeout is enabled for the external NMOS regulator, an over current limit may cause the output to fall below the minimum 4.5V UV threshold. This condition will cause a linear regulator timeout/restart sequence as described in the Linear Regulator Timeout section if this condition persists. plus an additional delay, before the output will reach its regulated value of: tDELAY,REG 0.8V C = ( 0.6s/µF ) CSS 1.4µA SS The start delay can be reduced by using diode D1 in Figure 14. 3.3V OR 5V D1 CSS CSS 38125 F14 RUN/SS RUN/SS Figure 14. RUN/SS Pin Interfacing 38125fb 26 LTC3812-5 APPLICATIONS INFORMATION EFFICIENCY CONSIDERATIONS The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3812-5 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from the second term of the PMAIN equation found in the Power MOSFET Selection section. When transition losses are significant, efficiency can be improved by lowering the frequency and/or using a top MOSFET(s) with lower CRSS at the expense of higher RDS(ON). 3. INTVCC current. This is the sum of the MOSFET driver and control currents. Control current is typically about 3mA and driver current can be calculated by: IGATE = f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are the gate charges of the top and bottom MOSFETs. This loss is proportional to the supply voltage that INTVCC is derived from, i.e., VIN for the external NMOS linear regulator, VOUT for the internal EXTVCC regulator, or VEXT when an external supply is connected to INTVCC. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. CHECKING TRANSIENT RESPONSE The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. DESIGN EXAMPLE As a design example, take a supply with the following specifications: VIN = 12V to 60V, VOUT = 5V ±5%, IOUT(MAX) = 6A, f = 250kHz. First, calculate the timing resistor: RON = 5V = 110k 2.4V • 250kHz • 76pF and choose the inductor for about 40% ripple current at the maximum VIN: L= 5V 5V 1 = 7.6μH 250kHz • 0.4 • 6 A 60 V With a 7.7μH inductor, ripple current will vary from 1.5A to 2.4A (25% to 40%) over the input supply range. Next, choose the bottom MOSFET switch. Since the drain of the MOSFET will see the full supply voltage 60V 38125fb 27 LTC3812-5 APPLICATIONS INFORMATION (max) plus any ringing, choose an 60V MOSFET. The Si7850DP has: BVDSS = 60V RDS(ON) = 25mΩ (max)/31mΩ (nom), δ = 0.007/°C, , CMILLER = (8.3nC – 2.8nC)/30V = 183pF VGS(MILLER) = 3.8V, θJA= 22°C/W. This yields a nominal sense voltage of: VSNS(NOM) = 6A • 1.3 • 0.025Ω = 195mV To guarantee proper current limit at worst-case conditions, increase nominal VSNS by at least 50% to 320mV (by tying VRNG to 2V). To check if the current limit is acceptable at VSNS = 320mV, assume a junction temperature of about 55°C above a 70°C ambient (ρ125°C = 1.7): ILIMIT 320mV 1 + • 2.4A = 7.3A 1.7 • 0.031 2 the EXTVCC pin. A small SOT23 MOSFET such as the ZXMN10A07F can be used for the pass device if fault timeout is enabled. Choose RNDRV to guarantee that fault timeout is enabled when power dissipation of M3 exceeds 0.4W (max for 70°C ambient): ICC = 250kHz • 2 • 18nC + 3mA = 12mA RNDRV 0.4W / 0.012A – 3V = 112k 270µA So, choose RNDRV = 100k. CIN is chosen for an RMS current rating of about 3A at 85°C. The output capacitors are chosen for a low ESR of 0.018Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: ΔVOUT(RIPPLE) = ΔIL(MAX) • ESR = 2.4A • 0.018Ω = 43mV However, a 0A to 6A load step will cause an output change of up to: ΔVOUT(STEP) = ΔILOAD • ESR = 6A • 0.018Ω = 108mV An optional 10μF ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 15. PC Board Layout Checklist When laying out a PC board follow one of two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. • Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3812-5. Use several bigger vias for power components. 38125fb and double-check the assumed TJ in the MOSFET: 60V 5V PBOT = • 7.3A 2 • 1.7 • 0.031 = 2.6W 60 V TJ = 70°C + 2.6W • 22°C/W = 127°C Verify that the Si7850DP is also a good choice for the top MOSFET by checking its power dissipation at current limit and maximum input voltage, assuming a junction temperature of 30°C above a 70°C ambient (ρ100°C = 1.5): PMAIN = 5V • 7.3A 2 (1.5 • 0.031 ) 60 V 7.3A 1 1 • 250kHz + 60V 2 • • 2 • 183pF • + 2 5V 3.8 V 3.8 V = 0.206W + 1.32W = 1.53W TJ = 70°C + 1.53W • 22°C/W = 104°C The junction temperature will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in this circuit. Since VOUT > 4.7V, the INTVCC voltage can be generated from VOUT with the internal LDO by connecting VOUT to 28 LTC3812-5 APPLICATIONS INFORMATION • Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. • Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. • Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. • Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. • Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. • Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and SGND pins. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. • Connect the bottom driver decoupling capacitor CINTVCC closely to the INTVCC and PGND pins. RON 110k CON 100pF 1 100k PGOOD 2 3 ION VRNG BOOST LTC3812-5 TG SW PGND BG RUN/SS SGND INTVCC EXTVCC NDRV CC2 47pF RFB2 1.89k RC 200k SGND RFB1 10k RNDRV 100k M3 ZXMN10A07F DB BAS19 16 15 14 13 12 11 10 9 CVCC 1μF CDRVCC 0.1μF CB 0.1μF CIN1 68μF 100V CIN2 1μF 100V PGND VIN 12V TO 60V 150k CSS 1000pF PGOOD 4 FCB 5 ITH 6 VFB 7 8 M1 Si7850DP L1 7.7μH VOUT 5V 6A COUT1 270μF 6.3V COUT2 10μF 6.3V M2 Si7850DP D1 B1100 CC1 5pF PGND 38125 F15 Figure 15. 12V to 60V Input Voltage to 5V/6A 38125fb 29 LTC3812-5 TYPICAL APPLICATIONS 7V to 60V Input Voltage to 5V/5A with IC Power from 12V Supply and All Ceramic Output Capacitors 12V CIN1 68μF 100V CIN2 1μF 80V PGND VIN 7V TO 60V RON 110k CON 100pF 1 2 PGOOD 3 ION VRNG BOOST LTC3812-5 TG SW PGND BG RUN/SS SGND INTVCC EXTVCC NDRV CC2 200pF RFB2 1.89k RC 100k CC1 5pF SGND RFB1 10k DB BAS19 16 15 14 13 12 11 10 9 CVCC 1μF CDRVCC 0.1μF CB 0.1μF CSS 1000pF PGOOD 4 FCB 5 ITH 6 VFB 7 8 M1 Si7850DP L1 4.7μH VOUT 5V 5A M2 Si7850DP D1 B1100 C5 22μF PGND COUT1 47μF 6.3V ×3 38125 TA02 15V to 60V Input Voltage to 3.3V/5A with Fault Timeout and Pulse Skip Disabled VIN 15V TO 60V RON 71.5k CON 100pF 1 2 PGOOD 3 ION VRNG BOOST LTC3812-5 TG SW PGND BG RUN/SS SGND INTVCC EXTVCC NDRV CC2 47pF RFB2 3.2k RC 200k SGND RFB1 10k RNDRV 250k M3 ZVN4210G DB BAS19 16 15 14 13 12 11 10 9 CVCC 1μF CDRVCC 0.1μF CB 0.1μF CIN1 68μF 100V CIN2 1μF 100V PGND CSS 1000pF PGOOD 4 FCB 5 ITH 6 VFB 7 8 M1 Si7850DP L1 4.7μH VOUT 3.3V 5A COUT1 270μF 6.3V COUT2 10μF 6.3V M2 Si7850DP D1 B1100 CC1 5pF PGND 38125 TA03 38125fb 30 LTC3812-5 PACKAGE DESCRIPTION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BA 4.90 – 5.10* (.193 – .201) 2.74 (.108) 16 1514 13 12 1110 9 2.74 (.108) 6.60 ±0.10 4.50 ±0.10 SEE NOTE 4 2.74 (.108) 0.45 ±0.05 1.05 ±0.10 0.65 BSC 2.74 6.40 (.108) (.252) BSC RECOMMENDED SOLDER PAD LAYOUT 12345678 1.10 (.0433) MAX 0° – 8° 4.30 – 4.50* (.169 – .177) 0.25 REF 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE16 (BA) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 38125fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC3812-5 TYPICAL APPLICATION 15V to 60V Input Voltage to 12V/5A with Trickle Charger Start-Up CIN1 68μF 100V CIN2 1μF 100V PGND VIN 15V TO 60V RON 261k CON 100pF 1 2 PGOOD 3 ION VRNG BOOST LTC3812-5 TG SW PGND BG RUN/SS SGND INTVCC EXTVCC NDRV CC2 47pF RFB2 1k RC 200k SGND RFB1 14k RNDRV 250k DB BAS19 16 15 14 13 12 11 10 9 CVCC 1μF C5 22μF CDRVCC 0.1μF M2 Si7850DP CB 0.1μF M1 Si7850DP CSS 1000pF PGOOD 4 FCB 5 ITH 6 VFB 7 8 L1 10μH VOUT 12V 5A COUT1 270μF 16V COUT2 10μF 16V D1 B1100 CC1 5pF PGND 38125 TA04 RELATED PARTS PART NUMBER LT 1074HV/LT1076HV LTC1735 LTC1778 LT1956 LT3010 LT3430/LT3431 LT3433 LTC3703 LT3800 LTC3810 LTC3810-5 LTC3835 LT3844 LT3845 ® DESCRIPTION Monolithic 5A/2A Step-Down DC/DC Converters Synchronous Step-Down DC/DC Controller No RSENSE™ Synchronous DC/DC Controller Monolithic 1.5A, 500kHz Step-Down Regulator 50mA, 3V to 80V Linear Regulator Monolithic 3A, 200kHz/500kHz Step-Down Regulator Monolithic Step-Up/Step-Down DC/DC Converter 100V Synchronous DC/DC Controller 60V Synchronous DC/DC Controller 100V Synchronous DC/DC Controller No RSENSE Current Mode Controller Low IQ Synchronous DC/DC Controller 60V Non-Synchronous DC/DC Controller 60V Synchronous DC/DC Controller COMMENTS VIN Up to 60V, TO-220 and DD Packages 3.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, Current Mode, IOUT ≤ 20A 4V ≤ VIN ≤ 36V, Fast Transient Response, Current Mode, IOUT ≤ 20A 5.5V ≤ VIN ≤ 60V, 2.5mA Supply Current, 16-Pin SSOP 1.275V ≤ VOUT ≤ 60V, No Protection Diode Required, 8-Lead MSOP 5.5V ≤ VIN ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP 4V ≤ VIN ≤ 60V, 500mA Switch, Automatic Step-Up/Step-Down, VIN Up to 100V, 9.3V to 15V Gate Drive Supply 4V ≤ VIN ≤ 60V, 200kHz, Low IQ VIN Up to 100V, Current Mode, No RSENSE Required VIN Up to 60V, IOUT ≤ 20A, Large 1Ω Gate Drivers VIN: 4V to 36V, VOUT: 0.8V to 10V 4V ≤ VIN ≤ 60V, 100kHz to 600kHz, Low IQ 4V ≤ VIN ≤ 60V, 100kHz to 600kHz, Low IQ No RSENSE is a trademark of Linear Technology Corporation. 38125fb 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0408 REV B • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007