LTC3828

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LTC3828 Dual, 2-Phase Step-Down Controller with Tracking DESCRIPTIO The LTC®3828 is a dual high performance step-down switching regulator controller that drives all N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows for a phaselockable frequency of up to 550kHz. The TRCKSS pin provides both soft-start and tracking functions. Multiple LTC3828s can be daisy-chained in applications requiring more than two voltages to be tracked. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The precision 0.8V reference and power good output indicator are compatible with a wide 4.5V to 28V (30V maximum) input supply range, encompassing all battery chemistries. The RUN pins control their respective channels independently. The FCB/PLLIN pin selects among Burst Mode® operation, skip-cycle mode and continuous current mode. Current foldback limits MOSFET dissipation during shortcircuit conditions. Reverse current and current foldback functions are disabled during soft-start. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6304066, 6580258 Dual, 180° Phased Controllers Reduce Required Input Capacitance and Power Supply Induced Noise Tracking for Both Outputs Constant Frequency Current Mode Control Wide VIN Range: 4.5V to 28V Operation Power Good Output Voltage Indicator Adjustable Soft-Start Current Ramping Foldback Output Current Limiting– Disabled at Start-Up No Reverse Current During Soft-Start Interval Clock Output for 3-, 4-, 6-Phase Operation Dual N-Channel MOSFET Synchronous Drive ±1% Output Voltage Accuracy Phase-Lockable Fixed Frequency 260kHz to 550kHz OPTI-LOOP® Compensation Minimizes COUT Very Low Dropout Operation: 99% Duty Cycle Output Overvoltage Protection Small 28-Lead SSOP and 5mm × 5mm QFN Packages APPLICATIO S ■ ■ ■ Telecom Infrastructure ASIC Power Supply Industry Equipment TYPICAL APPLICATIO High Efficiency Dual 2.5V/3.3V Step-Down Converter with Tracking 4.7µF + VIN PGOOD INTVCC TG1 TG2 BOOST2 SW2 LTC3828 BG2 PGND SENSE2 + 1000pF SENSE1– VOSENSE1 SENSE2 – VOSENSE2 TRCKSS1 ITH2 SGND RUN2 220pF 15k 0.1µF 1µF CERAMIC 3.2µH 0.1µF BOOST1 SW1 BG1 500kHz FCB/PLLIN SENSE1 + 0.01Ω 1000pF 3.3V 5A 63.4k 1% 63.4k 1% 20k 20k 1% 1% 0.1µF TRCKSS2 ITH1 220pF 15k RUN1 TRCKSS1 20k 1% 0.1µF + 47µF 4V SP U U U 4.5V TO 28V 22µF 50V CERAMIC 3.2µH 0.01Ω 42.5k 1% 2.5V 5A 56µF 4V SP + 3828 TA01 3828f 1 LTC3828 ABSOLUTE AXI U RATI GS Input Supply Voltage (VIN)........................ 30V to – 0.3V Top Side Driver Voltages (BOOST1, BOOST2) .................................. 36V to – 0.3V Switch Voltage (SW1, SW2) ........................ 30V to – 5V INTVCC, DRVCC, RUN1, RUN2, (BOOST1-SW1), (BOOST2-SW2) .......................................... 7V to – 0.3V SENSE1+, SENSE2 +, SENSE1–, SENSE2 – Voltages ....................... (1.1)INTVCC to – 0.3V FCB/PLLIN, PLLFLTR, CLKOUT, PHSMD Voltage .............................. INTVCC to – 0.3V TRCKSS1, TRCKSS2 ........................... INTVCC to – 0.3V PACKAGE/ORDER I FOR ATIO TOP VIEW TRCKSS1 ITH1 SENSE1+ SENSE1– VOSENSE1 PLLFLTR RUN1 FCB/PLLIN SGND 1 2 3 4 5 6 7 8 9 28 CLKOUT 27 PGOOD 26 BOOST1 25 TG1 24 SW1 23 VIN 22 INTVCC 21 PGND 20 BG1 19 BG2 18 SW2 17 TG2 16 BOOST2 15 RUN2 G PACKAGE 28-LEAD PLASTIC SSOP TRCKSS1 SENSE1– SENSE1+ CLKOUT BOOST1 PGOOD ITH1 LTC3828EG 32 31 30 29 28 27 26 25 VOSENSE1 1 PLLFLTR 2 RUN1 3 PHSMD 4 FCB/PLLIN 5 SGND 6 TRCKSS2 7 NC 8 9 10 11 12 13 14 15 16 33 24 SW1 23 VIN 22 INTVCC 21 DRVCC 20 PGND 19 BG1 18 BG2 17 SW2 TG1 ORDER PART NUMBER TRCKSS2 10 SENSE2– 11 SENSE2+ 12 ITH2 13 VOSENSE2 14 SENSE2– SENSE2+ RUN2 ITH2 VOSENSE2 BOOST2 TG2 NC TJMAX = 125°C, θJA = 95°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN1, 2 = 5V unless otherwise noted. SYMBOL VOSENSE1, 2 IVOSENSE1, 2 VREFLNREG VLOADREG PARAMETER Regulated Feedback Voltage Feedback Current Output Voltage Load Regulation CONDITIONS (Note 3); ITH1, 2 Voltage = 1.2V (Note 3) (Note 3) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 2.0V ITH1, 2 = 1.2V; Sink/Source 5uA; (Note 3) ● ELECTRICAL CHARACTERISTICS Main Control Loops 0.792 0.800 ±5 0.002 ● ● Reference Voltage Line Regulation VIN = 4.6V to 28V (Note 3) gm1, 2 Transconductance Amplifier gm 2 U U W WW U W (Note 1) PGOOD ..................................................... 5.5V to –0.3V ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ...2.7V to – 0.3V Peak Output Current fOSC IPGOOD = 2mA VPGOOD = 5V VOSENSE with Respect to Set Output Voltage VOSENSE Ramping Negative VOSENSE Ramping Positive –6 6 –7.5 7.5 360 230 480 4.8 ● ELECTRICAL CHARACTERISTICS CONDITIONS ITH1, 2 = 1.2V; (Note 3) (Note 4) VIN = 15V; VOUT1 = 5V VRUN/SS1, 2 = 0V ● MIN TYP 3 2 20 MAX UNITS MHz 3 100 0.84 – 0.1 4.8 4 0.88 mA µA V µA V V V µA % µA VFCB IFCB VBINHIBIT UVLO VOVL ISENSE DFMAX ITRCKSS1,2 VRUN1, 2 ON VSENSE(MAX) 0.76 – 0.50 0.800 – 0.18 4.3 VFCB = 0.85V Measured at FCB pin VIN Ramping Down Measured at VOSENSE1, 2 (Each Channel); VSENSE1–, 2 – = VSENSE1+, 2+ = 0V In Dropout ● ● 3.5 0.84 – 90 98 0.5 1.0 62 60 0.86 – 65 99.4 1.2 1.5 75 75 55 55 65 55 60 80 120 5.0 0.2 400 260 550 –17 17 0.1 2.0 85 88 100 100 120 100 V mV mV ns ns ns ns ns ns ns TG1, 2 tr TG1, 2 tf BG1, 2 tr BG1, 2 tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCC VLDO INT fNOM fLOW fHIGH I PLLFLTR INTVCC Linear Regulator 5.2 2.0 440 290 590 V % kHz kHz kHz µA µA 0.3 ±1 – 9.5 9.5 V µA % % Oscillator and Phase-Locked Loop PGOOD Output VPGL IPGOOD VPG 3828f 3 LTC3828 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3828UH: TJ = TA + (PD • 34°C/W) LTC3828G: TJ = TA + (PD • 95°C/W) Note 3: The IC is tested in a feedback loop that servos VITH1, 2 to a specified voltage and measures the resultant VOSENSE1, 2. Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 6: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥ 40% of IMAX (see minimum on-time considerations in the Applications Information section). Note 7: The LTC3828E is guaranteed to meet performance specifications over the –40°C to 85°C operating temperature range as assured by design, characterization and correlation with statistical process controls. TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Output Current and Mode (Figure 14) 100 100 VIN = 7V 90 VIN = 15V Burst Mode 90 OPERATION 80 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) VIN = 20V 70 60 50 40 30 20 10 0 0.001 CONSTANT FREQUENCY (BURST DISABLE) FORCED CONTINUOUS MODE 0.01 1 0.1 OUTPUT CURRENT (A) Supply Current vs Input Voltage (Figure 14) 1200 1000 BOTH CONTROLLERS ON 5.2 5.0 UNDERVOLTAGE LOCKOUT (V) SUPPLY CURRENT (µA) 800 600 400 200 SHUTDOWN 0 0 5 10 15 20 INPUT VOLTAGE (V) 25 30 3828 G04 INTVCC VOLTAGE (V) 4 UW VIN =15V VOUT = 5V F = 260kHz 3828 G01 TA = 25°C unless otherwise noted. Efficiency vs Input Voltage (Figure 14) 100 Efficiency vs Output Current (Figure 14) 90 80 80 70 70 60 VOUT = 5V F = 260kHz 0.01 1 0.1 OUTPUT CURRENT (A) 10 3828 G02 60 10 50 0.001 50 5 10 15 20 INPUT VOLTAGE (V VOUT = 5V IOUT = 3A F = 260kHz 25 30 3828 G03 Internal 5V LDO Line Regulation ILOAD = 1mA 3.8 Undervoltage Lockout vs Temperature 3.6 4.8 4.6 4.4 4.2 4.0 3.4 3.2 0 5 10 15 20 INPUT VOLTAGE (V) 25 30 3828 G05 3.0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 3828 G06 3828f LTC3828 TYPICAL PERFOR A CE CHARACTERISTICS Oscillator Frequency vs Temperature 700 600 VPLLFLTR = 2.4V 1.5 1.3 CURRENT SENSE INPUT CURRENT (µA) 50 25 75 0 TEMPERATURE (°C) 100 125 FREQUENCY (kHz) 500 400 300 200 100 0 –50 –25 VPLLFLTR = 1.2V TRCKSS CURRENT (µA) VPLLFLTR = 0V 50 25 75 0 TEMPERATURE (°C) Maximum Current Sense Threshold vs Temperature 80 VOUT = 5V 78 5.0 5.1 76 NORMALIZED VOUT (%) INTVCC VOLTAGE (V) VSENSE (mV) 74 72 70 –50 –25 50 25 75 0 TEMPERATURE (°C) Maximum Current Sense Threshold vs Duty Factor 75 80 70 60 VSENSE (mV) VSENSE (mV) 50 VSENSE (mV) 25 0 0 20 40 60 DUTY FACTOR (%) 3828 G13 UW 100 3828 G07 TA = 25°C unless otherwise noted. Current Sense Pin Input Current vs Temperature 37 TRCKSS Current vs Temperature 35 1.1 33 0.9 0.7 31 125 0.5 –50 –25 29 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3828 G08 3828 G09 INTVCC Voltage vs Temperature 0 Load Regulation FCB = 0V VIN = 15V FIGURE 14 – 0.1 4.9 – 0.2 4.8 – 0.3 100 125 4.7 –50 –25 – 0.4 50 25 75 0 TEMPERATURE (°C) 100 125 0 1 3 2 LOAD CURRENT (A) 4 5 3828 G12 3828 G10 3828 G11 Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) 80 Maximum Current Sense Threshold vs Sense Common Mode Voltage 75 50 40 30 20 10 0 70 65 80 100 60 0 0.25 0.5 0.75 1.0 PERCENT ON NOMINAL OUTPUT VOLTAGE (%) 3828 G14 0 1 3 4 2 COMM0N MODE VOLTAGE (V) 5 3828 G15 3828f 5 LTC3828 TYPICAL PERFOR A CE CHARACTERISTICS Current Sense Threshold vs ITH Voltage 80 70 DROPOUT VOLTAGE (V) 60 50 VSENSE (mV) 40 30 20 10 0 –10 –20 0 0.5 1.5 1.0 VITH (V) 2.0 2.5 3828 G16 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) 3.5 4.0 3828 G17 ISENSE (µA) Soft Start-Up: (Figure 14, with Coincident Tracking) VOUT1 1V/DIV VOUT2 1V/DIV VIN = 12V VOUT1 = 5V VOUT2 = 3.3V 5ms/DIV 3828 G19 Load Step: Burst Mode Operation (Figure 14) VOUT1 100mV/DIV VOUT2 100mV/DIV IL1 2A/DIV 50µs/DIV VIN = 12V VOUT1 = 5V VOUT2 = 3.3V LOAD STEP = 0A TO 3A WITH RATIOMETRIC TRACKING 6 UW TA = 25°C unless otherwise noted. Dropout Voltage vs Output Current (Figure 14) 4.0 3.5 3.0 2.5 50 100 SENSE Pins Total Source Current 0 –50 –100 0 5 1 2 3 4 VSENSE COMMON MODE VOLTAGE (V) 6 3828 G18 Soft Start-Up: (Figure 14, with Ratiometric Tracking) Soft Start-Up: (Figure 14, with Internal Soft Start-Up) VOUT1 1V/DIV VOUT2 1V/DIV VOUT1 1V/DIV VOUT2 1V/DIV VIN = 12V VOUT1 = 5V VOUT2 = 3.3V 2ms/DIV 3828 G20 VIN = 12V VOUT1 = 5V VOUT2 = 3.3V 100µs/DIV 3828 G21 Load Step: Continuous Mode (Figure 14) SW1 20V/DIV SW2 20V/DIV IIN 25A/DIV VIN RIPPLE 50mV/DIV 50µs/DIV VIN = 12V VOUT1 = 5V VOUT2 = 3.3V LOAD STEP = 0A TO 3A WITH RATIOMETRIC TRACKING Input Source/Capacitor Instantaneous Current (Figure 14) VOUT1 100mV/DIV VOUT2 100mV/DIV IL1 2A/DIV 500ns/DIV VIN = 12V VOUT1 = 5V VOUT2 = 3.3V IOUT5 = IOUT3.3 = 2A 3828 G23 3828 G24 3828 G22 3828f LTC3828 TYPICAL PERFOR A CE CHARACTERISTICS Burst Mode Operation (Figure 14) VOUT 20mV/DIV IL 1A/DIV VIN = 12V VOUT = 5V VFCB = OPEN IOUT = 20mA PI FU CTIO S ITH1, ITH2 (Pins 2, 13/Pins 30, 12): Error Amplifier Output and Switching Regulator Compensation Point. Each associated channels’ current comparator trip point increases with this control voltage. PHSMD (Pin 4, QFN Only): Control input to phase selector which determines the phase relationship between controller 1, controller 2 and the clockout signal. VOSENSE1, VOSENSE2 (Pins 5, 14/Pins 1, 13): Error Amplifier Feedback Input. Receives the remotely-sensed feedback voltage for each controller from an external resistive divider across the output. PLLFLTR (Pin 6/Pin 2): Filter Connection for PhaseLocked Loop. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. FCB/PLLIN (Pin 8/Pin 5): Forced Continuous Control Input and External Synchronization Input to Phase Detector. Pulling this pin below 0.8V will force continuous synchronous operation. Feeding an external clock signal will synchronize the LTC3828 to the external clock. SGND (Pin 9/Pin 6): Small Signal Ground. Common to both controllers, this pin must be routed separately from high current grounds to the common (–) terminals of the COUT capacitors. UW TA = 25°C unless otherwise noted. Constant Frequency (Burst Inhibit) Operation (Figure 14) VOUT 20mV/DIV IL 0.5A/DIV 100µs/DIV VIN = 12V VOUT = 5V VFCB = 5V IOUT = 20mA 2µs/DIV 3828 G25 3828 G26 U U U (SSOP/QFN) TRCKSS2, TRCKSS1 (Pins 10, 1/Pins 7, 29): Soft-Start and Output Voltage Tracking Inputs. When one channel is configured to be the master of two outputs a capacitor to ground at this pin sets the ramp rate. The slave channel tracks the output of the master channel by reproducing the VFB voltage of the master channel with a resistor divider and applying that voltage to its track pin. An internal 1.2µA soft-start current is always charging these pins. SENSE2 –, SENSE1 – (Pins 11, 4/Pins 10, 32): The (–) Input to the Differential Current Comparators. SENSE2 +, SENSE1 + (Pins 12, 3/Pins 11, 31): The (+) Input to the Differential Current Comparators. The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. RUN2, RUN1 (Pins 15, 7/Pins 14, 3): Run Control Inputs. Forcing RUN pins below 1V would shut down the circuitry required for that particular channel. Forcing the RUN pins over 2V would turn on the IC. BOOST2, BOOST1 (Pins 16, 26/Pins 15, 26): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the boost and switch pins and Schottky diodes are tied between the boost and INTVCC pins. Voltage swing at the boost pins is from INTVCC to (VIN + INTVCC). 3828f 7 LTC3828 PI FU CTIO S TG2, TG1 (Pins 17, 25/Pins 16, 25): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC – 0.5V superimposed on the switch node voltage SW. SW2, SW1 (Pins 18, 24/Pins 17, 24): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BG2, BG1 (Pins 19, 20/Pins 18, 19): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 21/Pin 20): Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs, anodes of the Schottky rectifiers and the (–) terminal(s) of CIN. DRVCC (Pin 21 QFN Only): External Power Input to gate drives. It can be connected with INTVCC together and use INTVCC as gate drives power supply. INTVCC (Pin 22/Pin 22): Output of the Internal 5V Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7µF tantalum or other low ESR capacitor. VIN (Pin 23/Pin 23): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. PGOOD (Pin 27/Pin 27): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on either VOSENSE pin is not within ±7.5% of its set point. CLKOUT (Pin 28/Pin 28): Output Clock Signal available to daisychain other controller ICs for additional MOSFET driver stages/phases. NC (Pins 8, 9 QFN Only): These “No Connect” pins are not tied internally to anything. On the PC layout, these pin landings should be connected to the SGND plane under the IC. Exposed Pad (Pin 33, QFN Only): Signal Ground. Must be soldered to the PCB, providing a local ground for the control components of the IC, and be tied to the PGND pin under the IC. 8 U U U 3828f LTC3828 FU CTIO AL DIAGRA PHSMD PHASE LOGIC CLKOUT PLLFLTR RLP CLP PGOOD PHASE DET CLK1 OSCILLATOR CLK2 – + – + – + 3V – + 4.5V – + BINH VOSENSE2 0.74V INTERNAL SUPPLY SGND (UH PACKAGE PAD) 0.86V VOSENSE1 0.74V 0.86V 5V LDO REG INTVCC 5V 0.18µA FCB/PLLIN PLL DETECTOR DUPLICATE FOR SECOND CONTROLLER CHANNEL DROP OUT DET S R Q Q 0.55V I1 + – – 0.86V 4(VFB) SLOPE COMP 45k – EA + 6V 100kΩ W 0.8V VREF VIN DRVCC U U + + – FCB DRVCC BOOST DB VIN TOP BOT TOP ON SWITCH LOGIC + – B FCB DRVCC BOT TG CB D1 + CIN SW BG PGND COUT + RSENSE SHDN – + I2 VOUT INTVCC SENSE + ++ 3mV – 30k – 30k SENSE 45k 2.4V 0.80V OV 1.2µA VFB VOSENSE TRCKSS R2 R1 CC CSS + – 0.86V ITH SHDN RST 4(VFB) RUN SOFT START RUN 3828 FD/F01 CC2 RC Figure 1 3828f 9 LTC3828 OPERATIO Main Control Loop The IC uses a constant frequency, current mode stepdown architecture with the two controller channels operating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VOSENSE pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VOSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 400ns every tenth cycle to allow CB to recharge. The main control loop is shut down by pulling the RUN pin low. When the RUN pin reaches 1.5V, the main control loop is enabled. When RUN1 is low, all controller functions are shut down, including the 5V regulator. Low Current Operation The FCB/PLLIN pin is a multifunction pin providing two functions: 1) to accept external clock signal; and 2) to select among three modes of light load operations. When the FCB/PLLIN pin voltage is below 0.8V, the controller forces continuous PWM current mode operation. In this mode, the top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB/PLLIN pin is below VINTVCC – 2V but greater than 0.8V, the controller 10 U (Refer to Functional Diagram) enters Burst Mode operation. Burst Mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will temporarily inhibit turn-on of both output MOSFETs until the output voltage drops. There is 60mV of hysteresis in the burst comparator B tied to the ITH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. When the FCB/PLLIN pin voltage is above 4.8V, the controller operates in constant frequency mode and the synchronous MOSFET is turned off when inductor current nears zero in each cycle. In order to prevent erratic operation if no external connections are made to the FCB/PLLIN pin, the FCB/PLLIN pin has a 0.18µA internal current source pulling the pin high. The following table summarizes the possible states available on the FCB/PLLIN pin: Table 1 FCB/PLLIN Pin 0V to 0.75V Condition Forced Continuous Both Controllers (Current Reversal Allowed— Burst Inhibited) Minimum Peak Current Induces Burst Mode Operation No Current Reversal Allowed Burst Mode Operation Disabled Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current 0.85V < VFCB/PLLIN < 4.3V >4.8V Besides providing a logic input to force continuous operation, the FCB/PLLIN pin acts as the input for external clock synchronization. Upon detecting the presence of an external clock signal, channel 1 will lock on to this external clock and this will be followed by channel 2 (see Frequency Synchronization section). The LTC3828 defaults to forced continuous mode when sychronized to an external clock. 3828f LTC3828 OPERATIO Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the FCB/PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 260kHz to 550kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. The internal master oscillator runs at a frequency twelve times that of each controller’s frequency. The PHSMD pin (UH package only) determines the relative phases between the internal controllers as well as the CLKOUT signal as shown in Table 2. The phases tabulated are relative to zero phase being defined as the rising edge of the top gate (TG1) driver output of controller 1. Table 2. VPHSMD Controller 1 Controller 2 CLKOUT GND 0° 180° 60° OPEN 0° 180° 90° INTVCC 0° 240° 120° The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). In the G28 package, CLKOUT is 90° out of phase with channel 1 and channel 2. Constant Frequency Operation When the FCB/PLLIN pin is tied to INTVCC, Burst Mode operation is disabled and the forced minimum output current requirement is removed. This provides constant frequency, discontinuous current (preventing reverse U (Refer to Functional Diagram) inductor current) operation over the widest possible output current range. This constant frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency operating mode down to approximately 1% of the designed maximum output current. Continuous Current (PWM) Operation Tying the FCB/PLLIN pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels—BEWARE! Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) Pin The PGOOD pin is connected to an open drain of an internal MOSFET. The MOSFET turns on and pulls the pin low when either output is not within ± 7.5% of the nominal output level as determined by the resistive feedback divider. When both outputs meet the ± 7.5% requirement, the MOSFET is turned off within 10µs and the pin is allowed to be pulled up by an external resistor to a source of up to 5.5V. Foldback Current Foldback current limiting is activated when the output voltage falls below 70% of its nominal level. If a short is present, a safe, low output current is provided due to internal current foldback and actual power wasted is low due to the efficient nature of the current mode switching regulator. This function is disabled at start-up. 3828f 11 LTC3828 OPERATIO THEORY AND BENEFITS OF 2-PHASE OPERATION The LTC3728 and the LTC3828 family of dual high efficiency DC/DC controllers brings the considerable benefits of 2-phase operation to portable applications for the first time. Notebook computers, PDAs, handheld terminals and automotive electronics will all benefit from the lower input filtering requirement, reduced electromagnetic interference (EMI) and increased efficiency associated with 2-phase operation. Why the need for 2-phase operation? Up until the 2-phase family, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase operation). This means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and battery. With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 2. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC3828 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency 3828f 12 U (Refer to Functional Diagram) Figure 2 compares the input waveforms for a representative single-phase dual switching regulator to the LTC3828 2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input current from 2.6ARMS to 1.9ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to IRMS2, meaning that the actual power wasted is reduced by a factor of 1.86. The reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative duty cycles which, in turn, are dependent upon the input voltage VIN (Duty Cycle = VOUT/VIN). Figure 3 shows how the RMS input current varies for single-phase and 2-phase operation for 3.3V and 5V regulators over a wide input voltage range. It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV IIN(MEAS) = 2.6ARMS DC236 F02a IIN(MEAS) = 1.9ARMS INPUT VOLTAGE 100mV/DIV DC236 F02b IN(MEAS) = 2.6ARMS IN(MEAS) = 1.9ARMS (a) (b) LTC3828 OPERATIO U (Refer to Functional Diagram) 3.0 2.5 INPUT RMS CURRENT (A) SINGLE PHASE DUAL CONTROLLER 2.0 1.5 1.0 0.5 0 2-PHASE DUAL CONTROLLER VO1 = 5V/3A VO2 = 3.3V/3A 0 10 20 30 INPUT VOLTAGE (V) 40 3828 F03 Figure 3. RMS Input Current Comparison APPLICATIO S I FOR ATIO Output Voltage Tracking The LTC3828 allows the user to program how the channel outputs ramp up and down by means of the TRCKSS pins. Through these pins, the channel outputs can be set up to either coincidentally or ratiometrically tracking, as shown in Figure 4. The TRCKSS pins act as clamps on the channels’ reference voltages. VOUT is referenced to the TRCKSS voltage when the TRCKSS < 0.8V and to the internal precision reference when TRCKSS > 0.8V. OUTPUT VOLTAGE VOUT2 OUTPUT VOLTAGE TIME (4a) Coincident Tracking Figure 4. Two Different Modes of Output Voltage Tracking U To implement the tracking in Figure 4a, connect an extra resistive divider to the output of the master channel and connect its midpoint to the slave channel’s TRCKSS pin. The ratio of this divider should be selected the same as that of channel 2’s feedback divider (Figure 5). In this tracking mode, the master channel’s output must be set higher than slave channel’s output. To implement the ratiometric tracking in Figure 4b, no extra divider is needed; simply connect one of TRCKSS pins to the other channel’s VFB pin (Figure 5). VOUT1 VOUT1 VOUT2 TIME 3828 F04 W UU (4b) Ratiometric Tracking 3828f 13 LTC3828 APPLICATIO S I FOR ATIO By selecting different resistors, the LTC3828 can achieve different modes of tracking including the two in Figure 4. Figure 6 helps to explaining the tracking function. At the input stage of an error amplifier, two diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same value. When the TRCKSS voltage is low, switch S1 is on and VOSENSE follows the TRCKSS voltage. When the TRCKSS voltage is close to 0.8V, the reference voltage, switch S1, is off and VOSENSE follows the reference voltage. The regulation for both channels’ outputs are not affected by the tracking mode. In the ratiometric tracking mode, the two channels do not exhibit cross talk. The number of resistors in Figure 5a can be further reduced with the scheme in Figure 7. In a system that requires more than two tracked supplies, multiple LTC3828s can be daisy-chained through the TRCKSS1 pin. TRCKSS1 clamps channel 1’s reference in the same manner TRCKSS2 clamps channel 2. To eliminate the possibility of multiple LTC3828s coming on at VOUT1 R3 TO TRCKSS2 PIN R4 R2 R1 TO TO VOSENSE1 VOSENSE2 PIN PIN R4 R3 VOUT2 (5a) Coincident Tracking Setup Figure 5. Setup for Coincident and Ratiometric Tracking ⎛ R1 VOUT1 R3 VOUT2 ⎞ = = – 1, – 1⎟ ⎜ 0.8 R4 0.8 ⎝ R2 ⎠ I S1 I + D1 TRCKSS 0.8V VOSENSE D3 3828 F06 D2 EA – Figure 6. Equivalent Input Circuit of Error Amplifier of Channel 2 14 U different times, only the master LTC3828’s TRCKSS1 pin should be connected to a soft-start capacitor. Figure 8 shows the circuit with four outputs. Three of them are programmed in the coincident mode while the fourth one tracks ratiometrically. If output tracking is not needed, the TRCKSS pins are used as soft start-up pins. The capacitors connected to those pins set the soft-start ramping up speed. Figure 15 is a basic LTC3828 application circuit. External component selection is driven by the load requirement, and begins with the selection of RSENSE and the inductor value. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected. The circuit shown in Figure 15 is configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection For Output Current RSENSE is chosen based on the required output current. The current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the VOUT1 R1 TO TRCKSS2 PIN R2 TO TO VOSENSE2 VOSENSE1 PIN PIN R3 VOUT2 R4 3828 F05 W U U (5b) Ratiometric Tracking Setup VOUT1 R1 TO TRCKSS2 PIN R2 TO VOSENSE1 PIN R3 R5 R4 VOUT2 TO VOSENSE2 PIN 3828 F07 Figure 7. Alternative Setup for Coincident Tracking ⎛ R1 + R2 VOUT1 R1 R4 VOUT2 ⎞ = = = – 1, – 1⎟ ⎜ 0.8 R2 + R3 R5 0.8 ⎝ R3 ⎠ 3828f LTC3828 APPLICATIO S I FOR ATIO VOUT1 R4 R5 R1 TRCKSS2 LTC3828 “MASTER” VOSENSE1 VOSENSE2 OUTPUT VOLTAGE R2 R2 R2 TRCKSS1 CSS TRCKSS1 TRCKSS2 VOUT3 R4 LTC3828 “SLAVE” VOSENSE1 VOSENSE2 R2 (8a) Circuit Setup Figure 8. Four Outputs with Tracking and Ratiometric Sequencing ⎛ R1 VOUT1 R3 VOUT2 R4 V R5 VOUT4 ⎞ = = = – 1, – 1 = OUT3 – 1, – 1⎟ ⎜ 0.8 R2 0.8 R2 0.8 R2 0.8 ⎝ R2 ⎠ peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Allowing a margin for variations in the IC and external component values yields: RSENSE = 50mV IMAX PLLFLTR PIN VOLTAGE (V) When using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. Operating Frequency The IC uses a constant frequency phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to Phase-Locked Loop and Frequency Synchronization in the Applications Information section for additional information. U VOUT2 R3 VOUT1 R2 VOUT3 VOUT4 R5 VOUT4 VOUT2 R2 TIME 3828 F08 W UU (8b) Output Voltage A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure 9. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 550kHz. 2.5 2.0 1.5 1.0 0.5 0 200 300 400 500 OPERATING FREQUENCY (kHz) 600 3828 F09 Figure 9. PLLFLTR Pin Voltage vs Frequency Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of 3828f 15 LTC3828 APPLICATIO S I FOR ATIO MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN: ∆IL = ⎛V⎞ 1 VOUT ⎜ 1 – OUT ⎟ ( f)(L) VIN ⎠ ⎝ Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL=0.3(IMAX). The maximum ∆IL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Selection Usually, high inductance is preferred for small current ripple and low core loss. Unfortunately, increased inductance requires more turns of wire or small air gap of the inductor, resulting in high copper loss or low saturation current. Once the value of L is known, the actual inductor must be selected. There are two popular types of core material of commercial available inductors. Ferrite core inductors usually have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. However, ferrite core saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. One advantage of the LTC3828 is its current mode control that detects and limits cycle-by-cycle peak inductor current. Therefore, accurate and fast protection 16 U is achieved if the inductor is saturated in steady state or during transient mode. Powder iron inductors usually saturate “soft”, which means the inductance drops in a linear fashion when the current increases. However, the core loss of the powder iron inductor is usually higher than the ferrite inductor. So design with high switching frequency should pay attention to the inductor core loss too. Inductor manufacturers usually provide inductance, DCR, (peak) saturation current and (DC) heating current ratings in the inductor data sheet. A good supply design should not exceed the saturation and heating current rating of the inductor. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for each controller in the LTC3828: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up. Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the Gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: W UU Main Switch Duty Cycle = VOUT VIN 3828f LTC3828 APPLICATIO S I FOR ATIO Synchronous Switch Duty Cycle = VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT (IMAX )2 (1+ δ)RDS(ON) + VIN (VIN )2 ⎛ IMAX ⎞ (RDR )(C MILLER) • ⎜ ⎟ ⎝2⎠ ⎡ 1 1⎤ + ⎢V ⎥( f ) ⎣ INTVCC – VTHMIN VTHMIN ⎦ PSYNC = VIN – VOUT IMAX VIN ( ) (1+ δ)RDS(ON) 2 where δ is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTHMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 12V the high current efficiency generally improves with larger MOSFETs, while for VIN ≥ 12V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the deadtime and requiring a reverse recovery period that could cost efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to U the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection The selection of CIN is simplified by the multiphase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS current requirement. Increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input RMS ripple current from this maximum value (see Figure 3). The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. The type of input capacitor, value and ESR rating have efficiency effects that need to be considered in the selection process. The capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 20µF to 40µF is usually sufficient for a 25W output supply operating at 260kHz. The ESR of the capacitor is important for capacitor power dissipation as well as overall battery efficiency. All of the power (RMS ripple current • ESR) not only heats up the capacitor but wastes power from the battery. Medium voltage (20V to 35V) ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coefficients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics’ higher ESR and dryout possibility require several to be used. Multiphase systems allow the lowest amount of capacitance overall. As little as one 22µF or two to three 10µF ceramic capacitors are an ideal choice in a 20W to 35W power supply due to their extremely low ESR. Even though the capacitance at 20V is substantially below their rating at zero-bias, very low ESR loss makes ceramics an ideal candidate for 3828f W UU 17 LTC3828 APPLICATIO S I FOR ATIO highest efficiency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk capacitance goals. In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN RequiredIRMS ≈ IMAX [ VOUT VIN − VOUT VIN ( This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The benefit of the LTC3828 multiphase clocking can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Remember that input protection fuse resistance, battery resistance and PC board trace resistance losses are also reduced due to the reduced peak currents in a multiphase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The drains of the two top MOSFETS should be placed within 1cm of each other and share a common CIN(s). Separating the drains and CIN may produce undesirable voltage and current resonances at VIN. 18 U The selection of COUT is driven by the required output voltage ripple and load transient response. Both the capacitor effective series resistance (ESR) and capacitance determine the output ripple: ⎛ 1⎞ ∆VOUT ≈ ∆IL • ⎜ ESR + ⎟ ⎝ 8fC OUT ⎠ W UU )] 1/ 2 Where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Usually, ceramic capacitors are used to minimize the output voltage ripple because of their ultralow ESR. Currently, multilayer ceramic capacitors have capacitor values up to hundreds of µF. However, the capacitance of the ceramic capacitors usually decreases with increased DC bias voltage and ambient temperature. In general, X5R or X7R type capacitors are recommended for high performance solutions. The OPTI-LOOP current mode control of LTC3828 provides stable, high performance transient response even with all ceramic output capacitors. Manufactures such as TDK, Taiyo Yuden, Murata and AVX provide high performance ceramic capacitors. When high capacitance is needed, especially for load transient requirement, low ESR polymerized electrolytic capacitors such as Sanyo POSCAP or Panasonic SP capacitor can be used in parallel with ceramic capacitors. Other high performance electolytic capacitor manufacturers include AVX, KEMET and NEC. With LTC3828, a combination of ceramic and low ESR electrolytic capacitors can provide a low ripple, fast transient, high density and cost-effective solution. Consult manufacturers for specific recommendations. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. INTVCC powers the drivers and internal circuitry within the IC. The INTV CC pin regulator can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7 µF tantalum, 10µF special polymer, or low ESR type electrolytic capacitor. A 1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly 3828f LTC3828 APPLICATIO S I FOR ATIO recommended. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between channels. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the IC to be exceeded. The system supply current is normally dominated by the gate charge current. Additional external loading of the INTVCC also needs to be taken into account for the power dissipation calculations. The absolute maximum rating for the INTVCC Pin is 50mA. To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the functional diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Output Voltage The output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor. The resultant feedback signal is compared with the internal precision 0.800V voltage reference by the error amplifier. The output voltage is given by the equation: U ⎛ R2⎞ VOUT = 0.8V⎜ 1 + ⎟ ⎝ R1⎠ where R1 and R2 are defined in Figure 1. SENSE+/SENSE– Pins The common mode input range of the current comparator sense pins is from 0V to (1.1)INTVCC. Continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8V to 7.7V. A differential NPN input stage is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This requires that current either be sourced or sunk from the SENSE pins depending on the output voltage. If the output voltage is below 2.4V current will flow out of both SENSE pins to the main output. The output can be easily preloaded by the VOUT resistive divider to compensate for the current comparator’s negative input bias current. The maximum current flowing out of each pair of SENSE pins is: ISENSE+ + ISENSE– = (2.4V – VOUT)/24k Since VOSENSE is servoed to the 0.8V reference voltage, we can choose R1 in Figure 1 to have a maximum value to absorb this current. W UU ⎛ 0.8V ⎞ R1(MAX) = 24k⎜ ⎟ ⎝ 2.4V – VOUT ⎠ for VOUT < 2.4V Regulating an output voltage of 1.8V, the maximum value of R1 should be 32k. Note that for an output voltage above 2.4V, R1 has no maximum value necessary to absorb the sense currents; however, R1 is still bounded by the VOSENSE feedback current. RUN and Soft-Start The LTC3828 RUN pins shut down their respective channels independently. The LTC3828 is put in a low quiescent current state (IQ < 30uA) if both RUN pin voltages are below 1V. TRCKSS pins are actively pulled to ground in this shutdown state. Once the RUN pin voltages are above 1.5V, the respective channel of the LTC3828 is powered 3828f 19 LTC3828 APPLICATIO S I FOR ATIO up. The LTC3828 has the ability to either soft-start by itself with an external soft-start capacitor or tracking the output of the other channel or supply. When the device is configured to soft-start by itself, an external soft-start capacitor should be connected to the TRCKSS pin. A soft-start current of 1.2µA is to charge the soft-start capacitor CSS. Note that soft-start during this mode is achieved not by limiting the maximum output current of the controller but by controlling the ramp rate of the output voltage. As a matter of fact, current foldback is defeated during softstart or tracking. During this phase, the LTC3828 is basically ramping the reference voltage until this voltage is 7.5% below the 0.8V reference. The total soft-start time can be estimated as: TSOFT-START = 0.925 • 0.8V • CSS/1.2µA The LTC3828 is designed such that the TRCKSS pin is not actively pulled down if only one of the channels is shut down. In this case, the TRCKSS pin voltage could be higher than 0.8V. If this particular channel is powered up again, the soft-start for this particular channel is provided by an internal soft-start timer about 450µs. The internal soft-start timer will also be in effect if the LTC3828 is trying to track an output supply that is already powered up. In any case, the force continuous mode is disabled and PGOOD signal is forced low during the first 90% of the soft-start phase. This time can be estimated for external soft-start as: TFORCE = 0.9 • 0.925 • 0.8V • CSS/1.2µA For internal soft-start, it will be 450µs. Fault Conditions: Current Limit and Current Foldback The current comparators have a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. The maximum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the highest power dissipation in the top MOSFET. Each controller includes current foldback to help further limit load current when the output is shorted to ground. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mV to 25mV. Under short-circuit conditions with very 20 U low duty cycles, the controller will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of each controller (typically 200ns), the input voltage and inductor value: ∆IL(SC) = tON(MIN) (VIN/L) The resulting short-circuit current is: ISC = 25mV 1 – ∆IL(SC) RSENSE 2 W UU Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor PC layout to function while the design is being debugged. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Phase-Locked Loop and Frequency Synchronization The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ± 50% around the center 3828f LTC3828 APPLICATIO S I FOR ATIO frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 400kHz. The nominal operating frequency range of the IC is 260kHz to 550kHz. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC: ∆fH = ∆fC = ± 0.5 fO (260kHz-550kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The IC’s FCB/PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A DC voltage of 0.7V to 1.7V applied to the master oscillator’s PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency can range from 300kHz to 500kHz. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to 0.1µF. U Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that each controller is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that W UU tON(MIN) < VOUT VIN (f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for each controller is approximately 200ns. However, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Voltage Positioning Voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step specifications. Voltage positioning can easily be added to either or both controllers by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage range of the error amplifier, or 1.2V (see Figure 10). INTVCC RT2 ITH RT1 RC CC 3828 F10 LTC3828 Figure 10. Active Voltage Positioning Applied to the LTC3828 3828f 21 LTC3828 APPLICATIO S I FOR ATIO The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A complete explanation is included in Design Solutions 10. (See www.linear.com) Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3828 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; VIN current typically results in a small (1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 11 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode 3828f W UU 23 LTC3828 APPLICATIO S I FOR ATIO prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC3828 have a maximum input voltage of 30V, most applications will also be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V VIN LTC3828 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 3828 F11 Figure 11. Automotive Application Protection Design Example As a design example for one channel, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, and f = 300kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFLTR pin to a resistive divider from the INTVCC pin, generating 0.7V for 300kHz operation. The minimum inductance for 30% ripple current is: ∆IL = VOUT ⎛ VOUT ⎞ ⎜1– ⎟ (f)(L) ⎝ VIN ⎠ A 4.7µH inductor will produce 23% ripple current and a 3.3µH will result in 33%. The peak inductor current will be the maximum DC value plus one half the ripple current, or 5.84A, for the 3.3µH value. Increasing the ripple current will also help ensure that the minimum on-time of 100ns is not violated. The minimum on-time occurs at maximum VIN: tON(MIN) = VOUT VIN(MAX)f = 1.8V = 273ns 22V(300kHz) 24 U The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: W UU RSENSE ≤ 60mV ≈ 0.01Ω 5.84A Since the output voltage is below 2.4V the output resistive divider will need to be sized to not only set the output voltage but also to absorb the SENSE pin’s specified input current. ⎛ 0.8V ⎞ R1(MAX) = 24k ⎜ ⎟ ⎝ 2.4V – VOUT ⎠ ⎛ 0.8V ⎞ = 24k ⎜ ⎟ = 32k ⎝ 2.4V – 1.8V ⎠ Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. The power dissipation on the top side MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual MOSFET results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At maximum input voltage with T(estimated) = 50°C: PMAIN = 1.8V 2 (5) [1+ (0.005)(50°C – 25°C )] • 22V A (0.035Ω) + (22V)2 ⎛ 52 ⎞ (4Ω)(215pF ) • ⎜⎟ ⎝⎠ 1⎤ ⎡1 ⎢ 5 – 2.3 + 2.3 ⎥(300kHz ) = 332mW ⎣ ⎦ A short-circuit to ground will result in a folded back current of: ISC = 25mV 1 ⎛ 120ns(22V)⎞ –⎜ ⎟ = 2.1A 0.01Ω 2 ⎝ 3.3µH ⎠ 3828f LTC3828 APPLICATIO S I FOR ATIO with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is: PSYNC = 22V – 1.8V (2.1A)2 (1.125)(0.022Ω) 22V = 100mW which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) = 0.02Ω(1.67A) = 33mVP–P PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 12. The Figure 13 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) U terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Do the LTC3828 VOSENSE pins’ resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The R2 and R4 connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE – should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposites channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3828 and occupy minimum PC trace area. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging 3828f W UU 25 LTC3828 APPLICATIO S I FOR ATIO 1 2 3 R1 R2 4 5 6 7 8 9 10 11 12 13 R3 R4 14 TRCKSS1 ITH1 PGOOD LTC3828 26 BOOST1 SENSE1+ SENSE1– VOSENSE1 PLLFLTR RUN1 FCB/PLLIN SGND TRCKSS2 SENSE2– SENSE2+ ITH2 VOSENSE2 TG1 SW1 VIN INTVCC PGND BG1 BG2 SW2 TG2 BOOST2 RUN2 25 24 23 22 21 20 19 18 17 16 15 L2 RSENSE2 VOUT2 3828 F12 fIN Figure 12. LTC3828 Recommended Printed Circuit Layout Diagram 26 U RPU CLKOUT 28 27 VPULL_UP