LTC3830-1ES8

LTC3830/LTC3830-1 High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation FEATURES s s s s s s DESCRIPTIO s s s s s s s s High Power Switching Regulator Controller for 3.3V-5V to 1.xV-3.xV Step-Down Applications No Current Sense Resistor Required Low Input Supply Voltage Range: 3V to 8V Maximum Duty Cycle > 91% Over Temperature All N-Channel External MOSFETs Excellent Output Regulation: ± 1% Over Line, Load and Temperature Variations High Efficiency: Over 95% Possible Adjustable or Fixed 3.3V Output (16-Pin Version) Programmable Fixed Frequency Operation: 100kHz to 500kHz External Clock Synchronization Soft-Start (Some Versions) Low Shutdown Current: 91% over temperature. They include a fixed frequency PWM oscillator for low output ripple operation. The 200kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to 500kHz. In shutdown mode, the LTC3830 supply current drops to 91%. sn3830 3830fs W UU LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO Similarly, the MAX comparator forces the output to 0% duty cycle if the feedback signal is greater than 40mV above the internal reference. To prevent these two comparators from triggering due to noise, the MIN and MAX comparators’ response times are deliberately delayed by two to three microseconds. These two comparators help prevent extreme output perturbations with fast output load current transients, while allowing the main feedback loop to be optimally compensated for stability. Thermal Shutdown The LTC3830/LTC3830-1 have a thermal protection circuit that disables both gate drivers if activated. If the chip junction temperature reaches 150°C, both G1 and G2 are pulled low. G1 and G2 remain low until the junction temperature drops below 125°C, after which, the chip resumes normal operation. Soft-Start and Current Limit The 16-lead LTC3830 devices include a soft-start circuit that is used for start-up and current limit operation. The LTC3830-1 only has the soft-start function; the current limit function is disabled. The 8-lead LTC3830 has both the soft-start and current limit function disabled. The SS pin requires an external capacitor, CSS, to GND with the value determined by the required soft-start time. An internal 12µA current source is included to charge CSS. During power-up, the COMP pin is clamped to a diode drop (B-E junction of QSS in the Block Diagram) above the voltage at the SS pin. This prevents the error amplifier from forcing the loop to maximum duty cycle. The LTC3830/LTC3830-1 operate at low duty cycle as the SS pin rises above 0.6V (VCOMP ≈ 1.2V). As SS continues to rise, QSS turns off and the error amplifier takes over to regulate the output. The MIN comparator is disabled during soft-start to prevent it from overriding the soft-start function. The 16-lead LTC3830 devices include yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples and holds the voltage drop measured across the external upper MOSFET, Q1, at the IFB pin. CC compares U the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases due to the drop across the RDS(ON) of Q1. When the voltage at IFB drops below IMAX, indicating that Q1’s drain current has exceeded the maximum level, CC starts to pull current out of CSS, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin falls gradually, creating a time delay before current limit takes effect. Very short, mild overloads may not affect the output voltage at all. More significant overload conditions allow the SS pin to reach a steady state, and the output remains at a reduced voltage until the overload is removed. Serious overloads generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. This helps minimize the number of components in the high current path. The current limit threshold can be set by connecting an external resistor RIMAX from the IMAX pin to the main VIN supply at the drain of Q1. The value of RIMAX is determined by: RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX where: ILMAX = ILOAD + (IRIPPLE/2) ILOAD = Maximum load current IRIPPLE = Inductor ripple current = W UU ( VIN – VOUT )( VOUT ) (fOSC )(LO )(VIN) fOSC = LTC3830 oscillator frequency = 200kHz LO = Inductor value RDS(ON)Q1 = On-resistance of Q1 at ILMAX IIMAX = Internal 12µA sink current at IMAX sn3830 3830fs 9 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO The RDS(ON) of Q1 usually increases with temperature. To keep the current limit threshold constant, the internal 12µA sink current at IMAX is designed with a positive temperature coefficient to provide first order correction for the temperature coefficient of RDS(ON)Q1. In order for the current limit circuit to operate properly and to obtain a reasonably accurate current limit threshold, the IIMAX and IFB pins must be Kelvin sensed at Q1’s drain and source pins. In addition, connect a 0.1µF decoupling capacitor across RIMAX to filter switching noise. Otherwise, noise spikes or ringing at Q1’s source can cause the actual current limit to be greater than the desired current limit set point. Due to switching noise and variation of RDS(ON), the actual current limit trip point is not highly accurate. The current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. Typically, RDS(ON) varies as much as ±40% and with ± 25% variation on the LTC3830’s IMAX current, this can give a ±65% variation on the current limit threshold. The RDS(ON) is high if the VGS applied to the MOSFET is low. This occurs during power up, when PVCC1 is ramping up. To prevent the high RDS(ON) from activating the current limit, the LTC3830 disables the current limit circuit if PVCC1 is less than 2.5V above VCC. To ensure proper operation of the current limit circuit, PVCC1 must be at least 2.5V above VCC when G1 is high. PVCC1 can go low when G1 is low, allowing the use of an external charge pump to power PVCC1. VIN LTC3830 RIMAX 0.1µF + CC 12µA 12 IMAX IFB G1 1k G2 Q2 Q1 LO – 13 Figure 4. Current Limit Setting 10 U Oscillator Frequency The LTC3830 includes an onboard current controlled oscillator that typically free-runs at 200kHz. The oscillator frequency can be adjusted by forcing current into or out of the FREQSET pin. With the pin floating, the oscillator runs at about 200kHz. Every additional 1µA of current into/out of the FREQSET pin decreases/increases the frequency by 10kHz. The pin is internally servoed to 1.265V, connecting a 50k resistor from FREQSET to ground forces 25µA out of the pin, causing the internal oscillator to run at approximately 450kHz. Forcing an external 10µA current into FREQSET cuts the internal frequency to 100kHz. An internal clamp prevents the oscillator from running slower than about 50kHz. Tying FREQSET to VCC forces the chip to run at this minimum speed. The LTC3830-1 and the 8-lead LTC3830 do not have this frequency adjustment function. Shutdown The LTC3830 includes a low power shutdown mode, controlled by the logic at the SHDN pin. A high at SHDN allows the part to operate normally. A low level at SHDN for more than 100µs forces the LTC3830 into shutdown mode. In this mode, all internal switching stops, the COMP and SS pins pull to ground and Q1 and Q2 turn off. The LTC3830 supply current drops to 100µs, or else the LTC3830 enters shutdown mode. Figure 5 describes the operation of the external synchronization function. A negative transition at the SHDN pin forces the internal ramp signal low to restart a new PWM cycle. Notice that with the traditional sync method, the ramp amplitude is lowered as the external clock frequency goes higher. The effect of this decrease in ramp amplitude increases the open-loop gain of the controller feedback loop. As a result, the loop crossover frequency increases and it may cause the feedback loop to be unstable if the phase margin is insufficient. SHDN TRADITIONAL SYNC METHOD WITH EARLY RAMP TERMINATION 200kHz FREE RUNNING RAMP SIGNAL RAMP SIGNAL WITH EXT SYNC RAMP AMPLITUDE ADJUSTED LTC3830 KEEPS RAMP AMPLITUDE CONSTANT UNDER SYNC INTERNAL CIRCUITRY Figure 5. External Synchronization Operation U To overcome this problem, the LTC3830 monitors the peak voltage of the ramp signal and adjusts the oscillator charging current to maintain a constant ramp peak. Input Supply Considerations/Charge Pump The 16-lead LTC3830 requires four supply voltages to operate: VIN for the main power input, PVCC1 and PVCC2 for MOSFET gate drive and a clean, low ripple VCC for the LTC3830 internal circuitry (Figure 6). The LTC3830-1 and the 8-lead LTC3830 have the PVCC2 and VCC pins tied together inside the package (Figure 7). This pin, brought out as VCC/PVCC2 , has the same low ripple requirements as the 16-lead part, but must also be able to supply the gate drive current to Q2. In many applications, VCC can be powered from VIN through an RC filter. This supply can be as low as 3V. The low quiescent current (typically 800µA) allows the use of relatively large filter resistors and correspondingly small VCC PVCC2 PVCC1 VIN G1 Q1 LO VOUT G2 INTERNAL CIRCUITRY Q2 W UU + COUT 3830 F6 LTC3830 (16-LEAD) Figure 6. 16-Lead Power Supplies VCC/PVCC2 PVCC1 VIN G1 Q1 LO VOUT G2 + Q2 COUT 3830 F7 LTC3830 (8-LEAD) 3830 F05 Figure 7. 8-Lead Power Supplies sn3830 3830fs 11 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO filter capacitors. 100Ω and 4.7µF usually provide adequate filtering for VCC. For best performance, connect the 4.7µF bypass capacitor as close to the LTC3830 VCC pin as possible. Gate drive for the top N-channel MOSFET Q1 is supplied from PVCC1. This supply must be above VIN (the main power supply input) by at least one power MOSFET VGS(ON) for efficient operation. An internal level shifter allows PVCC1 to operate at voltages above VCC and VIN, up to 14V maximum. This higher voltage can be supplied with a separate supply, or it can be generated using a charge pump. Gate drive for the bottom MOSFET Q2 is provided through PVCC2 for the 16-lead LTC3830 or VCC/PVCC2 for the LTC3830-1 and the 8-lead LTC3830. This supply only needs to be above the power MOSFET VGS(ON) for efficient operation. PVCC2 can also be driven from the same supply/ charge pump for the PVCC1, or it can be connected to a lower supply to improve efficiency. Figure 8 shows a tripling charge pump circuit that can be used to provide 2VIN and 3VIN gate drive for the external top and bottom MOSFETs respectively. These should fully enhance MOSFETs with 5V logic level thresholds. This circuit provides 3VIN – 3VF to PVCC1 while Q1 is ON and 2VIN – 2VF to PVCC2 where VF is the forward voltage of the Schottky diodes. The circuit requires the use of Schottky diodes to minimize forward drop across the diodes at start-up. The tripling charge pump circuit can rectify any DZ 12V 1N5242 1N5817 1N5817 0.1µF 0.1µF Q1 LO VOUT G2 VIN 1N5817 10µF PVCC2 PVCC1 G1 Q2 LTC3830 Figure 8. Tripling Charge Pump 12 U ringing at the drain of Q2 and provide more than 3VIN at PVCC1; a 12V zener diode should be included from PVCC1 to PGND to prevent transients from damaging the circuitry at PVCC1 or the gate of Q1. Care should be taken when using a charge pump to power PVCC1 in applications with low VCC supply voltages (less than 4V) or high switching frequencies. The charge pump capacitors refresh when the G2 pin goes high and the switch node is pulled low by Q2. The G2 on-time becomes narrow when LTC3830 operates at maximum duty cycle (95% typical), which can occur if the input supply rises more slowly than the soft-start capacitor or the input voltage droops during load transients. If the G2 on-time gets so narrow that the switch node fails to pull completely to ground, the charge pump voltage may collapse or fail to start, causing excessive dissipation in external MOSFET Q1. This is most likely with low VCC voltages and high switching frequencies, coupled with large external MOSFETs which slow the G2 and switch node slew rates. Workarounds include: • Increasing the soft-start capacitor to limit the duty cycle at start up • Using smaller MOSFETs with lower gate capacitance (where possible) to reduce the G2 rise/fall time and switch node slew rates • Using an external higher voltage supply to power PVCC1 if available Another alternative is to add an external circuit to limit the duty cycle when PVCC1 is low, as shown in Figure 9b. If the charge pump is not running, PVCC1 will be less than or equal to VCC and the voltage at the soft-start pin will be about (VCC/6 + VBE). This is about 1.2V with a VCC of 3.3V, which limits the duty cycle to about 50% and allows the charge pump to start up. Once PVCC1 rises higher than (VCC + VTQ3), the voltage at the soft-start pin goes high and the limit on duty cycle is removed. For applications with a 5V or higher VIN supply, PVCC2 can be tied to VIN if a logic level MOSFET is used. PVCC1 can be supplied using a doubling charge pump as shown in Figure 9a. This circuit provides 2VIN – VF to PVCC1 while Q1 is ON. sn3830 3830fs W UU + COUT 3830 F08 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO VIN OPTIONAL USE FOR VIN ≥ 7V DZ 12V 1N5242 PVCC2 PVCC1 G1 MBR0530T1 0.1µF Q1 LO VOUT G2 Q2 LTC3830 Figure 9a. Doubling Charge Pump Figure 12 shows a typical 5V to 3.3V application using a doubling charge pump to generate PVCC1. Power MOSFETs Two N-channel power MOSFETs are required for most LTC3830 circuits. These should be selected based primarily on threshold voltage and on-resistance considerations. Thermal dissipation is often a secondary concern in high efficiency designs. The required MOSFET threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump scheme. In 3.3V input designs where an auxiliary 12V supply is available to power PVCC1 and PVCC2, standard MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be used with good results. The current drawn from this supply varies with the MOSFETs used and the LTC3830’s operating frequency, but is generally less than 50mA. LTC3830 applications that use 5V or lower VIN voltage and a doubling/tripling charge pump to generate PVCC1 and PVCC2, do not provide enough gate drive voltage to fully enhance standard power MOSFETs. Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the dissipation in the FETs and reducing efficiency. Logic level FETs are the recommended choice for 5V or lower U VIN D2 10µF D1 PVCC2 PVCC1 G1 Q3 BSS284 SS Q4 3906 G2 0.1µF Q1 LO VOUT W UU + COUT 3830 F09a R1 1M R2 200k + Q2 COUT 3830 F09b LTC3830 Figure 9b. Duty Cycle Clamp Circuit voltage systems. Logic level FETs can be fully enhanced with a doubler/tripling charge pump and will operate at maximum efficiency. After the MOSFET threshold voltage is selected, choose the RDS(ON) based on the input voltage, the output voltage, allowable power dissipation and maximum output current. In a typical LTC3830 circuit, operating in continuous mode, the average inductor current is equal to the output load current. This current flows through either Q1 or Q2 with the power dissipation split up according to the duty cycle: VOUT VIN V V –V DC(Q2) = 1 – OUT = IN OUT VIN VIN DC(Q1) = The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. RDS(ON)Q1 = RDS(ON)Q2 = PMAX(Q1) DC(Q1) • (ILOAD )2 PMAX(Q2 ) DC(Q2) • (ILOAD)2 = = VIN • PMAX(Q1) VOUT • (ILOAD )2 VIN • PMAX(Q2 ) ( VIN – VOUT ) • (ILOAD)2 sn3830 3830fs 13 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed for 5V input and 3.3V at 10A output might allow no more than 3% efficiency loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: (3.3V)(10A/0.9)(0.03) = 1.1W per FET and a required RDS(ON) of: (5V) • (1.1W) RDS(ON)Q1 = = 0.017Ω (3.3V)(10 A)2 (5V) • (1.1W) RDS(ON)Q2 = = 0.032Ω (5V – 3.3V)(10 A)2 Note that the required RDS(ON) for Q2 is roughly twice that of Q1 in this example. This application might specify a single 0.03Ω device for Q2 and parallel two more of the same devices to form Q1. Note also that while the required RDS(ON) values suggest large MOSFETs, the power dissipation numbers are only 1.1W per device or less; large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY Table 1. Recommended MOSFETs for LTC3830 Applications RDS(ON) AT 25°C (mΩ) 19 20 35 8 10 9 19 28 37 PARTS Siliconix SUD50N03-10 TO-252 Siliconix Si4410DY SO-8 ON Semiconductor MTD20N03HDL DPAK Fairchild FDS6670A S0-8 Fairchild FDS6680 SO-8 ON Semiconductor MTB75N03HDL DD PAK IR IRL3103S DD PAK IR IRLZ44 TO-220 Fuji 2SK1388 TO-220 Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information. sn3830 3830fs 14 U or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semiconductor MTD20N03HDL (DPAK) are small footprint surface mount devices with RDS(ON) values below 0.03Ω at 5V of VGS that work well in LTC3830 circuits. Using a higher PMAX value in the RDS(ON) calculations generally decreases the MOSFET cost and the circuit efficiency and increases the MOSFET heat sink requirements. Table 1 highlights a variety of power MOSFETs for use in LTC3830 applications. Inductor Selection The inductor is often the largest component in an LTC3830 design and must be chosen carefully. Choose the inductor value and type based on output slew rate requirements. The maximum rate of rise of inductor current is set by the inductor’s value, the input-to-output voltage differential and the LTC3830’s maximum duty cycle. In a typical 5V input, 3.3V output application, the maximum rise time will be: W UU DCMAX • ( VIN – VOUT ) 1.615 A = LO LO µs RATED CURRENT (A) 15 at 25°C 10 at 100°C 10 at 25°C 8 at 70°C 20 at 25°C 16 at 100°C 13 at 25°C 11.5 at 25°C 75 at 25°C 59 at 100°C 64 at 25°C 45 at 100°C 50 at 25°C 36 at 100°C 35 at 25°C TYPICAL INPUT CAPACITANCE CISS (pF) 3200 2700 880 3200 2070 4025 1600 3300 1750 θJC (°C/W) 1.8 TJMAX (°C) 175 150 1.67 25 25 1 1.4 1 2.08 150 150 150 150 175 175 150 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO where LO is the inductor value in µH. With proper frequency compensation, the combination of the inductor and output capacitor values determine the transient recovery time. In general, a smaller value inductor improves transient response at the expense of ripple and inductor core saturation rating. A 2µH inductor has a 0.81A/µs rise time in this application, resulting in a 6.2µs delay in responding to a 5A load current step. During this 6.2µs, the difference between the inductor current and the output current is made up by the output capacitor. This action causes a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1µH to 5µH range for most 5V input LTC3830 circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. The ripple current is approximately equal to: IRIPPLE = ( VIN − VOUT ) • ( VOUT ) fOSC • LO • VIN fOSC = LTC3830 oscillator frequency = 200kHz LO = Inductor value Solving this equation with our typical 5V to 3.3V application with a 2µH inductor, we get: (5V – 3.3V) • 3.3V = 2.8 AP-P 200kHz • 2µH • 5V U Peak inductor current at 10A load: 10A + (2.8A/2) = 11.4A The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short-circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice. Input and Output Capacitors A typical LTC3830 design places significant demands on both the input and the output capacitors. During normal steady load operation, a buck converter like the LTC3830 draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current plus 1/2 the peak-to-peak ripple current. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor heats it and causes premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal to IOUT/2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours (3 months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer’s specification is recommended to extend the useful life of the circuit. Lower operating temperature has the largest effect on capacitor longevity. sn3830 3830fs W UU 15 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO The output capacitor in a buck converter under steadystate conditions sees much less ripple current than the input capacitor. Peak-to-peak current is equal to inductor ripple current, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the LTC3830 adjusts the inductor current to the new value. ESR in the output capacitor results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 5A load step with a 0.05Ω ESR output capacitor results in a 250mV output voltage shift; this is 7.6% of the output voltage for a 3.3V supply! Because of the strong relationship between output capacitor ESR and output load transient response, choose the output capacitor for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed to control steady-state output ripple. Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC3830 applications. OS-CON electrolytic capacitors from Sanyo and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. Other capacitors that can be used include the Sanyo POSCAP and MV-WX series. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. A typical LTC3830 application might exhibit 5A input ripple current. Sanyo OS-CON capacitors, part number 10SA220M (220µF/10V), feature 2.3A allowable ripple current at 85°C; three in parallel at the input (to withstand the input ripple current) meet the above requirements. Similarly, Sanyo POSCAP 4TPB470M (470µF/4V) capacitors have COMP 10 RC CC C1 ERR Figure 10a. Compensation Pin Hook-Up 16 – + U a maximum rated ESR of 0.04Ω; three in parallel lower the net output capacitor ESR to 0.013Ω. Feedback Loop Compensation The LTC3830 voltage feedback loop is compensated at the COMP pin, which is the output node of the error amplifier. The feedback loop is generally compensated with an RC + C network from COMP to GND as shown in Figure 10a. Loop stability is affected by the values of the inductor, the output capacitor, the output capacitor ESR, the error amplifier transconductance and the error amplifier compensation network. The inductor and the output capacitor create a double pole at the frequency: fLC = 1/ 2π (LO )(COUT ) W UU [ ] The ESR of the output capacitor and the output capacitor value form a zero at the frequency: fESR = 1/ [2π (ESR)(COUT )] The compensation network used with the error amplifier must provide enough phase margin at the 0dB crossover frequency for the overall open-loop transfer function. The zero and pole from the compensation network are: fZ = 1/[2π(RC)(CC)] and fP = 1/[2π(RC)(C1)] respectively 7 SENSE + LTC3830 C2 R2 VFB 6 R1 SENSE – 5 VREF 3830 F10a sn3830 3830fs LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO Figure 10b shows the Bode plot of the overall transfer function. When low ESR output capacitors (Sanyo OS-CON) are used, the ESR zero can be high enough in frequency that it provides little phase boost at the loop crossover frequency. As a result, the phase margin becomes inadequate and the load transient is not optimized. To resolve this problem, a small capacitor can be connected between the top of the resistor divider network and the VFB pin to create a pole-zero pair in the loop compensation. The zero location is prior to the pole location and thus, phase lead can be added to boost the phase margin at the loop crossover frequency. The pole and zero locations are located at: fZC2 = 1/[2π(R2)(C2)] and fPC2 = 1/[2π(R1||R2)(C2)] where R1||R2 is the parallel combination resistance of R1 and R2. Choose C2 so that the zero is located at a lower frequency compared to fCO and the pole location is high enough that the closed loop has enough phase margin for stability. Figure 10c shows the Bode plot using phase lead compensation around the LTC3830 resistor divider network. Note: This technique is effective only when R1 >> R2 i.e., at high output voltages only so that the pole and zero are sufficiently separated. fZ LOOP GAIN fSW = LTC3830 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY LOOP GAIN 20dB/DECADE 20dB/DECADE fCO fP fLC fESR fCO FREQUENCY fLC fZC2 fESR 3830 F10b Figure 10b. Bode Plot of the LTC3830 Overall Transfer Function U Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. Table 2 shows the suggested compensation component value for 5V to 3.3V applications based on Sanyo OS-CON 4SP820M low ESR output capacitors. Table 2. Recommended Compensation Network for 5V to 3.3V Applications Using Multiple Paralleled 820µF Sanyo OS-CON 4SP820M Output Capacitors L1 (µH) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (µF) 1640 2460 4100 1640 2460 4100 1640 2460 4100 RC (kΩ) 6.2 12 12 15 20 36 30 36 82 CC (nF) 3.3 3.3 1.8 2.7 1.0 1.0 1.8 1.0 1.0 C1 (pF) 470 470 220 330 220 220 330 180 180 C2 (pF) 1000 1000 1000 1000 1000 1000 1000 1000 1000 fSW = LTC3830 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY fZ fP fPC2 FREQUENCY 3830 F10c W UU Figure 10c. Bode Plot of the LTC3830 Overall Transfer Function Using a Low ESR Output Capacitor sn3830 3830fs 17 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO Table 3 shows the suggested compensation component values for 5V to 3.3V applications based on 470µF Sanyo POSCAP 4TPB470M output capacitors. Table 3. Recommended Compensation Network for 5V to 3.3V Applications Using Multiple Paralleled 470µF Sanyo POSCAP 4TPB470M Output Capacitors L1 (µH) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (µF) 1410 2820 4700 1410 2820 4700 1410 2820 4700 RC (kΩ) 6.8 15 22 18 43 62 43 91 150 CC (nF) 4.7 2.2 2.2 10 2.2 2.2 10 33 10 C1 (pF) 33 33 33 33 33 10 10 10 10 Table 4 shows the suggested compensation component values for 5V to 3.3V applications based on 1500µF Sanyo MV-WX output capacitors. Table 4. Recommended Compensation Network for 5V to 3.3V Applications Using Multiple Paralleled 1500µF Sanyo MV-WX Output Capacitors L1 (µH) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (µF) 4500 6000 9000 4500 6000 9000 4500 6000 9000 RC (kΩ) 22 30 39 51 62 82 100 150 200 CC (nF) 1.5 1 0.47 1 1 0.47 3.3 0.47 0.47 C1 (pF) 120 82 56 56 33 27 15 15 15 18 U LAYOUT CONSIDERATIONS When laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3830. These items are also illustrated graphically in the layout diagram of Figure 11. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10A. 1. In general, layout should begin with the location of the power devices. Be sure to orient the power circuitry so that a clean power flow path is achieved. Conductor widths should be maximized and lengths minimized. After you are satisfied with the power path, the control circuitry should be laid out. It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. The GND and PGND pins should be shorted directly at the LTC3830. This helps to minimize internal ground disturbances in the LTC3830 and prevent differences in ground potential from disrupting internal circuit operation. This connection should then tie into the ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capacitors. This is not always practical, however, due to physical constraints. Another reasonably good point to make this connection is between the output capacitors and the source connection of the bottom MOSFET Q2. Do not tie this single point ground in the trace run between the Q2 source and the input capacitor ground, as this area of the ground plane will be very noisy. sn3830 3830fs W UU LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO 3. The small-signal resistors and capacitors for frequency compensation and soft-start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. Do not connect these parts to the ground plane! 4. The VCC, PVCC1 and PVCC2 decoupling capacitors should be as close to the LTC3830 as possible. The 4.7µF and 1µF bypass capacitors shown at VCC, PVCC1 and PVCC2 will help provide optimum regulation performance. 100Ω 4.7µF + 1µF GND NC VCC PVCC2 PVCC1 LTC3830 FREQSET SHDN COMP G1 IMAX IFB SENSE + G2 FB SENSE – NC PGND C1 RC CC CSS GND SS GND PGND PGND Figure 11. Typical Schematic Showing Layout Considerations U 5. The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET, Q1. An additional 1µF ceramic capacitor between VIN and power ground is recommended. 6. The SENSE and VFB pins are very sensitive to pickup from the switching node. Care should be taken to isolate SENSE and VFB from possible capacitive coupling to the inductor switching signal. Connecting the SENSE+ and SENSE – close to the load can significantly improve load regulation. 7. Kelvin sense IMAX and IFB at Q1’s drain and source pins. PVCC VIN 1µF 0.1µF Q1A 1k Q1B LO VOUT Q2 W UU + CIN + COUT 3830 F11 sn3830 3830fs 19 LTC3830/LTC3830-1 APPLICATIO S I FOR ATIO 5V 100Ω 1µF + PVCC2 VCC SS PVCC1 G1 IMAX LTC3830 IFB FREQSET SHDN COMP G2 PGND GND SENSE + SENSE– FB CIN: SANYO 6TPB330M COUT: SANYO 4TPB470M LO: SUMIDA CDEP105-2R5 Q1, Q2: VISHAY Si7892DP Q2 1k 0.1µF LO 2.5µH 6.8k 0.1µF Q1 + 4.7µF 0.1µF 0.01µF NC SHUTDOWN C1 33pF RC 18k CC 0.01µF Figure 12. 5V to 3.3V, 10A Application 20 U + MBR0530T1 CIN 330µF ×2 W UU + COUT 470µF ×3 3.3V 10A 3830 F012 sn3830 3830fs LTC3830/LTC3830-1 PACKAGE DESCRIPTIO .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0° – 8° TYP .053 – .068 (1.351 – 1.727) 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) U GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0250 TYP .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC GN16 (SSOP) 0502 sn3830 3830fs 21 LTC3830/LTC3830-1 PACKAGE DESCRIPTIO .050 BSC 8 N N .245 MIN .160 ±.005 .228 – .244 (5.791 – 6.197) 1 .030 ±.005 TYP 2 3 N/2 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 22 U S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .045 ±.005 .189 – .197 (4.801 – 5.004) NOTE 3 7 6 5 .150 – .157 (3.810 – 3.988) NOTE 3 N/2 1 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0502 sn3830 3830fs LTC3830/LTC3830-1 PACKAGE DESCRIPTIO .050 BSC N 16 15 14 .245 MIN 1 .030 ±.005 TYP 2 3 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .010 – .020 × 45° (0.254 – 0.508) .053 – .069 (1.346 – 1.752) 0° – 8° TYP 2 3 4 5 6 7 8 .008 – .010 (0.203 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .045 ±.005 .386 – .394 (9.804 – 10.008) NOTE 3 13 12 11 10 9 N .160 ±.005 .228 – .244 (5.791 – 6.197) N/2 .150 – .157 (3.810 – 3.988) NOTE 3 .004 – .010 (0.101 – 0.254) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC S16 0502 sn3830 3830fs 23 LTC3830/LTC3830-1 TYPICAL APPLICATIO 100Ω 4.7µF 0.1µF 0.01µF 130k C1 33pF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3830 is Pin-for-Pin Compatible and is Recommended for New Designs SO-8 with Current Limit. No RSENSETM required Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V ≤ VIN ≤ 36V 550kHz, 25MHz GBW Voltage Mode, VIN ≤ 7V, No RSENSE Provides CPU Core, I/O and CLK Supplies for Portable Systems Current Mode, VIN to 36V, IOUT Up to 42A Fault Protection, Power Good, 3.5V to 36V Input, Current Mode Up to 95% Efficiency, 550kHz, 2.65V ≤ VIN ≤ 8.5V, 0.8V ≤ VOUT ≤ VIN, Synchronizable to 750kHz VIN Up to 36V, Current Mode, Power Good 1.3V to 3.5V Programmable Core Output Plus I/O Output Step-Down DC/DC Conversion from 3VIN, Minimum CIN and COUT, Uses Logic-Level N-Channel MOSFETs Current Mode Ensures Accurate Current Sensing VIN Up to 36V, IOUT Up to 40A Minimum VIN: 1.5V, Uses Standard Logic-Level N-Channel MOSFETs VOUT Tracks 1/2 of VIN or External Reference 0.6V ≤ VOUT ≤ 5V, Pin-for-Pin Compatible with the LTC3830 LTC1430/LTC1430A High Power Step-Down Switching Regulator Controllers LTC1530 LTC1628 LTC1702 LTC1705 LTC1709 LTC1736 LTC1773 LTC1778 LTC1873 LTC1876 LTC1929 LTC3713 LTC3831 LTC3832 High Power Synchronous Switching Regulator Controller Dual High Efficiency 2-Phase Synchronous Step-Down Controller Dual High Efficiency 2-Phase Synchronous Step-Down Controller Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID Plus LDO 2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller Synchronous Step-Down Controller with 5-Bit Mobile VID Control Synchronous Step-Down Controller in MS10 Wide Operating Range/Step-Down Controller, No RSENSE Dual Synchronous Switching Regulator with 5-Bit Desktop VID 2-Phase, Dual Step-Down Synchronous Controller with Integrated Step-Up DC/DC Regulator 2-Phase, Synchronous High Efficiency Converter with Mobile VID Low Input Voltage, High Power, No RSENSE, Step-Down Synchronous Controller High Power Synchronous Switching Regulator Controller for DDR Memory Termination Synchronous Step-Down Controller No RSENSE is a trademark of Linear Technology Corporation. sn3830 3830fs 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U Typical 3.3V to 2.5V, 14A Application 12V 3.3V CIN 330µF ×2 + 0.1µF 10µF 6.8k Q1 1k Q2 D1 LO 1.3µH 2.5V 14A 16.5k 1% 16.9k 1% PVCC2 VCC SS PVCC1 G1 IMAX LTC3830 IFB FREQSET G2 PGND GND SENSE + SENSE – NC FB NC + SHDN RC 18k CC 1500pF SHDN COMP COUT 470µF ×3 CIN: SANYO POSCAP 6TPB330M COUT: SANYO POSCAP 4TPB470M D1: MBRS330T3 LO: SUMIDA CDEP105-1R3 Q1, Q2: VISHAY Si7892DP 3830 TA01 LT/TP 0103 2K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001