LTC3851IUD-1-TRPBF

FEATURES n n n n n n n n n n n n n n n LTC3851-1 Synchronous Step-Down Switching Regulator Controller DESCRIPTION The LTC®3851-1 is a high performance synchronous step-down switching regulator controller that drives an all N-channel synchronous power MOSFET stage. A constant frequency current mode architecture allows a phase-lockable frequency of up to 750kHz. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3851-1 features a precision 0.8V reference and a power good indicator. A wide 4V to 38V (40V absolute maximum) input supply range encompasses most battery configurations and intermediate bus voltages. The TK/SS pin ramps the output voltage during start-up and shutdown with coincident or ratiometric tracking. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The MODE/PLLIN pin selects among Burst Mode operation, pulse skipping mode or continuous inductor current mode at light loads and allows the IC to be synchronized to an external clock. The LTC3851-1 is identical to the LTC3851 except that the ILIM pin is replaced by PGOOD. L, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131. Wide VIN Range: 4V to 38V Operation RSENSE or DCR Current Sensing ±1% Output Voltage Accuracy Power Good Output Voltage Monitor Phase-Lockable Fixed Frequency: 250kHz to 750kHz Dual N-Channel MOSFET Synchronous Drive Very Low Dropout Operation: 99% Duty Cycle Adjustable Output Voltage Soft-Start or Tracking Output Current Foldback Limiting Output Overvoltage Protection OPTI-LOOP® Compensation Minimizes COUT Selectable Continuous, Pulse-Skipping or Burst Mode® Operation at Light Loads Low Shutdown IQ: 20μA VOUT Range: 0.8V to 5.5V Thermally Enhanced 16-Lead MSOP or 3mm × 3mm QFN Package APPLICATIONS n n n n Automotive Systems Telecom Systems Industrial Equipment Distributed DC Power Systems TYPICAL APPLICATION High Efficiency Synchronous Step-Down Converter 100k INTVCC 82.5k 0.1μF PGO0D VIN 0.68μH 0.1μF 3.01k INTVCC ITH 15k 330pF PLLIN/MODE SENSE– VFB BG GND SENSE+ 0.047μF 30.1k 154k 4.7μF FREQ/PLLFLTR TG RUN SW LTC3851-1 BOOST TK/SS 22μF VIN 4.5V TO 38V VOUT 3.3V 15A 330μF 2 Efficiency and Power Loss vs Load Current 100 VIN = 12V 95 VOUT = 3.3V EFFICIENCY POWER LOSS (mW) 1000 POWER LOSS 10000 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 10 0.1μF 2200pF 100 48.7k 38511 TA01a 100 1000 10000 LOAD CURRENT (mA) 10 100000 38511TA01b 38511f 1 LTC3851-1 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN) ......................... 40V to –0.3V Topside Driver Voltage (BOOST) ................ 46V to –0.3V Switch Voltage (SW) ..................................... 40V to –5V INTVCC, (BOOST – SW), RUN, PGOOD ........ 6V to –0.3V TK/SS .................................................... INTVCC to –0.3V SENSE+, SENSE–.......................................... 6V to –0.3V MODE/PLLIN, FREQ/PLLFLTR ............... INTVCC to –0.3V ITH, VFB Voltages .......................................... 3V to –0.3V INTVCC Peak Output Current ..................................50mA Operating Junction Temperature Range (Notes 2, 3) ............................................ –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MSE .................................................................. 300°C PIN CONFIGURATION FREQ/PLLFLTR TOP VIEW MODE/PLLIN SW MODE/PLLIN FREQ/PLLFLTR RUN TK/SS ITH FB SENSE– SENSE+ 1 2 3 4 5 6 7 8 17 16 15 14 13 12 11 10 9 SW TG BOOST VIN INTVCC BG GND PGOOD 16 15 14 13 RUN 1 TK/SS 2 ITH 3 FB 4 5 SENSE– 6 SENSE+ 7 PGOOD 8 GND 17 12 BOOST 11 VIN 10 INTVCC 9 BG MSE PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 35°C/W TO 40°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB UD PACKAGE 16-LEAD (3mm 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC3851EMSE-1#PBF LTC3851IMSE-1#PBF LTC3851EUD-1#PBF LTC3851IUD-1#PBF TAPE AND REEL LTC3851EMSE-1#TRPBF LTC3851IMSE-1#TRPBF LTC3851EUD-1#TRPBF LTC3851IUD-1#TRPBF PART MARKING* 38511 38511 LDNT LDNT PACKAGE DESCRIPTION 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead (3mm × 3mm) Plastic QFN 16-Lead (3mm × 3mm) Plastic QFN TEMPERATURE RANGE –40°C to 85°C –40°C to 125°C –40°C to 85°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ TG TOP VIEW 38511f 2 LTC3851-1 ELECTRICAL CHARACTERISTICS SYMBOL VIN VFB IFB VREFLNREG VLOADREG PARAMETER Input Operating Voltage Range Regulated Feedback Voltage Feedback Current Reference Voltage Line Regulation Output Voltage Load Regulation ITH = 1.2V (Note 4) (Note 4) VIN = 6V to 38V (Note 4) (Note 4) Measured in Servo Loop, ΔITH = 1.2V to 0.7V (Note 4) Measured in Servo Loop, ΔITH = 1.2V to 1.6V gm gm GBW IQ Transconductance Amplifier gm Transconductance Amp Gain Bandwidth Input DC Supply Current Normal Mode Shutdown Undervoltage Lockout on INTVCC UVLO Hysteresis Feedback Overvoltage Lockout SENSE Pins Total Current Soft-Start Charge Current RUN Pin On Threshold RUN Pin On Hysteresis Maximum Current Sense Threshold TG Driver Pull-Up On-Resistance TG Driver Pull-Down On-Resistance BG Driver Pull-Up On-Resistance BG Driver Pull-Down On-Resistance TG Transition Time Rise Time Fall Time BG Transition Time Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation VFB = 0.7V, VSENSE = 3.3V TG High TG Low BG High BG Low (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF Each Driver CLOAD = 3300pF Each Driver (Note 7) 6V < VIN < 38V ICC = 0mA to 50mA 4.8 l l l The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V unless otherwise noted. CONDITIONS MIN 4 0.792 0.800 –10 0.002 0.01 TYP MAX 38 0.808 –50 0.02 0.1 UNITS V V nA %/V % Main Control Loops l –0.01 2 3 1 20 3.25 0.4 –0.1 % mmho MHz mA μA V V ITH = 1.2V, Sink/Source = 5μA (Note 4) ITH = 1.2V (Note 5) VOUT = 5V VRUN = 0V VINTVCC Ramping Down Measured at VFB VTK/SS = 0V VRUN Rising l l 35 UVLO UVLO Hys VOVL ISENSE ITK/SS VRUN VRUNHYS VSENSE(MAX) TG RUP TG RDOWN BG RUP BG RDOWN TG tr TG tf BG tr BG tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCC VLDO INT 0.86 0.6 1.10 40 0.88 ±1 1 1.22 130 50 2.6 1.5 2.4 1.1 25 25 25 25 30 30 90 5 0.5 0.90 ±2 2 1.35 65 V μA μA V mV mV Ω Ω Ω Ω ns ns ns ns ns ns ns INTVCC Linear Regulator 5.2 V % 38511f 3 LTC3851-1 ELECTRICAL CHARACTERISTICS SYMBOL fNOM fLOW fHIGH RMODE/PLLIN IFREQ PARAMETER Nominal Frequency Lowest Frequency Highest Frequency MODE/PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level fMODE > fOSC fMODE < fOSC IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Set Regulated Voltage VFB Ramping Negative VFB Ramping Positive –12 8 –10 10 Oscillator and Phase-Locked Loop RFREQ = 60k RFREQ = 160k RFREQ = 36k 480 220 710 500 250 750 100 –10 10 0.1 0.3 ±1 –8 12 530 280 790 kHz kHz kHz kΩ μA μA V μA % % The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V unless otherwise noted. CONDITIONS MIN TYP MAX UNITS PGOOD Output VPGL IPGOOD VPG Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3851E-1 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3851I-1 is guaranteed over the –40°C to 125°C operating junction temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3851MSE-1: TJ = TA + (PD • 90°C/W) LTC3851UD-1: TJ = TA + (PD • 68°C/W) Note 4: The LTC3851-1 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ~40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current and Mode 100 VIN = 12V 90 VOUT = 1.5V BURST PULSE SKIP EFFICIENCY(%) 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 10 100 1000 10000 LOAD CURRENT (mA) 100000 38511 G01 Efficiency vs Output Current and Mode 100 BURST 90 80 70 60 50 40 30 VIN = 12V VOUT = 3.3V FIGURE 11 CIRCUIT 10 100 1000 10000 LOAD CURRENT (mA) 100000 38511 G02 Efficiency vs Output Current and Mode 80 70 EFFICIENCY(%) 60 50 40 30 20 10 0 BURST PULSE SKIP CCM PULSE SKIP CCM CCM 20 10 0 10 VIN = 12V VOUT = 5V 100 1000 10000 LOAD CURRENT (mA) 100000 38511 G03 38511f 4 LTC3851-1 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency and Power Loss vs Input Voltage 100 95 90 85 80 75 70 4 8 16 12 24 20 INPUT VOLTAGE (V) 28 32 1000 EFFICIENCY, IOUT = 5A POWER LOSS, IOUT = 5A POWER LOSS (mW) 10000 ILOAD 5A/DIV 0.2A TO 7.5A IL 5A/DIV VOUT 100mV/DIV AC COUPLED VOUT = 1.5V 100μs/DIV VIN = 12V FIGURE 11 CIRCUIT 100 38511 G05 Load Step (Burst Mode Operation) ILOAD 5A/DIV 0.2A TO 7.5A IL 5A/DIV VOUT 100mV/DIV AC COUPLED Load Step (Forced Continuous Mode) EFFICIENCY (%) EFFICIENCY, IOUT = 0.5A POWER LOSS, IOUT = 0.5A VIN = 12V VOUT = 3.3V FIGURE 11 CIRCUIT VOUT = 1.5V 100μs/DIV VIN = 12V FIGURE 11 CIRCUIT 38511 G06 38511 G04 Load Step (Pulse skip Mode) ILOAD 5A/DIV 0.2A TO 7.5A IL 5A/DIV VOUT 100mV/DIV AC COUPLED VOUT = 1.5V 100μs/DIV VIN = 12V FIGURE 11 CIRCUIT 3851 G07 Inductor Current at Light Load FORCED CONTINOUS MODE 5A/DIV Burst Mode OPERATION 5A/DIV PULSE SKIP MODE 5A/DIV VOUT = 1.5V 1μs/DIV VIN = 12V ILOAD = 1mA FIGURE 11 CIRCUIT 38511 G08 Start-Up with Prebiased Output at 2V VOUT 2V/DIV TK/SS 0.5V/DIV VFB 0.5V/DIV 20ms/DIV 38511 G09 Coincident Tracking with Master Supply VMASTER 0.5V/DIV Ratiometric Tracking with Master Supply 3.0 VMASTER 0.5V/DIV 2.5 SUPPLY CURRENT (mA) 10ms/DIV 38511 G11 Input DC Supply Current vs Input Voltage VOUT 2A LOAD 0.5V/DIV 2.0 1.5 1.0 0.5 0 4 8 12 16 20 24 28 32 INPUT VOLTAGE (V) 36 40 VOUT 2A LOAD 0.5V/DIV 10ms/DIV 38511 G10 38511 G12 38511f 5 LTC3851-1 TYPICAL PERFORMANCE CHARACTERISTICS INTVCC Line Regulation 5.3 5.1 4.9 INTVCC VOLTAGE (V) 4.7 4.5 4.3 4.1 3.9 3.7 3.5 4 8 12 16 20 24 28 32 INPUT VOLTAGE (V) 36 40 ILOAD = 0mA VSENSE THRESHOLD (mV) ILOAD = 25mA 90 80 70 VSENSE (mV) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VSENSE COMMON MODE VOLTAGE (V) 5 Maximum Current Sense Threshold vs Common Mode Voltage 90 80 70 60 50 40 30 20 10 0 –10 –20 Maximum Peak Current Sense Threshold vs ITH Voltage DUTY CYCLE RANGE: 0% TO 100% 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VITH (V) 38511 G15 38511 G13 38511 G14 Burst Mode Peak Current Sense Threshold vs ITH Voltage 60 50 40 30 20 MINIMUIM 10 0 BURST COMPARATOR FALLING THESHOLD: VITH = 0.4V 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VITH (V) 38511 G16 Maximum Current Sense Threshold vs Duty Cycle 90 CURRENT SENSE THRESHOLD (mV) 90 80 MAXIMUM VSENSE (mV) 70 60 50 40 30 20 10 0 0 20 60 40 DUTY CYCLE (%) 80 100 38511 G17 Maximum Current Sense Threshold vs Feedback Voltage (Current Foldback) MAXIMUIM 80 70 60 50 40 30 20 10 0 VSENSE (mV) 0 0.1 0.2 0.3 0.4 0.5 0.6 FEEDBACK VOLTAGE (V) 0.7 0.8 38511 G18 TK/SS Pull-Up Current vs Temperature 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 RUN PIN VOLTAGE (V) TK/SS CURRENT (μA) 1.3 1.4 Shutdown (RUN) Threshold vs Temperature 806 REGULATED FEEDBACK VOLTAGE (mV) 804 802 800 798 796 Regulated Feedback Voltage vs Temperature RUN RISING THRESHOLD (ON) 1.2 RUN FALLING THRESHOLD (OFF) 1.1 1.0 0.9 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 794 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 38511 G19 38511 G20 38511 G21 38511f 6 LTC3851-1 TYPICAL PERFORMANCE CHARACTERISTICS Oscillator Frequency vs Temperature 900 800 FREQUENCY (kHz) 700 600 RFREQ = 60k 500 400 300 200 –50 –25 RFREQ = 150k 50 25 75 0 TEMPERATURE (°C) 100 125 RFREQ = 36k FREQUENCY (kHz) 420 415 410 405 400 395 390 385 380 5 10 15 30 25 20 INPUT VOLTAGE (V) 35 40 Oscillator Frequency vs Input Voltage INTVCC VOLTAGE AT UVLO THRESHOLD (V) RFREQ = 80k 5 Undervoltage Lockout Threshold (INTVCC) vs Temperature 4 INTVCC RAMPING UP INTVCC RAMPING DOWN 3 2 1 0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 125 38511 G22 38511 G23 38511 G24 Shutdown Input DC Supply Current vs Input Voltage SHUTDOWN INPUT DC SUPPLY CURRENT (μA) 40 SHUTDOWN SUPPLY CURRENT (μA) 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 40 35 30 25 20 15 10 5 Shutdown Input DC Supply Current vs Temperature 0 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 38511 G25 38511 G26 Input DC Supply Current vs Temperature 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 –25 CURRENT SENSE THRESHOLD (mV) INPUT DC SUPPLY CURRENT (mA) 90 80 70 60 50 40 30 20 10 0 Maximum Current Sense Threshold vs INTVCC Voltage 50 25 75 0 TEMPERATURE (°C) 100 125 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 INTVCC VOLTAGE(V) 38511 G28 38511 G27 38511f 7 LTC3851-1 PIN FUNCTIONS (MSE/UD) MODE/PLLIN (Pin 1/Pin 15): Force Continuous Mode, Burst Mode or Pulse skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to INTVCC to force continuous conduction mode of operation. Connect to GND to enable pulse skipping mode of operation. To select Burst Mode operation, tie this pin to INTVCC through a resistor no less than 50k, but no greater than 250k. A clock on the pin will force the controller into forced continuous mode of operation and synchronize the internal oscillator. FREQ/PLLFLTR (Pin 2/Pin 16): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, a resistor can be connected between this pin and GND to vary the frequency of the internal oscillator. RUN (Pin 3/Pin 1): Run Control Input. A voltage above 1.25V on this pin turns on the IC. However, forcing this pin below 1.1V causes the IC to shut down the IC. There is a 2μA pull-up current on this pin. TK/SS (Pin 4/Pin 2): Output Voltage Tracking and Soft-Start Input. A capacitor to ground at this pin sets the ramp rate for the output voltage. An internal soft-start current of of 1μA charges this capacitor. ITH (Pin 5/Pin 3): Current Control Threshold and Error Amplifier Compensation Point. The current comparator tripping threshold increases with its ITH control voltage. FB (Pin 6/Pin 4): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage from an external resistive divider across the output. SENSE– (Pin 7/Pin 5): Current Sense Comparator Inverting Input. The (–) input to the current comparator is connected to the output. SENSE+ (Pin 8/Pin 6): Current Sense Comparator Noninverting Input. The (+) input to the current comparator is normally connected to the DCR sensing network or current sensing resistor. PGOOD (Pin 9/Pin 7): Power Good Indicator Output. Opendrain logic out that is pulled to ground when the output voltage exceeds the ±10% regulation window, after the internal 17μs power bad mask timer expires. GND (Pin 10/Pin 8): Ground. All small-signal components and compensation components should be Kelvin connected to this ground. The (–) terminal of CVCC and the (–) terminal of CIN should be closely connected to this pin. BG (Pin 11/Pin 9): Bottom Gate Driver Output. This pin drives the gate of the bottom N-channel MOSFET between GND and INTVCC. INTVCC (Pin 12/Pin 10): Internal 5V Regulator Output. The control circuit is powered from this voltage. Decouple this pin to GND with a minimum 2.2μF low ESR tantalum or ceramic capacitor. VIN (Pin 13/Pin 11): Main Input Supply. Decouple this pin to GND with a capacitor. BOOST (Pin 14/Pin 12): Boosted Floating Driver Supply. The (+) terminal of the boost-strap capacitor is connected to this pin. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. TG (Pin 15/Pin 13): Top Gate Driver Output. This is the output of a floating driver with a voltage swing equal to INTVCC superimposed on the switch node voltage. SW (Pin 16/Pin 14): Switch Node Connection to the Inductor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. Exposed Pad (Pin 17): Ground. Must be soldered to PCB, providing a local ground for the IC. 38511f 8 LTC3851-1 FUNCTIONAL DIAGRAM FREQ/PLLFLTR MODE/PLLIN VIN + 100k CIN VIN MODE/SYNC DETECT PLL-SYNC 0.8V 5V REG – + BOOST BURSTEN CB M1 SW OSC S R Q PULSE SKIP TG + ICMP 5k ON – IREV – + RUN SWITCH LOGIC AND ANTISHOOT THROUGH SENSE+ SENSE– INTVCC BG DB L1 VOUT + COUT M2 OV SLOPE COMPENSATION CVCC GND PGOOD INTVCC UVLO 1 100k ITHB UV + – 0.72V VFB R2 R1 VIN SLEEP OV SS RUN + – + RUN 1μA 0.88V EA 0.64V 0.4V 38511 FD ITH RC CC1 + 0.8V REF 1.25V 2μA – – –++ + – TK/SS CSS 38511f 9 LTC3851-1 OPERATION Main Control Loop The LTC3851-1 is a constant frequency, current mode step-down controller. During normal operation, the top MOSFET is turned on when the clock sets the RS latch, and is turned off when the main current comparator, ICMP , resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, IREV, or the beginning of the next cycle. INTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. An internal 5V low dropout linear regulator supplies INTVCC power from VIN. The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage, VIN, decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 1/10 of the clock period every tenth cycle to allow CB to recharge. However, it is recommended that there is always a load present during the drop-out transition to ensure CB is recharged. Shutdown and Start-Up (RUN and TK/SS) The LTC3851-1 can be shut down using the RUN pin. Pulling this pin below 1.1V disables the controller and most of the internal circuitry, including the INTVCC regulator. Releasing the RUN pin allows an internal 2μA current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller’s output voltage, VOUT , is controlled by the voltage on the TK/SS pin. When the voltage on the TK/SS pin is less than the 0.8V internal reference, the LTC3851-1 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.8V reference. This allows the TK/SS pin to be used to program a soft-start by connecting an external capacitor from the TK/SS pin to GND. An internal 1μA pull-up current charges this capacitor creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively, the TK/SS pin can be used to cause the start-up of VOUT to “track” another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the RUN pin is pulled low to disable the controller, or when INTVCC drops below its undervoltage lockout threshold of 3.2V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the external MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse skipping or Continuous Conduction) The LTC3851-1 can be enabled to enter high efficiency Burst Mode operation, constant frequency pulse skipping mode or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to INTVCC. To select pulse skipping mode of operation, float the MODE/PLLIN pin or tie it to GND. To select Burst Mode operation, tie MODE/PLLIN to INTVCC through a resistor no less than 50k, but no greater than 250k. When the controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-forth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.4V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. 38511f 10 LTC3851-1 OPERATION In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IREV , turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference to audio circuitry. When the MODE/PLLIN pin is connected to GND, the LTC3851-1 operates in PWM pulse skipping mode at light loads. At very light loads the current comparator, ICMP , may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ/PLLFLTR and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3851-1 can be selected using the FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ/PLLFLTR pin can be used to program the controller’s operating frequency from 250kHz to 750kHz. A phase-locked loop (PLL) is available on the LTC3851-1 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller operates in forced continuous mode of operation when it is synchronized. A series RC should be connected between the FREQ/PLLFLTR pin and GND to serve as the PLL’s loop filter. It is suggested that the external clock be applied before enabling the controller unless a second resistor is connected in parallel with the series RC loop filter network. The second resistor prevents low switching frequency operation if the controller is enabled before the clock. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) Pin The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 0.8V reference voltage. The PGOOD pin is also pulled low when the RUN pin is low (shut down) or when the LTC3851-1 is in the soft-start or tracking phase. When the VFB pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD pin will flag power good immediately when the VFB pin is within the ±10% window. However, there is an internal 17μs power bad mask when VFB goes out of the ±10% window. 38511f 11 LTC3851-1 APPLICATIONS INFORMATION The Typical Application on the first page of this data sheet is a basic LTC3851-1 application circuit. The LTC3851-1 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice of the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and the inductor value. Next, the power MOSFETs and Schottky diodes are selected. Finally, input and output capacitors are selected. The circuit shown on the first page can be configured for operation up to 40V at VIN. SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 0V to 5.5V. Both SENSE pins are high impedance inputs with small base currents of less than 1μA. When the SENSE pins ramp up from 0V to 1.4V, the small base currents flow out of the SENSE pins. When the SENSE pins ramp down from 5V to 1.1V, the small base currents flow into the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 1. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold, VMAX = 50mV. The current comparator threshold sets the maximum peak of the inductor current, yielding a maximum average output current, IMAX, equal to the peak value less half the peak-to-peak ripple current, ΔIL. Allowing a margin VIN INTVCC BOOST TG SW LTC3851-1 BG GND SENSE+ SENSE– RSENSE VOUT VIN FILTER COMPONENTS PLACED NEAR SENSE PINS 38511 F01 Figure 1. Using a Resistor to Sense Current with the LTC3851-1 of 20% for variations in the IC and external component values yields: RSENSE = 0.8 • VMAX IMAX + ΔIL/ 2 Inductor DCR Sensing For applications requiring the highest possible efficiency, the LTC3851-1 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1mΩ for today’s low value, high current inductors. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR multiplied by R2/(R1 + R2). Therefore, R2 may be used to scale the voltage across the sense terminals when the DCR is greater than the target sense resistance. Check the manufacturer’s data sheet for specifications regarding the inductor DCR, in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter. 38511f 12 LTC3851-1 APPLICATIONS INFORMATION VIN INTVCC VIN BOOST TG SW LTC3851-1 BG GND SENSE+ C1* SENSE– *PLACE C1 NEAR SENSE+, SENSE– PINS R1||R2 • C1 = L DCR 38511 F02 INDUCTOR L DCR VOUT Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ΔIL = 0.3(IMAX). The maximum ΔIL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below ≈10% of the current limit determined by RSENSE. Lower inductor values (higher ΔIL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection R1 R2 R2 RSENSE(EQ) = DCR R1 + R2 Figure 2. Current Mode Control Using the Inductor DCR Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%. However, the LTC3851-1 uses a novel scheme that allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance or frequency and increases with higher VIN: ΔIL = ⎛V⎞ 1 VOUT ⎜1 – OUT ⎟ f •L VIN ⎠ ⎝ Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for the LTC3851-1 controller: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. 38511f 13 LTC3851-1 APPLICATIONS INFORMATION The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up. Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode, the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN VIN – VOUT VIN Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diode conducts during the dead time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good size due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. Soft-Start and Tracking The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT (IMAX )2 (1+ δ)RDS(ON) + VIN The LTC3851-1 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When the LTC3851-1 is configured to soft-start by itself, a capacitor should be connected to the TK/SS pin. The LTC3851-1 is in the shutdown state if the RUN pin voltage is below 1.25V. TK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.25V, the LTC3851-1 powers up. A soft-start current of 1μA then starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is Synchronous Switch Duty Cycle = (VIN)2 ⎛ IMAX ⎞ (RDR)(CMILLER) • ⎜2⎟ ⎝ ⎠ ⎡ 1 1⎤ + ⎢ ⎥ ( f) ⎢ VINTVCC – VTH(MIN) VTH(MIN) ⎥ ⎣ ⎦ PSYNC = VIN – VOUT (IMAX )2 (1+ δ)RDS(ON) VIN where δ is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTH(MIN) is the typical MOSFET minimum threshold voltage. 38511f 14 LTC3851-1 APPLICATIONS INFORMATION 0V to 0.8V on the TK/SS pin. The total soft-start time can be calculated as: t SOFT-START = 0.8 • CSS 1.0μA Output Voltage Tracking The LTC3851-1 allows the user to program how its output ramps up and down by means of the TK/SS pins. Through this pin, the output can be set up to either coincidentally or ratiometrically track with another supply’s output, as shown in Figure 3. In the following discussions, VMASTER refers to a master supply and VOUT refers to the LTC3851-1’s output as a slave supply. To implement the coincident tracking in Figure 3a, connect a resistor divider to VMASTER and connect its midpoint to the TK/SS pin of the LTC3851-1. The ratio of this divider should be selected the same as that of the LTC3851-1’s feedback divider as shown in Figure 4a. In this tracking mode, VMASTER must be higher than VOUT. To implement ratiometric tracking, the ratio of the resistor divider connected to VMASTER is determined by: VMASTER R2 ⎛ R3 + R4⎞ = ⎝ ⎠ VOUT R4 ⎜ R1+ R2 ⎟ So which mode should be programmed? While either mode in Figure 4 satisfies most practical applications, the coincident mode offers better output regulation. This concept can be better understood with the help of Figure 5. At the input stage of the LTC3851-1’s error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse skipping mode up to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.72V. The output ripple is minimized during the 80mV forced continuous mode window. When the regulator is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, one can select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another supply after the soft-start phase expires, the LTC3851-1 must be configured for forced continuous operation by connecting MODE/PLLIN to INTVCC. VMASTER OUTPUT VOLTAGE OUTPUT VOLTAGE VMASTER VOUT VOUT TIME TIME 38511 F03 (3a) Coincident Tracking (3b) Ratiometric Tracking Figure 3. Two Different Modes of Output Voltage Tracking 38511f 15 LTC3851-1 APPLICATIONS INFORMATION VMASTER R3 TO TK/SS PIN R4 TO VFB PIN R4 R3 TO TK/SS PIN R2 VOUT VMASTER R1 TO VFB PIN R4 38511 F04 VOUT R3 (4a) Coincident Tracking Setup (4b) Ratiometric Tracking Setup Figure 4. Setup for Coincident and Ratiometric Tracking I I + D1 TK/SS 0.8V VFB D3 38511 F05 D2 EA – The LDO can supply a peak current of 50mA and must be bypassed to ground with a minimum of 2.2μF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1μF ceramic capacitor placed directly adjacent to the INTVCC and GND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3851-1 to be exceeded. The INTVCC current, which is dominated by the gate charge current, is supplied by the 5V LDO. Power dissipation for the IC in this case is highest and is approximately equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3851-1 INTVCC current is limited to less than 17mA from a 36V supply in the GN package: TJ = 70°C + (17mA)(36V)(90°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = INTVCC) at maximum VIN. Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin 38511f Figure 5. Equivalent Input Circuit of Error Amplifier is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TK/SS voltage is substantially higher than 0.8V at steady-state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB and the internal precision 0.8V reference. In the ratiometric mode, however, TK/SS equals 0.8V at steady-state. D1 will divert part of the bias current to make VFB slightly lower than 0.8V. Although this error is minimized by the exponential I-V characteristic of the diode, it does impose a finite amount of output voltage deviation. Furthermore, when the master supply’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. INTVCC Regulator The LTC3851-1 features a PMOS low dropout linear regulator (LDO) that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3851-1 ’s internal circuitry. The LDO regulates the voltage at the INTVCC pin to 5V. 16 LTC3851-1 APPLICATIONS INFORMATION is low. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET. The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). Undervoltage Lockout The LTC3851-1 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.2V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 400mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a precision turn-on reference of 1.25V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. CIN Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: ⎛V ⎞ V IRMS ≅ IO(MAX ) OUT ⎜ IN – 1 VIN ⎝ VOUT ⎟ ⎠ 1/ 2 required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. COUT Selection The selection of COUT is primarily determined by the effective series resistance, ESR, to minimize voltage ripple. The output ripple, ΔVOUT, in continuous mode is determined by: ⎛ 1⎞ ΔVOUT ≈ ΔIL ⎜ESR + 8 fCOUT ⎟ ⎝ ⎠ where f = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. With ΔIL = 0.3IOUT(MAX) and allowing 2/3 of the ripple to be due to ESR, the output ripple will be less than 50mV at maximum VIN and: COUT Required ESR < 2.2RSENSE COUT > 1 8 fRSENSE The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. The selection of output capacitors for applications with large load current transients is primarily determined by the voltage tolerance specifications of the load. The resistive component of the capacitor, ESR, multiplied by the load current change, plus any output voltage ripple must be within the voltage tolerance of the load. 38511f This formula has a maximum at VIN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than 17 LTC3851-1 APPLICATIONS INFORMATION The required ESR due to a load current step is: RESR ≤ ΔV ΔI AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 1.5mm to 4.1mm. Aluminum electrolytic capacitors can be used in cost-driven applications, provided that consideration is given to ripple current ratings, temperature and long-term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Panasonic SP and Sprague 595D series. Consult manufacturers for other specific recommendations. Like all components, capacitors are not ideal. Each capacitor has its own benefits and limitations. Combinations of different capacitor types have proven to be a very cost effective solution. Remember also to include high frequency decoupling capacitors. They should be placed as close as possible to the power pins of the load. Any inductance present in the circuit board traces negates their usefulness. Setting Output Voltage The LTC3851-1 output voltage is set by an external feedback resistive divider carefully placed across the output, as shown in Figure 6. The regulated output voltage is determined by: ⎛ R⎞ VOUT = 0.8 V ⎜1+ B ⎟ ⎝ RA ⎠ To improve the transient response, a feed-forward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT LTC3851-1 VFB RA 38511 F06 where ΔI is the change in current from full load to zero load (or minimum load) and ΔV is the allowed voltage deviation (not including any droop due to finite capacitance). The amount of capacitance needed is determined by the maximum energy stored in the inductor. The capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. The opposite load current transition is generally determined by the control loop OPTI-LOOP components, so make sure not to over compensate and slow down the response. The minimum capacitance to assure the inductors’ energy is adequately absorbed is: COUT L (ΔI) > 2 (ΔV) VOUT 2 where ΔI is the change in load current. Manufacturers such as Nichicon, United Chemi-Con and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications, ESR, RMS current handling and load step specifications may require multiple capacitors in parallel. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, RB CFF Figure 6. Settling Output Voltage 38511f 18 LTC3851-1 APPLICATIONS INFORMATION Fault Conditions: Current Limit and Current Foldback The LTC3851-1 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 40% of its nominal output level, the maximum sense voltage is progressively lowered from its maximum programmed value to about 25% of the that value. Foldback current limiting is disabled during softstart or tracking. Under short-circuit conditions with very low duty cycles, the LTC3851-1 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC3851-1 (≈90ns), the input voltage and inductor value: ΔIL(SC) = tON(MIN) • VIN L Phase-Locked Loop and Frequency Synchronization The LTC3851-1 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. This phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the FREQ/PLLFLTR pin. Note that the LTC3851-1 can only be synchronized to an external clock whose frequency is within range of the LTC3851-1’s internal VCO.This is guaranteed to be between 250kHz and 750kHz. A simplified block diagram is shown in Figure 8. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC , then current is sunk continuously from the phase detector output, pulling down the FREQ/PLLFLTR pin. When the external clock frequency is less than fOSC , current is sourced continuously, pulling up the FREQ/PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the FREQ/PLLFLTR pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. 2.7V RLP CLP FREQ/PLLFLTR MODE/ PLLIN EXTERNAL OSCILLATOR DIGITAL PHASE/ FREQUENCY DETECTOR The resulting short-circuit current is: ISC = 1/ 4MaxVSENSE 1 – ΔIL(SC) 2 RSENSE Programming Switching Frequency To set the switching frequency of the LTC3851-1, connect a resistor, RFREQ, between FREQ/PLLFLTR and GND. The relationship between the oscillator frequency and RFREQ is shown in Figure 7. A 0.1μF bypass capacitor should be connected in parallel with RFREQ. 750 700 OSCILLATOR FREQUENCY (kHz) 650 600 550 500 450 400 350 300 250 20 40 60 80 100 120 RFREQ (kΩ) 140 160 VCO 38511 F07 38511 F08 Figure 7. Relationship Between Oscillator Frequency and Resistor Connected Between FREQ/PLLFLTR and GND Figure 8. Phase-Locked Loop Block Diagram 38511f 19 LTC3851-1 APPLICATIONS INFORMATION The loop filter components, CLP and RLP , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP is 1k to 10k and CLP is 2200pF to 0.01μF . When the external oscillator is active before the LTC3851 is enabled, the internal oscillator frequency will track the external oscillator frequency as described in the preceding paragraphs. In situations where the LTC3851 is enabled before the external oscillator is active, a low free-running oscillator frequency of approximately 50kHz will result. It is possible to increase the free-running, pre-synchronization frequency by adding a second resistor in parallel with RLP and CLP . The second resistor will also cause a phase difference between the internal and external oscillator signals. The magnitude of the phase difference is inversely proportional to the value of the second resistor. The external clock (on MODE/PLLIN pin) input high threshold is nominally 1.6V, while the input low threshold is nominally 1.2V. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3851-1 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN( f) amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3851-1 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver current. VIN current typically results in a small (1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can 38511f 21 LTC3851-1 APPLICATIONS INFORMATION alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3851-1. These items are also illustrated graphically in the layout diagram of Figure 9. Check the following in your layout: 1. Are the board signal and power grounds segregated? The LTC3851-1 GND pin should tie to the ground plane close to the input capacitor(s). The low current or signal ground lines should make a single point tie directly to the GND pin. The synchronous MOSFET source pins should connect to the input capacitor(s) ground. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. The 47pF to 100pF capacitor should be as close as possible to the LTC3851-1. Be careful locating the feedback resistors too far away from the LTC3851-1. The VFB line should not be routed close to any other nodes with high slew rates. 3. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the LTC3851-1. Ensure accurate current sensing with Kelvin connections as shown in Figure 10. Series resistance can be added to the SENSE lines to increase noise rejection and to compensate for the ESL of RSENSE. + 0.1mF 1 MODE/PLLIN SW 16 RFREQ 2 3 CSS 4 RC 47pF 6 CC CC2 5 RUN BOOST LTC3851-1 14 VIN TK/SS VIN 13 DB CB ITH INTVCC 12 VFB SENSE– SENSE+ BG 11 + 4.7μF 7 1000pF 8 GND 10 RPGOOD VPULL-UP L1 + D1 M2 FREQ/PLLFLTR TG 15 M1 CIN – PGOOD 9 – R1 COUT RSENSE VOUT R2 Figure 9. LTC3851-1 Layout Diagram 38511f 22 + 38511 F09 + LTC3851-1 APPLICATIONS INFORMATION HIGH CURRENT PATH 38511 F10 SENSE+ SENSE– CURRENT SENSE RESISTOR (RSENSE) The duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pick-up at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, the Schottky and the top MOSFET to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC. Design Example As a design example, assume VIN = 12V (nominal), VIN = 22V (maximum), VOUT = 1.8V, IMAX = 5A, and f = 250kHz (refer to Figure 12). The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Connect a 160k resistor between the FREQ/PLLFLTR and GND pins, generating 250kHz operation. The minimum inductance for 30% ripple current is: ΔIL = ⎛V⎞ 1 VOUT ⎜1− OUT ⎟ VIN ⎠ (f)(L) ⎝ Figure 10. Kelvin Sensing RSENSE 4. Does the (+) terminal of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). 5. Is the INTVCC decoupling capacitor connected closely between INTVCC and GND? This capacitor carries the MOSFET driver peak currents. An additional 1μF ceramic capacitor placed immediately next to the INTVCC and GND pins can help improve noise performance. 6. Keep the switching node (SW), top gate node (TG) and boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” (Pin 9 to Pin 16) of the LTC3851-1 and occupy minimum PC trace area. PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. 38511f 23 LTC3851-1 APPLICATIONS INFORMATION A 4.7μH inductor will produce 28% ripple current and a 3.3μH will result in 40%. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 6A, for the 3.3μH value. Increasing the ripple current will also help ensure that the minimum on-time of 90ns is not violated. The minimum on-time occurs at maximum VIN: tON(MIN) = VIN(MAX ) (f) VOUT = 1.8 V = 327ns 7 22V (250kHz) A short-circuit to ground will result in a folded back current of: ISC = 29mV 1 ⎛ 90ns (22V)⎞ –⎜ = 2.02A 0.0125Ω 2 ⎝ 3.3μH ⎟ ⎠ with a typical value of RDS(ON) and δ = (0.005/°C)(25°C) = 0.125. The resulting power dissipated in the bottom MOSFET is: PSYNC = 22V (2.02A)2 (1.125)(0.022Ω) = 101.0mW 22V The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances. 50mV RSENSE ≤ = 0.0083Ω 6A Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. The power dissipation on the topside MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual MOSFET . results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF At maximum input voltage with T (estimated) = 50°C: PMAIN = 1.8 V 2 (5) ⎡1+ (0.005)(50°C − 25°C)⎤ • ⎣ ⎦ 22V A (0.035Ω) + (22V)2 ⎛ 52 ⎞ (2Ω)(215pF) • ⎜⎟ ⎝⎠ 1⎤ ⎡1 ⎢5 − 2.3 + 2.3⎥ (250kHz) = 185mW ⎣ ⎦ which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (ΔIL) = 0.02Ω (2A) = 40mVP-P 38511f 24 LTC3851-1 TYPICAL APPLICATIONS VIN 4.5V TO 32V MODE/PLLIN RFREQ 82.5k FREQ/PLLFLTR TG CB 0.1μF VIN M1 HAT2170H + CIN 22μF C20 0.1μF CC RC 2200pF 15k CSS 0.1μF CC2 330pF RUN BOOST LTC3851-1 L1 0.68μH SW DB CMDSH05-4 R27 3.01k C15 47pF R2 154k 1% R1 48.7k 1% VOUT 3.3V 15A TK/SS ITH INTVCC 4.7μF + VFB SENSE– SENSE+ BG M2 HAT2170H COUT 330μF 2 30.1k C5 0.047μF GND RPG PGOOD VPULL-UP COUT: SANYO 6TPE330MIL CIN: SANYO 63HVH22M L1: VISHAY IHLP5050-EZERR68M01 38511 F11 Figure 11. High Efficiency 3.3V/15A Step-Down Converter VIN 4.5V TO 22V MODE/PLLIN RFREQ 160k FREQ/PLLFLTR 0.1μF CSS 0.1μF CC RC 470pF 33k RUN BOOST LTC3851-1 TK/SS CC2 220pF SW DB CMDSH-3 ITH INTVCC 4.7μF VFB SENSE– 1000pF SENSE+ PGOOD BG M2 FDS6982S L1 3.3μH RSENSE 0.01Ω R2 32.4k 1% R1 25.5k 1% VOUT 1.8V 5A TG CB 0.1μF VIN M1 FDS6982S + CIN 22μF 25V + COUT 150μF 6.3V 2 PANASONIC SP GND RPG VPULL-UP COUT: PANASONIC EEFUEOG151R CIN: MARCON THCR70LE1H226ZT L1: PANASONIC ETQP6F3R3HFA RSENSE: IRC LR 2010-01-R010F 38511 TA02 Figure 12. 1.8V/5A Converter from Design Example with Pulse Skip Operation 38511f 25 LTC3851-1 TYPICAL APPLICATIONS 1.5V/15A Synchronized at 350kHz VIN 6V TO 14V C2 0.01μF R5 10k PLLIN 350kHz MODE/PLLIN VIN M1 RJK0305DPB + CB 0.1μF FREQ/PLLFLTR C1 1000pF CSS 0.1μF CC RC 1000pF 7.5k RUN TG CIN 180μF BOOST LTC3851-1 L1 0.68μH SW DB CMDSH-3 C10 33pF R2 43.2k 1% R1 20k 1% RSENSE 0.002Ω VOUT 1.5V 15A TK/SS CC2 100pF ITH INTVCC 4.7μF M2 RJK0301DPB + COUT 330μF 2 VFB SENSE– 1000pF SENSE+ BG GND RPG PGOOD VPULL-UP R22 10Ω R20 10Ω 38511 TA03 COUT: SANYO 2R5TPE330M9 L1: SUMIDA CEP125-OR6MC 38511f 26 LTC3851-1 PACKAGE DESCRIPTION MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev A) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 (.112 0.102 .004) 0.889 (.035 0.127 .005) 2.845 (.112 1 0.102 .004) 8 0.35 REF 5.23 (.206) MIN 1.651 (.065 0.102 3.20 – 3.45 .004) (.126 – .136) 1.651 (.065 0.102 .004) 0.12 REF 0.305 0.038 (.0120 .0015) TYP 0.50 (.0197) BSC 16 4.039 0.102 (.159 .004) (NOTE 3) DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE RECOMMENDED SOLDER PAD LAYOUT 16151413121110 9 0.280 0.076 (.011 .003) REF 0.254 (.010) GAUGE PLANE DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.53 0.152 (.021 .006) DETAIL “A” 0.18 (.007) 12345678 1.10 (.043) MAX 0.86 (.034) REF SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.1016 (.004 0.0508 .002) MSOP (MSE16) 0608 REV A UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) BOTTOM VIEW—EXPOSED PAD 3.00 0.10 (4 SIDES) 0.70 0.05 PIN 1 TOP MARK (NOTE 6) 1.45 0.10 (4-SIDES) 0.75 0.05 R = 0.115 TYP 15 16 0.40 1 2 0.10 PIN 1 NOTCH R = 0.20 TYP OR 0.25 45 CHAMFER 3.50 0.05 2.10 1.45 0.05 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.200 REF 0.00 – 0.05 (UD16) QFN 0904 0.25 0.05 0.50 BSC 38511f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC3851-1 RELATED PARTS PART NUMBER LTC1625/LTC1775 LTC1735 LTC1778 LT®3724 LTC3727A-1 LTC3728 LTC3729L-6 LTC3731 LTC3773 LT3800 LTC3810 LTC3811 LTC3824 DESCRIPTION No RSENSE Current Mode Synchronous Step-Down Controllers High Efficiency Synchronous Step-Down Switching Regulator No RSENSE Wide Input Range Synchronous Step-Down Controller Low IQ High Voltage Current Mode Switching Regulator Controller Dual, 2-Phase Synchronous Controller 2-Phase 550kHz, Dual Synchronous Step-Down Controller 20A to 200A PolyPhase Synchronous Controller 3-Phase, 600kHz Synchronous Step-Down Controller Triple Output DC/DC Synchronous Controller Low IQ High Voltage Synchronous Regulator Controller 100V Current Mode Nonisolated Switching Regulator Controller Dual, PolyPhase Synchronous Step-Down Controller, 20A to 200A Low IQ High Voltage 100% Duty Cycle Step-Down Controller ® TM COMMENTS 97% Efficiency, No Sense Resistor, 16-Pin SSOP Output Fault Protection, 16-Pin SSOP Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN), IOUT Up to 20A VIN up to 60V, IOUT ≤ 5A, 16-Lead TSSOP FE Package, 100μA IQ, Onboard Bias Regulator, Burst Mode Operation, 200kHz Operation Very Low Dropout, VOUT ≤ 14V QFN and SSOP Packages, High Frequency for Smaller L and C Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components, No Heat Sink 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V, IOUT ≤ 60A, Integrated MOSFET Drivers 3-Phase Step-Down DC/DC Controller, 3.3V ≤ VIN ≤ 36V, Fixed Frequency 160kHz to 700kHz VIN up to 60V, IOUT ≤ 20A, Current Mode, Onboard Bias Regulator, 100μA IQ, Burst Mode Operation, 16-Lead TSSOP FE Package 6.2V ≤ VIN ≤ 100, 0.8V ≤ VOUT ≤ 0.9VIN, No RSENSE, Tracking and Synchronizable Differential Remote Sense Amplifier, RSENSE or DCR Current Sense 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN, 40μA Quiescent Current, MSOP-10 Package 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 30μA Quiescent Current Single Channel LTC3826/LTC3826-1 VIN up to 60V, IOUT ≤ 5A, Onboard Bias Regulator, Burst Mode Operation, 120μA IQ, Sync Capability, 16-Lead TSSOP FE Package 4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, 120μA Quiescent Current RSENSE or DCR Current Sensing, Tracking and Synchronizable RSENSE or DCR Current Sensing, Tracking and Synchronizable 92% Efficiency, VIN: 4.5V to 28V, VOUT = 0.6V, True Current Mode Control, UltraFast™ Transient Response 92% Efficiency, VIN: 4.5V to 28V, VOUT = 0.6V, True Current Mode Control, UltraFast Transient Response 4V ≤ VIN ≤ 36V, 1.25V ≤ VOUT ≤ 5V, 6.25mm × 6.25mm × 2.3mm LGA Package 3V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 5V, 6.25mm × 11.25mm × 2.8mm LGA Package Pin Compatible, 4.5V ≤ VIN ≤ 36V, 9mm × 11.25mm × 2.8mm LGA Package LTC3826/LTC3826-1 Low IQ Dual Synchronous Controllers LTC3834/LTC3834-1 Low IQ Synchronous Step-Down Controllers LTC3844 Low IQ High Voltage Current Mode Controller with Programmable Operating Frequency LTC3845 Low IQ Synchronous Step-Down Controller LTC3850/LTC3850-1 Dual, 2-Phase Synchronous Step-Down Controllers LTC3850-2 LTC3853 LTM®4600 LTM4601A LTM8020 LTM8021 LTM8022/LTM8023 Triple Output, Mulitphase Synchronous Step-Down Controller 10A Complete Switch Mode Power Supply 12A Complete Switch Mode Power Supply High VIN 0.2A DC/DC Step-Down μModule High VIN 0.5A DC/DC Step-Down μModule 36VIN, 1A and 2A DC/DC μModule PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE and UltraFast are trademarks of Linear Technology Corporation. 38511f 28 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1108 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008