LTC3853EUJ

FEATURES n n n n n n n n n n n n n n n LTC3853 Triple Output, Multiphase Synchronous Step-Down Controller DESCRIPTION The LTC®3853 is a high performance triple output stepdown switching regulator controller that drives all N-channel synchronous power MOSFET stages. Power loss and supply noise are minimized by operating the output stages out of phase. The part can be configured as a dual phase controller plus a single phase controller if needed. The part can also be configured to provide a single 3-phase output for even higher output currents. A wide 4.5V to 24V (28V maximum) input voltage supply range encompasses most battery chemistries and intermediate bus voltages. Phase 3 can regulate output voltages up to 13.5V. A constant frequency current mode architecture allows for a phase-lockable frequency up to 750kHz. Independent TK/SS pins for each output ramps the output voltages and can be configured for coincident or ratiometric tracking. Current foldback limits MOSFET heat dissipation during short-circuit conditions. The MODE/PLLIN pin selects among Burst Mode® operation, pulse-skipping or continuous inductor current modes. Triple, 120° Phased Controllers Reduce Required Input Capacitance and Power Supply Induced Noise Configurable as a 180° Dual Phase Controller Plus a Single Phase Controller The Third Phase Can Regulate Up to a 13.5V Output High Efficiency: Up to 92% RSENSE or DCR Current Sensing ±0.75% 0.8V Output Voltage Accuracy Phase-Lockable Fixed Frequency 250kHz to 750kHz Supports Pre-Biased Outputs Dual N-Channel MOSFET Synchronous Drive Wide VIN Range: 4.5V to 24V Operation (28V Abs Max) Adjustable Soft-Start Current Ramping or Tracking Foldback Output Current Limiting Output Overvoltage Protection Dual Power Good Output Voltage Monitors 40-Lead 6mm × 6mm QFN Package L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. TYPICAL APPLICATION High Efficiency Triple 5V/3.3V/1.2V Step-Down Converter VIN 7V TO 24V 4.7μF VIN TG1 PGOOD12 PGOOD3 SW1 BG1 fIN 500kHz INTVCC TG2 BOOST1,2,3 SW2 BG2 2.2k 1k 0.1μF SW1,2,3 2.2μH 1μH 22μF 50V 2.2μH LTC3853 2.2k 0.1μF MODE/PLLIN PGND ILIM FREQ/PLLFLTR SENSE1+ SENSE1– SENSE2+ SENSE2– VFB2 10nF RUN1,2,3 TG3 SW3 BG3 SENSE3+ SENSE3– TK/SS1,2,3 0.1μF 10k 20k 0.1μF VOUT2 3.3V 5A 0.1μF VOUT1 5V 5A 63.4k 105k 1500pF 220pF 100μF 10V 20k 15k VFB1 ITH1,2,3 VFB3 SGND + 100μF 6V 10k VOUT3 1.2V 5A + 20k + 100μF 6V 3853f 1 LTC3853 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW FREQ/PLLFLTR MODE/PLLIN Input Supply Voltage (VIN) ......................... 28V to –0.3V Topside Driver Voltages BOOST1, BOOST2, BOOST3 .................. 34V to –0.3V Switch Voltage (SW1, SW2, SW3) ................ 28V to –5V INTVCC, RUN1, RUN2, RUN3, PGOOD12, PGOOD3, DRVCC12, EXTVCC, (BOOST1-SW1), (BOOST2-SW2), (BOOST3-SW3) ................. 6V to –0.3V SENSE1+, SENSE2+, SENSE1–, SENSE2– Voltages..................................... 5.7V to –0.3V SENSE3+, SENSE3–.................................... 14V to –0.3V VFB2........................................................ 300μA Max IFB2 MODE/PLLIN, ILIM,TK/SS1, TK/SS2, TK/SS3 Voltages ..................... INTVCC to –0.3V ITH1, ITH2, ITH3, VFB1, VFB3 Voltages ...... INTVCC to –0.3V INTVCC Peak Output Current ................................150mA Operating Temperature Range (Note 2) LTC3853E............................................. –40°C to 85°C LTC3853I............................................ –40°C to 125°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range................... –65°C to 125°C BOOST1 TK/SS1 RUN1 RUN2 RUN3 40 39 38 37 36 35 34 33 32 31 TK/SS2 1 TK/SS3 2 SNSP1 3 SNSN1 4 SNSP2 5 SNSN2 6 SNSP3 7 SNSN3 8 VFB1 9 ITH1 10 11 12 13 14 15 16 17 18 19 20 SGND ITH2 VFB2 VFB3 ITH3 TG3 PGOOD3 PGOOD12 BOOST3 SW3 41 30 BG1 29 DRVCC12 28 BG2 27 SW2 26 TG2 25 BOOST2 24 VIN 23 EXTVCC 22 INTVCC 21 BG3 UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN TJMAX = 125°C, θJA = 33°C/W EXPOSED PAD (PIN 41) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC3853EUJ#PBF LTC3853IUJ#PBF LEAD BASED FINISH LTC3853EUJ LTC3853IUJ TAPE AND REEL LTC3853EUJ#TRPBF LTC3853IUJ#TRPBF TAPE AND REEL LTC3853EUJ#TR LTC3853IUJ#TR PART MARKING* LTC3853 LTC3853 PART MARKING* LTC3853 LTC3853 PACKAGE DESCRIPTION 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN PACKAGE DESCRIPTION 40-Lead (6mm × 6mm) Plastic QFN 40-Lead (6mm × 6mm) Plastic QFN TEMPERATURE RANGE –40°C to 85°C –40°C to 125°C TEMPERATURE RANGE –40°C to 85°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ SW1 ILIM TG1 3853f 2 LTC3853 ELECTRICAL CHARACTERISTICS SYMBOL VFB1,2,3 IFB1,2,3 VREFLNREG VLOADREG PARAMETER Regulated Feedback Voltage Feedback Current Reference Voltage Line Regulation Output Voltage Load Regulation Main Control Loops ITH1,2,3 Voltage = 1.2V (Note 4) ITH1,2,3 Voltage = 1.2V (0°C to 85°C) (Note 4) (Note 4) VIN = 6V to 24V (Note 4) (Note 4) Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ΔITH Voltage = 1.2V to 1.6V gm1,2,3 IQ Transconductance Amplifier gm Input DC Supply Current Normal Mode Shutdown Undervoltage Lockout on INTVCC UVLO Hysteresis Feedback Overvoltage Lockout Sense Pin Current Soft-Start Charge Current RUN Pin ON Threshold RUN Pin Hysteresis Maximum Current Sense Threshold ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = 0V ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = Float ITH1,2,3 = 1.85V, VSENSE1,2,3 = 3.3V, ILIM = INTVCC In Dropout TG High TG Low BG High BG Low (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF Each Driver (Note 6) CLOAD = 3300pF Each Driver (Note 7) l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2,3 = 5V, unless otherwise noted. CONDITIONS MIN 0.792 0.794 TYP 0.800 0.800 –10 0.002 MAX 0.808 0.806 –50 0.02 UNITS V V nA %/V l l 0.01 –0.01 2.2 4.1 42 3.35 0.5 0.1 –0.1 % % mmho mA μA V V ITH1,2,3 = 1.2V, Sink/Source 5μA (Note 4) (Note 5) VIN = 15V VRUN1,2,3 = 0V VINTVCC Ramping Down Measured at VFB1,2,3 VSENSE = 3.3V VTK/SS1,2,3 = 0V VRUN1, VRUN2, VRUN3 Rising l l 70 UVLO UVLOHYS VOVL ISENSE ITK/SS1,2,3 VRUN1,2,3 VRUN1,2,3HYS VSENSE(MAX) 0.84 0.9 1.1 22 42 65 97 0.86 ±1 1.3 1.2 80 30 50 75 98 2.6 1.5 2.4 1.1 25 25 25 25 30 30 90 0.88 ±2 1.7 1.35 38 58 85 V μA μA V mV mV mV mV % Ω Ω Ω Ω ns ns ns ns ns ns ns DFMAX TG RUP TG RDOWN BG RUP BG RDOWN TG1,2,3 tr TG1,2,3 tf BG1,2,3 tr BG1,2,3 tf TG/BG t1D BG/TG t2D tON(MIN) Maximum Duty Factor TG Driver Pull-Up On-Resistance TG Driver Pull-Down On-Resistance BG Driver Pull-Up On-Resistance BG Driver Pull-Down On-Resistance TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time 3853f 3 LTC3853 ELECTRICAL CHARACTERISTICS SYMBOL VINTVCC VLDO INT VEXTVCC VLDO EXT VLDOHYS fNOM fLOW fHIGH PhTRIPLE PARAMETER Internal VCC Voltage INTVCC Load Regulation EXTVCC Switchover Voltage EXTVCC Voltage Drop EXTVCC Hysteresis Nominal Frequency Lowest Frequency Highest Frequency Channel 2-Channel 1 Phase Channel 3-Channel 2 Phase Channel 1-Channel 3 Phase Channel 2-Channel 1 Phase Channel 3-Channel 2 Phase Channel 1-Channel 3 Phase MODE/PLLIN Input Resistance Phase Detector Output Current Sinking Capability Sourcing Capability PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level fMODE < fOSC fMODE > fOSC IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Set Regulated Voltage VFB Ramping Negative VFB Ramping Positive –5 5 – 7.5 7.5 VFB2 Tied to VIN Through 200kΩ VFREQ = 1.2V VFREQ = 0V VFREQ ≥ 2.4V 450 210 670 INTVCC Linear Regulator 7V < VIN < 24V ICC = 0mA to 50mA EXTVCC Ramping Positive ICC = 20mA, VEXTVCC = 5V l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2,3 = 5V, unless otherwise noted. CONDITIONS MIN 4.8 4.5 TYP 5 0.5 4.7 30 200 500 250 750 120 120 120 180 60 120 250 –13 13 0.1 0.3 ±2 –10 10 550 290 830 75 MAX 5.2 2 UNITS V % V mV mV kHz kHz kHz Deg Deg Deg Deg Deg Deg kΩ μA μA V μA % % Oscillator and Phase-Locked Loop PhDUAL(2+1) RMODE/PLLIN IFREQ PGOOD Outputs VPGL IPGOOD VPG Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3853E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3853I is guaranteed over the full –40°C to 125°C operating temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3853EUJ: TJ = TA + (PD • 33°C/W) Note 4: The LTC3853 is tested in a feedback loop that servos VITH1,2,3 to a specified voltage and measures the resultant VFB1,2,3. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). 3853f 4 LTC3853 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current and Mode 100 90 80 EFFICIENCY (%) BURST EFFICIENCY (%) 70 60 50 40 30 20 10 0 1.00E-02 VIN = 12V VOUT = 1.8V FIGURE 15 MODIFIED WITH DCR SENSING 1.00E-01 1.00E+00 LOAD CURRENT (mA) 1.00E+01 3853 G01 Efficiency vs Output Current and Mode 100 90 80 70 60 50 40 30 20 10 0 1.00E-02 VIN = 12V VOUT = 3.3V FIGURE 15 MODIFIED WITH DCR SENSING 1.00E-01 1.00E+00 LOAD CURRENT (mA) 1.00E+01 3853 G02 Efficiency and Power Loss vs Input Voltage 100 95 2.0 1.8 1.6 EFFICIENCY BURST EFFICIENCY (%) 90 85 80 75 70 65 60 0 5 POWER LOSS (mW) 1.4 1.2 1.0 DCM CCM CCM DCM POWER LOSS VOUT = 3.3V IOUT = 2A FIGURE 15 MODIFIED WITH DCR SENSING 10 20 15 INPUT VOLTAGE (V) 25 30 3853 G03 0.8 0.6 0.4 0.2 0 Load Step (Burst Mode Operation) ILOAD 2A/DIV ILOAD 2A/DIV Load Step (Forced Continuous Mode) IL 2A/DIV VOUT 100mV/DIV AC COUPLED 40μs/DIV VIN = 12V VOUT = 3.3V ILOAD = 0A TO 3A FIGURE 15 CIRCUIT 3853 G04 IL 2A/DIV VOUT 100mV/DIV AC COUPLED 40μs/DIV VIN = 12V VOUT = 3.3V ILOAD = 0A TO 3A FIGURE 15 CIRCUIT 3853 G05 Load Step (Pulse Skip Mode) ILOAD 2A/DIV FORCED CONTINUOUS MODE 2A/DIV Burst Mode OPERATION 2A/DIV PULSE SKIPPING MODE 2A/DIV 40μs/DIV VIN = 12V VOUT = 3.3V ILOAD = 0A TO 3A FIGURE 15 CIRCUIT 3853 G06 Inductor Current at Light Load IL 2A/DIV VOUT 100mV/DIV AC COUPLED 1μs/DIV VIN = 12 VOUT = 1.8V ILOAD = 100mA FIGURE 15 CIRCUIT 3853 G07 3853f 5 LTC3853 TYPICAL PERFORMANCE CHARACTERISTICS Prebiased Output at 2V VOUT 1V/DIV RUN1 2V/DIV VTK/SS 500mV/DIV VFB 500mV/DIV VOUT1,2,3 1V/DIV Coincident Tracking TK/SS1 TK/SS2 TK/SS3 2V/DIV VOUT1,2,3 1V/DIV Tracking Up and Down with External Ramp 50ms/DIV 3853 G08 VIN = 12V VOUT1 = 3.3V VOUT2 = 2.5V VOUT3 = 1.8V 10ms/DIV 3853 G09 VIN = 12V VOUT1 = 3.3V VOUT2 = 2.5V VOUT3 = 1.8V 5ms/DIV 3853 G10 Quiescent Current vs Input Voltage Without EXTVCC 6.0 5.25 5.00 SUPPLY CURRENT (mA) 5.5 INTERNAL VCC (V) 4.75 4.50 4.25 4.00 3.75 4.0 3.50 20 25 3853 G11 Internal VCC Line Regulation 80 60 Current Sense Threshold vs ITH Voltage ILIM = INTVCC ILIM = FLOAT VSENSE (mV) 40 20 0 –20 –40 ILIM = GND 5.0 4.5 5 10 15 INPUT VOLTAGE (V) 0 5 10 15 20 25 3853 G12 0 0.5 INPUT VOLTAGE (V) 1 VITH (V) 1.5 2 3853 G13 Maximum Current Sense Threshold vs Common Mode Voltage 80 CURRENT SENSE THRESHOLD (mV) CURRENT SENSE THRESHOLD (mV) 70 60 50 40 30 20 10 0 0 4 3 VSENSE COMMON MODE VOLTAGE (V) 1 2 5 ILIM = GND ILIM = FLOAT ILIM = INTVCC 100 90 80 70 60 50 40 30 20 10 0 Maximum Current Sense Threshold vs Duty Cycle MAXIMUM CURRENT SENSE VOLTAGE (mV) 80 70 60 50 40 30 20 10 0 Maximum Current Sense Voltage vs Feedback Voltage (Current Foldback) ILIM = INTVCC ILIM = INTVCC ILIM = FLOAT ILIM = FLOAT ILIM = GND ILIM = GND 0 20 60 DUTY CYCLE (%) 40 80 100 3853 G15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FEEDBACK VOLTAGE (V) 3853 G16 3853 G14 3853f 6 LTC3853 TYPICAL PERFORMANCE CHARACTERISTICS TK/SS Pull-Up Current vs Temperature 1.75 1.4 REGULATED FEEDBACK VOLTAGE (mV) Shutdown (RUN) Threshold vs Temperature 806 804 802 800 798 796 Regulated Feedback Voltage vs Temperature 1.65 RUN PIN VOLTAGE (V) TK/SS CURRENT (μA) 1.3 ON 1.2 OFF 1.1 1.55 1.45 1.35 1.25 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1.0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 794 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 3853 G19 3853 G17 3853 G18 Oscillator Frequency vs Temperature 900 800 FREQUENCY (kHz) 700 600 500 400 300 200 –50 –25 VFREQ = 0V 50 25 75 0 TEMPERATURE (°C) 100 125 VFREQ = INTVCC 4.00 INTVCC VOLTAGE (V) 4.25 Undervoltage Lockout Threshold (INTVCC) vs Temperature 500 Oscillator Frequency vs Input Voltage 450 RISING FREQUENCY (kHz) 3.75 VFREQ = 1.2V 400 3.50 FALLING 3.25 350 3.00 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3853 G21 300 5 10 15 INPUT VOLTAGE (V) 20 25 3853 G22 3853 G20 Shutdown Current vs Input Voltage 60 70 Shutdown Current vs Temperature 6 VIN = 12V Quiescent Current vs Temperature Without EXTVCC INPUT CURRENT (μA) 50 SHUTDOWN CURRENT (μA) QUIESCENT CURRENT (mA) 60 5 50 40 40 4 30 30 20 5 10 15 INPUT VOLTAGE (V) 20 25 3853 G23 20 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3 –50 –25 50 25 75 0 TEMPERATURE (˚C) 100 125 3853 G24 3853 G25 3853f 7 LTC3853 PIN FUNCTIONS SENSE1+, SENSE2+, SENSE3+ (Pins 3, 5, 7): Current Sense Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks or current sensing resistors. SENSE3+ common modes up to 13.5V, allowing higher VOUT voltages on channel 3. SENSE1–, SENSE2–, SENSE3– (Pins 4, 6, 8): Current Sense Comparator Inputs. The (–) inputs to the current comparators are connected to the outputs. SENSE3– common modes up to 13.5V, allowing higher VOUT voltages on channel 3. VFB1, VFB2, VFB3 (Pins 9, 12, 14): Error Amplifier Feedback Inputs. These pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. Connecting VFB2 to VIN through a 200k resistor enables dual output (2 + 1) mode. ITH1, ITH2, ITH3 (Pins 10, 13, 15): Current Control Thresholds and Error Amplifier Compensation Points. Each associated channels’ current comparator tripping threshold increases with its ITH control voltage. In dual output (2 + 1) mode, ITH1 and ITH2 need to be shorted externally. SGND (Pin 11): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. PGOOD3 (Pin 16): Power Good Indicator Output for Phase 3. Open-drain logic out that is pulled to ground when any channel output exceeds the ±7.5% regulation window, after the internal 17μs power bad mask timer expires. PGOOD12 (Pin 17): Power Good Indicator Output for Phases 1 and 2. Open-drain logic out that is pulled to ground when any channel output exceeds the ±7.5% regulation window, after the internal 17μs power bad mask timer expires. INTVCC (Pin 22): Internal 5V Regulator Output. The control circuits are powered from this voltage. Also provides channel 3 driver power. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor. EXTVCC (Pin 23): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 4.7V. Do not exceed 6V on this pin and ensure VIN > VEXTVCC at all times. VIN (Pin 24): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1μF to 1μF). DRVCC12 (Pin 29): Driver Voltage Input for Channels 1 and 2. Do not exceed 6V on this pin. This pin must be tied to INTVCC externally. BG1, BG2, BG3 (Pins 30, 28, 21): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-channel MOSFETs between PGND and INTVCC/DRVCC12. SW1, SW2, SW3 (Pins 31, 27, 20): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. 3853f 8 LTC3853 PIN FUNCTIONS TG1, TG2, TG3 (Pins 32, 26, 19): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch nodes voltages. BOOST1, BOOST2, BOOST3 (Pins 33, 25, 18): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. RUN1, RUN2, RUN3 (Pins 36, 35, 34): Run Control Inputs. A voltage above 1.2V on any RUN pin turns on the IC. However, forcing any of these pins below 1.2V causes the IC to shut down the circuitry required for that particular channel. There are 0.5μA pull-up currents for these pins. Once the RUN pin rises above 1.2V, an additional 4.5μA pull-up current is added to the pin. MODE/PLLIN (Pin 37): Force Continuous Mode, Burst Mode, or Pulse Skip Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force all channels into the continuous mode of operation. Connect to INTVCC to enable pulse skip mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator. FREQ/PLLFLTR (Pin 38): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. ILIM (Pin 39): Current Comparator Sense Voltage Range Inputs. This pin is to be programmed to SGND, FLOAT or INTVCC to set the maximum current sense threshold to three different levels. TK/SS1, TK/SS2, TK/SS3 (Pins 40, 1, 2): Output Voltage Tracking and Soft-Start Inputs. When one particular channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave, the VFB voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.3μA are charging the soft-start capacitors. In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to be shorted externally. Exposed Pad (Pin 41): Power Ground. Connect these pins closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. 3853f 9 LTC3853 FUNCTIONAL DIAGRAM FREQ/PLLFLTR MODE/PLLIN EXTVCC 4.7V VIN + CIN VIN – F + 5V REG MODE/SYNC DETECT PLL-SYNC 0.8V – F + INTVCC INTVCC BOOST OSC S R Q FCNT BURSTEN TG SW SWITCH LOGIC AND ANTISHOOT THROUGH SENSE+ SENSE– CB M1 + ICMP 3k ON – IREV DB L1 VOUT – + RUN + COUT BG M2 CVCC PGND PGOOD OV SLOPE COMPENSATION ILIM INTVCC UVLO + 1 51k ITHB SLOPE RECOVERY ACTIVE CLAMP 0.74V VFB R2 UV – VIN SLEEP OV + – EA 0.86V SGND 1.3μA R1 0.64V 1.2V 0.5μA 3853 FD 0.55V CC1 CSS ITH RC RUN 10 + + 0.8V REF – SS RUN – –++ + – TK/SS 3853f LTC3853 OPERATION Main Control Loop The LTC3853 is a constant-frequency, current mode step-down controller with three channels operating 120 degrees out-of-phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP , resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier, EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator IREV , or the beginning of the next cycle. INTVCC/EXTVCC/DRVCC12 Power Power for the top and bottom MOSFET drivers of phase 3 and most other internal circuitry is derived from the INTVCC pin. DRVCC12 provides driver power for phase 1 and phase 2. This pin must be externally tied to INTVCC. If EXTVCC is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one of the LTC3853 switching regulator outputs. Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage, VIN, decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period every fifth cycle to allow CB to recharge. However, it is recommended that there is always a load be present during the drop-out transition to ensure CB is recharged. Shutdown and Start-Up (RUN1, RUN2, RUN3 and TK/SS1, TK/SS2, TK/SS3 Pins) The three channels of the LTC3853 can be independently shut down using the RUN1, RUN2 and RUN3 pins. Pulling any of these pins below 1.2V shuts down the main control loop for that controller. Pulling all pins low disables all three controllers and most internal circuits, including the INTVCC regulator. Releasing any RUN pin allows an internal 0.5μA current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of each controller’s output voltage VOUT is controlled by the voltage on the TK/SS1, TK/SS2 and TK/SS3 pins. When the voltage on the TK/SS pin is less than the 0.8V internal reference, the LTC3853 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.8V reference. This allows the TK/SS pin to be used to program a soft-start by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.3μA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TK/SS pin can be used to cause the start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when INTVCC drops below its undervoltage lockout threshold of 3.35V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, all controllers are disabled and the external MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse Skipping or Continuous Conduction) The LTC3853 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse skipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC 3853f 11 LTC3853 OPERATION voltage below 0.8V (e.g., SGND). To select pulse skipping mode of operation, tie the MODE/PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When the controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTVCC, the LTC3853 operates in PWM pulse skipping mode at light loads. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ/PLLFLTR and MODE/PLLIN Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3853’s controllers can be selected using the FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ/PLLFLTR pin can be used to program the controller’s operating frequency from 250kHz to 750kHz. A phase-locked loop (PLL) is available on the LTC3853 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is synchronized. A series R-C should be connected between the FREQ/PLLFLTR pin and SGND to serve as the PLL’s loop filter. Power Good (PGOOD12 and PGOOD3 Pins) The PGOOD12 pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD12 pin low when either VFB1 or VFB2 pin voltage is not within ±7.5% of the 0.8V reference voltage. The PGOOD12 pin is also pulled low when either RUN1 or RUN2 pin is below 1.2V or when the LTC3853 is in the soft-start or tracking phase. When the VFB pin voltage is within the ±7.5% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD12 pin will flag power good immediately when both VFB1 and VFB2 pins are within the ±7.5% window. However, there is an internal 17μs power bad mask when either VFB is out of the ±7.5% window. PGOOD3 monitors VFB3 and is also pulled low when RUN3 is below 1.2V. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. 3853f 12 LTC3853 OPERATION Triple vs Dual (2 + 1) Operation The LTC3853 can be used to regulate three different outputs. It can also be used as a dual output controller with a high current 2-phase output and a single phase output. Tying VFB2 to VIN through a 200k resistor switches the controller from triple to dual (2 + 1) operation. Do not exceed the absolute maximum current rating for the VFB2 pin. In dual (2 + 1) mode, phase 1 and phase 2 are 180 degrees apart (instead of 120 degrees) with phase 3 remaining at 240 degrees from phase 1. The ITH1 and ITH2 pins must be shorted together externally and so must the TK/SS1 and TK/SS2 pins for proper operating of the 2 phase portion of the controller. RUN2 should be grounded. RUN1 will now control both phases 1 and 2, while RUN3 continues to control the turn on of phase 3. Phase 3 is also capable of regulating up to a 13.5V output in either mode, while phases 1 and 2 are limited to a 5.3V output. APPLICATIONS INFORMATION The Typical Application on the first page is a basic LTC3853 application circuit. LTC3853 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design tradeoff between cost, power consumption, and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs are selected. Finally, input and output capacitors are selected. Current Limit Programming The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is either grounded, floated or tied to INTVCC, the typical value for the maximum current sense threshold will be 30mV, 50mV or 75mV, respectively. Which setting should be used? For the best current limit accuracy, use the 75mV setting. The 30mV setting will allow for the use of very low DCR inductors or sense resistors, but at the expense of current limit accuracy. The 50mV setting is a good balance between the two. For single output dual phase applications ((2 + 1) mode), use the 50mV or 75mV setting for optimal current sharing. SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 0V to 5.3V for phases 1 and 2, and 0V to 13.5V for phase 3. Both SENSE pins are high impedance inputs with small base currents of less than 1μA. When the SENSE pins ramp up from 0V to 1.4V, the small base currents flow out of the SENSE pins. When the SENSE pins ramp down from the maximum common mode voltage to 1.1V, the small base currents flow into the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. Filter components mutual to the sense lines should be placed close to the LTC3853, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading TO SENSE FILTER, NEXT TO THE CONTROLLER COUT INDUCTOR OR RSENSE 3853 F01 Figure 1. Sense Lines Placement with Inductor or Sense Resistor 3853f 13 LTC3853 APPLICATIONS INFORMATION the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. VIN INTVCC VIN The current comparator has a maximum threshold VSENSE(MAX) determined by the ILIM setting. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ΔIL. To calculate the sense resistor value, use the equation: R SENSE = VSENSE(MAX ) ΔI I(MAX ) + L 2 BOOST TG LTC3853 SW BG PGND SENSE+ SENSE– SGND RF CF RF L1 RS RSENSE ESL FILTER COMPONENTS PLACED NEAR SENSE PINS Because of possible PCB noise in the current sensing loop, the AC current sensing ripple of ΔVSENSE = ΔIL • RSENSE also needs to be checked in the design to get a good signal-to-noise ratio. In general, for a reasonably good PCB layout, a 15mV ΔVSENSE voltage is recommended as a conservative number to start with, either for RSENSE or DCR sensing applications. 3853 F02a (2a) Using a Resistor to Sense Current VIN INTVCC BOOST TG LTC3853 SW BG PGND SENSE+ C1* SENSE– SGND *PLACE C1 NEAR SENSE+, SENSE– PINS R1||R2 • C1 = L R2 RSENSE(EQ) = DCR DCR R1 + R2 R2 R1 INDUCTOR L DCR VOUT VIN 3853 F02b (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628 / LTC3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. For today’s highest current density solutions, however, the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be as low as 20mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 2a. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of capacitive and inductive noise coupled inthe sense traces on the PCB. A typical filter consists of two series 10Ω resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 20ns. This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 3 illustrates the voltage waveform across a 2mΩ sense resistor with a 2010 footprint for the 1.2V/15A converter operating at 100% load. The waveform is the 3853f Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. 14 LTC3853 APPLICATIONS INFORMATION superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) tON • tOFF ΔIL tON + tOFF over-filter. Keep the RC time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on VRSENSE. The above generally applies to high density/high current applications where I(MAX) > 10A and low values of inductors are used. For applications where I(MAX) < 10A, . set RF to 10Ω and CF to 1000pF This will provide a good starting point. The filter components need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair and Kelvin connected to the sense resistor. Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC3853 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to DCR sensing. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers’ data sheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: VSENSE(MAX ) R SENSE(EQUIV ) = ΔI I(MAX ) + L 2 3853f If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 4. For applications using low maximum sense voltages, check the sense resistor manufacturer’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use the equation above to determine the ESL. However, do not VSENSE 20mV/DIV VESL(STEP) 500ns/DIV 3853 F03 Figure 3. Voltage Waveform Measured Directly Across The Sense Resistor VSENSE 20mV/DIV 500ns/DIV 3853 F04 Figure 4. Voltage Waveform Measured After the Sense Resitor Filter. CF = 1000pF RF = 100Ω , 15 LTC3853 APPLICATIONS INFORMATION To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold (VSENSE(MAX)) in the Electrical Characteristics table (22mV, 42mV, or 65mV, depending on the state of the ILIM pin). Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C. A conservative value for TL(MAX) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: R SENSE(EQUIV ) RD = DCR(MAX ) at TL(MAX ) C1 is usually selected to be in the range of 0.047μF to 0.47μF This forces R1||R2 to around 2kΩ, reducing error . that might have been caused by the SENSE pins’ ±1μA current. The equivalent resistance R1||R2 is scaled to the room temperature inductance and maximum DCR: L R1|| R2 = (DCR at 20 °C ) • C1 The sense resistor values are: R1|| R2 R1 • RD R1 = ; R2 = RD 1 − RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: VIN(MAX ) − VOUT • VOUT PLOSS R1 = R1 However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal-to-noise ratio for the current sense signal, use a minimum ΔVSENSE of 10mV to 15mV. For a DCR sensing application, the actual ripple voltage will be determined by: ΔVSENSE = VIN – VOUT VOUT • R1 • C1 VIN • fOSC Slope Compensation and Inductor Peak Current Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%. However, the LTC3853 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency, fOSC, directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT ⎛ VIN – VOUT ⎞ VIN ⎜ fOSC • L ⎟ ⎠ ⎝ ( ) Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: V –V V L ≥ IN OUT • OUT fOSC • IRIPPLE VIN 3853f Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. 16 LTC3853 APPLICATIONS INFORMATION Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3853: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC/ DRVCC12 voltage. This voltage is typically 5V during startup (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN VIN – VOUT VIN Synchronous Switch Duty Cycle = The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT (IMAX )2 (1+ δ )RDS(ON) + VIN I ( VIN )2 ⎛ MAX ⎞ (RDR )(CMILLER ) • ⎜2⎟ ⎝ ⎠ ⎡ ⎤ 1 1 + ⎢ ⎥ • fOSC ⎢ VINTVCC – VTH(MIN) VT H(MIN) ⎥ ⎣ ⎦ PSYNC = VIN – VOUT (IMAX )2 (1+ δ )RDS(ON) VIN where δ is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTH(MIN) is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. 3853f 17 LTC3853 APPLICATIONS INFORMATION The optional Schottky diodes conduct during the dead time between the conduction of the two power MOSFETs. These prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. Soft-Start and Tracking The LTC3853 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.2V. Its TK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1.3μA then starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.8V on the TK/SS pin. The total soft-start time can be calculated as: t SOFTSTART = 0 . 8 • C SS 1 . 3 μA the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC3853 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.74V regardless of the setting of the MODE/PLLIN pin. However, the LTC3853 should always be set in force continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, its channel will operate in discontinuous mode. Output Voltage Tracking The LTC3853 allows the user to program how its output ramps up and down by means of the TK/SS pins. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 5. In the following discussions, VOUT1 refers to the LTC3853’s output 1 as a master channel and VOUT2 refers to the LTC3853’s output 2 as a slave channel. In practice though, any phase can be used as the master. To implement the coincident tracking in Figure 5a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 6a. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking, the ratio of the slave’s divider should be exactly the same as the master channel’s feedback divider. By selecting different resistors, the LTC3853 can achieve different modes of tracking including the two in Figure 5. So which mode should be programmed? While either mode in Figure 6 satisfies most practical applications, there are some tradeoffs. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. This can be better understood with the help of Figure 7. At the input stage of the slave channel’s error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode 3853f Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse skipping mode up to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.74V. The output ripple is minimized during the 100mV forced continuous mode window ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, 18 LTC3853 APPLICATIONS INFORMATION VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 VOUT2 TIME 3853 F05a TIME 3853 F05b (5a) Coincident Tracking (5b) Ratiometric Tracking Figure 5. Two Different Modes of Output Voltage Tracking VOUT1 R3 TO TK/SS2 PIN R4 R2 R1 TO VFB1 PIN TO VFB2 PIN R4 R3 VOUT2 VOUT1 R1 TO TK/SS2 PIN R2 TO VFB1 PIN TO VFB2 PIN R4 3853 F06 VOUT2 R3 (6a) Coincident Tracking Setup (6b) Ratiometric Tracking Setup Figure 6. Setup for Coincident and Ratiometric Tracking I I + D1 TK/SS2 0.8V VFB2 D3 D2 EA2 – 3853 F07 Although this error is minimized by the exponential I-V characteristic of the diode, it does impose a finite amount of output voltage deviation. Furthermore, when the master channel’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. INTVCC Regulators and EXTVCC The LTC3853 features an NPN linear regulator that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3853’s internal circuitry. The linear regualtor regulates the voltage at the INTVCC pin to 5V when VIN is greater than 6.5V. EXTVCC connects to INTVCC through a P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V. Each of these can supply a peak current of 150mA and must be bypassed to ground with a minimum of 1μF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1μF Figure 7. Equivalent Input Circuit of Error Amplifier is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TK/SS voltage is substantially higher than 0.8V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.8V reference. In the ratiometric mode, however, TK/SS equals 0.8V at steady state. D1 will divert part of the bias current to make VFB2 slightly lower than 0.8V. 3853f 19 LTC3853 APPLICATIONS INFORMATION ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3853 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5V linear regulator or EXTVCC. When the voltage on the EXTVCC pin is less than 4.7V, the linear regulator is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3853 INTVCC current is limited to less than 50mA from a 24V supply in the UJ package and not using the EXTVCC supply: TJ = 85°C + (50mA)(24V)(33°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using the EXTVCC allows the MOSFET driver and control power to be derived from one of the LTC3853’s switching regulator outputs during normal operation and from the INTVCC when the output is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC < VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to: TJ = 85°C + (50mA)(5V)(33°C/W) = 94°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. For applications where the main input power is 5V, tie the VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 8 to minimize the voltage drop caused by the gate charge current. This will override the INTVCC linear regulator and will prevent INTVCC from dropping too low due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds the RDS(ON) test voltage for the MOSFET which is typically 4.5V for logic-level devices. LTC3853 VIN INTVCC CINTVCC 4.7μF RVIN 1Ω 5V + CIN 3853 F08 Figure 8. Setup for a 5V Input 3853f 20 LTC3853 APPLICATIONS INFORMATION Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode, DB, from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor, CB, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Undervoltage Lockout The LTC3853 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.35V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 500mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pins have a precision turn-on reference of 1.2V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5μA of current flows out of the RUN pin once the RUN pin voltage passes 1.2V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. For accurate VIN undervoltage detection using the RUN pin, VIN needs to be higher then 4V. CIN and COUT Selection The selection of CIN is simplified by the 3-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controllers will actually decrease the input RMS ripple current from its maximum value. The out-ofphase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Re quired IRMS ≈ IMAX 1/ 2 ⎡( VOUT )( VIN – VOUT ) ⎤ ⎣ ⎦ VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3853, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3853 3-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if all controller channels switched on at the same 3853f 21 LTC3853 APPLICATIONS INFORMATION time. The total RMS power lost is lower when more than one controller is operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual or triple controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 3-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1μF to 1μF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3853, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (ΔVOUT) is approximated by: ⎛ 1⎞ Δ VOUT ≈ IRIPPLE ⎜ ESR + 8 fCOUT ⎟ ⎠ ⎝ where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3853 output voltages are each set by an external feedback resistive divider carefully placed across the output, as shown in Figure 9. The regulated output voltage is determined by: ⎛ R⎞ VOUT = 0 . 8 V • ⎜ 1 + B ⎟ ⎝ RA ⎠ VOUT 1/3 LTC3853 VFB RA 3853 F09 RB CFF Figure 9. Setting Output Voltage To improve the frequency response, a feed-forward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Fault Conditions: Current Limit and Current Foldback The LTC3853 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up. Under short-circuit conditions with very low duty cycles, the LTC3853 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The shortcircuit ripple current is determined by the minimum ontime tON(MIN) of the LTC3853 (≈ 90ns), the input voltage and inductor value: Δ IL(SC) = t ON(MIN) • VIN L The resulting short-circuit current is: ISC = 1/ 3 VSENSE(MAX ) R SENSE 1 – Δ IL(SC) 2 Phase-Locked Loop and Frequency Synchronization The LTC3853 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of 3853f 22 LTC3853 APPLICATIONS INFORMATION controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the FREQ/PLLFLTR pin. The relationship between the voltage on the FREQ/PLLFLTR pin and operating frequency is shown in Figure 10 and specified in the Electrical Characteristics table. Note that the LTC3853 can only be synchronized to an external clock whose frequency is within range of the LTC3853’s internal VCO. This is guaranteed to be between 250kHz and 750kHz. A simplified block diagram is shown in Figure 11. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, or if the external clock’s phase lags the internal oscillator, then current is sourced from the phase detector output, pulling up the FREQ/PLLFLTR pin. When the external clock frequency is less than fOSC, or if the external clock’s phase leads the internal oscillator, current is sunk, pulling down the FREQ/PLLFLTR pin. The voltage on the FREQ/PLLFLTR pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor, CLP , holds the voltage. 800 2.4V 700 FREQUENCY (kHz) 600 500 400 300 200 EXTERNAL OSCILLATOR MODE/ PLLIN DIGITAL PHASE/ FREQUENCY DETECTOR RLP CLP FREQ/ PLLFLTR The loop filter components, CLP and RLP , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01μF . Typically, the external clock (on MODE/PLLIN pin) input high threshold is 1.6V, while the input low threshold is 1V. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3853 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that V t ON(MIN) < OUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3853 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 10mV to 15mV ripple VCO 0 0.5 1 1.5 2 FREQ/PLLFLTR PIN VOLTAGE (V) 2.5 3853 F10 3853 F11 Figure 10. Relationship Between Oscillator Frequency and Voltage at the FREQ/PLLFLTR Pin Figure 11. Phase-Locked Loop Block Diagram 3853f 23 LTC3853 APPLICATIONS INFORMATION on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. However, as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3853 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. 3853f 25 LTC3853 APPLICATIONS INFORMATION PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. Figure 12 illustrates the current waveforms present in the various branches of the 3-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs located within 1 cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the three channels as it can cause a large resonant loop. 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Do the LTC3853 VFB pins’ resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE+ and SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6. Keep the switching nodes (SW), top gate nodes (TG), and boost nodes (BOOST) away from sensitive smallsignal nodes, especially from another channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3853 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 2b, R1) close to the switching node. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. 3853f 26 LTC3853 APPLICATIONS INFORMATION SW1 L1 RSENSE1 D1 COUT1 VOUT1 + RL1 SW2 VIN RIN L2 RSENSE2 VOUT2 + CIN D2 COUT2 + RL2 BOLD LINES INDICATE HIGH SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH. SW3 L3 VOUT3 RSENSE3 D3 COUT3 + RL3 3853 F12 Figure 12. Branch Current Waveforms 3853f 27 LTC3853 APPLICATIONS INFORMATION PC Board Layout Debugging Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should all controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when another channel is turning on its top MOSFET. This occurs around 33% and 66% duty cycle on a channel in triple mode, due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. Design Example As a design example for a three channel medium current regulator, assume VIN = 12V(nominal), VIN = 20V(maximum), VOUT1 = 5V, VOUT2 = 3.3V, VOUT3 = 1.2V, IMAX1,2,3 = 5A, and f = 500kHz (see Figure 13). The regulated output voltages are determined by: ⎛ R⎞ VOUT = 0 . 8 V • ⎜ 1 + B ⎟ ⎝ RA ⎠ Using 20k 1% resistors from both VFB nodes to ground, the top feedback resistors are (to the nearest 1% standard value) 105k, 63.4k and 10k. The minimum on-time occurs on channel 3 at the maximum VIN, and should not be less than 90ns: t ON(MIN) = VOUT VIN(MAX ) f = 1 . 2V = 120n s 20 V(500kHz) The frequency is set by biasing the FREQ/PLLFLTR pin to 1.2V (see Figure 10), using a divider from INTVCC. This voltage will decrease as VIN approaches 5V, lowering the switching frequency. If a separate 5V supply is connected to EXTVCC, INTVCC will remain at 5V even if VIN decreases. The inductance values are based on a 35% ripple current assumption (1.75A for each channel) at nominal input voltage: L= ⎛ VOUT VOUT ⎞ ⎜ 1− ⎟ f • Δ IL (NOM) ⎝ VIN(NOM) ⎠ Channel 1 will require 3.3μH, channel 2 will require 2.8μH and channel 3 will require 1.25μH. The next highest 3853f 28 LTC3853 APPLICATIONS INFORMATION VIN 7V TO 20V 4.7μF M1 VIN DRVCC12 INTVCC TG1 PGOOD12 PGOOD3 SW1 BG1 TG2 BOOST1,2,3 SW2 BG2 10k INTVCC 1430Ω VOUT2 3.3V 5A 0.068μF 1.82k 4.75k 0.1μF 2.43k DB1,2,3 CB1,2,3 0.1μF SW1,2,3 3.3μH 1.5μH 22μF 50V M2 M3 3.3μH LTC3853 4.75k MODE/PLLIN PGND ILIM FREQ/PLLFLTR SENSE1 1430Ω VOUT1 5V 5A 0.1μF SENSE1– 105k 1% RITH1,2,3 10pF CP1,2,3 VFB1 ITH1,2,3 VFB3 + SENSE2+ – SENSE2 VFB2 63.4k 1% RUN1,2,3 3.16k 1nF 20k 1% 10pF + + 330μF 10V 20k 1% CITH1,2,3 TG3 SW3 BG3 SENSE3+ EXTVCC SENSE3– TK/SS1,2,3 SGND CSS1,2,3 0.1μF 330μF 6V 10k 1% VOUT3 1.2V 5A 20k 1% + 330μF 6V M1, M2, M3: Si4816BDY CHANNEL 1: RITH1 = 15k, CITH1 = 1.5nF, CP1 = 220pF CHANNEL 2: RITH2 = 18k, CITH2 = 1.5nF, CP2 = 220pF CHANNEL 3: RITH3 = 10k, CITH3 = 1.5nF, CP3 = 330pF FOR CHANNEL 3, 0.068μF WAS SUBSTITUTED FOR 0.1μF AND 2.43k WAS SUBSTITUTED FOR 2.21k TO MEET MINIMUM 15mV RIPPLE AT SENSE INPUT REQUIREMENT 3853 F13 Figure 13. High Efficiency Triple 5V/3.3V/1.2V Step-Down Converter standard values are 3.3μH, 3.3μH and 1.5μH. At the maximum input voltage (20V), the ripple will be: ⎛ V VOUT ⎞ Δ IL(MAX ) = OUT ⎜ 1 − ⎟ f •L ⎝ VIN(MAX ) ⎠ Channel 1 will have ~2.3A (46%) ripple, and both channel 2 and channel 3 will have ~1.75A (35%) ripple. The peak inductor current will be the maximum DC value plus onehalf the ripple current, or 6.15A for channel 1 and 5.88A for channels 2 and 3. With ILIM high, the equivalent RSENSE resistor value can be calculated by using the minimum value for the maximum current sense threshold (65mV). R SENSE(EQUIV ) = VSENSE(MIN) Δ IL(NOM) ILOAD(MAX ) + 2 65mV = ≅ 9mΩ Δ IL(MAX ) ⎞ ⎛ 1 . 2 • ⎜ 5A + ⎟ 2 ⎝ ⎠ The 1.2 factor adds margin for component variation and overcurrent headroom during full load transients. The equivalent RSENSE is the same for channels 1, 2 and 3. The Vishay IHLP2525CZER3R3M01 (30mΩ DCRMAX at 20°C) and IHLP2525CZER1R5M01 (15mΩ DCRMAX at 20°C,) are chosen. At 100°C, the estimated maximum DCR values are 39.6mV and 19.8mV. The divider ratios are: RD = R SENSE(EQUIV ) DCRMAX at TL(MAX ) and = 9mΩ = 0 . 23; 39 . 6 mΩ 9mΩ ≅ 0 . 45 19 . 8 mΩ For each channel, 0.1μF is selected for C1. R1|| R2 = 3 . 3μ H L = (DCRMAX at 20 °C) • C1 30 mΩ • 0 . 1μ F 1 . 5 μH = 1 1 00 Ω and = 1000 Ω 15mΩ • 0 . 1μ F 3853f 29 LTC3853 APPLICATIONS INFORMATION For channel 1, the DCRSENSE filter/divider values are: R1|| R2 1100 Ω = ≅ 4 . 75 k ; RD 0 . 23 R1 • RD 4 . 7 5 k • 0 . 23 ≅ 1430Ω R2 = = 1 − 0 . 23 1 − RD R1 = The power loss in R1 at the maximum input voltage is: PLOSS R1 = ( VIN(MAX ) − VOUT ) • VOUT R1 (20 V − 5V) • 5V = = 15 . 8mW 4 . 75k The power dissipation on the topside MOSFET can be easily estimated. Choosing a Siliconix Si4816BDY dual MOSFET . results in: RDS(ON) = 0.023Ω/0.016Ω, CMILLER ≅ 100pF At maximum input voltage with T(estimated) = 50°C: PMAIN = 5V (5)2 [1+ (0 . 005)(50 °C – 25 °C)] • 20 V 5A (0 . 023Ω) + (20V )2 ⎛ 2 ⎞ (2Ω)(100pF ) • ⎜⎟ ⎝⎠ 1⎤ ⎡1 ⎢ 5 – 2 . 3 + 2 . 3 ⎥ ( 500kHz ) = 243mW ⎣ ⎦ A short-circuit to ground will result in a folded back current of: ISC = The respective values for Channel 2 are R1 = 4.75k, R2 = 1430Ω; and PLOSSR1 = 11.6mW. And for Channel 3 are R1 = 2.21k, R2 = 1.82k; and PLOSSR1 = 10.2mW. Burst Mode operation is chosen for high light load efficiency (Figure 14) by floating the MODE/PLLIN pin. Power loss due to the DCR sensing network is slightly higher at light loads than would have been the case with a suitable sense resistor (9mΩ). At heavier loads, DCR sensing provides higher efficiency. 100 DCR 90 EFFICIENCY (%) 80 70 60 50 40 0.01 EFFICIENCY POWER LOSS 0.1 1 LOAD CURRENT (mA) 10 3853 F14 (1 / 3) 75mV – 1 ⎛ 90ns(20V) ⎞ = 2 . 5 A 0 . 009Ω 2⎜ ⎝ 3 . 3 μH ⎟ ⎠ with a typical value of RDS(ON) and δ = (0.005/°C)(25) = 0.125. The resulting power dissipated in the bottom MOSFET is: PSYNC = 20 V – 5V (2 . 5A )2 (1 . 125)(0 . 016Ω) 20 V = 8 4mW 10 which is less than under full-load conditions. 9mΩ DCR POWER LOSS (mW) 1 0.1 CIN is chosen for an RMS current rating of at least 2A at temperature assuming only one channel is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (ΔIL) = 0.02Ω(1.5A) = 30mVP-P 0.01 Figure 14. Design Example Efficiency vs Load 3853f 30 LTC3853 APPLICATIONS INFORMATION 4.7μF M1 VIN DRVCC12 INTVCC TG1 PGOOD12 PGOOD3 SW1 BG1 TG2 BOOST1,2,3 SW2 BG2 10k INTVCC 10Ω* 1000pF* 24.9k 1% 3.16k 1000pF 20k 1% VOUT2 1.8V 5A 10Ω* 0.008Ω 5% 10Ω* 1000pF* 10Ω* 0.008Ω 5% VOUT3 3.3V 5A DB1,2,3 CB1,2,3 0.1μF SW1,2,3 33μF 35V M2 1.5μH M3 2.2μH VIN 7V TO 24V 1.5μH LTC3853 10Ω* 0.008Ω 5% 10Ω* VOUT1 2.5V 5A 1000pF* PGND MODE/PLLIN ILIM FREQ/PLLFLTR SENSE1+ SENSE1– VFB1 ITH1,2,3 RITH1,2,3 VFB3 SENSE2+ SENSE2– VFB2 RUN1,2,3 43.2k 1% 10pF CP1,2,3 + + CITH1,2,3 220μF 4V 20k 1% TG3 SW3 BG3 SGND SENSE3+ EXTVCC SENSE3– TK/SS1,2,3 CSS1,2,3 0.1μF 220μF 4V 63.4k 1% 10pF 20k 1% + 220μF 4V M1, M2, M3: Si4816BDY CHANNEL 1: RITH1 = 18k, CITH1 = 1500pF, CP1 = 220pF CHANNEL 2: RITH2 = 12k, CITH2 = 1500pF, CP2 = 220pF CHANNEL 3: RITH3 = 18k, CITH3 = 1500pF, CP3 = 220pF 3853 F15 *THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC Figure 15. Triple 2.5V/1.8V/3.3V 5A Step-Down Converter with RSENSE, fSW = 500kHz 3853f 31 LTC3853 TYPICAL APPLICATIONS Triple 3.3V/2.5V/12V, 5A Step-Down Converter with RSENSE Synchronized at 400kHz 33μF 35V M2 2.2μH M3 6.8μH VIN 13V TO 24V 4.7μF M1 VIN DRVCC12 INTVCC TG1 PGOOD12 PGOOD3 SW1 BG1 ILIM 10Ω* 0.008Ω 5% 10Ω* VOUT1 3.3V 5A 1000pF* PLLIN 400kHz SENSE1+ MODE/PLLIN SENSE1– VFB1 ITH1,2,3 RITH1,2,3 CP1,2,3 VFB3 TG2 BOOST1,2,3 SW2 BG2 PGND FREQ/PLLFLTR SENSE2+ SENSE2– VFB2 RUN1,2,3 DB1,2,3 CB1,2,3 0.1μF SW1,2,3 3.3μH LTC3853 10Ω* 0.008Ω 5% 10Ω* 10Ω* 1000pF* 43.2k 1% 10k 1000pF 20k 1% 10pF VOUT2 2.5V 5A 1000pF* 10Ω* 0.011Ω 5% VOUT3 12V 4A 63.4k 1% 10pF + + CITH1,2,3 220μF 4V 20k 1% TG3 SW3 BG3 SGND SENSE3+ EXTVCC SENSE3– TK/SS1,2,3 CSS1,2,3 0.1μF 10nF 220μF 4V 140k 1% 22pF 10k 1% + 220μF 16V M1, M2, M3: Si4816BDY CHANNEL 1: RITH1 = 18k, CITH1 = 1500pF, CP1 = 220pF CHANNEL 2: RITH2 = 18k, CITH2 = 1500pF, CP2 = 220pF CHANNEL 3: RITH3 = 43k, CITH3 = 470pF, CP3 = 330pF 3853 TA02 *THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC Triple 1.8V/1.2V/2.5V, 15A High Current Step-Down Converter with RSENSE, fSW = 400kHz VIN 6.5V TO 14V 4.7μF VIN DRVCC12 INTVCC M1 0.56μH TG1 PGOOD12 PGOOD3 SW1 BG1 TG2 BOOST1,2,3 SW2 BG2 DB1,2,3 CB1,2,3 0.1μF SW1,2,3 M4 10k INTVCC 100Ω* 1000pF* 10k 1% 2.55k 1000pF 20k 1% 47pF VOUT2 1.2V 15A 0.002Ω 5% M6 M3 0.47μH M5 180μF 16V 0.78μH M2 LTC3853 100Ω* 100Ω* 0.002Ω 5% 100Ω* VOUT1 1.8V 15A 1000pF* MODE/PLLIN PGND ILIM FREQ/PLLFLTR SENSE1 + 100Ω* 1000pF* 100Ω* 0.002Ω 5% VOUT3 2.5V 15A SENSE2 + SENSE1– VFB1 ITH1,2,3 RITH1,2,3 VFB3 SENSE2– VFB2 RUN1,2,3 24.9k 1% 22pF CP1,2,3 + + CITH1,2,3 660μF 2.5V 20k 1% TG3 SW3 BG3 SGND SENSE3+ SENSE3– EXTVCC TK/SS1,2,3 CSS1,2,3 0.1μF 660μF 2.5V 43.2k 1% 20k 1% + 660μF 4V M1, M3, M5: RJK0305DPB M2, M4, M6: RJK0301DPB CHANNEL 1: RITH1 = 15k, CITH1 = 1500pF, CP1 = 330pF CHANNEL 2: RITH2 = 10k, CITH2 = 1500pF, CP2 = 220pF CHANNEL 3: RITH3 = 13k, CITH3 = 1500pF, CP3 = 330pF 3853 TA03 *THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC 3853f 32 LTC3853 TYPICAL APPLICATIONS Dual 1.2V/2.5V High Current Step-Down Converter with RSENSE 180μF 16V VIN 6.5V TO 14V 4.7μF VIN DRVCC12 INTVCC TG1 PGOOD12 PGOOD3 SW1 BG1 TG2 BOOST1,2,3 SW2 BG2 DB1,2,3 CB1,2,3 0.1μF SW1,2,3 0.002Ω 5% 0.47μH 0.47μH 0.78μH LTC3853 100Ω* 10k INTVCC 1000pF* 100Ω* 100Ω* 0.002Ω 5% 100Ω* VOUT1 1.2V 30A 1000pF* MODE/PLLIN PGND ILIM FREQ/PLLFLTR SENSE1 EXTVCC SENSE1– VFB1 ITH1,2,3 RITH1,3 VFB3 SGND TK/SS1 CSS1 0.22μF + 100Ω* 1000pF* 100Ω* 0.002Ω 5% VOUT3 2.5V 15A SENSE2 + SENSE2– VFB2 RUN1,3 RUN2 TG3 SW3 BG3 SENSE3+ SENSE3– TK/SS3 CSS3 0.1μF 2.55k VOUT1 200k 1000pF 10k 1% 47pF CP1,3 43.2k 1% + 660μF 2.5V 2 CITH1,3 20k 1% 20k 1% + 660μF 4V 3853 TA04 CHANNEL 1: RITH1 = 10k, CITH1 = 1500pF, CP1 = 220pF CHANNEL 2: ITH1 AND ITH2 SHORTED TOGETHER, TK/SS1 AND TK/SS2 SHORTED TOGETHER CHANNEL 3: RITH3 = 13k, CITH3 = 1500pF, CP3 = 330pF *THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC 3853f 33 LTC3853 TYPICAL APPLICATIONS Three Phase 2.5V Output High Current Step-Down Converter with RSENSE 180μF 16V VIN 6.5V TO 14V 4.7μF TG1 PGOOD12 PGOOD3 SW1 BG1 VIN DRVCC12 INTVCC TG2 BOOST1,2,3 SW2 BG2 DB1,2,3 CB1,2,3 0.1μF SW1,2,3 0.002Ω 5% 0.78μH 0.78μH 0.78μH LTC3853 100Ω* 10k INTVCC 1000pF* 100Ω* 100Ω* 0.002Ω 5% 100Ω* VOUT1 2.5V 40A 1000pF* MODE/PLLIN PGND ILIM FREQ/PLLFLTR SENSE1+ EXTVCC SENSE1– VFB1 VFB2 VFB3 ITH1 ITH2 ITH3 SGND TK/SS1 CSS1 0.33μF SENSE2+ SENSE2– RUN1 RUN2 RUN3 TG3 SW3 BG3 SENSE3+ SENSE3– 100Ω* 1000pF* 100Ω* 0.002Ω 5% VOUT1 VOUT1 43.2k 1% 47pF CP1 RITH1 CITH1 2.55k 1000pF + 660μF 4V 3 20k 1% 3853 TA05 RITH1 = 3.9k, CITH1 = 10nF, CP1 = 470pF • 3 SHORT TK/SS1, TK/SS2 AND TK/SS3 TOGETHER *THESE FILTER COMPONENTS NEED TO BE CLOSE TO THE IC 3853f 34 LTC3853 PACKAGE DESCRIPTION UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 1 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 2 0.10 PIN 1 TOP MARK (SEE NOTE 6) 4.50 REF (4-SIDES) 4.42 0.10 4.42 0.10 (UJ40) QFN REV Ø 0406 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 BOTTOM VIEW—EXPOSED PAD 0.05 0.50 BSC 3853f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC3853 RELATED PARTS PART NUMBER DESCRIPTION LTC1625/ LTC1775 LTC1735 LTC1778 LTC3727A-1 LTC3728 LTC3729 LTC3731 LTC3773 LTC3810 LTC3811 LTC3826 LTC3828 LTC3834/ LTC3834-1 LT3845 LTC3850 LTC3851 No RSENSE Current Mode Synchronous Step-Down Controllers High Efficiency Synchronous Step-Down Switching Regulator No RSENSE Wide Input Range Synchronous Step-Down Controller Dual, 2-Phase Synchronous Controller 2-Phase 550kHz, Dual Synchronous Step-Down Controller 20A to 200A PolyPhase Synchronous Controllers 3-Phase, Single Output From 250kHz to 600kHz Synchronous Step-Down Controller Triple Output DC/DC Synchronous Controller ® TM COMMENTS 97% Efficiency, 99% Duty Cycle Output Fault Protection, 16-Pin SSOP Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN), IOUT Up to 20A Very Low Dropout; VOUT ≤ 14V, 4V ≤ VIN ≤ 36V QFN and SSOP Packages, High Frequency for Smaller L and C Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V, IOUT ≤ 60A, Integrated MOSFET Drivers 3-Phase Step-Down DC/DC Controller, 3.3V ≤ VIN ≤ 36V, Fixed Frequency 160kHz to 700kHz 100V Current Mode Synchronous Nonisolated Switching Regulator 6.2V ≤ VIN ≤ 100V, No RSENSE, Synchronizable with Tracking Controller Dual, PolyPhase Synchronous Step-Down Controller, 20A to 200A Low IQ, Dual, 2-Phase Synchronous Step-Down Controller Dual, 2-Phase Synchronous Step-Down Controller with Tracking Low IQ, Synchronous Step-Down Controller Low IQ, High Voltage Single Output Synchronous Step-Down DC/DC Controller Dual 2-Phase Synchrounous Controller No RSENSE Wide Input Range Step-Down Controller Differential Remote Sense Amplifier, RSENSE or DCR Current Sense 30μA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V Up to Six Phases, 0.8V ≤ VOUT ≤ 7V, 4.5V ≤ VIN ≤ 28V 30μA IQ, 0.8V ≤ VOUT ≤ 10V, 4V ≤ VIN ≤ 36V 1.23V ≤ VOUT ≤ 36V, 4V ≤ VIN ≤ 60V, 120μA IQ 2-Phase Version of LTC3853 in a 28-Lead 4mm × 4mm QFN, 4mm × 5mm QFN or 28-Lead SSOP Narrow 4V ≤ VIN ≤ 38V, Very Low Dropout with Tracking PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. 3853f 36 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0808 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008