LTC3858EUFD-1TRPBF

FeaTures n n n n n LTC3858-1 Low IQ, Dual 2-Phase Synchronous Step-Down Controller DescripTion The LTC®3858-1 is a high performance dual step-down switching regulator controller that drives all N-channel synchronous power MOSFET stages. A constant frequency current mode architecture allows a phase-lockable frequency of up to 850kHz. Power loss and noise due to the input capacitor ESR are minimized by operating the two controller outputs out of phase. The 170μA no-load quiescent current extends operating life in battery powered systems. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3858-1 features a precision 0.8V reference and a power good output indicator. A wide 4V to 38V input supply range encompasses a wide range of intermediate bus voltages and battery chemistries. Independent soft-start pins for each controller ramp the output voltages during start-up. The output latch-off feature protects the circuit in short-circuit conditions. For a leadless 32-pin QFN package with the additional features of adjustable current limit, clock out, phase modulation and two PGOOD outputs, see the LTC3858 data sheet. L, LT, LTC, LTM, Burst Mode, OPTI-LOOP , µModule, Linear Technology and the Linear logo are registered trademarks and No RSENSE and UltraFast are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. n n n n n n n n n n n n n Low Operating IQ: 170µA (One Channel On) Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 24V Wide VIN Range: 4V to 38V RSENSE or DCR Current Sensing Out-of-Phase Controllers Reduce Required Input Capacitance and Power Supply Induced Noise OPTI-LOOP® Compensation Minimizes COUT Phase-Lockable Frequency (75kHz-850kHz) Programmable Fixed Frequency (50kHz-900kHz) Selectable Continuous, Pulse-Skipping or Burst Mode® Operation at Light Loads Very Low Dropout Operation: 99% Duty Cycle Adjustable Output Voltage Soft-Start Power Good Output Voltage Monitor Output Overvoltage Protection Output Latch-Off Protection During Short Circuit Low Shutdown IQ: 8µA Internal LDO Powers Gate Drive from VIN or EXTVCC No Current Foldback During Start-Up Tiny 4mm × 5mm QFN and Narrow SSOP Packages applicaTions Automotive Systems Battery Operated Digital Devices n Distributed DC Power Systems n n Typical applicaTion High Efficiency Dual 8.5V/3.3V Step-Down Converter 4.7µF TG1 3.3µH 0.1µF VIN INTVCC TG2 22µF 50V VIN 9V TO 38V 100 90 7.2µH EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.0001 0.001 VIN = 12V VOUT = 3.3V FIGURE 12 CIRCUIT 0.01 0.1 1 OUTPUT CURRENT (A) 10 38581 TA01b Efficiency and Power Loss vs Load Current 10000 1000 POWER LOSS (mW) EFFICIENCY POWER LOSS BOOST1 SW1 BG1 LTC3858-1 BOOST2 SW2 BG2 PGND SENSE2+ 0.1µF 100 10 SENSE1+ 0.007Ω VOUT1 3.3V 5A SENSE1– VFB1 ITH1 SS1 0.1µF SGND 0.01Ω SENSE2– VFB2 ITH2 SS2 0.1µF VOUT2 8.5V 3.5A 150µF 1 62.5k 150µF 20k 193k 680pF 15k 20k 680pF 15k 0.1 38581 TA01 38581fb  LTC3858-1 absoluTe MaxiMuM raTings (Note 1) Input Supply Voltage (VIN) ......................... –0.3V to 40V Topside Driver Voltages BOOST1, BOOST2 ................................ –0.3V to 46V . Switch Voltage (SW1, SW2) ........................ –5V to 40V (BOOST1-SW1), (BOOST2-SW2) ................ –0.3V to 6V RUN1, RUN2 ............................................... –0.3V to 8V Maximum Current Sourced Into Pin from Source >8V...............................................100µA SENSE1+, SENSE2+, SENSE1– SENSE2– Voltages ..................................... –0.3V to 28V . PLLIN/MODE, FREQ Voltages .............. –0.3V to INTVCC EXTVCC ..................................................... –0.3V to 14V . ITH1, ITH2,VFB1, VFB2 Voltages ...................... –0.3V to 6V PGOOD1 Voltage ......................................... –0.3V to 6V SS1, SS2, INTVCC Voltages ......................... –0.3V to 6V Operating Junction Temperature Range (Note 2) ................................................. –40°C to 125°C . Maximum Junction Temperature (Note 3) ............ 125°C Storage Temperature Range .................. –65°C to 150°C . Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C pin conFiguraTion TOP VIEW PGOOD1 SW1 ITH1 VFB1 SENSE1+ 22 BOOST1 21 BG1 20 VIN 29 SGND 19 PGND 18 EXTVCC 17 INTVCC 16 BG2 15 BOOST2 9 10 11 12 13 14 VFB2 SENSE2+ ITH2 SS2 TG2 SW2 SENSE1– FREQ PLLIN/MODE SGND RUN1 RUN2 SENSE2+ 1 2 3 4 5 6 7 8 9 11 VFB1 ITH1 SS1 TG1 TOP VIEW 28 SS1 27 PGOOD1 26 TG1 25 SW1 24 BOOST1 23 BG1 22 VIN 21 PGND 20 EXTVCC 19 INTVCC 18 BG2 17 BOOST2 16 SW2 15 TG2 28 27 26 25 24 23 SENSE1+ 1 SENSE1– 2 FREQ 3 PLLIN/MODE 4 SGND 5 RUN1 6 RUN2 7 SENSE2– 8 SENSE2– 10 VFB2 12 ITH2 13 SS2 14 TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN GN PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 90°C/W orDer inForMaTion LEAD FREE FINISH LTC3858EUFD-1#PBF LTC3858IUFD-1#PBF LTC3858EGN-1#PBF LTC3858IGN-1#PBF TAPE AND REEL LTC3858EUFD-1#TRPBF LTC3858IUFD-1#TRPBF LTC3858EGN-1#TRPBF LTC3858IGN-1#TRPBF PART MARKING* 38581 38581 LTC3858GN-1 LTC3858GN-1 PACKAGE DESCRIPTION 28-Lead (4mm × 5mm) Plastic QFN 28-Lead (4mm × 5mm) Plastic QFN 28-Lead Plastic SSOP 28-Lead Plastic SSOP TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 38581fb  LTC3858-1 elecTrical characTerisTics SYMBOL VIN VFB1,2 IFB1,2 VREFLNREG VLOADREG PARAMETER Input Supply Operating Voltage Range Regulated Feedback Voltage (Note 4) ITH1,2 = 1.2V –40°C to 125°C –40°C to 85°C (Note 4) (Note 4) VIN = 4.5V to 38V (Note4) Measured in Servo Loop, ∆ITH Voltage = 1.2V to 0.7V (Note4) Measured in Servo Loop, ∆ITH Voltage = 1.2V to 2V gm1,2 IQ Transconductance Amplifier gm Input DC Supply Current Pulse Skip or Forced Continuous Mode (One Channel On) Pulse Skip or Forced Continuous Mode (Both Channels On) Sleep Mode (One Channel On) (Note 4) ITH1,2 = 1.2V, Sink/Source = 5µA (Note 5) RUN1 = 5V and RUN2 = 0V or RUN1 = 0V and RUN2 = 5V, VFB1 = 0.83V (No Load) RUN1,2 = 5V, VFB1,2 = 0.83V (No Load) RUN1 = 5V and RUN2 = 0V or RUN1 = 0V and RUN2 = 5V, VFB1 = 0.83V (No Load) RUN1,2 = 5V, VFB1,2 = 0.83V (No Load) RUN1,2 = 0V INTVCC Ramping Up INTVCC Ramping Down Measured at VFB1,2, Relative to Regulated VFB1,2 Each Channel Each Channel VOUT1,2 < INTVCC – 0.5 VOUT1,2 > INTVCC + 0.5 In Dropout, FREQ = 0V VSS1,2 = 0V VRUN1, VRUN2 Rising VSS1, VSS2 Rising from 1V VSS1, VSS2 Rising from 2V Short-Circuit Condition VFB1,2 = 0.5V VSS1,2 = 4.5V VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V l l l l l l The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise noted. CONDITIONS MIN 4 0.788 0.792 0.800 0.800 ±5 0.002 0.01 –0.01 2 1.3 2 170 300 8 3.6 7 4.0 3.8 10 540 98 0.7 1.23 1.9 1.3 7 43 99.4 1.0 1.28 50 2 1.5 10 50 2.1 1.7 13 57 1.4 1.33 250 450 20 4.2 4.0 13 ±1 ±1 700 TYP MAX 38 0.812 0.808 ±50 0.02 0.1 –0.1 UNITS V V V nA %/V % % mmho mA mA µA µA µA V V % µA µA µA % µA V mV V V µA mV Feedback Current Reference Voltage Line Regulation Output Voltage Load Regulation l Sleep Mode (Both Channels On) Shutdown UVLO VOVL Undervoltage Lockout Feedback Overvoltage Protection SENSE+ Pin Current SENSE– Pins Current ISENSE+ ISENSE– DFMAX ISS1,2 VRUN1,2 On VSS1,2 LA VSS1,2 LT IDSC1,2 LT VSENSE(MAX) Gate Driver TG1,2 BG1,2 Maximum Duty Factor Soft-Start Charge Current RUN Pin On Threshold Voltage SS Pin Latch-Off Arming Threshold Voltage SS Pin Latch-Off Threshold Voltage SS Discharge Current Maximum Current Sense Threshold Voltage Pull-Up On-Resistance Pull-Down On-Resistance Pull-Up On-Resistance Pull-Down On-Resistance VRUN1,2 Hyst RUN Pin Hysteresis Voltage 2.5 1.5 2.4 1.1 Ω Ω Ω Ω 38581fb  LTC3858-1 elecTrical characTerisTics SYMBOL TG1,2 tr TG1,2 tf BG1,2 tr BG1,2 tf TG/BG t1D BG/TG t1D tON(MIN) VINTVCCVIN VLDOVIN VINTVCCEXT VLDOEXT VEXTVCC VLDOHYS f25kΩ f65kΩ f105kΩ fLOW fHIGH fSYNC VPGL IPGOOD VPG PARAMETER TG Transistion Time: Rise Time Fall Time BG Transistion Time: Rise Time Fall Time Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation Internal VCC Voltage INTVCC Load Regulation EXTVCC Switchover Voltage EXTVCC Hysteresis Voltage Programmable Frequency Programmable Frequency Programmable Frequency Low Fixed Frequency High Fixed Frequency Synchronizable Frequency PGOOD1 Voltage Low PGOOD1 Leakage Current PGOOD1 Trip Level RFREQ = 25k, PLLIN/MODE = DC Voltage RFREQ = 65k, PLLIN/MODE = DC Voltage RFREQ = 105k, PLLIN/MODE = DC Voltage VFREQ = 0V, PLLIN/MODE = DC Voltage VFREQ = INTVCC, PLLIN/MODE = DC Voltage PLLIN/MODE = External Clock IPGOOD = 2mA VPGOOD = 5V VFB with Respect to Set Regulated Voltage VFB Ramping Negative Hysteresis VFB with Respect to Set Regulated Voltage VFB Ramping Positive Hysteresis tPG Delay for Reporting a Fault (PGOOD Low) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Ratings for extended periods may affect device reliability and lifetime. Note 2: The LTC3858E-1 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3858I-1 is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA) where θJA = 43°C/W for the QFN package and θJA = 90°C/W for the SSOP package. –13 7 –10 2.5 10 2.5 25 l The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise noted. CONDITIONS (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF CLOAD = 3300pF Each Driver CLOAD = 3300pF Each Driver (Note 7) 6V < VIN < 38V, VEXTVCC = 0V ICC = 0mA to 50mA, VEXTVCC = 0V 6V < VEXTVCC < 13V ICC = 0mA to 50mA, VEXTVCC = 8.5V EXTVCC Ramping Positive 4.5 4.85 4.85 MIN TYP 25 16 28 13 30 30 95 5.1 0.7 5.1 0.6 4.7 250 105 375 320 485 75 0.2 440 835 350 535 380 585 850 0.4 ±1 –7 13 505 5.35 1.1 5.35 1.1 4.9 MAX UNITS ns ns ns ns ns ns ns V % V % V mV kHz kHz kHz kHz kHz kHz V µA % % % % µs INTVCC Linear Regulator Oscillator and Phase-Locked Loop PGOOD1 Output Note 4: The LTC3858-1 is tested in a feedback loop that ser vos VITH1,2 to a specified voltage and measures the resultant VFB1,2. The specification at 85°C is not tested in production. This specification is assured by design, characterization and correlation to production testing at 125°C. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels Note 7: The minimum on-time condition is specified for an inductor peakto-peak ripple current ≥ of IMAX (See Minimum On-Time Considerations in the Applications Information section). 38581fb  LTC3858-1 Typical perForMance characTerisTics Efficiency and Power Loss vs Output Current 100 FIGURE 12 CIRCUIT 90 VIN = 12V VOUT = 3.3V 80 70 60 50 40 30 20 10 0 0.0001 100 Burst Mode OPERATION 10 PULSESKIPPING MODE 1 FORCED CONTINUOUS MODE 0.1 0.001 0.01 0.1 1 10 OUTPUT CURRENT (A) 3858 G01 Efficiency vs Load Current 10000 100 90 1000 POWER LOSS (mW) EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.0001 0.001 VOUT = 3.3V FIGURE 12 CIRCUIT 0.01 0.1 1 OUTPUT CURRENT (A) 10 3858 G02 VIN = 5V VIN = 12V EFFICIENCY (%) Efficiency vs Input Voltage 98 96 94 EFFICIENCY (%) 92 90 88 86 84 82 80 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 IL 2A/DIV FIGURE 12 CIRCUIT VOUT = 3.3V IOUT = 4A VOUT 100mV/DIV ACCOUPLED Load Step (Burst Mode Operation) VOUT 100mV/DIV ACCOUPLED Load Step (Forced Continuous Mode) IL 2A/DIV VOUT = 3.3V 20µs/DIV FIGURE 12 CIRCUIT 3858 G04 20µs/DIV VOUT = 3.3V FIGURE 12 CIRCUIT 3858 G05 3858 G03 Load Step (Pulse-Skipping Mode) VOUT 100mV/DIV ACCOUPLED Inductor Current at Light Load Soft-Start FORCED CONTINUOUS MODE Burst Mode OPERATION 2A/DIV PULSESKIPPING MODE VOUT = 3.3V 20µs/DIV FIGURE 12 CIRCUIT 3858 G06 VOUT2 2V/DIV VOUT1 2V/DIV IL 2A/DIV VOUT = 3.3V 2µs/DIV ILOAD = 200µA FIGURE 12 CIRCUIT 3858 G07 20ms/DIV FIGURE 12 CIRCUIT 3858 G08 38581fb  LTC3858-1 Typical perForMance characTerisTics Total Input Supply Current vs Input Voltage 400 350 SUPPLY CURRENT (µA) 300 250 200 150 100 50 0 5 10 15 30 25 20 INPUT VOLTAGE (V) 35 40 3858 G10 EXTVCC Switchover and INTVCC Voltages vs Temperature 5.6 EXTVCC AND INTVCC VOLTAGE (V) 5.4 INTVCC VOLTAGE (V) 5.2 5.0 4.8 4.6 4.4 4.2 4.0 –45 –20 5 80 55 30 TEMPERATURE (°C) 105 130 5.0 EXTVCC RISING EXTVCC FALLING INTVCC 5.2 5.2 INTVCC Line Regulation FIGURE 12 CIRCUIT VOUT = 3.3V ONE CHANNEL ON 300µA LOAD 5.1 NO LOAD 5.1 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 3858 G11 3858 G12 CURRENT SENSE THRESHOLD (mV) –50 –100 SENSE– CURRENT (µA) –150 –200 –250 –300 –350 –400 –450 –500 –550 1.4 –600 0 25 10 15 20 VSENSE COMMON MODE VOLTAGE (V) 5 3858 G14 60 40 20 0 –20 –40 MAXIMUM CURRENT SENSE VOLTAGE (mV) 80 Maximum Current Sense Voltage vs ITH Voltage PULSE-SKIPPING MODE FORCED CONTINUOUS MODE Burst Mode OPERATION (FALLING) Burst Mode OPERATION (RISING) 0 SENSE– Pin Input Bias Current 80 Maximum Current Sense Threshold vs Duty Cycle 60 40 20 5% DUTY CYCLE 0 0.2 0.4 0.6 0.8 1.0 ITH PIN VOLTAGE 1.2 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3858 G15 3858 G13 Foldback Current Limit MAXIMUM CURRENT SENSE VOLTAGE (mV) 90 80 QUIESCENT CURRENT (µA) 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FEEDBACK VOLTAGE (V) 3858 G16 Quiescent Current vs Temperature 230 210 190 170 150 130 110 –45 PLLIN/MODE = 0 VIN = 12V VOUT = 3.3V ONE CHANNEL ON 10 9 8 7 6 5 Shutdown Current vs Temperature SHUTDOWN CURRENT (µA) –20 80 5 55 30 TEMPERATURE (°C) 105 130 4 –45 –20 55 30 80 5 TEMPERATURE (°C) 105 130 3858 G17 3858 G18 38581fb  LTC3858-1 Typical perForMance characTerisTics Soft-Start Pull-Up Current vs Temperature 1.20 1.15 SS PULL-UP CURRENT (µA) RUN PIN VOLTAGE (V) 1.10 1.05 1.00 0.95 0.90 0.85 0.80 –45 –20 5 80 55 30 TEMPERATURE (°C) 105 130 1.40 REGULATED FEEDBACK VOLTAGE (mV) 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 –45 –20 55 30 5 80 TEMPERATURE (°C) 105 130 Shutdown (RUN) Threshold vs Temperature 808 806 804 802 800 798 796 794 Regulated Feedback Voltage vs Temperature 792 –45 –20 5 80 55 30 TEMPERATURE (°C) 105 130 3858 G19 3858 G20 22554 G21 SENSE– Pin Input Current vs Temperature 50 0 –50 –100 –150 –200 –250 –300 –350 –400 –450 –500 –550 –600 –45 14 VOUT = 3.3V INPUT CURRENT (µA) 12 Shutdown Input Current vs Input Voltage 800 700 600 FREQUENCY (kHz) 500 400 300 200 100 5 10 25 20 30 15 INPUT VOLTAGE (V) 35 40 3858 G23 Oscillator Frequency vs Temperature SENSE– CURRENT (µA) 10 8 6 4 2 0 FREQ = INTVCC FREQ = GND VOUT = 28V –20 80 55 5 30 TEMPERATURE (°C) 105 130 0 –45 –20 5 80 55 30 TEMPERATURE (°C) 105 130 3858 G22 3858 G24 Oscillator Frequency vs Input Voltage 356 OSCILLATOR FREQUENCY (kHz) 354 352 350 348 346 344 INTVCC VOLTAGE (V) FREQ = GND 4.4 4.3 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 5 10 25 20 30 15 INPUT VOLTAGE (V) 35 40 3858 G28 Undervoltage Lockout Threshold vs Temperature 3.4 –45 –20 55 5 80 30 TEMPERATURE (°C) 105 130 3858 G25 38581fb  LTC3858-1 Typical perForMance characTerisTics INTVCC vs Load Current 5.20 VIN = 12V 2.3 2.2 2.1 INTVCC VOLTAGE (V) 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 4.95 0 20 40 60 80 100 120 140 160 180 200 LOAD CURRENT (mA) 3858 G26 Latch-Off Threshold Voltage vs Temperature 5.15 INTVCC VOLTAGE (V) 5.10 EXTVCC = 0V 5.05 5.00 EXTVCC = 8V ARMING THRESHOLD LATCH-OFF THRESHOLD 1.2 –45 –20 55 30 5 80 TEMPERATURE (°C) 105 130 3858 G27 pin FuncTions (QFN/SSOP) SENSE1–, SENSE2– (Pin 2, Pin 4/Pin 8, Pin 10): The (–) Input to the Differential Current Comparators. When greater than INTVCC – 0.5V, the SENSE– pin supplies current to the current comparator. FREQ (Pin 3/Pin 5): The Frequency Control Pin for the Internal Voltage-Contolled Oscillator (VCO). Connecting this pin to GND forces the VCO to a fixed low frequency of 350kHz. Connecting this pin to INTVCC forces the VCO to a fixed high frequency of 535kHz. Other frequencies between 50kHz and 900kHz can be programmed using a resistor between FREQ and GND. An internal 20µA pullup current develops the voltage to be used by the VCO to control the frequency PLLIN/MODE (Pin 4/Pin 6): External Synchronization Input to Phase Detector and Forced Continuous Mode Input. When an external clock is applied to this pin, the phase-locked loop will force the rising TG1 signal to be synchronized with the rising edge of the external clock. When not synchronizing to an external clock, this input, which acts on both controllers, determines how the LTC3858-1 operates at light loads. Pulling this pin to ground selects Burst Mode operation. An internal 100k resistor to ground also invokes Burst Mode operation when the pin is floated. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to a voltage greater than 1.2V and less than INTVCC – 1.3V selects pulse-skipping operation. SGND (Pin 5, Exposed Pad Pin 29/Pin 7): Small-signal ground common to both controllers, must be routed separately from high current grounds to the common (–) terminals of the CIN capacitors. The exposed pad (QFN only) must be soldered to the PCB for rated thermal performance. RUN1, RUN2 (Pin 6, Pin 8/Pin 7, Pin 9): Digital Run Control Inputs for Each Controller. Forcing either of these pins below 1.2V shuts down that controller. Forcing both of these pins below 0.7V shuts down the entire LTC3858-1, reducing quiescent current to approximately 8µA. Do NOT float these pins. 38581fb  LTC3858-1 pin FuncTions (QFN/SSOP) INTVCC (Pin 17/Pin 19): Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7µF ceramic or other low ESR capacitor. Do not use the INTVCC pin for any other purpose. EXTVCC (Pin 18/Pin 20): External Power Input to an Internal LDO Connected to INTVCC. This LDO supplies INTVCC power, bypassing the internal LDO powered from VIN whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 14V on this pin. PGND (Pin 19/Pin 21): Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs and the (–) terminal(s) of CIN. VIN (Pin 20/Pin 22): Main Input Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. BG1, BG2 (Pin 21, Pin 23/Pin 16, Pin 18): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTVCC. BOOST1, BOOST2 (Pin 22, Pin 24/Pin 15, Pin 17): Bootstrapped Supplies to the Topside Floating Drivers. Capacitors are connected between the BOOST and SW pins and Schottky diodes are tied between the BOOST and INTVCC pins. Voltage swing at the BOOST pins is from INTVCC to (VIN + INTVCC). SW1, SW2 (Pin 23, Pin 25/Pin 14, Pin 16): Switch Node Connections to Inductors. TG1, TG2 (Pin 24, Pin 26/Pin 13, Pin 15): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC – 0.5V superimposed on the switch node voltage SW. PGOOD1 (Pin 25/Pin 27): Open-Drain Logic Output. PGOOD1 is pulled to ground when the voltage on the VFB1 pin is not within ±10% of its set point. SS1, SS2 (Pin 26, Pin 28/Pin 12, Pin 14): External SoftStart Input. The LTC3858-1 regulates the VFB1,2 voltage to the smaller of 0.8V or the voltage on the SS1,2 pin. An internal 1µA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. This pin is also used as the short-circuit latchoff timer. ITH1, ITH2 (Pin 27, Pin 1/Pin 11, Pin 13): Error Amplifier Outputs and Switching Regulator Compensation Points. Each associated channel’s current comparator trip point increases with this control voltage. VFB1, VFB2 (Pin 28, Pin 2/Pin 10, Pin 12): Receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. SENSE1+, SENSE2+ (Pin 1, Pin 3/Pin 9, Pin 11): The (+) input to the differential current comparators that are normally connected to inductor DCR sensing networks or current sensing resistors. The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. 38581fb  LTC3858-1 FuncTional DiagraM INTVCC DUPLICATE FOR SECOND CONTROLLER CHANNEL BOOST DB CB D SW INTVCC BG PGND VCO CLK2 CLK1 – + 0.425V SLEEP IR – L RSENSE CIN VIN FREQ 20µA –+ +– 3mV PLLIN/MODE 100k SYNC DET 2(VFB) 0.45V SLOPE COMP + VIN EXTVCC OV 5.1V LDO EN + 5.1V LDO EN 0.5µA SHDN RST 2(VFB) FOLDBACK 1µA SS CSS CC2 RC 10V operaTion Main Control Loop The LTC3858-1 uses a constant frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. During normal operation, each external top MOSFET is turned on when the clock for that channel sets the RS latch, and is turned off when the main current comparator, ICMP , resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, EA. The error amplifier compares the output voltage feedback signal at the VFB pin (which is generated with an external resistor divider connected across the output voltage, VOUT , to ground) to the internal 0.800V reference voltage. When the load current increases, it causes a slight decrease in VFB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current matches the new load current. After the top MOSFET is turned off each cycle, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of the next clock cycle. 38581fb 0 – 4.7V SGND INTVCC RUN SHORT CKT LATCH-OFF SHDN 10µA 38581 FD + – – + + – + + – – PGOOD1 0.88V VFB1 0.72V S R Q Q DROP OUT DET TOP BOT TOP ON SWITCH LOGIC BOT TG SHDN COUT VOUT PFD ICMP SENSE+ SENSE– VFB EA 0.80V TRACK/SS RA RB 0.88V ITH CC LTC3858-1 operaTion (Refer to the Functional Diagram) INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.7V, the VIN LDO (low dropout linear regulator) supplies 5.1V from VIN to INTVCC. If EXTVCC is taken above 4.7V, the VIN LDO is turned off and the EXTVCC LDO is turned on. Once enabled, the EXTVCC LDO supplies 5.1V from EXTVCC to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one of the LTC3858-1 switching regulator outputs. Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each switching cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage close to VOUT , the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period every tenth cycle to allow CB to recharge. Shutdown and Start-Up (RUN1, RUN2 and SS1, SS2 Pins) The two channels of the LTC3858-1 can be independently shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 1.26V shuts down the main control loop for that controller. Pulling both pins below 0.7V disables both controllers and most internal circuits, including the INTVCC LDOs. In this state, the LTC3858-1 draws only 8µA of quiescent current. The RUN pin may be externally pulled up or driven directly by logic. When driving the RUN pin with a low impedance source, do not exceed the absolute maximum rating of 8V on this pin. The RUN pin has an internal 11V voltage clamp that allows the RUN pin to be connected through a resistor to a higher voltage (for example, VIN), so long as the maximum current into the RUN pin does not exceed 100µA. The start-up of each controller’s output voltage VOUT is controlled by the voltage on the SS pin for that channel. When the voltage on the SS pin is less than the 0.8V internal reference, the LTC3858-1 regulates the VFB voltage to the SS pin voltage instead of the 0.8V reference. This allows the SS pin to be used to program a soft-start by connecting an external capacitor from the SS pin to SGND. An internal 1µA pull-up current charges this capacitor creating a voltage ramp on the SS pin. As the SS voltage rises linearly from 0V to 0.8V (and beyond up to the absolute maximum rating of 6V), the output voltage VOUT rises smoothly from zero to its final value. Short-Circuit Latch-Off After the controller has been started and been given adequate time to ramp up the output voltage, the SS capacitor is used in a short-circuit time-out circuit. Specifically, once the voltage on the SS pin rises above 2V (the arming threshold), the short-circuit timeout circuit is enabled (see Figure 1). If the output voltage falls below 70% of its nominal regulated voltage, the SS capacitor begins discharging with a net 9µA pull-down current on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts long enough to allow the SS pin voltage to fall below 1.5V (the latchoff threshold) , the controller will shut down (latch off) until the RUN pin voltage or the VIN voltage is recycled. The delay time from when an short-circuit occurs until the controller latches off can be calculated using the following equation: tLATCH ≈ CSS VSS – 1.5V 9µA where VSS is the initial voltage (must be greater than 2V) on the SS pin at the time the short-circuit occurs. Normally the SS pin voltage will have been pulled up to the INTVCC voltage (5.1V) by the internal 1µA pull-up current. Note that the two controllers on the LTC3858-1 have separate, independent short-circuit latchoff circuits. Latchoff can be overridden/defeated by connecting a resistor 150k or less from the SS pin to INTVCC. This resistor provides enough pull-up current to overcome the 9µA pull-down current present during a short-circuit. Note that this resistor also shortens the soft-start period. 38581fb  LTC3858-1 operaTion (Refer to the Functional Diagram) INTVCC SS VOLTAGE 2V 0.8V LATCH-OFF COMMAND 0V 1µA –9µA OUTPUT VOLTAGE LATCH-OFF ENABLE 38581 F01 1.5V SS PIN CURRENT 1µA When a controller is enabled for Burst Mode operation, the minimum peak current in the inductor is set to approximately 30% of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current. If one channel is shut down and the other channel is in sleep mode, the LTC3858-1 draws only 170µA of quiescent current. If both channels are in sleep mode, the LTC3858-1 draws only 300µA of quiescent current. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator, IR, turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller is in discontinuous operation. In forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantages of lower output voltage ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode, the LTC3858-1 operates in PWM pulse-skipping mode at light loads. In this mode, constant frequency 38581fb ARMING SOFT-START INTERVAL tLATCH Figure 1. Latch-Off Timing Diagram Foldback Current On the other hand, when the output voltage falls to less than 70% of its nominal level, foldback current limiting is also activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. Even if a short-circuit is present and the short-circuit latch-off is not yet enabled (when SS voltage has not yet reached 2V), a safe, low output current is provided due to internal current foldback and actual power wasted is low due to the efficient nature of the current mode switching regulator. Foldback current limiting is disabled during the soft-start inter val (as long as the VFB voltage is keeping up with the SS voltage). Light Load Current Operation (Burst Mode Operation, Pulse-Skipping or Forced Continuous Conduction) (PLLIN/MODE Pin) The LTC3858-1 can be enabled to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/ MODE pin to ground. To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To select pulseskipping mode, tie the PLLIN/MODE pin to a DC voltage greater than 1.2V and less than INTVCC – 1.3V.  LTC3858-1 operaTion (Refer to the Functional Diagram) operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference when compared to Burst Mode operation. It provides higher light load efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and PLLIN/MODE Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3858-1’s controllers can be selected using the FREQ pin. If the PLLIN/MODE pin is not being driven by an external clock source, the FREQ pin can be tied to SGND, tied to INTVCC or programmed through an external resistor. Tying FREQ to SGND selects 350kHz while tying FREQ to INTVCC selects 535kHz. Placing a resistor between FREQ and SGND allows the frequency to be programmed between 50kHz and 900kHz. A phase-locked loop (PLL) is available on the LTC3858-1 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. The phase detector adjusts the voltage (through an internal lowpass filter) of the VCO input to align the turn-on of controller 1’s external top MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2’s external top MOSFET is 180 degrees out of phase to the rising edge of the external clock source. The VCO input voltage is pre-biased to the operating frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL loop only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock’s to the rising edge of TG1. The ability to pre-bias the loop filter allows the PLL to lock-in rapidly without deviating far from the desired frequency. The typical capture range of the phase-locked loop is from approximately 55kHz to 1MHz, with a guarantee over all manufacturing variations to be between 75kHz and 850kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.1V (falling). Output Overvoltage Protection An over voltage comparator guards against transient overshoots as well as other more serious conditions that may overvoltage the output. When the VFB pin rises by more than 10% above its regulation point of 0.800V, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) Pin The PGOOD1 pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD1 pin low when the corresponding VFB1 pin voltage is not within ±10% of the 0.8V reference voltage. The PGOOD1 pin is also pulled low when the RUN1 pin is low (shut down). When the VFB1 pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6V. Theory and Benefits of 2-Phase Operation Why the need for 2-phase operation? Up until the 2-phase family, constant frequency dual switching regulators operated both channels in phase (i.e., single phase operation). This means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. These large amplitude current 38581fb  LTC3858-1 operaTion (Refer to the Functional Diagram) pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and battery. With 2-phase operation, the two channels of the dual switching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 2 compares the input waveforms for a representative single phase dual switching regulator to the LTC3858-1 2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input current from 2.53ARMS to 1.55ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to IRMS2, meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative duty cycles which, in turn, are dependent upon the input voltage VIN (Duty Cycle = VOUT/VIN). Figure 3 shows how the RMS input current varies for single-phase and 2-phase operation for 3.3V and 5V regulators over a wide input voltage range. It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. 3.0 2.5 INPUT RMS CURRENT (A) 2.0 1.5 1.0 0.5 0 SINGLE PHASE DUAL CONTROLLER 2-PHASE DUAL CONTROLLER VO1 = 5V/3A VO2 = 3.3V/3A 0 10 20 30 INPUT VOLTAGE (V) 40 3858 F03 Figure 3. RMS Input Current Comparison 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV IIN(MEAS) = 2.53ARMS IIN(MEAS) = 1.55ARMS 38581 F01 Figure 2. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency 38581fb  LTC3858-1 applicaTions inForMaTion The Typical Application on the first page is a basic LTC3858-1 application circuit. LTC3858-1 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design tradeoff between cost, power consumption and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs and Schottky diodes are selected. Finally, input and output capacitors are selected. SENSE+ and SENSE– Pins The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode voltage range on these pins is 0V to 28V (Abs Max), enabling the LTC3858-1 to regulate output voltages up to a nominal 24V (allowing margin for tolerances and transients). The SENSE+ pin is high impedance over the full common mode range, drawing at most ±1µA. This high impedance allows the current comparators to be used in inductor DCR sensing. The impedance of the SENSE– pin changes depending on the common mode voltage. When SENSE– is less than INTVCC – 0.5V, a small current of less than 1µA flows out of the pin. When SENSE– is above INTVCC + 0.5V, a higher current (~550µA) flows into the pin. Between INTVCC – 0.5V and INTVCC + 0.5V, the current transitions from the smaller current to the higher current. Filter components mutual to the sense lines should be placed close to the LTC3858-1, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 4). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If inductor DCR sensing is used (Figure 5b), resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. TO SENSE FILTER, NEXT TO THE CONTROLLER 38581 F04 COUT INDUCTOR OR RSENSE Figure 4. Sense Lines Placement with Inductor or Sense Resistor VIN INTVCC BOOST TG SW LTC3858-1 BG VIN VOUT SENSE+ SENSE– SGND PLACE CAPACITOR NEAR SENSE PINS 38581 F05a (5a) Using a Resistor to Sense Current VIN INTVCC BOOST TG SW LTC3858-1 BG R1 C1* SENSE– SGND *PLACE C1 NEAR SENSE PINS (R1||R2) • C1 = L DCR RSENSE(EQ) = DCR R2 R1 + R2 38581 F05b VIN INDUCTOR L DCR VOUT SENSE+ R2 (5b) Using the Inductor DCR to Sense Current Figure 5. Current Sensing Methods 38581fb  LTC3858-1 applicaTions inForMaTion Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 5a. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX) of 50mV (typ). The current comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current, IMAX, equal to the peak value less half the peak-to-peak ripple current, ∆IL. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) IMAX + ∆IL 2 using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers’ data sheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: RSENSE(EQUIV) = VSENSE(MAX) IMAX + ∆IL 2 When using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided in the Typical Performance Characteristics section to estimate this reduction in peak output current depending upon the operating duty factor. Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC3850 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 5b. The DCR of the inductor represents the small amount of DC resistance of the copper wire, which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor DCR sensing. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold Voltage (VSENSE(MAX)) in the Electrical Characteristics table. Next, determine the DCR of the inductor. When provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of copper, which is approximately 0.4%/°C. A conservative value for TL(MAX) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = RSENSE(EQUIV ) DCRMAX at TL(MAX ) C1 is usually selected to be in the range of 0.1µF to 0.47µF . This forces R1||R2 to around 2k, reducing error that might have been caused by the SENSE+ pin’s ±1µA current. The equivalent resistance R1||R2 is scaled to the room temperature inductance and maximum DCR: R1|| R2 = ( L DCR   at   20°C • C1 ) The sense resistor values are: R1 = R1 • RD R1|| R2 ;  R2 = RD 1 – RD 38581fb  LTC3858-1 applicaTions inForMaTion The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS  R1 = 30% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3858-1: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5.1V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 4V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. ( VIN(MAX) – VOUT ) • VOUT R1 Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding to use inductor DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or higher frequency and increases with higher VIN: ΔIL = V 1 VOUT 1– OUT  ( f) (L)  VIN  Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 38581fb  LTC3858-1 applicaTions inForMaTion Selection criteria for the power MOSFETs include the onresistance, RDS(ON), Miller capacitance, CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty  Cycle = VOUT VIN VIN − VOUT VIN synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+ δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes D1 and D2 shown in Figure 10 conduct during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula shown in Equation 1 to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN  Required IRMS ≈ 1/2 IMAX  ( VOUT ) ( VIN – VOUT ) (1)  VIN  38581fb Synchronous  Switch Duty  Cycle = The MOSFET power dissipations at maximum output current are given by: V 2 PMAIN = OUT (IMAX ) (1+ δ) RDS(ON) + VIN  2 I ( VIN)  MAX  (RDR ) (CMILLER ) • 2  1 1 +  ( f)  VINTVCC – VTHMIN VTHMIN  PSYNC = VIN – VOUT 2 (IMAX ) (1+ δ)RDS(ON) VIN where δ is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTHMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The  LTC3858-1 applicaTions inForMaTion Equation 1 has a maximum at VIN = 2VOUT , where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3858-1, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the 2-phase operation can be calculated by using Equation 1 for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1µF to 1µF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3858-1, is also suggested. A 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: ΔVOUT   1 ≈ ΔIL ESR +  8 • f • COUT   where f is the operating frequency, COUT is the output capacitance and ∆IL is the ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Setting Output Voltage The LTC3858-1 output voltages are each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 6. The regulated output voltage is determined by:  R VOUT = 0.8V 1+ B   RA  To improve the frequency response, a feedforward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT 1/2 LTC3858-1 VFB RA 38581 F05 RB CFF Figure 6. Setting Output Voltage Soft-Start (SS Pins) The start-up of each VOUT is controlled by the voltage on the respective SS pin. When the voltage on the SS pin is less than the internal 0.8V reference, the LTC3858-1 regulates the VFB pin voltage to the voltage on the SS pin instead of 0.8V. The SS pin can be used to program an external soft-start function. Soft-start is enabled by simply connecting a capacitor from the SS pin to ground, as shown in Figure 7. An internal 1µA current source charges the capacitor, providing a 1/2 LTC3858-1 SS CSS SGND 38581 F06 Figure 7. Using the SS Pin to Program Soft-Start 38581fb  LTC3858-1 applicaTions inForMaTion linear ramping voltage at the SS pin. The LTC3858-1 will regulate the VFB pin (and hence VOUT) according to the voltage on the SS pin, allowing VOUT to rise smoothly from 0V to its final regulated value. The total soft-start time will be approximately: 0.8 V tSS = CSS • 1µA INTVCC Regulators The LTC3858-1 features two separate internal P-channel low dropout linear regulators (LDO) that supply power at the INTVCC pin from either the VIN supply pin or the EXTVCC pin depending on the connection of the EXTVCC pin. INTVCC powers the gate drivers and much of the internal circuitry. The VIN LDO and the EXTVCC LDO regulate INTVCC to 5.1V. Each of these can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7µF low ESR capacitor. Regardless of what type of bulk capacitor is used, an additional 1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3858-1 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the VIN LDO or the EXTVCC LDO. When the voltage on the EXTVCC pin is less than 4.7V, the VIN LDO is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3858-1 INTVCC current is limited to less than 15mA from a 40V supply when not using the EXTVCC supply at 70°C ambient temperature in the SSOP package: TJ = 70°C + (15mA)(40V)(90°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in forced continuous mode (PLLIN/MODE = INTVCC) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the VIN LDO is turned off and the EXTVCC LDO is enabled. The EXTVCC LDO remains on as long as the voltage applied to EXTVCC remains above 4.5V. The EXTVCC LDO attempts to regulate the INTVCC voltage to 5.1V, so while EXTVCC is less than 5.1V, the LDO is in dropout and the INTVCC voltage is approximately equal to EXTVCC. When EXTVCC is greater than 5.1V, up to an absolute maximum of 14V, INTVCC is regulated to 5.1V. Using the EXTVCC LDO allows the MOSFET driver and control power to be derived from one of the switching regulator outputs (4.7V ≤ VOUT ≤ 14V) during normal operation and from the VIN LDO when the output is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTVCC LDO than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. In this case, do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC ≤ VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). For 5V to 14V regulator outputs, this means connecting the EXTVCC pin directly to VOUT . Tying the EXTVCC pin to a 8.5V supply reduces the junction temperature in the previous example from 125°C to: TJ = 70°C + (15mA)(8.5V)(90°C/W) = 82°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 38581fb 0 LTC3858-1 applicaTions inForMaTion 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5.1V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected Directly to VOUT . This is the normal connection for a 5V to 14V regulator and provides the highest efficiency. 3. EXTVCC Connected to an External Supply. If an external supply is available in the 5V to 14V range, it may be used to power EXTVCC. Ensure that EXTVCC < VIN. 4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with the capacitive charge pump shown in Figure 8. Ensure that EXTVCC < VIN. on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor, CB, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Fault Conditions: Current Limit and Current Foldback When the output current hits the current limit, the output voltage begins to drop. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered to about one-half of its maximum selected value. Under short-circuit conditions with very low duty cycles, the LTC3858-1 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time, tON(MIN), of the LTC3858-1 (≈90ns), the input voltage and inductor value: V  ΔIL(SC) = tON(MIN)  IN  L The resulting average short-circuit current is: ISC = 50% • ILIM(MAX) RSENSE 1 – ∆IL(SC) 2 CIN VIN MTOP TG1 1/2 LTC3858-1 EXTVCC SW MBOT BG1 PGND VIN BAT85 BAT85 BAT85 VN2222LL L RSENSE VOUT COUT 38581 F08 D Figure 8. Capacitive Charge Pump for EXTVCC Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator detects faults greater than 10% above the nominal output voltage. When this condition 38581fb  LTC3858-1 applicaTions inForMaTion is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The bottom MOSFET remains on continuously for as long as the overvoltage condition persists; if VOUT returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Phase-Locked Loop and Frequency Synchronization The LTC3858-1 has an internal phase-locked loop (PLL) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (VCO). This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET is thus 180 degrees out of phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the VCO input. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the VCO input. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage at the VCO input is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the internal filter capacitor, CLP , holds the voltage at the VCO input. Note that the LTC3858-1 can only be synchronized to an external clock whose frequency is within range of the LTC3858-1’s internal VCO, which is nominally 55kHz to 1MHz. This is guaranteed to be between 75kHz and 850kHz. 1000 900 800 FREQUENCY (kHz) 700 600 500 400 300 200 100 0 15 25 35 45 55 65 75 85 95 105 115 125 FREQ PIN RESISTOR (k ) 38581 F09 Figure 9. Relationship Between Oscillator Frequency and Resistor Value at the FREQ Pin Typically, the external clock (on the PLLIN/MODE pin) input high threshold is 1.6V, while the input low threshold is 1.1V. Rapid phase locking can be achieved by using the FREQ pin to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased at a frequency corresponding to the frequency set by the FREQ pin. Once prebiased, the PLL only needs to adjust the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks. Table 2 summarizes the different states in which the FREQ pin can be used. Table 2 FREQ PIN 0V INTVCC Resistor Any of the Above PLLIN/MODE PIN DC Voltage DC Voltage DC Voltage External Clock FREQUENCY 350kHz 535kHz 50kHz–900kHz Phase–Locked to External Clock 38581fb  LTC3858-1 applicaTions inForMaTion Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC3858-1 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN f 1. The VIN current is the DC input supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of 38581fb  LTC3858-1 applicaTions inForMaTion CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Design Example As a design example for one channel, assume VIN = 12V(nominal), VIN = 22V (max), VOUT = 3.3V, IMAX = 6A, VSENSE(MAX) = 50mV and f = 350kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the FREQ pin to GND, generating 350kHz operation. The minimum inductance for 30% ripple current is: ΔIL = VOUT  VOUT  1–  ( f) (L)  VIN  The power dissipation on the topside MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual MOSFET . At results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF maximum input voltage with T(estimated) = 50°C: PMAIN = 2 3.3V 6A 1+ 0.005 50°C – 25°C    22V 2 6A 2.5Ω 215pF • 0.035Ω + 22V 2  1 1  5V – 2.3V + 2.3V  350kHz = 433mW   () ( )( ) ( )( ) ( )( ) ( ) A short-circuit to ground will result in a folded back current of: 25mV 1  95ns 22V  ISC = –  = 3.9A 0.006Ω 2  3.9µH  with a typical value of RDS(ON) and δ = (0.005/°C)(25°C) = 0.125. The resulting power dissipated in the bottom MOSFET is: P = 3.9A SYNC ( ) A 3.9µH inductor will produce 29% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 6.88A. Increasing the ripple current will also help ensure that the minimum on-time of 95ns is not violated. The minimum on-time occurs at maximum VIN: V 3.3V tON(MIN) = OUT = = 429ns 22V 350kHz VIN f ( )2 (1.125)(0.022Ω) = 376mW which is less than full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02Ω for low output ripple voltage. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR(∆IL) = 0.02Ω(1.75A) = 35mVP-P () ( ) The equivalent RSENSE resistor value can be calculated by using the minimum value for the maximum current sense threshold (43mV): RSENSE 43mV ≤ = 0.006Ω 6.88A Choosing 0.5% resistors: RA = 24.9k and RB = 77.7k yields an output voltage of 3.296V. 38581fb  LTC3858-1 applicaTions inForMaTion PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 10. Figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs MTOP1 and MTOP2 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Do the LTC3858-1 VFB pins’ resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposites channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3858-1 and occupy minimum PC trace area. 7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging Start with one controller on at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due 38581fb  LTC3858-1 applicaTions inForMaTion SS1 LTC3858-1 ITH1 VFB1 SENSE1+ SENSE1– FREQ PGOOD1 TG1 SW1 CB1 BOOST1 BG1 fIN PLLIN/MODE RUN1 RUN2 SGND SENSE2– SENSE2+ VFB2 ITH2 SS2 VIN PGND EXTVCC INTVCC BG2 BOOST2 SW2 TG2 L2 CB2 RSENSE VOUT2 VOUT1 1µF CERAMIC COUT1 M1 M2 D1 RPU1 PGOOD1 VPULL-UP (