LTC4006

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LTC4006 4A, High Efficiency, Standalone Li-Ion Battery Charger DESCRIPTIO The LTC®4006 is a complete constant-current/constantvoltage charger controller for 2-, 3- or 4-cell lithium batteries in a small package using few external components. The PWM controller is a synchronous, quasi-constant frequency, constant off-time architecture that will not generate audible noise even when using ceramic capacitors. The LTC4006 is available in 8.4V, 12.6V and 16.8V versions with ±0.8% voltage accuracy. Charging current is programmable with a single sense resistor to ±4% typical accuracy. Charging current can be monitored as a representative voltage at the IMON pin. A timer, programmed by an external resistor, sets the total charge time or is reset to 25% of total charge time after C/10 charging current is reached. Charging automatically resumes when the cell voltage falls below 3.9V/cell. Fully discharged cells are automatically trickle charged at 10% of the programmed current until the cell voltage exceeds 2.5V/cell. Charging terminates if the low-battery condition persists for more than 25% of the total charge time. The LTC4006 includes a thermistor sensor input that suspends charging if an unsafe temperature condition is detected and automatically resumes charging when the battery temperature returns to within safe limits. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5723970. Complete Charger Controller for 2-, 3- or 4-Cell Lithium-Ion Batteries High Conversion Efficiency: Up to 96% Output Currents Exceeding 4A ±0.8% Accurate Preset Voltages: 8.4V, 12.6V, 16.8V Built-In Charge Termination with Automatic Restart AC Adapter Current Limiting Maximizes Charge Rate* Automatic Conditioning of Deeply Discharged Batteries Thermistor Input for Temperature Qualified Charging Wide Input Voltage Range: 6V to 28V 0.5V Dropout Voltage; Maximum Duty Cycle: 98% Programmable Charge Current: ±4% Accuracy Indicator Outputs for Charging, C/10 Current Detection and AC Adapter Present Charging Current Monitor Output 16-Pin Narrow SSOP Package APPLICATIO S ■ ■ ■ ■ Notebook Computers Portable Instruments Battery-Backup Systems Standalone Li-Ion Chargers TYPICAL APPLICATIO DCIN 0V TO 28V 3A VLOGIC 4A Li-Ion Battery Charger INPUT SWITCH 0.1µF 100k DCIN CHG INFET LTC4006 CLP CLN TGATE BGATE PGND CSP BAT 4006 TA01 5k 15nF 0.033Ω TO SYSTEM LOAD 20µF 10µH 0.025Ω BATTERY 20µF CHG ACP CHARGING CURRENT MONITOR ACP/SHDN 32.4k 0.0047µF IMON NTC RT ITH 6k 0.12µF GND THERMISTOR 10k NTC 0.47µF 309k TIMING RESISTOR (~2 HOURS) U U U 4006fa 1 LTC4006 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW DCIN CHG ACP/SHDN RT GND NTC ITH IMON 1 2 3 4 5 6 7 8 16 INFET 15 BGATE 14 PGND 13 TGATE 12 CLN 11 CLP 10 BAT 9 CSP Voltage from DCIN, CLP, CLN, TGATE, INFET, ACP/SHDN, CHG to GND ....................... + 32V to – 0.3V Voltage from CLP to CLN ..................................... ±0.3V CSP, BAT to GND ................................... +28V to – 0.3V RT to GND ................................................. +7V to – 0.3V NTC ........................................................ +10V to – 0.3V Operating Ambient Temperature Range (Note 4) ............................................. – 40°C to 85°C Operating Junction Temperature ......... – 40°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC4006EGN-2 LTC4006EGN-4 LTC4006EGN-6 GN PART MARKING 40062 40064 40066 GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL IDCIN VTOL PARAMETER DCIN Operating Range DCIN Operating Current Voltage Accuracy The ● denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted. CONDITIONS Sum of Current from CLP, CLN, DCIN (Note 2) LTC4006-6 LTC4006-6 LTC4006-2 LTC4006-2 LTC4006-4 LTC4006-4 VCSP – VBAT Target = 100mV VBAT = 11.5V (LTC4006-2) VBAT = 7.6V (LTC4006-6) VBAT = 12V (LTC4006-4) VBAT < 6V, VCSP – VBAT Target = 10mV 6V ≤ VBAT ≤ VLOBAT, VCSP – VBAT Target = 10mV TTOL Shutdown Battery Leakage Current DCIN = 0V DCIN = 0V DCIN = 20V, VSHDN = 0V, VBAT = 12V DCIN Rising, VBAT = 0V VSHDN = 0V, Sum of Current from CLP, CLN, DCIN ● ● ● ● MIN 6 TYP 3 MAX 28 5 8.467 8.484 12.700 12.726 16.935 16.968 4 5 UNITS V mA V V V V V V % % ● ● ● ● 8.333 8.316 12.499 12.474 16.665 16.632 –4 –5 8.4 8.4 12.6 12.6 16.8 16.8 ITOL Current Accuracy (Note 3) – 60 – 40 ● 60 40 15 20 25 0 4.7 2 35 45 10 5.5 2.5 3 Termination Timer Accuracy RRT = 270k –15 –10 4.2 1 UVLO Undervoltage Lockout Threshold Shutdown Threshold at ACP/SHDN DCIN Current in Shutdown Current Sense Amplifier, CA1 Input Bias Current Into BAT Pin CMSL CMSH CA1/I1 Input Common Mode Low CA1/I1 Input Common Mode High ● ● 11.67 0 VCLN – 0.2 2 U W U U WW W % % % µA µA µA V V mA µA V V 4006fa LTC4006 ELECTRICAL CHARACTERISTICS SYMBOL ITMAX ITREV PARAMETER Maximum Current Sense Threshold (VCSP – VBAT) Reverse Current Threshold (VCSP – VBAT) Transconductance Source Current Sink Current Current Limit Amplifier Transconductance VCLP ICLP Current Limit Threshold CLP Input Bias Current Transconductance Sink Current OVSD Overvoltage Shutdown Threshold as a Percent of Programmed Charger Voltage DCIN Detection Threshold (VDCIN – VCLN) Forward Regulation Voltage (VDCIN – VCLN) Reverse Voltage Turn-Off Voltage (VDCIN – VCLN) INFET “On” Clamping Voltage (VDCIN – VINFET) INFET “Off” Clamping Voltage (VDCIN – VINFET) Thermistor NTCVR Reference Voltage During Sample Time High Threshold Low Threshold Thermistor Disable Current Indicator Outputs (ACP/SHDN, CHG) C10TOL LBTOL C/10 Indicator Accuracy LOBAT Threshold Accuracy Current Comparators ICMP and IREV The ● denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted. CONDITIONS VITH = 2.5V ● MIN 140 TYP 165 – 30 1 MAX 200 UNITS mV mV mmho µA µA mmho Current Sense Amplifier, CA2 Measured at ITH, VITH = 1.4V Measured at ITH, VITH = 1.4V – 40 40 1.5 ● 93 100 100 1 107 mV nA mmho µA Voltage Error Amplifier, EA Measured at ITH, VITH = 1.4V ● 36 102 107 110 % Input P-Channel FET Driver (INFET) DCIN Voltage Ramping Up from VCLN – 0.1V DCIN Voltage Ramping Down IINFET = 1µA IINFET = – 25µA 4.5 VNTC Rising VNTC Falling VNTC ≤ 10V Voltage Falling at PROG LTC4006-6 LTC4006-2 LTC4006-4 LTC4006-6 LTC4006-2 LTC4006-4 IOL = 100µA IOH = –1µA V = 0V VOH = 3V VOH = 3V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● 0 0.17 25 0.25 50 6.5 0.25 V mV mV V V V – 60 5 – 25 5.8 NTCVR • 0.48 NTCVR • 0.115 NTCVR • 0.5 NTCVR • 0.125 NTCVR • 0.52 NTCVR • 0.135 10 V V µA V V V V V V V V V µA 0.375 4.70 7.27 9.70 7.5 11.35 15.15 2.7 0.400 4.93 7.5 10 7.8 11.7 15.6 0.425 5.14 7.71 10.28 7.96 11.94 15.92 0.5 RESTART Threshold Accuracy VOL VOH IPO IC10 IOFF Low Logic Level of ACP/SHDN, CHG High Logic Level of ACP/SHDN Pull-Up Current on ACP/SHDN C/10 Indicator Sink Current from CHG Off State Leakage Current of CHG Timer Defeat Threshold at CHG –10 15 –1 1 25 38 1 µA µA V 4006fa 3 LTC4006 ELECTRICAL CHARACTERISTICS SYMBOL Oscillator fOSC fMIN DCMAX Regulator Switching Frequency Regulator Switching Frequency in Drop Out Regulator Maximum Duty Cycle VTGATE High (VCLN – VTGATE) VBGATE High VTGATE Low (VCLN – VTGATE) VBGATE Low TGTR TGTF BGTR BGTF TGATE Transition Time TGATE Rise Time TGATE Fall Time BGATE Transition Time BGATE Rise Time BGATE Fall Time VTGATE at Shutdown (VCLN – VTGATE) VBGATE at Shutdown PARAMETER The ● denotes specifications which apply over the full operating temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted. CONDITIONS MIN 255 Duty Cycle ≥ 98% VCSP = VBAT ITGATE = – 1mA CLOAD = 3000pF CLOAD = 3000pF IBGATE = 1mA CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% CLOAD = 3000pF, 10% to 90% ITGATE = –1µA, DCIN = 0V, CLN = 12V IBGATE = 1µA, DCIN = 0V, CLN = 12V 50 50 40 40 4.5 4.5 5.6 5.6 20 98 TYP 300 25 99 50 10 10 50 110 100 90 80 100 100 MAX 345 UNITS kHz kHz % mV V V mV ns ns ns ns mV mV Gate Drivers (TGATE, BGATE) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: See Test Circuit Note 3: Does not include tolerance of current sense resistor. Note 4: The LTC4006E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. TYPICAL PERFOR A CE CHARACTERISTICS INFET Response Time to Reverse Current Vgs OF PFET (2V/DIV) Vgs = 0 OUTPUT VOLTAGE ERROR (%) 0 –0.5 –1.0 PWM FREQUENCY (kHz) –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 DCIN = 20V VBAT = 12.6V –5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT CURRENT (A) 4006 G02 Vs OF PFET (5V/DIV) Vs = 0V Id (REVERSE) OF PFET (5A/DIV) Id = 0A 1.25µs/DIV TEST PERFORMED ON DEMOBOARD LTC4006-2 VIN = 15VDC CHARGER = ON INFET = 1/2 Si4925DY ICHARGE = BAT >BAT >BAT >BAT >BAT >BAT BAT VOLTAGE >UVLO 2.5V/Cell >2.5V/Cell X X T/4 Stopped T/4 After C/10 Comparator Trip. Stopped >T Stopped CHG* HIGH LOW LOW LOW LOW or 25µA (Faulted) HIGH HIGH (Faulted) 25µA Timer is Reset by C/10 Comparator (Latched), then Terminates After 1/4 T Terminated by Expired Timer Timer Defeated. (Low-Battery Conditioning Still Functional) Shut Down by Undervoltage Lockout Timer Defeated Until VBAT > 3.9V/Cell *Open Drain. High when used with pull-up resistor. **Most probable condition, X = Don’t care compares this current against the desired current programmed by RIMON at the IMON pin and adjusts ITH until: VREF V –V + 11.67µA • 3kΩ = CSP BAT RIMON 3kΩ therefore, ⎛V ⎞ 3kΩ ICHARGE = ⎜ REF – 11.67µA⎟ • ⎝ RIMON ⎠ RSENSE The voltage at BAT is divided down by an internal resistor divider and is used by error amp EA to decrease ITH if the divider voltage is above the 1.19V reference. When the charging current begins to decrease, the voltage at IMON will decrease in direct proportion. The voltage at IMON is then given by: R VIMON = (ICHARGE • RSENSE + 11.67µA • 3kΩ) • IMON 3kΩ VIMON (V) U >BAT VFLOAT OFF HIGH >BAT VFLOAT** OFF HIGH X >BAT and BAT X BAT and BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT >BAT 2.5V/Cell >2.5V/Cell T/4 then Reset LOW or 25µA (Faulted) HIGH HIGH (Faulted) HIGH HIGH Running Running Ignored Paused >T/4 Reset Running Ignored Reset Running Reset Running LOW 25µA 25µA Forced LOW LOW LOW LOW Forced LOW LOW (Faulted) HIGH (Faulted) HIGH LTC4006: State Diagram (Supplemental) MASTER SHUTDOWN 2 1 ANY SHUTDOWN 4 3, 8, 9, 10 3, 18, 19, 20, 21, 22 13 5, 6, 7 CONDITION 11 CHARGE 12, 14, 15, 16, 17 4006 F15 4006fa LTC4006 OPERATIO be inhibited if it is not already active. If the charging current decreases below 10% to 15% of programmed current, while engaged in input current limiting, BGATE will be forced low to prevent the charger from discharging the battery. Audible noise can occur in this mode of operation. An overvoltage comparator guards against voltage transient overshoots (>7% of programmed value). In this case, both MOSFETs are turned off until the overvoltage condition is cleared. This feature is useful for batteries which “load dump” themselves by opening their protection switch to perform functions such as calibration or pulse mode charging. As the voltage at BAT increases to near the input voltage at DCIN, the converter will attempt to turn on the top MOSFET continuously (“dropout’’). A watchdog timer detects this condition and forces the top MOSFET to turn off for about 300ns at 40µs intervals. This is done to prevent audible noise when using ceramic capacitors at the input and output. Charger Startup When the charger is enabled, it will not begin switching until the ITH voltage exceeds a threshold that assures initial current will be positive. This threshold is 5% to 15% of the maximum programmed current. After the charger begins switching, the various loops will control the current at a level that is higher or lower than the initial current. The duration of this transient condition depends upon the loop compensation but is typically less than 100µs. Thermistor Detection The thermistor detection circuit is shown in Figure 3. It requires an external resistor and capacitor in order to function properly. The thermistor detector performs a sample-and-hold function. An internal clock, whose frequency is determined by the timing resistor connected to RT, keeps switch S1 closed to sample the thermistor: tSAMPLE = 127.5 • 20 • RRT • 17.5pF = 13.8ms, for RRT = 309k The external RC network is driven to approximately 4.5V and settles to a final value across the thermistor of: VNTC COMPARATOR LOW LIMIT 4006 F04 VRTH(FINAL) 4.5V • RTH = RTH + R9 U LTC4006 CLK R9 32.4k 6 RTH 10k NTC C7 0.47µF – NTC S1 + ~4.5V 60k + – – + 15k D C 4006 F03 45k Q TBAD Figure 3 This voltage is stored by C7. Then the switch is opened for a short period of time to read the voltage across the thermistor. tHOLD = 10 • RRT • 17.5pF = 54µs, for RRT = 309k When the tHOLD interval ends the result of the thermistor testing is stored in the D flip-flop (DFF). If the voltage at NTC is within the limits provided by the resistor divider feeding the comparators, then the NOR gate output will be low and the DFF will set TBAD to zero and charging will continue. If the voltage at NTC is outside of the resistor divider limits, then the DFF will set TBAD to one, the charger will be shut down, and the timer will be suspended until TBAD returns to zero (see Figure 4). CLK (NOT TO SCALE) tHOLD tSAMPLE VOLTAGE ACROSS THERMISTOR COMPARATOR HIGH LIMIT Figure 4 4006fa 11 LTC4006 APPLICATIO S I FOR ATIO Charger Current Programming The basic formula for charging current is: ICHARGE(MAX) 100mV = RSENSE tTIMER (MINUTES) Table 3. Recommended RSENSE Resistor Values IMAX (A) 1.0 2.0 3.0 4.0 RSENSE (Ω) 1% 0.100 0.050 0.033 0.025 RSENSE (W) 0.25 0.25 0.5 0.5 Setting the Timer Resistor The charger termination timer is designed for a range of 1 hour to 3 hours with a ±15% uncertainty. The timer is programmed by the resistor RRT using the following equation: tTIMER = 10 • 227 • RRT • 17.5pF (Refer to Figure 5) (seconds) It is important to keep the parasitic capacitance on the RT pin to a minimum. The trace connecting RT to RRT should be as short as possible. CHG Status Output Pin When the charge cycle starts, the CHG pin is pulled down to ground by an internal N-channel MOSFET that can drive more than 100µA. When the charge current drops to 10% of the full-scale current (C/10), the N-channel MOSFET is turned off and a weak 25µA current source to ground is connected to the CHG pin. After a time out occurs, the pin will go into a high impedance state. By using two different value pull-up resistors, a microprocessor can detect three states from this pin (charging, C/10 and stop charging). See Figure 6. Battery Detection It is generally not good practice to connect a battery while the charger is running. The timer is in an unknown state and the charger could provide a large surge current into the battery for a brief time. The circuit shown in Figure 7 keeps the charger shut down and the timer reset while a battery is not connected. 12 U Alternatively, a normally closed switch can be used to detect when the battery is present (see Figure 8). 200 180 160 140 120 100 80 60 40 20 0 100 150 200 250 300 350 400 450 500 RRT (kΩ) 4006 F05 W UU Figure 5. tTIMER vs RRT 3.3V LTC4006 CHG 2 200k 33k VDD µP OUT IN 4006 F06 Figure 6. Microprocessor Interface ADAPTER POWER 470k LTC4006 1 DCIN 3 ACP/SHDN 4006 F07 SWITCH CLOSED IF BATTERY CONNECTED Figure 7 ADAPTER POWER LTC4006 1 DCIN 3 ACP/SHDN 4006 F08 SWITCH OPEN WHEN BATTERY CONNECTED Figure 8 4006fa LTC4006 APPLICATIO S I FOR ATIO Soft-Start The LTC4006 is soft started by the 0.12µF capacitor on the ITH pin. On start-up, ITH pin voltage will rise quickly to 0.5V, then ramp up at a rate set by the internal 40µA pull-up current and the external capacitor. Battery charging current starts ramping up when ITH voltage reaches 0.8V and full current is achieved with ITH at 2V. With a 0.12µF capacitor, time to reach full charge current is about 2ms and it is assumed that input voltage to the charger will reach full value in less than 2ms. The capacitor can be increased up to 1µF if longer input start-up times are needed. Input and Output Capacitors The input capacitor (C2) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current. Actual capacitance value is not critical. Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass. High input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. Only Kemet T495 series of “Surge Robust” low ESR tantalums are rated for high surge conditions such as battery to ground. The relatively high ESR of an aluminum electrolytic for C1, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Refer to Application Note 88 for more information. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20µF) from Tokin, United Chemi-Con/Marcon, et al. Other alternative capacitors include OS-CON capacitors from Sanyo. The output capacitor (C3) is also assumed to absorb output switching current ripple. The general formula for capacitor current is: U IRMS ⎛ ⎞ V 0.29(VBAT )⎜ 1 – BAT ⎟ ⎝ VDCIN ⎠ = (L1)( f) For example: VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and f = 300kHz, IRMS = 0.41A. EMI considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2Ω and the battery impedance is raised to 4Ω with a bead or inductor, only 5% of the current ripple will flow in the battery. Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition, the effect of inductor value on ripple current and low current operation must also be considered. The inductor ripple current ∆IL decreases with higher frequency and increases with higher VIN. ∆IL = ⎛V⎞ 1 VOUT ⎜ 1– OUT ⎟ ( f)(L) ⎝ VIN ⎠ W UU Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.4(IMAX). In no case should ∆IL exceed 0.6(IMAX) due to limits imposed by IREV and CA1. Remember the maximum ∆IL occurs at the maximum input voltage. In practice 10µH is the lowest value recommended for use. Lower charger currents generally call for larger inductor values. Use Table 4 as a guide for selecting the correct inductor value for your application. 4006fa 13 LTC4006 APPLICATIO S I FOR ATIO Table 4 MAXIMUM AVERAGE CURRENT (A) 1 1 2 2 3 3 4 4 INPUT VOLTAGE (V) ≤ 20 > 20 ≤ 20 > 20 ≤ 20 > 20 ≤ 20 > 20 MINIMUM INDUCTOR VALUE (µH) 40 ± 20% 56 ± 20% 20 ± 20% 30 ± 20% 15 ± 20% 20 ± 20% 10 ± 20% 15 ± 20% Charger Switching Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with the charger: a P-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set internally. This voltage is typically 6V. Consequently, logic-level threshold MOSFETs must be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), total gate capacitance QG, reverse transfer capacitance CRSS, input voltage and maximum output current. The charger is operating in continuous mode at moderate to high currents so the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT/VIN Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN. The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT/VIN(I2MAX)(1 + δ∆T)RDS(ON) + k(V2IN)(IMAX)(CRSS)(fOSC) PSYNC = (VIN – VOUT)/VIN(I2MAX)(1 + δ∆T)RDS(ON) Where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the PMAIN equation includes an additional term for transition losses, which are 14 U highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. The term (1 + δ∆T) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics; if not, then CRSS can be calculated using CRSS = QGD/∆VDS. The constant k = 2 can be used to estimate the contributions of the two terms in the main switch dissipation equation. If the charger is to operate in low dropout mode or with a high duty cycle greater than 85%, then the topside P-channel efficiency generally improves with a larger MOSFET. Using asymmetrical MOSFETs may achieve cost savings or efficiency gains. The Schottky diode D1, shown in the Typical Application on the back page, conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 4A regulators due to the relatively small average current. Larger diodes can result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. Calculating IC Power Dissipation The power dissipation of the LTC4006 is dependent upon the gate charge of the top and bottom MOSFETs (QG1 and QG2 respectively). The gate charge is determined from the manufacturer’s data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the MOSFET. Use 6V for the gate voltage swing and VDCIN for the drain voltage swing. PD = VDCIN • (fOSC (QG1 + QG2) + IDCIN) 4006fa W UU LTC4006 APPLICATIO S I FOR ATIO Example: VDCIN = 19V, fOSC = 345kHz, QG1 = QG2 = 15nC. PD = 292mW IDCIN = 5mA Adapter Limiting An important feature of the LTC4006 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being charged without complex load management algorithms. Additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. True analog control is used, with closed-loop feedback ensuring that adapter load current remains within limits. Amplifier CL1 in Figure 9 senses the voltage across RCL, connected LTC4006 100mV – CL1 + CLP 11 15nF 5k AC ADAPTER INPUT VIN + CLN 12 100mV ADAPTER CURRENT LIMIT RCL* + CIN *RCL = TO SYSTEM LOAD 4006 F09 Figure 9. Adapter Current Limiting Table 5. Common RCL Resistor Values ADAPTER RATING (A) 1.5 1.8 2.0 2.3 2.5 2.7 3.0 3.3 3.6 4.0 –7% ADAPTER RATING (A) 1.40 1.67 1.86 2.14 2.33 2.51 2.79 3.07 3.35 3.72 RCL VALUE* (Ω) 1% 0.068 0.062 0.051 0.047 0.043 0.039 0.036 0.033 0.030 0.027 RCL LIMIT (A) 1.47 1.61 1.96 2.13 2.33 2.56 2.79 3.07 3.35 3.72 RCL POWER DISSIPATION (W) 0.15 0.16 0.20 0.21 0.23 0.26 0.28 0.31 0.33 0.37 RCL POWER RATING (W) 0.25 0.25 0.25 0.25 0.50 0.50 0.50 0.50 0.50 0.50 4006fa * Rounded to nearest 5% standard step value. Many non-standard values are popular. U between the CLP and DCIN pins. When this voltage exceeds 100mV, the amplifier will override programmed charging current to limit adapter current to 100mV/RCL. A lowpass filter formed by 5kΩ and 15nF is required to eliminate switching noise. If the current limit is not used, CLP should be connected to CLN. Setting Input Current Limit To set the input current limit, you need to know the minimum wall adapter current rating. Subtract 7% for the input current limit tolerance and use that current to determine the resistor value. RCL = 100mV/ILIM ILIM = Adapter Min Current – (Adapter Min Current • 7%) As is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see Figure 9). Designing the Thermistor Network There are several networks that will yield the desired function of voltage vs temperature needed for proper operation of the thermistor. The simplest of these is the voltage divider shown in Figure 10. Unfortunately, since the HIGH/LOW comparator thresholds are fixed internally, there is only one thermistor type that can be used in this network; the thermistor must have a HIGH/LOW resistance ratio of 1:7. If this happy circumstance is true for W UU 15 LTC4006 APPLICATIO S I FOR ATIO LTC4006 NTC 6 C7 RTH 4006 F10 R9 Figure 10. Voltage Divider Thermistor Network you, then simply set R9 = RTH(LOW) If you are using a thermistor that doesn’t have a 1:7 HIGH/ LOW ratio, or you wish to set the HIGH/LOW limits to different temperatures, then the more generic network in Figure 11 should work. Once the thermistor, RTH, has been selected and the thermistor value is known at the temperature limits, then resistors R9 and R9A are given by: For NTC thermistors: R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – RTH(HIGH)) R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – 7 • RTH(HIGH)) where RTH(LOW) > 7 • RTH(HIGH) For PTC thermistors: R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – RTH(LOW)) R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – 7 • RTH(LOW)) where RTH(HIGH) > 7RTH(LOW) Example #1: 10kΩ NTC with custom limits TLOW = 0°C, THIGH = 50°C RTH = 10k at 25°C, RTH(LOW) = 32.582k at 0°C RTH(HIGH) = 3.635k at 50°C R9 = 24.55k → 24.3k (nearest 1% value) R9A = 99.6k → 100k (nearest 1% value) Example #2: 100kΩ NTC TLOW = 5°C, THIGH = 50°C RTH = 100k at 25°C, RTH(LOW) = 272.05k at 5°C RTH(HIGH) = 33.195k at 50°C R9 = 226.9k → 226k (nearest 1% value) R9A = 1.365M → 1.37M (nearest 1% value) Example #3: 22kΩ PTC TLOW = 0°C, THIGH = 50°C 16 U LTC4006 NTC 6 C7 R9A RTH 4006 F11 W UU R9 Figure 11. General Thermistor Network RTH = 22k at 25°C, RTH(LOW) = 6.53k at 0°C RTH(HIGH) = 61.4k at 50°C R9 = 43.9k → 44.2k (nearest 1% value) R9A = 154k Sizing the Thermistor Hold Capacitor During the hold interval, C7 must hold the voltage across the thermistor relatively constant to avoid false readings. A reasonable amount of ripple on NTC during the hold interval is about 10mV to 15mV. Therefore, the value of C7 is given by: C7 = t HOLD /(R9/7 • –ln(1 – 8 • 15mV/4.5V)) = 10 • RRT • 17.5pF/(R9/7 • – ln(1 – 8 • 15mV/4.5V) Example: R9 = 24.3k RRT = 309k (~2 hour timer) C7 = 0.57µF → 0.56µF (nearest value) Disabling the Thermistor Function If the thermistor is not needed, connecting a resistor between DCIN and NTC will disable it. The resistor should be sized to provide at least 10µA with the minimum voltage applied to DCIN and 10V at NTC. Do not exceed 30µA into NTC. Generally, a 301k resistor will work for DCIN less than 15V. A 499k resistor is recommended for DCIN between 15V and 24V. Optional Simple Battery Discharge Path Circuit It is NOT recommended that one permit battery current to flow backwards through RSENSE, inductor and out the TGATE MOSFET internal diode to reach VOUT. The TGATE MOSFET is off when VIN < VBAT. Figure 12 shows an optional high efficiency discharge path for the battery such that VOUT power comes from lossless “diode or” of VIN and VBAT. Normally when VIN > VBAT, P-channel MOSFET Q1B VGS = 4006fa LTC4006 APPLICATIO S I FOR ATIO 100k VIN Q1A ZENER 18V TGATE INDUCTOR RSENSE VBAT Q1B 4006 F12 Figure 12. Optional Simple High Efficiency Battery Discharge Path 0V keeping Q1B in the off state while P-channel MOSFET Q1A is on. If VIN were to suddenly go away, Q1B internal diode will provide a passive but instant discharge path for battery current to reach VOUT and hold up the load. Q1B internal diode has the same current rating as the FET itself, but has a very high Vf of about a volt such that heat will quickly build up in Q1B if left alone. However as VIN’s voltage falls below VBAT by Q1B’s VGS threshold, Q1B will then turn on shorting out its internal diode removing both the heat and voltage losses created by the diode. When VIN falls to zero volts, Q1B gate will be driven to the same voltage as VBAT providing the lowest possible RDSON value. A zener diode along with a 100k resistor in series with the Q1B gate protects the gate from any hazardous voltage spikes that can exceed Q1B maximum permissible VGS voltage. The zener voltage rating must be less than Q1B VGS(MAX) voltage but greater than VBAT. Since Q1A and Q1B are always at opposite states and share the same load, it is often advantagous to combine both FETs into a single package and save PCB space. The PD rate of the FET that is on is enhanced when the other FET is off. The choice of a combined Q1 should take into account the highest load current conditions of both paths and choose whichever is greater as the driving force behind the MOSFET U selection. If the VIN supply is going to collapse very slowly such that Q1B is not turned on quickly enough for the given load and stay within its PD limits, you should install a suitable Schottky diode in parallel with Q1B. PCB Layout Considerations VOUT W UU For maximum efficiency, the switch node rise and fall times should be minimized. To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential. (See Figure 13.) Here is a PCB layout priority list for proper layout. Layout the PCB using this specific order. 1. Input capacitors need to be placed as close as possible to switching FET’s supply and ground connections. Shortest copper trace connections possible. These parts must be on the same layer of copper. Vias must not be used to make this connection. 2. The control IC needs to be close to the switching FET’s gate terminals. Keep the gate drive signals short for a clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB relative to above. 3. Place inductor input as close as possible to switching FET’s output connection. Minimize the surface area of this trace. Make the trace width the minimum amount needed to support current—no copper fills or pours. Avoid running the connection using multiple layers in parallel. Minimize capacitance from this node to any other trace or plane. SWITCH NODE L1 VBAT HIGH FREQUENCY CIRCULATING PATH VIN C2 D1 C3 BAT 4006 F13 Figure 13. High Speed Switching Path 4006fa 17 LTC4006 APPLICATIO S I FOR ATIO 4. Place the output current sense resistor right next to the inductor output but oriented such that the IC’s current sense feedback traces going to resistor are not long. The feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. Locate any filter component on these traces next to the IC and not at the sense resistor location. 5. Place output capacitors next to the sense resistor output and ground. 6. Output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. General Rules 7. Connection of switching ground to system ground or internal ground plane should be single point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. Figure 14. Kelvin Sensing of Charging Current 18 U 8. Route analog ground as a trace tied back to IC ground (analog ground pin if present) before connecting to any other ground. Avoid using the system ground plane. CAD trick: make analog ground a separate ground net and use a 0Ω resistor to tie analog ground to system ground. 9. A good rule of thumb for via count for a given high current path is to use 0.5A per via. Be consistent. 10. If possible, place all the parts listed above on the same PCB layer. 11. Copper fills or pours are good for all power connections except as noted above in Rule 3. You can also use copper planes on multiple layers in parallel too—this helps with thermal management and lower trace inductance improving EMI performance further. 12. For best current programming accuracy provide a Kelvin connection from RSENSE to CSP and BAT. See Figure 13 as an example. It is important to keep the parasitic capacitance on the RT, CSP and BAT pins to a minimum. The traces connecting these pins to their respective resistors should be as short as possible. DIRECTION OF CHARGING CURRENT RSNS 4006 F14 W UU CSP BAT 4006fa LTC4006 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT 1 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0250 BSC .015 ± .004 × 45° (0.38 ± 0.10) 0° – 8° TYP .0532 – .0688 (1.35 – 1.75) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 4006fa 19 LTC4006 TYPICAL APPLICATIO DCIN 0V TO 20V 2.5A VLOGIC R3 100k CHG ACP CHARGING CURRENT MONITOR R9 32.4k THERMISTOR 10k NTC C5 0.0047µF C7 0.47µF RT 309k TIMING RESISTOR (~2 HOURS) RELATED PARTS PART NUMBER LT1511 LT1513 LTC1709 LTC1760/ LTC1960 LTC1778 LTC3711 LTC3728 LTC4002 LTC4007 LTC4008 DESCRIPTION 3A Constant-Current/Constant-Voltage Battery Charger SEPIC Constant- or Programmable-Current/ConstantVoltage Battery Charger 2-Phase, Dual Synchronous Step-Down Controller with VID Dual Battery Charger/Selector Wide Operating Range, No RSENSETM Synchronous Step-Down Controller No RSENSE Synchronous Step-Down Controller with VID 2-Phase, Dual Synchronous Step-Down Controller Li-Ion Battery Charger Controller High Efficiency, Programmable Voltage, Battery Charger with Termination High Efficiency, Programmable Voltage/Current Battery Charger Smart Battery Charger Controller PowerPathTM Ideal Diode or Controller COMMENTS High Efficiency, Minimum External Components to Fast Charge Lithium, NIMH and NiCd Batteries Charger Input Voltage May be Higher, Equal to or Lower Than Battery Voltage, 500kHz Switching Frequency Up to 42A Output, Minimum CIN and COUT, Uses Smallest Components for Intel and AMD Processors Simultaneous Charge or Discharge of Two Batteries, DAC Programmable Current and Voltage, Input Current Limiting Maximizes Charge Current 2% to 90% Duty Cycle at 200kHz, Stable with Ceramic COUT 3.5V ≤ VIN ≤ 36V, 0.925V ≤ VOUT ≤ 2V, for Transmeta, AMD and Intel Mobile Processors Minimizes CIN and COUT, Power Good Output, 3.5V ≤ VIN ≤ 36V 1- and 2-Cell Li-Ion Batteries, VIN ≤ 22V, 500kHz Switching Frequency, 3hr Charge Termination, IOUT ≤ 4A Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit, Thermistor Sensor and Indicator Outputs Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage/ Current Programming, AC Adapter Current Limit and Thermistor Sensor and Indicator Outputs SMBus (Rev 1.1) Compliant, 6.4V ≤ VIN ≤ 26V, SMBus Accelerator Minimizes Bus Errors Very Low Loss Replacement for OR’ing Diodes LTC4100 LTC4412 No RSENSE and PowerPath are trademarks of Linear Technology Corporation. 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U 2A Li-Ion Battery Charger Q3 INPUT SWITCH C1 0.1µF 1 2 3 8 6 4 7 R4 6.04k C6 0.12µF 5 16 INFET LTC4006 11 CHG CLP 12 CLN ACP/SHDN 13 TGATE IMON 15 BGATE NTC 14 PGND RT 9 CSP ITH 10 BAT GND DCIN R1 5k C4 15nF RCL 0.04Ω TO SYSTEM LOAD C2 20µF Q1 Q2 L1 22µH 2A D1 RSENSE 0.05Ω D1: MBRM140T3 Q1, Q2: Si7501DN Q3: Si5435B BATTERY C3 20µF 4006 TA02 4006fa LT 0506 REV A • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003