LTC4012CUF-2PBF

FEATURES n n n n n n n n n n n n n LTC4012/ LTC4012-1/LTC4012-2 High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control DESCRIPTION The LTC4012 is a constant-current/constant-voltage battery charger controller. It uses a synchronous quasi-constant frequency PWM control architecture that will not generate audible noise with ceramic bulk capacitors. Charge current is set by external resistors and can be monitored as an output voltage. With no built-in termination, the LTC4012 family charges a wide range of batteries under external control. The LTC4012 features fully adjustable output voltage, while the LTC4012-1 and LTC4012-2 can be pin-programmed for Lithium-Ion/Polymer battery packs of 1-, 2-, 3- or 4-series cells. The LTC4012-1 provides output voltage of 4.1V/cell and the LTC4012-2 is a 4.2V/cell version. The device includes AC adapter input current limiting, which maximizes charge rate for a fixed input power level. An external sense resistor programs the input current limit, and the ICL status pin indicates reduced charge current as a result of AC adapter current limiting. Ideal diode control at the adaptor input improves charger efficiency. The CHRG status pin is active during all charging modes, including special indication for low charge current. General Purpose Battery Charger Controller Efficient 550kHz Synchronous Buck PWM Topology ±0.5% Output Float Voltage Accuracy Programmable Charge Current: 4% Accuracy Programmable AC Adapter Current Limit: 3% Accuracy No Audible Noise with Ceramic Capacitors INFET Low Loss Ideal Diode PowerPath™ Control Wide Input Voltage Range: 6V to 28V Wide Output Voltage Range: 2V to 28V Indicator Outputs for AC Adapter Present, Charging, C/10 Current Detection and Input Current Limiting Analog Charge Current Monitor Micropower Shutdown 20-Pin 4mm × 4mm × 0.75mm QFN Package APPLICATIONS n n n Notebook Computers Portable Instruments Battery Backup Systems L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5723970. TYPICAL APPLICATION FROM ADAPTER 13V TO 28V INFET DCIN 0.1μF ACP TO/FROM MCU CHRG ICL SHDN ITH 6.04k 0.1μF CLP CLN BOOST TGATE SW INTVDD BGATE GND 3.01k CSP 25mΩ 0.1μF 5.1k 20μF POWER TO SYSTEM Efficiency at DCIN = 20V 100 95 EFFICIENCY (%) EFFICIENCY POWER LOSS (mW) 10000 0.1μF 90 85 80 75 70 VOUT = 12.3V RSENSE = 33mΩ RIN = 3.01k RPROG = 26.7k 0 0.5 1 1.5 2 CHARGE CURRENT (A) PIN NAME 2.5 3 100 POWER LOSS 1000 2μF 6.8μH LTC4012 CSN PROG BAT FBDIV 33mΩ 3.01k 20μF 301k 26.7k 4.7nF + VFB 32.8k 12.3V Li-Ion BATTERY 4012 TA01 PART INFET DCDIV LTC4009 X LTC4012 X 4012 TA02 4012f 1 LTC4012/ LTC4012-1/LTC4012-2 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION BOOST to SW............................................... –0.3V to 7V SHDN, FVS0, FVS1 or VFB to GND................ –0.3V to 7V ACP, CHRG or ICL to GND ......................... –0.3V to 30V Operating Temperature Range (Note 2)........................................................ 0°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range...................–65°C to 150°C LTC4012-1 LTC4012-2 TOP VIEW INTVDD BOOST BGATE 15 CSP 14 CSN 21 13 PROG 12 ITH 11 BAT 6 SHDN 7 CHRG 8 ICL 9 10 FVS0 FVS1 TGATE SW DCIN ........................................................... –14V to 30V DCIN to CLP ................................................ –32V to 20V CLP CLN or SW to GND ............................. –0.3V to 30V , CLP to CLN ............................................................±0.3V CSP CSN or BAT to GND ............................ –0.3V to 28V , CSP to CSN ............................................................±0.3V BOOST to GND ........................................... –0.3V to 36V LTC4012 BOOST TOP VIEW INTVDD BGATE TGATE SW 20 19 18 17 16 CLN 1 CLP 2 INFET 3 DCIN 4 ACP 5 6 SHDN 7 CHRG 8 ICL 9 10 VFB FBDIV 21 15 CSP 14 CSN 13 PROG 12 ITH 11 BAT CLN 1 CLP 2 INFET 3 DCIN 4 ACP 5 20 19 18 17 16 UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125°C, JA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125°C, JA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC4012CUF#PBF LTC4012CUF-1#PBF LTC4012CUF-2#PBF TAPE AND REEL LTC4012CUF#TRPBF LTC4012CUF-1#TRPBF LTC4012CUF-2#TRPBF PART MARKING 4012 40121 40122 PACKAGE DESCRIPTION 20-Lead (4mm × 4mm) Plastic QFN 20-Lead (4mm × 4mm) Plastic QFN 20-Lead (4mm × 4mm) Plastic QFN TEMPERATURE RANGE 0°C to 85°C 0°C to 85°C 0°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4012f 2 LTC4012/ LTC4012-1/LTC4012-2 ELECTRICAL CHARACTERISTICS SYMBOL VTOL PARAMETER VBAT Accuracy (See Test Circuits) Charge Voltage Regulation LTC4012 LTC4012-1/LTC4012-2 IVFB RON ILEAK-FBDIV VBOV VFB Input Bias Current FBDIV On Resistance FBDIV Output Leakage Current VFB Overvoltage Threshold BAT Overvoltage Threshold Charge Current Regulation ITOL Charge Current Accuracy with RIN = 3.01k, 6V < BAT < 18V (LTC4012) 6V < BAT < 15V (LTC4012-1, LTC4012-2) Current Sense Amplifier Gain (PROG ΔI) with RIN = 3.01k, 6V < BAT < 18V (LTC4012) 6V < BAT < 15V (LTC4012-1, LTC4012-2) Maximum Peak Current Sense Threshold Voltage per Cycle (RIN = 3.01k) C/10 Indicator Threshold Voltage Reverse Current Threshold Voltage Current Limit Threshold CLN Input Bias Current ICL Indicator Threshold Operating Voltage Range CLP Undervoltage Lockout Threshold UVLO Threshold Hysteresis CLP Operating Current AC Present Threshold Voltage ACP Threshold Hysteresis Voltage SHDN Input Voltage Low SHDN Input Voltage High SHDN Pull-Down Resistance CLP Shutdown Current BAT Leakage Current CSN Leakage Current CLP = 12V, DCIN = 0V SHDN = 0V SHDN = 0V or DCIN = 0V, 0V ≤ CSP = CSN = BAT ≤ 18V SHDN = 0V or DCIN = 0V, 0V ≤ CSP = CSN = BAT ≤ 20V l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. CONDITIONS MIN –0.5 –0.8 –0.6 –0.8 ±20 85 –1 1.235 103 0 1.281 106 190 1 1.32 109 TYP MAX 0.5 0.8 0.6 0.8 UNITS % % % % nA Ω μA V % VFB = 1.2V ILOAD = 100μA SHDN = 0V, FBDIV = 0V LTC4012 LTC4012-1/LTC4012-2, Relative to Selected Output Voltage RPROG = 26.7k VSENSE = 0mV, PROG = 1.2V VSENSE Step from 0mV to 5mV, PROG = 1.2V ITH = 2V ITH = 5V PROG Falling PROG Falling CLP – CLN CLN = CLP (CLP – CLN) – VCL –8 6 CLP Increasing CLP = 20V, No Gate Loads DCIN – BAT, DCIN Rising l l l l l –4 –5 –12.75 –1.78 –11.67 –1.66 4 5 –10.95 –1.54 % % μA μA AI VCS-MAX VC10 VREV VCL ICLN VICL CLP Supply OVR VUVLO VUV(HYST) ICLPO Shutdown VACP VACP(HYST) VIL VIH RIN ICLPS ILEAK-BAT ILEAK-CSN 140 340 180 97 96 195 325 400 253 100 100 ±100 –5 250 430 460 295 103 104 –2 28 mV mV mV mV mV mV nA mV V V mV mA mV mV mV V kΩ Input Current Regulation l 4.65 4.85 200 2 5.25 3 650 300 350 500 200 1.4 40 15 350 –1 –1 0 0 25 500 1 1 μA μA μA μA 4012f 3 LTC4012/ LTC4012-1/LTC4012-2 ELECTRICAL CHARACTERISTICS SYMBOL ILEAK-CSP ILEAK-SW PARAMETER CSP Leakage Current SW Leakage Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. CONDITIONS SHDN = 0V or DCIN = 0V, 0V ≤ CSP = CSN = BAT ≤ 20V SHDN = 0V or DCIN = 0V, 0V ≤ SW ≤ 20V No Load IDD = 20mA INTVDD = 0V ITH = 1.4V 467 CLOAD = 3.3nF CLOAD = 3.3nF CLOAD = 3.3nF, 10% – 90% CLOAD = 3.3nF, 90% – 10% CLOAD = 3.3nF, 10% – 90% CLOAD = 3.3nF, 90% – 10% CLOAD = 3.3nF, 10% – 10% 0V ≤ DCIN ≤ CLP DCIN-CLP, DCIN rising DCIN-CLP DCIN-CLP DCIN falling , DCIN-CLP = 0.1V, IINFET =1μA DCIN-CLP = –0.1V, IINFET = –5μA To CLP-INFET > 3V, CINFET = 1nF To CLP-INFET < 1.5V, CINFET = 1nF l l l l l l MIN –1 –1 TYP 0 0 MAX 1 2 UNITS μA μA INTVDD Regulator INTVDD ΔVDD IDD IITH fTYP fMIN DCMAX tR-TG tF-TG tR-BG tF-BG tNO IDCIN VFTO VFR VRTO VOL(INFET) VOH(INFET) tIF(ON) tIF(OFF) VIL VIH IIN VOL Output Voltage Load Regulation Short-Circuit Current (Note 5) ITH Current Typical Switching Frequency Minimum Switching Frequency Maximum Duty Cycle TGATE Rise Time TGATE Fall Time BGATE Rise Time BGATE Fall Time TGATE, BGATE Non-Overlap Time DCIN Input Current Forward Turn-on Voltage (DCIN Detection Threshold) Forward Regulation Voltage Reverse Turn-Off Voltage INFET Output Low Voltage, Relative to CLP INFET Output High Voltage, Relative to CLP INFET Turn-On Time INFET Turn-Off Time Input Voltage Low Input Voltage High Input Current Output Voltage Low 0V ≤ VIN ≤ 5V ILOAD = 100μA, PROG = 1.2V 3.5 –10 10 500 l 4.85 50 5 –0.4 85 –40/+90 550 25 99 60 50 60 60 110 5.15 –1 130 V % mA μA Switching Regulator 633 kHz kHz % 110 110 110 110 ns ns ns ns ns 60 60 25 –25 35 –15 –5 250 85 2.5 180 6 0.5 μA mV mV mV V mV μs μs V V μA mV 20 98 PowerPath Control –10 15 15 –45 –6.5 –250 Float Voltage Select Inputs (LTC4012-1/LTC4012-2 Only) Indicator Outputs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC4012 is guaranteed to meet performance specifications over the 0°C to 85°C operating temperature range. Note 3: Operating junction temperature TJ (in °C) is calculated from the ambient temperature TA and the total continuous package power dissipation PD (in watts) by the formula TJ = TA + (θJA • PD). Refer to the Applications Information section for details. Note 4: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified. Note 5: Output current may be limited by internal power dissipation. Refer to the Applications Information section for details. 4012f 4 LTC4012/ LTC4012-1/LTC4012-2 TEST CIRCUITS LTC4012 FROM ICL (CLP = CLN) 1.2085V – – – + EA PROG 13 9 VFB ITH 12 1.2085V TARGET + LTC1055 – 40012 TC01 0.6V LTC4012-1 LTC4012-2 FROM ICL (CLP = CLN) 1.2085V – – – + EA PROG 13 BAT 11 TARGET VARIES WITH FVSO,1 ITH 12 + LTC1055 – 40012 TC02 0.6V 4012f 5 LTC4012/ LTC4012-1/LTC4012-2 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise noted. L = IHLP-2525 6.8μH) Efficiency at DCIN = 20V, BAT = 8V 100 RSENSE = 33mΩ RIN = 3.01k 95 POWER LOSS(mW) EFFICIENCY (%) EFFICIENCY 90 POWER LOSS 1000 EFFICIENCY (%) 95 10000 100 RSENSE = 33mΩ RIN = 3.01k EFFICIENCY POWER LOSS(mW) Efficiency at DCIN = 20V, BAT = 12V 10000 90 POWER LOSS 1000 85 85 80 0 0.5 1 1.5 2 CHARGE CURRENT (A) 2.5 3 4012 G01 100 80 0 0.5 1 1.5 2 CHARGE CURRENT (A) 2.5 3 4012 G02 100 Efficiency at DCIN = 20V, BAT = 16V 100 EFFICIENCY 95 POWER LOSS(mW) EFFICIENCY (%) VFB ERROR (%) 10000 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 3 4012 G03 VFB Line Regulation LTC4012 TEST CIRCUIT 90 POWER LOSS 1000 85 RSENSE = 33mΩ RIN = 3.01k 80 0 0.5 1 1.5 2 CHARGE CURRENT (A) 2.5 100 –0.10 5 10 20 25 15 CLP PIN VOLTAGE (V) 30 4012 G04 FBDIV Pin RON vs Battery Voltage 300 275 250 225 RON (Ω) 200 175 150 125 100 75 0 5 20 15 10 BATTERY VOLTAGE (V) 25 4012 G05 Battery Load Dump 2 BATTERY VOLTAGE (500mV/DIV) 2A CHARGE CURRENT ERROR (%) 12.1V 1A 3A RECONNECT DISCONNECT TIME (1ms/DIV) CLP = 20V VOUT = 12.3V 4012 G06 Charge Current Accuracy 1 CLP = BAT + 3V (CLP ≥ 6V) 1A 0 –1 –2 –3 –4 –5 –6 0 2 4 6 8 10 12 14 16 18 20 22 24 BATTERY VOLTAGE (V) 4012 G07 DCIN = 24V RPROG = 35.7k DCIN = 12V RPROG = 26.7k LOAD STATE RSENSE = 33mΩ RIN = 3.01k 4012f 6 LTC4012/ LTC4012-1/LTC4012-2 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise noted. L = IHLP-2525 6.8μH) Charge Current Line Regulation 0.5 BAT = 6V 0.4 RSENSE = 33mΩ RIN = 3.01k 0.3 ICHG = 1A 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 5 15 10 20 DCIN PIN VOLTAGE (V) 25 4012 G08 Charge Current Load Regulation 3.5 3.0 CHARGE CURRENT (A) 2.5 2.0 1.5 1.0 0.5 0 DCIN = 20V RSENSE = 33mΩ RIN = 3.01k 11.4 12.6 11.8 12.2 BATTERY VOLTAGE (V) 13.0 4012 G09 Input Current Limit 3.0 2.5 2.0 CURRENT (A) ICHG = 3A IIN ICHG CHARGE CURRENT ERROR (%) ICHG = 2A 1.5 1.0 0.5 0 –0.5 –1.0 0 0.5 ICHG = 2A ICHG = 3A ICHG = 1A 2.5A BULK CHARGE 2.1A INPUT CURRENT LIMIT ICL STATE 1.0 1.5 SYSTEM LOAD (A) 2.0 2.5 4012 G10 –0.5 11.0 PWM Soft-Start ICHG 2A/DIV ITH 1V/DIV PROG 1V/DIV SHDN 5V/DIV TIME (500μs/DIV) 4012 G11 Gate Drive Non-Overlap 600 EXTERNAL FET DRIVE (1V/DIV) BGATE PWM FREQUENCY (kHz) 500 400 300 200 100 0 PWM Frequency vs Duty Cycle ICHG = 750mA TGATE TIME (80ns/DIV) 4012 G12 CLP = 6V CLP = 12V CLP = 20V CLP = 25V 0 20 40 60 DUTY CYCLE (%) 80 100 4012 G13 PWM Frequency vs Charge Current 600 500 PWM FREQUENCY (kHz) 400 300 200 100 0 BAT = 14.5V CLP = 15V RSENSE = 33mΩ RIN = 3.01k BAT = 5V BAT = 12V BATTERY CURRENT (μA) 20 25 Battery Shutdown Current DC1256-CLASS APPLICATION DCIN = 0V VGS = 0V INFET Response Time to DCIN Short to Ground PFET VGS (1V/DIV) 15 LTC4012, ALL PINS DCIN = 0V LTC4012, BAT PINS DCIN = 20V 0A IDCIN, REVERSE (5A/DIV) 10 5 0 0.5 1.0 1.5 2.0 CHARGE CURRENT (A) 2.5 3.0 4012 G14 0 0 5 20 10 15 BATTERY VOLTAGE (V) 25 4012 G15 TIME (1μs/DIV) DCIN = 15V INFET = Si7423DN IOUT = < 50mA VOUT = 12.3V COUT = 0.27F 4012 G16 4012f 7 LTC4012/ LTC4012-1/LTC4012-2 PIN FUNCTIONS CLN (Pin 1): Adapter Input Current Limit Negative Input. The LTC4012 senses voltage on this pin to determine if less charge current should be sourced to limit total input current. The threshold is set 100mV below the CLP pin. An external filter should be used to remove switching noise. This input should be tied to CLP if not used. Operating voltage range is (CLP – 110mV) to CLP. CLP (Pin 2): Adapter Input Current Limit Positive Input. The LTC4012 also draws power from this pin, including a small amount for some shutdown functions. Operating voltage range is GND to 28V. INFET (Pin 3): PowerPath Control Output. This output drives the gate of a PMOS pass transistor connected between the DC input (DCIN) and the raw system supply rail (CLP) to maintain a forward voltage of 25mV when a DC input source is present. INFET is internally clamped about 6V below CLP. Maximum operating voltage is CLP, which is used to turn off the input PMOS transistor when the DC input is removed. DCIN (Pin 4): DC Sense Input. One of two voltage sense inputs to the internal PowerPath controller (the other input to the controller is CLP). This input is usually supplied from an input DC power source. Operating voltage ranges from GND to 28.2V. ACP (Pin 5): Active-Low AC Adapter Present Indicator Output. This open-drain output pulls to GND when adequate AC adapter (DCIN) voltage is present. This output should be left floating if not used. SHDN (Pin 6): Active-low Shutdown Input. Driving SHDN below 300mV unconditionally forces the LTC4012 into the shutdown state. This input has a 40kΩ internal pulldown to GND. Operating voltage range is GND to INTVDD. CHRG (Pin 7): Active-Low Charge Indicator Output. This open-drain output provides three levels of information about charge status using a strong pull-down, 25μA weak pull-down or high impedance. Refer to the Operation and Applications Information sections for further details. This output should be left floating if not used. ICL (Pin 8): Active-Low Input Current Limit Indicator Output. This open-drain output pulls to GND when the charge current is reduced because of AC adapter input current limiting. This output should be left floating if not used. VFB (Pin 9, LTC4012): Battery Voltage Feedback Input. An external resistor divider between FBDIV and GND with the center tap connected to VFB programs the charger output voltage. In constant voltage mode, this pin is nominally at 1.2085V. Refer to the Applications Information section for complete details on programming battery voltage. Operating voltage range is GND to 1.25V. FVS0 (Pin 9, LTC4012-1/LTC4012-2): Battery Voltage Select Input (LSB). This pin is one of two pins used on the LTC4012-1 or LTC4012-2 to select one of four preset battery voltages. Selection is done by connecting to either GND or INTVDD. Operating voltage range is GND to INTVDD. FBDIV (Pin 10, LTC4012): Battery Voltage Feedback Resistor Divider Source. The LTC4012 connects this pin to BAT when charging is in progress. FBDIV is an opendrain PFET output to BAT with an operating voltage range of GND to BAT. FVS1 (Pin 10, LTC4012-1/LTC4012-2): Battery Voltage Select Input (MSB). This pin is one of two pins used on the LTC4012-1 or LTC4012-2 to select one of four preset battery voltages. Selection is done by connecting to either GND or INTVDD. Operating voltage range is GND to INTVDD. BAT (Pin 11): Battery Pack Connection. The LTC4012 uses the voltage on this pin to control PWM operation when charging. Operating voltage range is GND to CLN. ITH (Pin 12): PWM Control Voltage and Compensation Node. The LTC4012 develops a voltage on this pin to control cycle-by-cycle peak inductor current. An external R-C network connected to ITH provides PWM loop compensation. Refer to the Applications Information section for further details on establishing loop stability. Operating voltage range is GND to INTVDD. 4012f 8 LTC4012/ LTC4012-1/LTC4012-2 PIN FUNCTIONS PROG (Pin 13): Charge Current Programming and Monitoring Pin. An external resistance connected between PROG and GND, along with the current sense and PWM input resistors, programs the maximum charge current. The voltage on this pin can also provide a linearized indicator of charge current. Refer to the Applications Information section for complete details on current programming and monitoring. Operating voltage range is GND to INTVDD. CSN (Pin 14): Charge Current Sense Negative Input. Place an external input resistor (R IN , Figure 1) between this pin and the negative side of the charge current sense resistor. Operating voltage ranges from (BAT – 50mV) to (BAT + 200mV). CSP (Pin 15): Charge Current Sense Positive Input. Place an external input resistor (RIN , Figure 1) between this pin and the positive side of the charge current sense resistor. Operating voltage ranges from (BAT – 50mV) to (BAT + 200mV). BGATE (Pin 16): External Synchronous NFET Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used for synchronous rectification to increase efficiency in the step-down DC/DC converter. Operating voltage is GND to INTVDD. BGATE should be left floating if not used. INTVDD (Pin 17): Internal 5V Regulator Output. This pin provides a means of bypassing the internal 5V regulator used to power the LTC4012 PWM FET drivers. This supply shuts down when the LTC4012 shuts down. Refer to the Application Information section for details if additional power is drawn from this pin by the application circuit. SW (Pin 18): PWM Switch Node. The LTC4012 uses the voltage on this pin as the source reference for its topside NFET (PWM switch) driver. Refer to the Applications Information section for additional PCB layout suggestions related to this critical circuit node. Operating voltage range is GND to CLN. TGATE (Pin 19): External NFET Switch Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used in the DC/DC converter. Operating voltage range is GND to (CLN + 5V). BOOST (Pin 20): TGATE Driver Supply Input. A bootstrap capacitor is returned to this pin from a charge network connected to SW and INTVDD. Refer to the Applications Information section for complete details on circuit topology and component values. Operating voltage ranges from (INTVDD – 1V) to (CLN + 5V). Exposed Pad (Pin 21): Ground. The package paddle provides a single-point ground for the internal voltage reference and other critical LTC4012 circuits. It must be soldered to a suitable PCB copper ground pad for proper electrical operation and to obtain the specified package thermal resistance. 4012f 9 LTC4012/ LTC4012-1/LTC4012-2 BLOCK DIAGRAM 4 DCIN (LTC4012) – 3 INFET IF + 2 1 CLP CLN ICL CHRG 7 9 VFB INPUT CURRENT LIMIT FAULT DETECTION 8 C/10 DETECTION + CA CSP 15 6 CC TO INTERNAL CIRCUITS – EA 5 ACP TO INTERNAL CIRCUITS 11 BAT OSCILLATOR BOOST TGATE CHARGE PWM LOGIC FBDIV 10 10 + – – – 1.2085V REFERENCE SHDN SHUTDOWN CONTROL SHUTDOWN + R1 – CSN 14 PROG 13 ITH 12 20 19 TO INTERNAL CIRCIUTS 5V REGULATOR SW 18 INTVDD 17 BGATE GND (PADDLE) 16 21 4012 BD01 4012f LTC4012/ LTC4012-1/LTC4012-2 BLOCK DIAGRAM 4 DCIN (LTC4012-1/LTC4012-2) – 3 INFET IF + 2 1 CLP CLN ICL CHRG 7 INPUT CURRENT LIMIT FAULT DETECTION 8 C/10 DETECTION VFB + CA CSP 15 6 SHDN SHUTDOWN CONTROL SHUTDOWN TO INTERNAL CIRCUITS + CC R1 – EA CSN 14 10 FVS1 – Output Voltage Select 9 FVS0 TO INTERNAL CIRCUITS BAT 11 ACP 5 CHARGE OSCILLATOR PWM LOGIC TO INTERNAL CIRCIUTS 5V REGULATOR INTVDD 17 BGATE 16 TGATE 19 BOOST 20 + – – – 1.2085V REFERENCE PROG 13 ITH 12 SW 18 GND (PADDLE) P 4012 BD02 4012f 11 LTC4012/ LTC4012-1/LTC4012-2 OPERATION Overview The LTC4012 is a synchronous step-down (buck) current mode PWM battery charger controller. The maximum charge current is programmed by the combination of a charge current sense resistor (RSENSE), matched input resistors (RIN , Figure 1), and a programming resistor (RPROG) between the PROG and GND pins. Battery voltage is programmed with an external resistor divider between FBDIV and GND (LTC4012) or two digital battery voltage select pins (LTC4012-1/LTC4012-2). In addition, the PROG pin provides a linearized voltage output of the actual charge current. The LTC4012 family does not have built-in charge termination and is flexible enough for charging any type of battery chemistry. These are building block ICs intended for use with an external circuit, such as a microcontroller, capable of managing the entire algorithm required for the specific battery being charged. Each member of the LTC4012 family features a shutdown input and various state indicator outputs, allowing easy and direct management by a wide range of external (digital) charge controllers. Due to the popularity of rechargeable Lithium-Ion chemistries, the LTC4012-1 and LTC4012-2 also offer internal precision resistors that can be digitally selected to produce one of four preset output voltages for simplified design of those charger types. Shutdown The LTC4012 remains in shutdown until DCIN is greater than 5.1V and exceeds CLP by 60mV and SHDN is driven above 1.4V. In shutdown, current drain from the battery is reduced to the lowest possible level, thereby increasing standby time. When in shutdown, the ITH pin is pulled to GND and CHRG, ICL , FET gate drivers and INTVDD output are all disabled. The charging can be stopped at any time by forcing SHDN below 300mV. AC Present Indication The ACP status output correctly indicates sensed adapter input voltage during all LTC4012 states. AC present is indicated (ACP output low) as soon as DCIN exceeds BAT by at least 500mV. Charging is not enabled until this condition is first met. After this event, charging is no longer gated by AC present detection. If battery voltage rises due to ESR, or DCIN droops due to current load, AC present may no longer be indicated by the IC if charging was started with very low input overhead. However, charging will remain enabled unless DCIN falls below the supply voltage on CLP . Input PowerPath Control The input PFET controller performs many important functions. First, it monitors DCIN and enables the charger when this input voltage is higher than the raw CLP system supply. Next, it controls the gate of an external input power PFET to maintain a low forward voltage drop when charging, creating improved efficiency. It also prevents reverse current flow through this same PFET, providing a suitable input blocking function. Finally, it helps avoid synchronous boost operation during invalid operating conditions by detecting elevated CLP voltage and forcing the charger off. If DCIN voltage is less than CLP, then DCIN must rise 60mV higher than CLP to enable the charger and activate the ideal diode control. At this point, the ACPb status output also transitions to low impedance to indicate to the host system that an external adapter is present. The gate of the input PFET is driven to a voltage sufficient to regulate a forward drop between DCIN and CLP of about 25mV. If the input voltage differential drops below this point, the FET is turned off slowly. If the voltage between DCIN and CLP drops to less than –25mV, the input FET is turned off in less than 6μs to prevent significant reverse current from flowing back through the PFET. In this case, ACPb also switches back to high impedance and the charger is disabled. Soft-Start Exiting the shutdown state enables the charger and releases the ITH pin. When enabled, switching will not begin until DCIN exceeds BAT by 500mV and ITH exceeds a threshold that assures initial current will be positive (about 5% to 25% of the maximum programmed current). To limit inrush current, soft-start delay is created with the compensation values used on the ITH pin. Longer soft-start times can be realized by increasing the filter capacitor on ITH, if reduced loop bandwidth is acceptable. The actual charge current at 4012f 12 LTC4012/ LTC4012-1/LTC4012-2 OPERATION LTC4012 WATCHDOG TIMER SYSTEM POWER 2 11 CLP BAT OSCILLATOR CLOCK S RD Q PWM LOGIC TGATE 19 L1 BGATE 16 RIN 15 RIN 14 13 RPROG CPROG RSENSE VSENSE + + CC R1 CA CSP + – CSN PROG – – ICHRG EA Figure 1. PWM Circuit Diagram the end of soft-start will depend on which loop (current, voltage or adapter limit) is in control of the PWM. If this current is below that required by the ITH start-up threshold, the resulting charge current transient duration depends on loop compensation but is typically less than 100μs. Bulk Charge When soft-start is complete, the LTC4012 begins sourcing the current programmed by the external components connected to CSP CSN and PROG. Some batteries may , require a small conditioning trickle current if they are heavily discharged. As shown in the Applications Information section, the LT4012 can address this need through a variety of low current circuit techniques on the PROG pin. Once a suitable cell voltage has been reached, charge current can be switched to a higher, bulk charge value. End of Charge and CHRG Output As the battery approaches the programmed output voltage, charge current will begin to decrease. The open-drain CHRG output can indicate when the current drops to 10% of its programmed full-scale value by turning off + – – – FROM ICL 1.2085V VFB + 9 ITH 12 LOOP COMPENSATION 4012 F01 the strong pull-down (open-drain FET) and turning on a weak 25μA pull-down current. This weak pull-down state is latched until the part enters shutdown or the sensed current rises to roughly C/6. C/10 indication will not be set if charge current has been reduced due to adapter input current limiting. As the charge current approaches 0A, the PWM continues to operate in full continuous mode. This avoids generation of audible noise, allowing bulk ceramic capacitors to be used in the application. Charge Current Monitoring When the LTC4012 is charging, the voltage on the PROG pin varies in direct proportion to the charge current. Referring to Figure 1, the nominal PROG voltage is given by VPROG = ICHRG • RSENSE • RPROG + 11.67μA • RPROG RIN Voltage tolerance on PROG is limited by the charge current accuracy specified in the Electrical Characteristics table. Refer to the Applications Information section on programming charge current for additional details. 4012f 13 LTC4012/ LTC4012-1/LTC4012-2 OPERATION Adapter Input Current Limit The LTC4012 can monitor and limit current from the input DC supply, which is normally an AC adapter. When the programmed adapter input current is reached, charge current is reduced to maintain the desired maximum input current. The ITH and PROG pins will reflect the reduced charge current. This limit function avoids overloading the DC input source, allowing the product to operate at the same time the battery is charging without complex load management algorithms. The battery will automatically be charged at the maximum possible rate that the adapter will support, given the application’s operating condition. The LTC4012 can only limit input current by reducing charge current, and in this case the charger uses nonsynchronous PWM operation to prevent boosting if the average charge current falls below about 25% of the maximum programmed current. Note that the ICL indicator output becomes active (low) at an adapter input current level just slightly less than that required for the internal amplifier to begin to assert control over the PWM loop. Charger Status Indicator Outputs The LTC4012 open-drain indicator outputs provide valuable information about the IC’s operating state and can be used for a variety of purposes in applications. Table 1 summarizes the state of the three indicator outputs as a function of LTC4012 operation. Table 1. LTC4012 Open-Drain Indicator Outputs ACP Off On On On On On Off CHRG Off Off On 25μA On 25μA On or 25μA ICL Off Off Off Off On On On or Off CHARGER STATE No DC Input (Shutdown) Shutdown or Reverse Current Bulk Charge Low Current Charge or Initial DCIN – BAT 100) at 10μA levels. Low gain NPNs will increase programming errors. Q1 must be a matched NPN pair. Since RF has been reduced in value by half, the capacitor value of CF should double to 0.22μF to remain effective at filtering out any noise. If you wish to reduce RCL power dissipation for a given current limit, the programming equation becomes: ⎛ 5 • 2.49k ⎞ 100mV – ⎜ ⎝ R1 ⎟ ⎠ = ILIM In many notebook applications, there are situations where two different ILIM values are needed to allow two different power adapters or power sources to be used. In such cases, start by setting RLIM for the high power ILIM configuration and then use Figure 7 to set the lower ILIM value. To toggle between the two ILIM values, take the three ground connections shown in Figure 7, combine them into one common connection and use a small-signal NFET (2N7002) to open or close that common connection to circuit ground. When the NFET is off, the circuit is defeated (floating) allowing ILIM to be the maximum value. When the NFET is on, the circuit will become active and ILIM will drop to the lower set value. Monitoring Charge Current The PROG pin voltage can be used to indicate charge current where 1.2085V indicates full programmed current (1C) and zero charge current is approximately equal to RPROG • 11.67μA. PROG voltage varies in direct proportion to the charge current between this zero-current (offset) value and 1.2085V. When monitoring the PROG pin voltage, using a buffer amplifier as shown in Figure 8 will minimize charge current errors. The buffer amplifier may be powered from the INTVDD pin or any supply that is always on when the charger is on. RCL If you wish to make the input current limit programmable, the equation becomes: ⎛ 5 • 2.49k ⎞ 100mV – ⎜ ⎝ R1 ⎟ ⎠ ILIM = RCL The equation governing R2 for both applications is based on the value of R1. R3 should always be equal to R1. R2 = 0.875 • R1 INTVDD 17 LTC4012 PROG 13 0.125 • VCLP ⎛ 150mV ⎞ fPWM • ⎜ – IMAX ⎟ ⎝ RSENSE ⎠ A reasonable starting point for setting ripple current is ΔIL = 0.4 • IMAX. The voltage compliance of internal LTC4012 circuits also imposes limits on ripple current. Select RIN (in Figure 1) to avoid average current errors in high ripple designs. The following equation can be used for guidance: RSENSE • ΔIL R • ΔIL ≤ RIN ≤ SENSE 50μA 20μA 4012f 21 LTC4012/ LTC4012-1/LTC4012-2 APPLICATIONS INFORMATION RIN should not be less than 2.37k or more than 6.04k. Values of RIN greater than 3.01k may cause some reduction in programmed current accuracy. Use these equations and guidelines, as represented in Table 6, to help select the correct inductor value. This table was developed to maintain maximum ΔIL near 0.6 • IMAX with fPWM at 550kHz and VBAT = 0.5 • VCLP (the point of maximum ΔIL), assuming that inductor value could also vary by 25% at IMAX. Table 6. Minimum Typical Inductor Values VCLP L1 IMAX RSENSE (Typ) 20V 20V 20V 20V ≥10μH ≥20μH ≥28μH ≥5.1μH ≥10μH ≥14μH ≥3.4μH ≥6.8μH ≥9.5μH ≥2.5μH ≥5.1μH ≥7.1μH 1A 1A 1A 2A 2A 2A 3A 3A 3A 4A 4A 4A 100mΩ 100mΩ 100mΩ 50mΩ 50mΩ 50mΩ 33mΩ 33mΩ 33mΩ 25mΩ 25mΩ 25mΩ TGATE BOOST Supply Use the external components shown in Figure 11 to develop a bootstrapped BOOST supply for the TGATE FET driver. A good set of equations governing selection of the two capacitors is: C1 = 20 • QG , C2 = 20 • C1 4.5V RIN 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k 3.01k RPROG 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k 26.7k where QG is the rated gate charge of the top external NFET with VGS = 4.5V. The maximum average diode current is then given by: ID = QG • 665kHz To improve efficiency by increasing VGS applied to the top FET, substitute a Schottky diode with low reverse leakage for D1. PWM jitter has been observed in some designs operating at higher VIN/VOUT ratios. This jitter does not substantially affect DC charge current accuracy. A series resistor with a value of 5Ω to 20Ω can be inserted between the cathode of D1 and the BOOST pin to remove this jitter, if present. A resistor case size of 0603 or larger is recommended to lower ESL and achieve the best results. BOOST 20 LTC4012 INTVDD 17 D1 1N4148 C2 2μF C1 0.1μF L1 TO RSENSE To guarantee that a chosen inductor is optimized in any given application, use the design equations provided and perform bench evaluation in the target application, particularly at duty cycles below 20% or above 80% where PWM frequency can be much less than the nominal value of 550kHz. SW 18 4012 F11 Figure 11. TGATE Boost Supply 4012f 22 LTC4012/ LTC4012-1/LTC4012-2 APPLICATIONS INFORMATION FET Selection Two external power MOSFETs must be selected for use with the charger: an N-channel power switch (top FET) and an N-channel synchronous rectifier (bottom FET). Peak gate-to-source drive levels are internally set to about 5V. Consequently, logic-level FETs must be used. In addition to the fundamental DC current, selection criteria for these MOSFETs also include channel resistance RDS(ON), total gate charge QG, reverse transfer capacitance CRSS, maximum rated drain-source voltage BVDSS and switching characteristics such as td(ON/OFF). Power dissipation for each external FET is given by: PD(TOP) = VBAT • IMAX 2 • (1+ δΔT) RDS(ON) VCLP + k • VCLP 2 • IMAX • CRSS • 665kHz PD(BOT) = The synchronous (bottom) FET losses are greatest at high input voltage or during a short circuit, which forces a low side duty cycle of nearly 100%. Increasing the size of this FET lowers its losses but increases power dissipation in the LTC4012. Using asymmetrical FETs will normally achieve cost savings while allowing optimum efficiency. Select FETs with BVDSS that exceeds the maximum VCLP voltage that will occur. Both FETs are subjected to this level of stress during operation. Many logic-level MOSFETs are limited to 30V or less. The LTC4012 uses an improved adaptive TGATE and BGATE drive that is insensitive to MOSFET inertial delays, td(ON/OFF), to avoid overlap conduction losses. Switching characteristics from power MOSFET data sheets apply only to a specific test fixture, so there is no substitute for bench evaluation of external FETs in the target application. In general, MOSFETs with lower inertial delays will yield higher efficiency. Diode Selection A Schottky diode in parallel with the bottom FET and/or top FET in an LTC4012 application clamps SW during the non-overlap times between conduction of the top and bottom FET switches. This prevents the body diode of the MOSFETs from forward biasing and storing charge, which could reduce efficiency as much as 1%. One or both diodes can be omitted if the efficiency loss can be tolerated. A 1A Schottky is generally a good size for 3A chargers due to the low duty cycle of the non-overlap times. Larger diodes can actually result in additional efficiency (transition) losses due to larger junction capacitance. Loop Compensation and Soft-Start The three separate PWM control loops of the LTC4012 can be compensated by a single set of components attached between the ITH pin and GND. As shown in the typical LTC4012 application, a 6.04k resistor in series with a capacitor of at least 0.1μF provides adequate loop compensation for the majority of applications. (VCLP – VBAT) • IMAX 2 • (1+ δΔT)RDS(ON) VCLP where δ is the temperature dependency of RDS(ON), ΔT is the temperature rise above the point specified in the FET data sheet for RDS(ON) and k is a constant inversely related to the internal LTC4012 top gate driver. The term (1 + δ ΔT) is generally given for a MOSFET in the form of a normalized RDS(ON) curve versus temperature, but δ of 0.005/°C can be used as a suitable approximation for logic-level FETs if other data is not available. CRSS = ΔQGD /ΔVDS is usually specified in the MOSFET characteristics. The constant k = 2 can be used in estimating top FET dissipation. The LTC4012 is designed to work best with external FET switches with a total gate charge at 5V of 15nC or less. For VCLP < 20V, high charge current efficiency generally improves with larger FETs, while for VCLP > 20V, top gate transition losses increase rapidly to the point that using a topside NFET with higher RDS(ON) but lower CRSS can actually provide higher efficiency. If the charger will be operated with a duty cycle above 85%, overall efficiency is normally improved by using a larger top FET. 4012f 23 LTC4012/ LTC4012-1/LTC4012-2 APPLICATIONS INFORMATION The LTC4012 can be soft-started with the compensation capacitor on the ITH pin. At start-up, ITH will quickly rise to about 0.25V, then ramp up at a rate set by the compensation capacitor and the 40μA ITH bias current. The full programmed charge current will be reached when ITH reaches approximately 2V. With a 0.1μF capacitor, the time to reach full charge current is usually greater than 1.5ms. This capacitor can be increased if longer start-up times are required, but loop bandwidth and dynamic response will be reduced. INTVDD Regulator Output Bypass the INTVDD regulator output to GND with a low ESR X5R or X7R ceramic capacitor with a value of 0.47μF or larger. The capacitor used to build the BOOST supply (C2 in Figure 11) can serve as this bypass. Do not draw more than 30mA from this regulator for the host system, governed by IC power dissipation. Calculating IC Power Dissipation The user should ensure that the maximum rated junction temperature is not exceeded under all operating conditions. The thermal resistance of the LTC4012 package (θJA) is 37°C/W, provided the Exposed Pad is in good thermal contact with the PCB. The actual thermal resistance in the application will depend on forced air cooling and other heat sinking means, especially the amount of copper on the PCB to which the LTC4012 is attached. The following formula may be used to estimate the maximum average power dissipation PD (in watts) of the LTC4012, which is dependent upon the gate charge of the external MOSFETs. This gate charge, which is a function of both gate and drain voltage swings, is determined from specifications or graphs in the manufacturer’s data sheet. For the equation below, find the gate charge for each transistor assuming 5V gate swing and a drain voltage swing equal to the maximum VCLP voltage. Maximum LTC4012 power dissipation under normal operating conditions is then given by: PD = DCIN(3mA + IDD + 665kHz(QTGATE + QBGATE)) – 5IDD where: IDD = Average external INTVDD load current, if any QTGATE = Gate charge of external top FET in Coulombs QBGATE = Gate charge of external bottom FET in Coulombs PCB Layout Considerations To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the LTC4012 is essential. Refer to Figure 12. For maximum efficiency, the switch node rise and fall times should be minimized. The following PCB design priority list will help insure proper topology. Layout the PCB using this specific order. 1. Input capacitors should be placed as close as possible to switching FET supply and ground connections with the shortest copper traces possible. The switching FETs must be on the same layer of copper as the input capacitors. Vias should not be used to make these connections. 2. Place the LTC4012 close to the switching FET gate terminals, keeping the connecting traces short to produce clean drive signals. This rule also applies to IC supply and ground pins that connect to the switching FET source pins. The IC can be placed on the opposite side of the PCB from the switching FETs. SWITCH NODE L1 VIN CIN HIGH FREQUENCY CIRCULATING PATH COUT D1 RSENSE VBAT + BAT ANALOG GROUND GND SWITCHING GROUND 4012 F12 SYSTEM GROUND Figure 12. High Speed Switching Path 4012f 24 LTC4012/ LTC4012-1/LTC4012-2 APPLICATIONS INFORMATION 3. Place the inductor input as close as possible to the switching FETs. Minimize the surface area of the switch node. Make the trace width the minimum needed to support the programmed charge current. Use no copper fills or pours. Avoid running the connection on multiple copper layers in parallel. Minimize capacitance from the switch node to any other trace or plane. 4. Place the charge current sense resistor immediately adjacent to the inductor output, and orient it such that current sense traces to the LTC4012 are not long. These feedback traces need to be run together as a single pair with the smallest spacing possible on any given layer on which they are routed. Locate any filter component on these traces next to the LTC4012, and not at the sense resistor location. 5. Place output capacitors adjacent to the sense resisitor output and ground. 6. Output capacitor ground connections must feed into the same copper that connects to the input capacitor ground before connecting back to system ground. 7. Connection of switching ground to system ground, or any internal ground plane, should be single-point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. 8. Route analog ground as a trace tied back to the LTC4012 GND paddle before connecting to any other ground. Avoid using the system ground plane. A useful CAD technique is to make analog ground a separate ground net and use a 0 Ω resistor to connect analog ground to system ground. 9. A good rule of thumb for via count in a given high current path is to use 0.5A per via. Be consistent when applying this rule. 10. If possible, place all the parts listed above on the same PCB layer. 11. Copper fills or pours are good for all power connections except as noted above in Rule 3. Copper planes on multiple layers can also be used in parallel. This helps with thermal management and lowers trace inductance, which further improves EMI performance. 12. For best current programming accuracy, provide a Kelvin connection from RSENSE to CSP and CSN. See Figure 13 for an example. 13. It is important to minimize parasitic capacitance on the CSP and CSN pins. The traces connecting these pins to their respective resistors should be as short as possible. DIRECTION OF CHARGING CURRENT RSENSE 4012 F13 TO CSP RIN TO CSN RIN Figure 13. Kelvin Sensing of Charge Current 4012f 25 LTC4012/ LTC4012-1/LTC4012-2 TYPICAL APPLICATION 12.6V 4 Amp Charger R7 25mΩ POWER TO SYSTEM FROM ADAPTER 15V AT 4A Q5 C1 0.1μF D1 R1 3k R 7 4 3 CHRG DCIN INFET CLP CLN BOOST 19 TGATE LTC4012 18 SW 5 17 ACP INTVDD 8 16 ICL BGATE 6 SHDN 21 GND 15 12 ITH CSP 14 D3 2 1 20 R15 0Ω* C4 0.1μF R8 5.1k C8 10μF C5 0.1μF D5 OR R14 100k D6 18V ZENER Q4 Q2 D4 C6 2μF R9 3.01k R11 25mΩ Q3 L1 4.7μH TO/FROM MCU TO POWER SYSTEM LOAD WHEN ADAPTER IS NOT PRESENT, USE SCHOTTKY DIODE D5 OR THE COMBINATION OF R14, D6 AND Q4 C2 0.1μF R4 6.04k R10 3.01k 13 R5 26.7k BULK CHARGE Q1 R6 53.6k C3 4.7nF 11 BAT 10 FBDIV PROG VFB 9 R12 294k R13 31.2k C10 10pF C9 10μF CSN + 12.6V Li-Ion BATTERY 4012 TA03 D3: CMDSH-3 D4: MBR230LSFT1 Q1: 2N7002 Q2, Q3: Si7212DN OR SiA914DJ OR Si4816BDY (OMIT D4) Q4, Q5: Si7423DN L1: 1HLP-2525CZER4R7M11 *: SEE TGATE BOOST SUPPLY IN APPLICATIONS INFORMATION 4012f 26 LTC4012/ LTC4012-1/LTC4012-2 PACKAGE DESCRIPTION UF Package 20-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1710 Rev A) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.00 REF 2.45 ± 0.05 2.45 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 ± 0.05 4.00 ± 0.10 R = 0.05 TYP BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 45° CHAMFER 19 20 0.40 ± 0.10 1 PIN 1 TOP MARK (NOTE 6) 2.45 ± 0.10 4.00 ± 0.10 2.00 REF 2.45 ± 0.10 2 (UF20) QFN 01-07 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 4012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC4012/ LTC4012-1/LTC4012-2 RELATED PARTS PART NUMBER LTC1760 LTC1769 LTC1960 LTC4006 LTC4007 LTC4008/LTC4008-1 DESCRIPTION Smart Battery System Manager 2A Switching Battery Charger Dual Battery Charger/Selector with SPI Small, High Efficiency, Fixed Voltage, Lithium-Ion Battery Chargers with Termination High Efficiency, Programmable Voltage, Lithium-Ion Battery Charger with Termination COMMENTS Autonomous Power Management and Battery Charging for Two Smart Batteries, SMBus Rev 1.1 Compliant Constant-Current/Constant-Voltage Switching Regulator, Input Current Limiting Maximizes Charge Current 11-bit V-DAC, 0.8% Voltage Accuracy, 10-Bit I-DAC, 5% Current Accuracy Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit and Thermistor Sensor, 16-pin SSOP Package Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit, Thermistor Sensor and Indicator Outputs High Efficiency, Programmable Voltage/Current Battery Constant-Current/Constant-Voltage Switching Regulator, Resistor Chargers Voltage/Current Programming, Thermistor Sensor and Indicator Outputs, AC Adapter Current Limit (Omitted on 4008-1) High Efficiency, Multichemistry Battery Charger High Efficiency Standalone Nickel Battery Charger High Efficiency Standalone Nickel Battery Charger Standalone Linear NiMH/NiCd Fast Charger Smart Battery Charger Controller Battery Backup Manager Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead QFN Package, AC Adapter Current Limit, Indicator Outputs Complete NiMH/NiCd Charger in a Small 16-Lead Package, ConstantCurrent Switching Regulator Complete NiMH/NiCd Charger in a Small 20-Lead Package, ConstantCurrent Switching Regulator, PowerPath Control and Indicators Complete NiMH/NiCd Charger in a Small 16-Pin Package, No Sense Resistor or Blocking Diode Required Level 2 Charger Operates with or without MCU Host, SMBus Rev 1.1 Compliant Multi-Chemistry and Smart Battery Charge and Discharge Manager. Four Operating Modes: Battery Backup, Battery Charge, Battery Calibration, Shutdown. 5mm × 7mm QFN-38 Package High Side Sense of Charge Quantity and Polarity in a 10-Pin MSOP No External MOSFET, Automatic Switching Between DC sources, 140mΩ On Resistance in ThinSOTTM package Very Low Loss Replacement for Power Supply ORing Diodes Using Minimal External Complements, Operates up to 28V (36V for HV) Low Loss Replacement for ORing Diodes, 100mΩ On Resistance Low Loss Replacement for ORing Diodes, Operates up to 36V Low Loss Replacement for ORing Diodes, Operates up to 36V, Drives Large PFETs, Programmable, Autonomous Switching LTC4009/LTC4009-1 LTC4009-2 LTC4010 LTC4011 LTC4060 LTC4100 LTC4110 LTC4150 LTC4411 LTC4412/LTC4412HV LTC4413 LTC4414 LTC4416 Coulomb Counter/Battery Gas Gauge 2.6A Low Loss Idea Diode Low Loss PowerPath Controllers Dual 2.6A, 2.5V to 5.5V Ideal Diodes 36V, Low Loss PowerPath Controller for Large PFETs Dual Low Loss PowerPath Controllers ThinSOT is a trademark of Linear Technology Corporation. 4012f 28 Linear Technology Corporation (408) 432-1900 ● LT 0509 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009