LTC4216IDE

LTC4216 Ultralow Voltage Hot Swap Controller FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTIO ■ ■ ■ ■ ■ ■ Allows Safe Board Insertion and Removal from a Live Backplane Controls Load Voltages from 0V to 6V Fast Response Limits Peak Fault Current Adjustable Analog Current Limit Adjustable Soft-Start with Inrush Current Limiting Adjustable Response Time for Overcurrent Protection Low Circuit Breaker Trip Threshold: 25mV No External Gate Capacitor Required Gate Drive for External N-Channel MOSFET Adjustable Supply Voltage Power-Up Rate ⎯R⎯E⎯S⎯E⎯T and ⎯F⎯A⎯U⎯L⎯T Output 10-Lead MSOP and 12-Lead (4mm × 3mm) DFN Packages The LTC®4216 is a positive low-voltage Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. It controls load voltages ranging from 0V to 6V and isolates a severe fault with instantaneous analog current limiting. An internal high side switch driver controls the gate of an external N-channel MOSFET. An adjustable soft-start limits the rate of change of the inrush current at start-up for a large load capacitor. Together with an analog current limit amplifier, an electronic circuit breaker with adjustable response time provides dual level overcurrent protection. No external gate capacitor is required for the analog current limit loop compensation. The FB pin monitors the output supply voltage and signals the ⎯R⎯E⎯S⎯E⎯T output pin. An ON pin provides on/off control and a ⎯F⎯A⎯U⎯L⎯T pin indicates the fault status. The LTC4216 is available in the 10-lead MSOP and 12-lead (4mm × 3mm) DFN packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ Electronic Circuit Breaker Live Board Insertion and Removal Industrial High Side Switch/Circuit Breaker Optical Networking TYPICAL APPLICATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VIN 1.8V LONG Single Channel 1.8V Hot Swap Controller 0.004Ω Si4864DY + LONG 22Ω VCC 330nF LTC4216 SHORT 15k 1% LONG ON 20k TIMER 1% 10nF SS FILTER 18nF FAULT GND RESET SENSEP SENSEN GATE 17.4k 1% 3.3V FB 10k 1% 10k 10k 1000µF VOUT 1.8V 5A VCC 3.3V µP LOGIC FAULT RESET VOUT 1V/DIV GND 10nF 4216 TA01 U Normal Power-Up with Soft-Start VGATE 5V/DIV IOUT 2.5A/DIV 0.5ms/DIV 4216 TA01b U U 4216f 1 LTC4216 ABSOLUTE (Note 1) AXI U RATI GS Operating Temperature Range LTC4216C ................................................ 0°C to 70°C LTC4216I .............................................–40°C to 85°C Storage Temperature Range MS .....................................................–65°C to 150°C DE ......................................................–65°C to 125°C Lead Temperature (Soldering, 10sec) MS Package ...................................................... 300°C Bias Supply Voltage (VCC) ............................– 0.3V to 9V Input Voltages FB, ON, SS, SENSEP, SENSEN .................– 0.3V to 9V TIMER, FILTER............................ –0.3V to VCC + 0.3V Output Voltages ⎯R⎯E⎯S⎯E⎯T, ⎯F⎯A⎯U⎯L⎯T ......................................... –0.3V to 9V GATE ...................................................... –0.3V to 15V PACKAGE/ORDER I FOR ATIO TOP VIEW RESET ON FILTER TIMER SS GND 1 2 3 4 5 6 13 12 FAULT 11 VCC 10 SENSEP 9 8 7 SENSEN GATE FB ORDER PART NUMBER LTC4216CDE LTC4216IDE DE PART* MARKING 4216 TOP VIEW RESET ON FILTER TIMER GND 1 2 3 4 5 10 9 8 7 6 VCC SENSEP SENSEN GATE FB DE PACKAGE 12-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W EXPOSED PAD (PIN 13) INTERNALLY CONNECTED TO GND (PCB CONNECTION OPTIONAL) Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is indicated by a label on the shipping container. ELECTRICAL CHARACTERISTICS SYMBOL VCC VSENSEP ICC VCC(UVL) ΔVCC(UVL,HYST) ΔVCB(TH) ΔVACL(TH) ISENSEP(IN) ISENSEN(IN) PARAMETER Bias Supply Range VSENSEP Supply Range Bias Supply Current Bias Supply Undervoltage Lockout Bias Supply Undervoltage Lockout Hysteresis Circuit Breaker Trip Voltage Threshold (VSENSEP – VSENSEN) Analog Current Limit Voltage Threshold (VSENSEP – VSENSEN) SENSEP Pin Input Current SENSEN Pin Input Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted. (Note 2) CONDITIONS ● ● VON = 2V, VFB = 2V VCC Rising VSENSEP = VSENSEN = VCC = 6V VSENSEP = VSENSEN = 0V, VCC = 6V VSENSEN = VSENSEP = VCC = 6V VSENSEN = VSENSEP = 0V, VCC = 6V 2 U U W WW U W ORDER PART NUMBER LTC4216CMS LTC4216IMS MS PART* MARKING LTBKV MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W MIN 2.3 0 TYP MAX 6 6 UNITS V V mA V mV mV mV mV µA µA µA µA 4216f ● ● ● 1.6 1.97 50 22.5 21.5 32 20 2.12 120 25 25 40 70 –7 10 –10 3 2.23 190 27.5 28.5 48 250 –20 15 –15 ● ● ● ● ● ● –5 LTC4216 ELECTRICAL CHARACTERISTICS SYMBOL IGATE(UP) IGATE(DN) PARAMETER GATE Pull Up Current GATE Pull Down Current The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted. (Note 2) CONDITIONS Gate Drive On, VGATE = 0V, VON = 2V Gate Drive Off, VGATE = 5V, VON = 0.6V VSENSEP - VSENSEN = 55mV, VGATE = 5V VSENSEP - VSENSEN = 100mV, VGATE = 5V 2.3V ≤ VCC < 3V 3V ≤ VCC ≤ 6V VGATE Falling After End of SS Timing Cycle VSS Falling VON = 2V, VSS = 1.2V, VFB = 2V VON = 2V, VFB = 0V VON = 0V, VSS = 2V VFB Falling 2.3V ≤ VCC ≤ 6V VFB = 1.2V, VCC = 6V VON Rising VON Falling VON = 1.2V, VCC = 6V VTIMER Rising VTIMER Falling Timer On, VON = 2V, VTIMER = 1V Timer Off, VON = 0V, VTIMER = 2V VFILTER Rising VFILTER Falling VON = 2V, VFILTER = 1V, In Fault Mode VON = 2V, VFILTER = 1V, No Faults VON = 0V, VFILTER = 2V, In Reset Mode V⎯F⎯A⎯U⎯L⎯T Falling VON = 0V, V⎯F⎯A⎯U⎯L⎯T = 1.5V I⎯R⎯E⎯S⎯E⎯T = I⎯F⎯A⎯U⎯L⎯T = 1.6mA V⎯R⎯E⎯S⎯E⎯T = VCC = 6V (VSENSEP - VSENSEN) = Step 0V to 30mV, VSENSEP = VCC, FILTER = 10nF to GND V⎯F⎯A⎯U⎯L⎯T = Step 2V to 0V VFILTER = Step 0V to 2V VON = Step 2V to 0V VON = 2V, VCC = Step 3.3V to 1.8V VON = Step 2V to 0.6V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN – 16 100 1 15 4.0 4.5 0.15 1.3 0.15 –7 – 0.3 0.593 TYP –20 600 5 50 5.0 6.2 0.2 1.65 0.2 –10 –1 8 0.602 0.2 3 0 0.8 80 0.4 0 1.253 0.2 –2 8 1.253 0.2 –60 2.4 8 1.253 10 –5 0.15 0 240 10 20 30 50 15 MAX –26 1500 20 100 7.9 7.9 0.3 2.0 0.35 –13 –2 0.611 3 ±1 0.83 130 0.44 ±1 1.291 0.35 –2.5 1.291 0.35 –75 3.3 1.291 –7 0.4 ±10 360 20 40 60 100 UNITS µA µA mA mA V V V V V µA µA mA V mV mV µA V mV V µA V V µA mA V V µA µA mA V mV µA V µA µs µs µs µs µs µs ΔVGATE VGATE(TH) VSS(CLP) VSS(TH) ISS(UP) ISS(DN) VFB(TH) ΔVFB(LINEREG) ΔVFB(HYST) IFB(IN) VON(TH) ΔVON(HYST) VON(FC) ION(IN) VTMR(TH) ITMR(UP) ITMR(DN) VFILT(TH) IFILT(UP) IFILT(DN) V⎯F⎯A⎯U⎯L⎯T(TH) ΔV⎯F⎯A⎯U⎯L⎯T(HYST) I⎯F⎯A⎯U⎯L⎯T(UP) VOL I⎯R⎯E⎯S⎯E⎯T(LEAK) tCB(TRIP) t⎯F⎯A⎯U⎯L⎯T(EXT) tFILTER tRST(ONLO) tRST(VCCLO) tOFF External N-Channel Gate Drive (VGATE – VSENSEN) GATE Pin Threshold Voltage SS Pin Clamp Voltage SS Pin Threshold Voltage SS Pull Up Current SS Pull Down Current FB Pin Threshold Voltage FB Pin Threshold Line Regulation FB Pin Hysteresis FB Pin Input Current ON Pin Threshold Voltage ON Pin Hysteresis ON Pin Fault Clear Threshold Voltage ON Pin Input Current TIMER Pin Threshold Voltage Timer Pull Up Current Timer Pull Down Current FILTER Pin Threshold Voltage Filter Pull Up Current Filter Pull Down Current ⎯FA⎯U⎯L⎯T Pin Threshold Voltage ⎯ ⎯F⎯A⎯U⎯L⎯T Pin Hysteresis ⎯FAULT Pin Current ⎯⎯⎯⎯ ⎯⎯⎯⎯⎯ ⎯ Output Low Voltage (RESET, F⎯A⎯U⎯L⎯T) ⎯R⎯E⎯S⎯E⎯T Pin Input Leakage Current Circuit Breaker Trip to Gate Discharging ⎯⎯⎯ ⎯⎯ FAULT Low to Gate Discharging FILTER High to Gate Discharging Circuit Breaker Reset Delay Time, ON Low to ⎯F⎯A⎯U⎯L⎯T High Circuit Breaker Reset Delay Time, VCC Low to ⎯F⎯A⎯U⎯L⎯T High Turn-Off Time, ON Low to GATE Discharging 0.77 40 0.36 1.216 0.15 – 1.5 1.216 0.15 – 45 1.5 1.216 –3 120 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of the device pins are negative; all voltages are referenced to GND unless otherwise specified. 4216f 3 LTC4216 TYPICAL PERFOR A CE CHARACTERISTICS unless otherwise noted. ICC vs VCC 3.0 3.0 2.5 ICC (mA) ICC (mA) 2.0 2.0 VCC = 6V VCC = 3.3V VCC = 2.3V VCC(UVL) (V) 1.5 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 VCC (V) ΔVCB(TH) vs Temperature 27 7.0 26 ∆VCB(TH) (mV) ∆VGATE (V) VGATE (V) 25 24 23 –50 –25 25 75 0 50 TEMPERATURE (°C) ΔVACL(TH) vs Temperature 42 –22 41 ∆VACL(TH) (mV) IGATE(UP) (µA) VFB(TH) (V) 40 39 38 –50 –25 25 75 0 50 TEMPERATURE (°C) 4 UW 5.0 5.5 100 100 Specifications are at TA = 25°C. VCC = 3.3V, ICC vs Temperature 2.20 2.15 2.10 2.05 VCC(UVL) vs Temperature 2.5 RISING 1.5 FALLING 2.00 1.0 1.95 1.90 –50 6.0 0.5 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 –25 25 75 0 50 TEMPERATURE (°C) 100 125 4216 G01 4216 G02 4216 G03 ΔVGATE vs Temperature VSENSEP = VSENSEN = VCC 14 12 VCC = 5V 6.0 VCC = 3.3V 10 8 6 4 2 –25 25 75 0 50 TEMPERATURE (°C) 100 125 VGATE vs VSENSEN VCC = 6V 6.5 5.5 VCC = 2.5V 5.0 125 4.5 –50 0 1 2 3 4 VSENSEN (V) 5 6 4216 G06 4216 G04 4216 G05 IGATE(UP) vs Temperature 0.611 VFB(TH) vs Temperature –21 0.608 RISING 0.605 FALLING –20 0.602 –19 0.599 125 –18 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 0.596 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 4216 G07 4216 G08 4216 G09 4216f LTC4216 TYPICAL PERFOR A CE CHARACTERISTICS VTMR(TH) vs Temperature 1.27 0.90 0.85 1.26 VTMR(TH) (V) 0.80 1.25 VON(TH) (V) 0.75 FALLING 0.70 1.24 0.65 1.23 –50 0.60 –50 1.23 –50 RISING VFAULT(TH) (V) 1.26 –25 25 75 0 50 TEMPERATURE (°C) ITMR(UP) vs Temperature –2.2 1.27 –2.1 ITMR(UP) (µA) VFILT(TH) (V) VSS(CLP) (V) –2.0 –1.9 –1.8 –50 –25 25 75 0 50 TEMPERATURE (°C) IFILT(UP) vs Temperature –70 2.8 –65 IFILT(DN) (µA) IFILT(UP) (µA) ISS(UP) (µA) –60 –55 –50 –50 –25 25 75 0 50 TEMPERATURE (°C) UW 100 100 100 VON(TH) vs Temperature 1.27 VFAULT(TH) vs Temperature 1.25 1.24 125 –25 25 75 0 50 TEMPERATURE (°C) 100 125 –25 25 75 0 50 TEMPERATURE (°C) 100 125 4216 G10 4216 G11 4216 G12 VFILT(TH) vs Temperature 1.9 VSS(CLP) vs Temperature 1.26 1.8 1.7 1.25 1.6 1.24 1.5 125 1.23 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 1.4 –50 –25 25 75 0 50 TEMPERATURE (°C) 100 125 4216 G13 4216 G14 4216 G15 IFILT(DN) vs Temperature –12 –10 2.6 –8 2.4 –6 –4 2.2 –2 2.0 –50 ISS(UP) vs Temperature VFB = 2V VFB = 0V –25 25 75 0 50 TEMPERATURE (°C) 100 125 125 –25 25 75 0 50 TEMPERATURE (°C) 100 125 0 –50 4216 G16 4216 G17 4216 G18 4216f 5 LTC4216 PI FU CTIO S ⎯R⎯E⎯S⎯E⎯T (Pin 1/Pin 1): Reset or Power-Good Output. Open drain output that pulls low if the FB pin voltage falls below its threshold (0.6V). If an undervoltage lockout condition occurs, the ⎯R⎯E⎯S⎯E⎯T pin pulls low and ignores the FB pin voltage. ON (Pin 2/Pin 2): ON Control Input. A rising edge above the ON pin threshold (0.8V) initiates the start-up cycle and turns on the external N-channel MOSFET. A falling edge below 0.72V (80mV ON pin hysteresis) turns it off. If this pin is pulled below 0.4V, following a circuit breaker trip, it resets the electronic circuit breaker and fault latch. FILTER (Pin 3/Pin 3): Fault Filter Input. Connect a capacitor between this pin and ground to set up the fault filter delay. This pin sources 60µA or sinks 2.4µA when the voltage across the sense resistor exceeds 25mV or drops below 25mV respectively. TIMER (Pin 4/Pin 4): Timer Input. Connect a capacitor between this pin and ground to set up the start-up timing ⎯⎯⎯⎯⎯ cycle duration. It also defines the RESET power-good delay from the instant the FB pin voltage exceeds 0.6V. This pin sources 2µA pull-up current during ramp up. SS (Pin 5/Not Available): Soft-Start Control Input. Connect a capacitor between this pin and ground for soft-start during power-up. It controls the GATE ramp up, limiting the rate of change of the inrush current when the external MOSFET turns on. If soft-start function is not used, leave this pin unconnected. GND (Pin 6/Pin 5): Device Ground. FB (Pin 7/Pin 6): Output Monitor for Reset Output. A resistive divider from the external MOSFET’s source terminal is tied to this pin. When the voltage at this pin drops below 0.6V, the ⎯R⎯E⎯S⎯E⎯T pin pulls low. 6 U U U (DE12 Package/MS Package) GATE (Pin 8/Pin 7): Gate Drive for External N-Channel MOSFET. An internal charge pump provides 20µA gate pull-up current and sufficient gate overdrive to the external MOSFET. An internal shunt regulator limits the GATE pin voltage to about 6.2V (typ) above the SENSEN pin voltage. SENSEN (Pin 9/Pin 8): Circuit Breaker Negative Sense Input. Connect this pin to the sense resistor terminal wired to the drain of the external N-channel MOSFET. The sense resistor is placed in the power path between SENSEP and SENSEN pins to sense the output current. The electronic circuit breaker trips if the voltage across the sense resistor exceeds 25mV for more than a fault filter delay. SENSEP (Pin 10/Pin 9): Circuit Breaker Positive Sense Input. Connect this pin to the sense resistor terminal wired to the positive supply input for the external output load. This positive supply range extends from 0V to 6V. VCC (Pin 11/Pin 10): Bias Supply Input. Operates from 2.3V to 6V. An internal undervoltage lockout circuit disables the device until the input supply voltage at VCC exceeds 2.12V typically. ⎯F⎯A⎯U⎯L⎯T (Pin 12/Not Available): Fault Input and Output. As an input, driving this pin low ( 2.12V); TIMER, SS, FILTER and GATE pin voltages < 0.2V. When the C1 voltage rises above the TIMER pin threshold (1.253V), TIMER pulls low and releases both the SS and GATE pins. C2 starts to ramp up at the SS pin, controlling the rate of GATE ramp. This limits the rate of change of the inrush current flowing into the output load capacitance. ⎯R⎯E⎯S⎯E⎯T pin goes high after the second timing cycle when the FB pin voltage exceeds 0.6V and its hysteresis. When the external MOSFET is fully turned on, the output will ramp to load supply voltage if the inrush into the load capacitance is low. However, if the inrush current exceeds the analog current limit of ΔVACL(TH)/RSENSE, the LTC4216 will ramp the output by sourcing the limited current into the load capacitance. The LTC4216 provides protection against output shortcircuits or current overload through an internal electronic circuit breaker with trip threshold of 25mV and an analog current limit circuit. The circuit breaker response time is set by C3 at the FILTER pin. 4216f – M1 M3 M4 CB TRIPS OR UVLO + – – + 0.6V FB + + – – 20µA + – + M2 100µA GATE OFF GATE ON GATE OFF M5 M6 SS** R1 RESET M7 5µA VCC + CP7 1.253V D2 FAULT** – M8 GND 4216 BD U 7 LTC4216 APPLICATIO S I FOR ATIO Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient current from the power bus as they charge. Potentially, the flow of current could damage the connector pins and glitch the power bus, causing other boards in the system to reset. The LTC4216 is designed to turn on or off a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Overview of LTC4216 Features 1. Allows safe board insertion and removal from a live backplane. 2. Controls load voltages from 0V to 6V. 3. High side gate drive for external N-channel MOSFET. 4. Adjustable soft-start with inrush current limiting for large load capacitor during start-up. 5. Adjustable analog current limit (ACL) with circuit breaker fault time-out during an overcurrent fault condition. No external gate capacitor is required for the ACL loop compensation. 6. Electronic circuit breaker tripping at 25mV across the sense resistor. The response time is adjustable through an external capacitor at the FILTER pin. 7. Provides an ON pin to turn on and off the device. This can also be used to reset the device after a circuit breaker trip. 8. Provides output supply voltage monitoring through the FB pin and signals the ⎯R⎯E⎯S⎯E⎯T pin output. 9. Provides fault status output. ON Control The ON pin has two hysteretic comparators with different threshold levels (0.8V and 0.4V) and they serve two purposes: 1. Turn on the device if the ON pin voltage > 0.8V for more than 6µs and turn it off if the ON pin voltage < 0.72V for more than 15µs. 8 U 2. Reset the device if the ON pin voltage < 0.4V for more than 30µs after a circuit breaker trip. There are various methods of setting the ON pin voltage: 1. Tie the ON pin to the load supply (VIN) through a 10k pull-up resistor. 2. Drive the ON pin with an ON/OFF logic signal from the system controller. 3. Connect an external resistive divider at the ON pin. This divider can be used to set a higher value for the load supply undervoltage lockout voltage than the internal VCC undervoltage lockout circuit. For example, as shown in Figure 17, if both VCC and SENSEP pins are connected to a 5V load supply, choosing the resistive divider values, R1 = 20k, R2 = 80.6k, turns on the device when the load supply voltage reaches around 80% of its final value. VCC Undervoltage Lockout A hysteretic comparator, UVLO, monitors bias supply (VCC) for undervoltage. The thresholds are defined by VCC(UVL) (2.12V) and its hysteresis, ΔVCC(UVL,HYST) (120mV). When VCC rises above VCC(UVL), the device is enabled. When VCC falls below (VCC(UVL) – ΔVCC(UVL,HYST)), the device is disabled and GATE is pulled low. If VCC cycles below this threshold for more than 200µs, following a circuit breaker trip, it clears the fault latch. Any bias supply glitches that last less than 10µs will be rejected by the UVLO glitch filter. Timer An external capacitor, C1, is used at TIMER pin to provide two timing cycles for the LTC4216. The first timing cycle is the debounce cycle when the ON pin is first turned on, both the GATE and SS pins are held low and any shortcircuit faults are ignored by the electronic circuit breaker. Second timing cycle is the power-good delay before the ⎯R⎯E⎯S⎯E⎯T pin goes high when the FB pin voltage exceeds 0.6V and its hysteresis. The TIMER pin sources 2µA into C1 during the two timing cycles and is then pulled low by an internal N-channel 4216f W U U LTC4216 APPLICATIO S I FOR ATIO switch when the TIMER pin voltage exceeds its threshold. The timer period for C1 to charge up to the TIMER pin threshold, VTMR(TH) (1.253V), is given by: tTIMER = 1.253V • C1 2µA For example, if C1 = 10nF, tTIMER = 6.2ms. FB Glitch Filtering The FB pin is used to monitor the output voltage of the external MOSFET through a resistive divider. Any transients on the FB pin due to the output low spikes will pull ⎯R⎯E⎯S⎯E⎯T low. To prevent ⎯R⎯E⎯S⎯E⎯T from generating an unwanted system reset, the FB comparator has a glitch filter to ride out these glitches. The filter time is 20µs for large transients (greater than 150mV) and up to 100µs for small transients. The relationship between glitch filter time and the FB pin transient voltage or FB overdrive is shown in Figure 1. 140 120 GLITCH FILTER TIME (µs) 100 80 60 TA = 25°C ON LOGIC TIMER 0.6V M2 TIMER LTC4216** **ADDITIONAL DETAILS OMITTED FOR CLARITY 4216 F02 40 C1 20 0 0 40 80 120 160 FB OVERDRIVE (mV) 200 Figure 2. Output Voltage Monitor Block Diagram Figure 1. FB Comparator Glitch Filter Time vs FB Overdrive 12 3 Output Voltage Monitor As shown in Figure 2, the output voltage is monitored through a resistive divider, R3 and R4, connected at the FB pin, and a FB comparator with 0.6V threshold. The normal operation of the output voltage monitor after a start-up cycle is shown in Figure 3. At time point 1, when the FB pin voltage falls below 0.6V, the FB comparator output goes high. ⎯R⎯E⎯S⎯E⎯T is pulled low by an internal N-channel switch after a glitch filter delay at time point 2. When the VOUT VFB < 0.6V VFB > 0.6V 2µA TIMER POWER-GOOD DELAY GLITCH FILTER DELAY 4216 F03 RESET Figure 3. Output Voltage Monitor Waveforms in Normal Operation 4216f – + U (1) FB pin voltage rises above 0.6V, the FB comparator output goes low and a new timing cycle starts. After a complete timing cycle at time point 6, ⎯R⎯E⎯S⎯E⎯T is pulled high by the external pull-up resistor, R5. The timer period given by Equation (1) sets the power-good delay for ⎯R⎯E⎯S⎯E⎯T going high. If the FB pin voltage stays above 0.6V for less than a timing cycle at time point 4, the ⎯R⎯E⎯S⎯E⎯T output remains low. Any overcurrent fault detected by the electronic circuit breaker or ⎯F⎯A⎯U⎯L⎯T pin driven low externally during the timing cycle, will also pull the TIMER pin low and ⎯R⎯E⎯S⎯E⎯T output remains low. When the device enters an undervoltage lockout condition or the ON pin voltage drops below 0.4V, ⎯R⎯E⎯S⎯E⎯T is pulled low, ignoring the FB pin voltage. RSENSE VIN R4 SENSEP SENSEN VCC GATE FB R3 R5 M1 W U U + VOUT CLOAD + – µP RESET RESET 4 5 6 VFB < 0.6V VFB > 0.6V 2µA VTMR(TH) 9 LTC4216 APPLICATIO S I FOR ATIO Electronic Circuit Breaker The LTC4216 features an electronic circuit breaker function that protects the external MOSFET against short-circuits or excessive load current conditions on the supply. An external sense resistor connected between SENSEP and SENSEN pins is used to measure the load current. If the voltage across the sense resistor exceeds the circuit breaker trip threshold of 25mV for more than a fault filter delay, the gate of the MOSFET is pulled low, turning it off. The fault filter delay is determined by a capacitor, C3, connected between the FILTER pin and ground as in Equation (2). The FILTER pin sources 60µA pull-up current when the sense voltage across the sense resistor exceeds 25mV. Otherwise, it pulls down with 2.4µA. When the FILTER pin voltage exceeds VFILT(TH) threshold (1.253V), there is an internal 20µs delay before the GATE pulls low and the ⎯F⎯A⎯U⎯L⎯T pin will be pulled low. If no FILTER capacitor is used, the filter fault delay defaults to 20µs. The circuit breaker response time or fault filter delay with the FILTER capacitor, C3, is given by: tCB(TRIP) 1.253V • C 3 = + 20µs 60µA The FILTER capacitor, C3, should be chosen so that the fault filter delay is not too short to trip the circuit breaker as the MOSFET current charges up a large output load capacitance in analog current limit during power-up. It also should not be too long to exceed the safe operating area (SOA) of the external MOSFET. Intermittent overloads may exceed the current limit as in Figure 5, but if the duration is sufficiently short, the FILTER pin voltage may not reach the VFILT(TH) threshold and the device will not shut off. To handle this situation, the FILTER discharges with 2.4µA whenever voltage across the sense resistor is below 25mV. Any intermittent overload with an aggregate duty cycle of more than 4% will eventually trip the circuit breaker. Figure 6 shows the circuit breaker response time in seconds normalized to 1µF as given by Equation (3). The asymmetric charging and discharging of FILTER is a fair gauge of MOSFET heating. 10 U t 1.253 (s / µF ) = C3 (60 • D)– 2.4 (3) Following a circuit breaker trip, the device is latched-off and ⎯F⎯A⎯U⎯L⎯T is pulled low until the fault latch is cleared by pulling the ON pin low (< 0.4V) for at least 100µs. The FILTER pin is pulled low by an internal N-channel switch to discharge the capacitor quickly when the ON pin voltage falls below 0.4V and pulls down with 2.4µA when the ON pin voltage rises above 0.8V to initiate a new start-up cycle. The new timing cycle will not start until the FILTER pin voltage is below 0.2V. The electronic circuit breaker is disabled during the first timing cycle upon start-up and any short-circuit faults will be ignored. A 1.253V VFILTER 60µA 2.4µA B CIRCUIT BREAKER TRIPS NORMAL MODE FAULT MODE 4216 F04 W U U (2) A1 Figure 4. A Continuous Fault Timing B1 A2 B2 A3 B3 25mV/RSENSE ILOAD 2.4µA 1.253V 60µA 60µA 2.4µA VFILTER VGATE 2.4µA 60µA CIRCUIT BREAKER TRIPS CB FAULT CB FAULT CB FAULT Figure 5. Multiple Intermittent Overcurrent Condition 4216f LTC4216 APPLICATIO S I FOR ATIO 1 NORMALIZED RESPONSE TIME (s/µF) t/C3(s/µF) = 1.253/[(60 • D) – 2.4] 0.1 0.01 0 20 40 60 80 OVERLOAD DUTY CYCLE, D (%) 100 4216 F06 Figure 6. Circuit Breaker Filter Response for Intermittent Overload Analog Current Limiting In addition to an electronic circuit breaker, the LTC4216 has included a novel analog current limit (ACL) amplifier that does not require an external compensation capacitor at the GATE pin. The amplifier’s stability is compensated by the large gate input capacitance (CISS) of the external MOSFET used. These MOSFETs usually have CISS ≥ 1nF. However, if the MOSFET’s gate input capacitance (CISS) is too small for loop stability, then connect an external capacitor between the GATE pin and ground to increase the total gate capacitance to ≥ 1nF. As given by Equation (4), the MOSFET current, IACL, is limited to the analog current limit voltage, ΔVACL(TH), 40mV typical, across the sense resistor, RSENSE, connected between SENSEP and SENSEN pins. IACL = ∆VACL(TH) RSENSE The ΔVACL(TH) threshold is 1.6 times higher than the ΔVCB(TH) threshold (25mV typical) to provide dual level current sensing. When the ACL amplifier servos the MOSFET current at ΔVACL(TH) across the sense resistor, it exceeds ΔVCB(TH) threshold causing the FILTER pin to charge C3 with 60µA pull-up. If the condition persists long enough for C3 to reach the VFILT(TH) threshold (1.253V), GATE is pulled low and ⎯F⎯A⎯U⎯L⎯T latched low. U If the voltage across the sense resistor is greater than ΔVACL(TH) during an overload condition, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since the GATE pin voltage overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge the GATE to the threshold of the MOSFET for gate regulation. For mild overload, the ACL amplifier can control the MOSFET current, but in the event of a severe overload, the MOSFET current may overshoot as the MOSFET has large GATE overdrive initially. The GATE is quickly discharged to ground followed by the ACL amplifier taking control. For applications that require very fast analog current limit recovery from the GATE undershoot as it discharges, connect a series resistor, RZ, with an external capacitor, CZ, at the GATE pin as shown in Figure 17. Soft-Start The LTC4216 features a soft-start function that controls the di/dt of the inrush current during power-up. As large output load capacitors are commonly used in low-voltage applications, the normal inrush can be large enough to glitch the load supply. With the soft-start function, the gate of the external MOSFET is allowed to turn on very gradually to control the inrush current flowing into the load capacitor without causing a supply glitch. With an external capacitor, C2, connected between the SS pin and ground, the GATE is servoed by the ACL amplifier to track the rate of SS ramp-up during power-up. There are two slopes in the SS ramp-up profile: 10µA current source pull-up for a normal ramp rate; and 1µA current source pull-up for a slower ramp rate. Both the SS ramp rates are given as follows: Normal SS Ramp Rate: dVSS(NOM) 10µA = dt C2 dVSS(SLOW) 1µA = dt C2 (4) (5) Slower SS Ramp Rate: (6) 4216f W U U 11 LTC4216 APPLICATIO S I FOR ATIO For example, if C 2 = 10nF, dVSS(SLOW) = 0.1V /ms. dt After the initial timing cycle, the SS capacitor is charged by a 10µA current source pull-up and GATE is held low by the ACL amplifier. As SS ramps up, the ACL amplifier releases the GATE when it crosses its input offset voltage. At this instant, SS switches the pull-up current from 10µA to 1µA for a slower ramp rate. GATE continues to charge up with 20µA pull-up before the MOSFET reaches its turn-on threshold voltage. When the external MOSFET is first turned on, there is always a current step due to the high gain of the MOSFET. The slower SS ramp rate allows the gate of the external MOSFET to be turned on with a smaller inrush current step. When the external MOSFET is turned on, load current starts to flow through the sense resistor, developing a voltage drop across it. This allows the ACL amplifier to servo the GATE to the voltage across the sense resistor, thus controlling the rate of change of the inrush current. At this instant, SS switches back from 1µA to 10µA current source pull-up for a normal ramp rate. GATE continues to ramp up as the ACL amplifier servos to track the SS ramp rate. At the end of SS ramp-up when SS reaches its final value, GATE is servoed to ΔVACL(TH) across the sense resistor. If the voltage across the sense resistor drops below ΔVACL(TH) due to a falling load current, the ACL amplifier shuts off and GATE ramps further by a 20µA pull-up. SS is pulled low under any of the following conditions: in VCC undervoltage lockout condition, during the first timing cycle or when the circuit breaker fault times out. If the soft-start function is not used, leave the SS pin unconnected. Inrush Control with GATE Capacitor For applications not requiring soft-start to control the di/dt of the inrush current during power-up, an alternative dVSS(NOM) = 1V /ms and dt 12 U way to limit the inrush is to control the GATE pin voltage slew rate by connecting an external capacitor, C4, from the GATE pin to ground, as shown in Figure 7. The GATE slew rate is given by: 20µA dVGATE = dt C 4 + C GATE (7) where CGATE is the associated parasitic GATE capacitance due to the external MOSFET’s gate input capacitance, CISS. The inrush current flowing into the load capacitor, CLOAD, is limited to: IINRUSH = C LOAD • dVGATE C LOAD = • 20µA dt C 4 + C GATE (8) For example, if CLOAD = 4700µF, C4 = 33nF and CGATE = 5nF, IINRUSH = 2.5A. If CLOAD is very large and IINRUSH exceeds the analog current limit, the GATE is servoed to control the inrush current to ΔVACL(TH)/RSENSE. One limitation with this technique is that it slows down the system turn-on and turn-off time by adding a capacitor at the GATE pin. Should this technique be used, C4 ≤ 50nF is recommended. However, having an external gate capacitor helps to eliminate voltage spikes coupled through the MOSFET’s drain-to-gate capacitance to the GATE pin when the supply power is first applied. VIN RSENSE M1 W U U + C4 R4 VOUT CLOAD SENSEP SENSEN GATE LTC4216** FB R3 **ADDITIONAL DETAILS OMITTED FOR CLARITY 4216 F07 Figure 7. Inrush Control with External Gate Capacitor 4216f LTC4216 APPLICATIO S I FOR ATIO Normal Power-Up and Power-Down Figure 8 illustrates the timing diagram for a normal powerup sequence in the case where a printed circuit board is inserted into a live backplane. At time point 1, the bias supply (VCC) ramps up and enables the device when the supply voltage rises above the undervoltage lockout threshold (2.12V). At time point 2, SENSEP supply, together with the ON pin, ramp up and start the first timing cycle when the ON pin voltage exceeds 0.8V. The TIMER capacitor is allowed to ramp up with 2µA pull-up once all these conditions are met: GATE < 0.2V, FILTER < 0.2V, TIMER < 0.2V, SS < 0.2V. At time point 3, TIMER reaches the VTMR(TH) threshold and the first timing cycle terminates. The electronic circuit breaker is enabled and TIMER capacitor is quickly discharged. At time point 4 checks are made for TIMER, GATE, FILTER and SS < 0.2V, ∆VSENSE below 25mV and ⎯F⎯A⎯U⎯L⎯T high before a GATE ramp-up cycle begins. GATE is held low by the analog current limit amplifier as SS capacitor ramps up with a 10µA current source. SS switches to 1µA pull-up for a slower ramp rate when it crosses the input offset voltage of the ACL amplifier. At this time point, the ACL amplifier releases the GATE and allows it to ramp up with a 20µA pull-up. At time point 6, when the GATE voltage reaches the turn-on threshold of the external MOSFET, current begins flowing into the load capacitor. The MOSFET current level at this time point is controlled by the ACL amplifier and the GATE ramp is slowed down. SS switches the pull-up current from 1µA to 10µA for a normal ramp rate. Between time points 6 and 7, the ACL amplifier servos the GATE voltage to track the SS ramp rate, limiting the slew rate of the load current. At time point 7, SS reaches its final value and GATE continue to ramp up with the 20µA pull-up if the load current is not in analog current limit. At time point 8, the FB pin voltage exceeds 0.6V and the second timing cycle is started. When the conditions of TIMER < 0.2V, ∆VSENSE < 25mV and ⎯F⎯A⎯U⎯L⎯T high are met, the TIMER capacitor is allowed to ramp up. When TIMER reaches the VTMR(TH) threshold at time point 9, ⎯R⎯E⎯S⎯E⎯T goes high, indicating to the system controller that power is good. After this, the TIMER is held low. U When the ON pin voltage falls below (VON(TH) – ΔVON(HYST)) threshold (0.72V), it initiates a power-down sequence. At time point 11, GATE is discharged by both the ACL amplifier and a 100µA current source pull-down, causing the output voltage to fall gradually. When the FB pin voltage falls below 0.6V at time point 12, ⎯R⎯E⎯S⎯E⎯T goes low after a glitch filter delay (see the section on FB glitch filtering), indicating that power is bad. When the ON pin voltage falls below 0.4V, the device resets and GATE is pulled low by a strong pull-down device. Soft-Start with Analog Current Limiting When a very large output load capacitor is connected during soft-start, the GATE voltage is servoed to regulate the inrush current to ΔVACL(TH)/RSENSE. This is illustrated in the timing diagram of Figure 9. After the initial timing cycle, the GATE is allowed to ramp up, tracking the SS ramp rate between time points 5 and 8. At time point 7, when the load current builds up as the GATE pin voltage increases, the voltage across the sense resistor rises above ΔVCB(TH) (25mV typical). The FILTER capacitor starts to charge up by a 60µA current source pull-up. At time point 8, SS reaches its final value at the end of SS ramp cycle. This allows the GATE to be regulated by the ACL amplifier at ΔVACL(TH) (40mV typical) across the sense resistor, RSENSE, limiting the inrush to: ILIMIT = 40mV RSENSE (9) The FILTER pin voltage continues to rise as the load capacitor charges up with the limited load current. At time point 9, the FB pin voltage exceeds 0.6V, but the second timing cycle is not allowed to start as the voltage across the sense resistor exceeds 25mV. At time point 10, the load current falls as the load capacitor is near full charge and the voltage across the sense resistor drops below 40mV. The analog current limit loop shuts off and the GATE ramps further till its final value. The FILTER capacitor discharges by a 2.4µA pull-down when the voltage across the sense resistor falls below 25mV at time point 11. The duration between time points 7 and 11 must be shorter than one circuit breaker delay, as given by Equation (2), to avoid a fault time-out during GATE ramp-up for very large load 4216f W U U 13 LTC4216 APPLICATIO S I FOR ATIO capacitors. A second timing cycle starts at time point 11 when the FB pin voltage exceeds 0.6V and the voltage across the sense resistor drops below 25mV. ⎯R⎯E⎯S⎯E⎯T goes ELECTRONIC CIRCUIT BREAKER ARMED CHECK FOR GATE, FILTER, TIMER, SS < 0.2V 12 3 4 CHECK FOR GATE, FILTER, TIMER, SS < 0.2V AND FAULT HIGH START 2ND TIMING CYCLE START (CHECK TIMER < 0.2V AND GATE FAULT HIGH) RAMP 56 78 9 VCC SENSEP ON 0.8V VTMR(TH) TIMER 2µA 2µA SS 10µA 10µA 1µA TRACKS SS RAMP GATE (VGATE – VOUT) > VGS(TH) VOUT RESET 4216 F08 PLUG-IN CYCLE FIRST TIMING CYCLE Figure 8. Normal Power-Up/Power-Down Sequence 14 U high at the end of the second timing cycle (time point 12) when TIMER reaches the VTMR(TH) threshold. ON GOES LOW RESET PULLED LOW DUE TO POWER BAD IN RESET MODE 10 11 12 13 RESET GOES HIGH 0.72V 0.4V VTMR(TH) 20µA POWER GOOD VFB > 0.6V POWER BAD VFB < 0.6V POWER-GOOD DELAY SECOND TIMING CYCLE 4216f W U U LTC4216 APPLICATIO S I FOR ATIO CHECK FOR GATE, FILTER, TIMER, SS < 0.2V AND FAULT HIGH ELECTRONIC CIRCUIT BREAKER ARMED CHECK FOR GATE, FILTER, TIMER, SS < 0.2V 12 3 4 56 78 FILTER RAMPS UP WHEN (VSENSEP – VSENSEN) > 25mV VCC SENSEP 0.8V ON VTMR(TH) TIMER 2µA 2µA SS 10µA IN REGULATION TRACKS SS RAMP GATE (VGATE – VOUT) > VGS(TH) VOUT ILOAD (VSENSEP – VSENSEN) > 25mV VFILT(TH) 60µA FILTER RESET 4216 F09 PLUG-IN CYCLE FIRST TIMING CYCLE Figure 9. Normal Power-Up Sequence (with Analog Current Limiting) U OUTPUT IN ANALOG CURRENT LIMIT, (VSENSEP – VSENSEN) = 40mV 2ND TIMING CYCLE CANNOT START WITH OUTPUT IN ANALOG CURRENT LIMIT OUTPUT NO LONGER IN CURRENT LIMIT 9 10 11 RESET GOES HIGH 12 ON GOES LOW (ON < 0.72V) 13 14 15 RESET PULLED LOW DUE TO POWER BAD IN RESET MODE (ON < 0.4V) 16 0.72V 0.4V VTMR(TH) 10µA 1µA 20µA POWER GOOD VFB > 0.6V LOAD CURRENT REGULATING AT 40mV/RSENSE (VSENSEP – VSENSEN) < 25mV 2.4µA POWER BAD VFB < 0.6V POWER-GOOD DELAY SECOND TIMING CYCLE 4216f W U U 15 LTC4216 APPLICATIO S I FOR ATIO Power-Up into an Output-Short Figure 10 shows the timing diagram in the case when the output is a dead short during power-up. As GATE ramps up at time point 6, the MOSFET current increases due to the output short causing the voltage drop across the sense resistor to rise above 25mV. FILTER sources 60µA, charging the external capacitor. At time point 7, GATE regulates to limit the output current to 40mV/RSENSE. If the output continues to be in analog current limit when the FILTER pin voltage reaches its threshold (1.253V) at time point 8, the circuit breaker trips and GATE is pulled low. The device latches-off and ⎯F⎯A⎯U⎯L⎯T is pulled low, indicating a fault condition. The FILTER capacitor discharges through a 2.4µA pull-down until the device resets. Resetting the Electronic Circuit Breaker When the LTC4216’s electronic circuit breaker is tripped during a fault condition, ⎯F⎯A⎯U⎯L⎯T is asserted low and the ⎯R⎯E⎯S⎯E⎯T, SS and GATE pins are all pulled to ground. This is shown in the timing diagram of Figure 11. The LTC4216 remains latched-off until the external fault is cleared. To clear the internal fault latch and restart the device, pull the ON pin low (< 0.4V) at time point 4 for at least 100µs, after which the ⎯F⎯A⎯U⎯L⎯T will go high at time point 5. Toggling the ON pin from low to high (> 0.8V) initiates a new start-up cycle. 1 ON SS 0.8V 10µA 10µA 1µA GATE REGULATING FPD 40mV SENSEP-SENSEN VTMR(TH) TIMER 2µA VFILT(TH) 25mV GATE FPD SS 23 45 67 8 GATE VOUT TRACKS SS RAMP VGATE – VOUT < VGS(TH) FILTER 60µA FAULT FILTER DELAY FAULT RESET RESET 4216 F10 Figure 10. Power-Up into an Output-Short and Circuit Breaker Trips 16 U Sense Resistor Considerations The circuit breaker trip threshold of 25mV and the value of the sense resistor, RSENSE, connected between the SENSEP and SENSEN pins, determine the trip current level as given by Equation (10). If the fault current level exceeds the analog current limit, the current is limited to a value given by Equation (11). Should the overload condition exist for more than one fault filter delay as given by Equation (2), the circuit breaker trips and the device is latched-off. ITRIP(CB) = IACL = ∆VCB(TH) 25mV = RSENSE RSENSE (10) ∆VACL(TH) 40mV = RSENSE RSENSE (11) For a new circuit design, the sense resistor value is first calculated from the maximum operating load current under normal conditions and the minimum circuit breaker trip threshold. This is given by: RSENSE = ∆VCB(TH,MIN) 21.5mV = ILOAD(MAX) ILOAD(MAX) CIRCUIT BREAKER TRIPS AND LATCHED-OFF MILD OVERCURRENT 1 ON 23 0.4V RESET PULLED LOW DUE TO POWER BAD FAULT LATCH RESET 4 5 W U U (12) VOUT ILOAD(MAX) = 5A) and IINRUSH(MIN) = 7.9A respectively. Equation (19) gives C3 = 10nF. To account for errors in C3, FILTER current (60µA) and FILTER threshold (1.253V), the calculated value should be multiplied by 1.5, giving the nearest standard value of C3 = 18nF. If a short-circuit occurs, a current of up to ISHORTCIRCUIT(MAX) = 12.1A will flow through the MOSFET for 400µs as dictated by C3 = 18nF in Equation (2). The MOSFET must be selected based on this criterion and checked against the SOA curve. VCC Supply RC Network The LTC4216 has two separate pins, VCC and SENSEP, for supply input and sensing: 1. VCC pin for powering the internal circuitry. 2. SENSEP pin, together with the SENSEN pin, for sensing the current flowing from the load supply through the external sense resistor and N-channel MOSFET to the output load. In most hot swap devices, VCC and SENSEP are one common pin, providing the device’s supply and external MOSFET’s current sensing. However, supply dips due to output-shorts can potentially trigger the device into an undervoltage lockout condition, causing the device to disable and its internal latches to reset. As bypass capacitors are not allowed on the powered supply side of the external MOSFET switch residing on 4216f W U U (16) (18) LTC4216 APPLICATIO S I FOR ATIO the plug-in boards, the LTC4216 provides two separate pins for bias supply input and load supply sensing. With this configuration, an RC network, RY and CY, shown in Figure 13, can be used with the VCC pin to ride out supply glitches during output-shorts or adjacent board shorts. The RC network shown has a time constant of 7µs and this is good enough for the supply to ride out most supply glitches, preventing the device from entering an undervoltage lockout condition unnecessarily or losing supply temporarily. When VCC and SENSEP pins are connected together, the RY value should be chosen such that VCC pin voltage is lower than SENSEP by 70mV; otherwise, part of VCC pin current will be diverted through SENSEP pin. This unique scheme of separating the device’s supply input and sensing also provides the flexibility of operating the load supply from ground to its supply rail with a minimum bias supply voltage of 2.3V. For proper operation, the load supply is required to be equal to or less than the bias supply voltage (maximum 6V). Supply Transients Protection There are two methods used in most applications to eliminate supply transients: 1. Transient voltage suppressor to clip the transient to a safe level. 2. Snubber (series RC) network. For applications with load supply voltages of 3.3V or higher, the ringing and overshoot during hot-swapping or output-shorts can easily exceed the absolute maximum rating of the LTC4216. To minimize the risk, a transient voltage suppressor and snubber network are highly recommended at the SENSEP pin. For applications with load supply voltages of 2.5V or below, usually a snubber network is adequate to reduce the supply ringing. Figure 13 shows the connections of the supply transient protection devices, Z1, RX and CX, around the LTC4216. The RC network, RY and CY, at the VCC pin also serve as a snubber circuit for the load supply (VIN). On the PCB layout, these transient protection devices should be mounted very close to the LTC4216’s load U supply rail using short lead lengths to minimize lead inductance. VIN 5V RY 22Ω RX 10Ω VCC RSENSE M1 VOUT 5V R4 SENSEP SENSEN GATE FB R3 LTC4216** Z1 CX 0.1µF GND CY 0.33µF GND **ADDITIONAL DETAILS OMITTED FOR CLARITY Z1: SMAJ6.0A 4216 F13 W U U + TIMER C1 FILTER C2 SS C3 CLOAD Figure 13. Connecting Transient Protection Devices to the LTC4216’s Load Supply Rail Staggered Pins Connections The LTC4216 can be used on either the backplane side of the connector or a printed circuit board, and examples for both are shown in Figure 14 and 15. Printed circuit board edge connectors with staggered pins are recommended as the insertion and removal of circuit boards will sequence the pin connections. Supplies (VCC and SENSEP) and ground connections on the printed circuit board should be wired to the long pins or blades of the edge connector. Control signal (ON) and status signals (⎯R⎯E⎯S⎯E⎯T and ⎯F⎯A⎯U⎯L⎯T) passing through the edge connector should be wired to short pins or blades. Backplane and PCB Connection Sensing The LTC4216’s ON pin can be used in various ways to detect whether the printed circuit board is seated properly in the backplane connector before the LTC4216 begins a start-up cycle. An example is shown in Figure 14, in which the LTC4216 is mounted on the PCB and the R1/R2 resistive divider is connected to the ON pin. On the edge connector, R2 is wired to a short pin. Before the connectors are mated, the ON pin is held low by R1, keeping the LTC4216 in an off state. When the connectors are mated, the resistive divider is connected to the load supply (VIN) and the ON pin voltage rises above 0.8V, turning the LTC4216 on. 4216f 19 LTC4216 APPLICATIO S I FOR ATIO An example with LTC4216 mounted on the backplane is shown in Figure 15. In this case, the NPN transistor, Q1, and two resistors, R7 and R8, form the PCB connection sensing circuit with the ON pin. With the PCB out of the backplane connector, Q1 base is tied to load supply through R7, turning Q1 on and pulling the LTC4216’s ON pin low. The base of Q1 is also wired to the backplane connector pin. When the PCB is inserted into the backplane, Q1 base is grounded through a short pin connection on the PCB. This turns off Q1 and the LTC4216’s ON pin is allowed to pull high to the load supply through R8, turning it on. In the previous examples, the PCB connection sensing circuits are not wired with interrupt capability from the system controller. As shown in Figure 16, adding logiclevel discrete N-channel MOSFETs, M2 and M3, and a couple of resistors allow interrupt control to the sensing BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VCC 3.3V VIN 1.5V LONG RY 22Ω RX 10Ω CX 100nF SHORT R2 3.3k 1% R1 C4 20k 10nF 1% CY 330nF RSENSE 0.004Ω M1 Si4864DY R4 13k 1% R3 10k 1% 12 1 VOUT 1.5V 5A LONG GND LONG PCB CONNECTION SENSING Figure 14. Single Channel 1.5V Hot Swap Controller VIN 3.3V Z1 CX 100nF RX 10Ω R7 10k R8 10k CY 330nF 11 10 9 8 VCC SENSEP SENSEN GATE 2 ON LTC4216 6 GND PCB CONNECTION SENSING Q1 Z1: SMAJ6.0A Q1: MMBT3904 Figure 15. Hot Swap Controller on Backplane with Staggered Pin Connections 4216f 20 U circuit. M2 is held on by its gate, pulling high through R8 to the load supply until the PCB is mated firmly to the backplane connector. A low logic-level for both the ⎯⎯ ⎯⎯ ON/RST and ON/OFF signals turns M2 and M3 off, allowing the ON pin to be pulled high and turning LTC4216 on. A high logic-level for the ⎯O⎯N/OFF signal turns off the device and pulls the GATE low. The device is reset by pulling the ⎯O⎯N/RST signal high. 5V Hot Swap Application Figure 17 shows a hot swap application circuit with VCC and SENSEP pins connected together to a 5V load supply (VIN). The resistive divider, R1/R2, sets the undervoltage threshold for the load supply and allows the system to start up only after the supply voltage rises above 4V. The resistive divider, R3/R4, monitors VOUT and signals the + R6 10k 8 VCC SENSEP SENSEN GATE 2 LTC4216 FAULT TIMER 4 C1 10nF SS 5 C2 10nF FILTER 3 C3 68nF GND RESET 6 4216 F14 W U U 11 10 9 CLOAD 4700µF FB 7 R5 10k ON µP LOGIC FAULT RESET RY 22Ω RSENSE 0.004Ω M1 Si4864DY R6 10k FAULT 12 R5 10k RESET 1 7 R3 10k 1% BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG + LONG SHORT CLOAD 1000µF FAULT VOUT 3.3V 5A SHORT SHORT SHORT 4216 F15 R4 39.2k 1% RESET TIMER 4 C1 10nF SS 5 FILTER 3 C2 4.7nF C3 33nF FB R9 100k LTC4216 APPLICATIO S I FOR ATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VCC 5V LONG CY 330nF LONG Z1 R8 10k R3 20k 1% R2 M2 4.42k 1% R1 M3 5.62k 1% PCB CONNECTION SENSING CX RX 100nF 10Ω 11 10 9 8 VCC SENSEP SENSEN GATE RY 22Ω RSENSE 0.004Ω M1 Si4864DY R5 39.2k 1% 7 R4 10k 1% 12 1 Z1: SMAJ6.0A M2, M3: 2N7002K R7 10k VOUT 3.3V 5A VIN 3.3V SHORT ON/RST SHORT ON/OFF SHORT GND LONG Figure 16. PCB Connection Sensing with ON/OFF Control BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG Z1 RX 10Ω CX 100nF R2 80.6k 1% CY 330nF 11 10 9 8 VCC SENSEP SENSEN GATE 2 LTC4216 FAULT SS 5 C1 10nF C2 4.7nF FILTER 3 C3 22nF 4216 F17 VIN 5V SHORT GND LONG Z1: SMAJ6.0A Figure 17. 5V Hot Swap Application ⎯RE⎯S⎯E⎯T high when VOUT rises above 4.5V. Transient volt⎯ age suppressor, Z1, and snubber network, RX and CX, connected at SENSEP pin are highly recommended to protect the 5V supply system from ringing and voltage spikes during a fault condition. The RC network, RY and CY, connected at the VCC pin, allows the LTC4216 bias supply to ride out supply glitches during a fault condition or adjacent board shorts. Auto-Retry after a Fault As shown in Figure 18, the LTC4216 can be configured to automatically retry after a fault condition by connecting both the ⎯F⎯A⎯U⎯L⎯T and ON pins together with an RC network. The network has a pull-up resistor, RAUTO, tied to the load supply (VIN) and an external capacitor, CAUTO, connected to ground. The auto-retry circuit will attempt to restart U + CLOAD 1000µF 2 ON FB LTC4216 FAULT TIMER 4 C1 10nF SS 5 C2 4.7nF FILTER 3 C3 33nF GND RESET 6 R6 10k µP LOGIC FAULT RESET 4216 F16 W U U RY 22Ω RSENSE 0.004Ω M1 Si4864DY CZ RZ 10nF 100Ω R4 64.9k 1% 7 R3 10k 1% 12 1 R6 10k + CLOAD 470µF VOUT 5V 5A FB R5 10k ON µP LOGIC FAULT RESET R1 20k 1% TIMER 4 GND RESET 6 the LTC4216 after a circuit breaker trip, as shown in the timing diagram of Figure 19. In addition to the cooling cycle provided by the TIMER period during auto-retry sequence, the RC time constant for the ON pin voltage to reach 0.8V provides additional turn-off time to prevent the external MOSFET from overheating. The auto-retry duty cycle is given by: Duty Cycle ≈ where tTIMER = TIMER period as given by Equation (1); tOFF = time taken to charge the capacitor, CAUTO, from ⎯F⎯A⎯U⎯L⎯T VOL to VON(TH) threshold (0.8V). As there is an internal 5µA current source pull-up at the ⎯F⎯A⎯U⎯L⎯T pin, it 4216f tSS + tFILTER • 100% tOFF + tTIMER + tSS + tFILTER (20) 21 LTC4216 APPLICATIO S I FOR ATIO RAUTO • C AUTO •(VON(TH) − VOL ) (VIN – VON(TH) ) + RAUTO • 5µA complicates the equation for tOFF. This is approximately given by: tOFF ≈ tFILTER = circuit breaker response time as given by Equation (2); tSS = approximated time taken to charge the soft-start capacitor, C2, from 0V to its final value (1.65V) by 10µA current source only. BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG Z1 RAUTO 200k R5 10k RX 10Ω CX 100nF CY 330nF VIN 5V RESET SHORT CAUTO 1µF GND LONG Z1: SMAJ6.0A Figure 18. Auto-Retry Application CHECK FOR GATE, FILTER, TIMER, SS < 0.2V AND FAULT HIGH CHECK FOR GATE, FILTER, TIMER, SS < 0.2V 1 SENSEP 0.8V ON/FAULT 10µA 1µA 10µA TRACKS SS RAMP GATE (VGATE – VOUT) > VGS(TH) GATE REGULATING 2 ELECTRONIC CIRCUIT BREAKER ARMED 3 4 5 6 789 10 SS SENSEP–SENSEN VTMR(TH) TIMER 2µA FILTER tOFF tTIMER tSS Figure 19. Auto-Retry Timing 4216f 22 U (21) For the component values shown, the external RC time constant is set at 0.2 second, tTIMER = 62ms, tOFF = 25ms at VIN = 5V, tSS = 1.6ms, tFILTER = 480µs and the auto-retry duty cycle is 2.3%. The auto-retry duty cycle can be further reduced by increasing both the tTIMER delay and the RC delay. As an example, increasing the TIMER capacitor, C1, value from 100nF to 330nF, and RAUTO value from 200k to 470k reduces the duty cycle to 0.8%. RSENSE 0.004Ω RY 22Ω 11 10 9 8 VCC SENSEP SENSEN GATE 1 12 2 RESET FAULT ON GND 6 LTC4216 M1 Si4864DY R4 64.9k 1% FB 7 R3 10k 1% W U U + VOUT 5V CLOAD 5A 470µF FILTER SS TIMER 4 5 3 C1 C2 C3 100nF 4.7nF 22nF 4216 F18 FILTER RAMPS UP WHEN (VSENSEP–VSENSEN) >25mV OUTPUT IN ANALOG CURRENT LIMIT ON/FAULT PULLED LOW DEVICE RESET 1ST TIMING CYCLE RESTART 11 12 13 14 0.8V 0.4V VOL 40mV 25mV VTMR(TH) 2µA VFILT(TH) 60µA tFILTER tRST(ONLO) 2.4µA tTIMER tOFF 4216 F19 LTC4216 PACKAGE DESCRIPTIO U DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695) NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.65 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 3.30 ± 0.05 (2 SIDES) 0.50 BSC 4.00 ± 0.10 (2 SIDES) R = 0.20 TYP 3.00 ± 0.10 (2 SIDES) 1.70 ± 0.10 (2 SIDES) PIN 1 NOTCH (UE12/DE12) DFN 0603 3.50 ± 0.05 1.70 ± 0.05 2.20 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 0.38 ± 0.10 12 7 PIN 1 TOP MARK (NOTE 6) 0.200 REF 0.75 ± 0.05 6 0.25 ± 0.05 3.30 ± 0.10 (2 SIDES) 1 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.254 (.010) GAUGE PLANE DETAIL “A” 0° – 6° TYP 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 12345 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) 1.10 (.043) MAX 0.86 (.034) REF NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS) 0603 4216f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC4216 TYPICAL APPLICATIO VIN 5V BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG Z1 RX 10Ω CX 100nF R5 10k RESET GND Figure 20. LTC4216CMS with Gate Capacitor for Slew Rate Control RELATED PARTS PART NUMBER LTC1421 LTC1422 LTC1642 LTC1645 LTC1647-1/LTC1647-2/ LTC1647-3 LTC4210 LTC4211 LTC4212 LTC4214 LT4220 LTC4221 LTC4230 DESCRIPTION Dual Channels, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Dual Channel, Hot Swap Controller Dual Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Negative Voltage, Hot Swap Controller Positive and Negative Voltage, Dual Channels, Hot Swap Controller Dual Hot Swap Controller/Sequencer Triple Channels, Hot Swap Controller COMMENTS Operates from 3V to 12V, Supports -12V, SSOP-24 Operates from 2.7V to 12V, SO-8 Operates from 3V to 16.5V, Overvoltage Protection up to 33V, SSOP-16 Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14 Operates from 2.7V to 16.5V, SO-8 or SSOP-16 Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 Operates from –6V to –16V, MSOP-10 Operates from ±2.7V to ±16.5V, SSOP-16 Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20 24 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 ● ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005 U RSENSE 0.01Ω M1 Si9426DY R4 64.9k 1% + VOUT 5V CLOAD 2A 470µF CY 330nF RY 22Ω R6 10Ω C4 22nF VCC SENSEP SENSEN GATE SHORT R2 10k ON TIMER C1 10nF LONG Z1: SMAJ6.0A FILTER GND C3 68nF RESET LTC4216 FB R3 10k 1% SHORT 4216 F20 4216f LT/TP 0205 1K • PRINTED IN USA