LTC4219CDHC-12-TRPBF

LTC4219 5A Integrated Hot Swap Controller FEATURES n n n n n n n n n n DESCRIPTION The LTC®4219 is an integrated solution for Hot Swap™ applications that allows a board to be safely inserted and removed from a live backplane. The part integrates a Hot Swap controller, power MOSFET and current sense resistor in a single package for small form factor applications. The LTC4219 provides separate inrush current control and a 10% accurate 5.6A current limit with foldback current limiting. The current limit threshold can be adjusted dynamically using an external pin. Additional features include a current monitor output that amplifies the sense resistor voltage for ground referenced current sensing and a MOSFET temperature monitor output. Thermal limit and power good monitoring are also provided. The power good detection level and foldback current limit profile are internally preset for 5V (LTC4219-5) and 12V (LTC4219-12) applications. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Small Footprint 33mΩ MOSFET with RSENSE Available in Preset 12V and 5V Versions Adjustable, 10% Accurate Current Limit Current and Temperature Monitor Outputs Overtemperature Protection Adjustable Current Limit Timer Before Fault Power Good and Fault Outputs Adjustable Inrush Current Control Available in 16-Lead 5mm × 3mm DFN Packages APPLICATIONS n n n RAID Systems Server I/O Cards Industrial TYPICAL APPLICATION 12V, 5A Card Resident Application 12V VDD OUT 12V LTC4219DHC-12 10k EN1 EN2 TIMER INTVCC 0.1μF GND PG 10k FLT ISET IMON 20k ADC 4219 TA01a Power-Up Waveforms + 330μF 12V VOUT 12V 5A VIN 10V/DIV IIN 0.1A/DIV VOUT 10V/DIV PG 10V/DIV 20ms/DIV 4219 TA01b 4219f 1 LTC4219 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW VDD EN1 EN2 TIMER INTVCC GND OUT OUT 1 2 3 4 5 6 7 8 17 SENSE 16 VDD 15 ISET 14 IMON 13 FB 12 FLT 11 PG 10 GATE 9 OUT Supply Voltage (VDD) ................................. –0.3V to 28V Input Voltages FB, EN1, EN2 ......................................... –0.3V to 12V TIMER................................................... –0.3V to 3.5V SENSE .............................VDD – 10V or – 0.3V to VDD Output Voltages ISET, IMON ................................................. –0.3V to 3V PG, FLT .................................................. –0.3V to 35V OUT ............................................ –0.3V to VDD + 0.3V INTVCC .................................................. –0.3V to 3.5V GATE (Note 3) ........................................ –0.3V to 33V Operating Temperature Range LTC4219C ................................................ 0°C to 70°C LTC4219I.............................................. –40°C to 85°C Junction Temperature (Notes 4, 5)........................ 125°C Storage Temperature Range................... –65°C to 150°C DHC PACKAGE 16-LEAD (5mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W θJA = 43°C/W EXPOSED PAD SOLDERED, OTHERWISE θJA = 140°C/W ORDER INFORMATION LEAD FREE FINISH LTC4219CDHC-12#PBF LTC4219IDHC-12#PBF LTC4219CDHC-5#PBF LTC4219IDHC-5#PBF TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION 16-Lead (5mm × 3mm) Plastic DFN 16-Lead (5mm × 3mm) Plastic DFN 16-Lead (5mm × 3mm) Plastic DFN 16-Lead (5mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C LTC4219CDHC-12#TRPBF 421912 LTC4219IDHC-12#TRPBF 421912 LTC4219CDHC-5#TRPBF LTC4219IDHC-5#TRPBF 42195 42195 Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4219f 2 LTC4219 ELECTRICAL CHARACTERISTICS SYMBOL VDD IDD VDD(UVL) VOUT(PGTH) ΔVOUT(PGHYST) IOUT PARAMETER Input Supply Range Input Supply Current Input Supply Undervoltage Lockout Output Power Good Threshold Output Power Good Hysteresis OUT Pin Leakage Current MOSFET On, No Load VDD Rising LTC4219-12, VOUT Rising LTC4219-5, VOUT Rising LTC4219-12 LTC4219-5 VOUT = VGATE = 0V, VDD = 15V VOUT = VGATE = 12V, LTC4219-12 VOUT = VGATE = 5V, LTC4219-5 ΔVGATE/Δt RON ILIM(TH) GATE Pin Turn-On Ramp Rate MOSFET + Sense Resistor On Resistance Current Limit Threshold VFB = 1.23V VFB = 0V VFB = 1.23V, RSET = 20kΩ Inputs IIN RFB VTH ΔVEN(HYST) ΔVFB(HYST) RISET Outputs VINTVCC VOL IOH VTIMER(H) VTIMER(L) ITIMER(UP) ITIMER(DN) ITIMER(RATIO) AIMON IOFF(IMON) IGATE(UP) IGATE(DN) IGATE(FST) INTVCC Output Voltage PG, FLT Pin Output Low Voltage PG, FLT Pin Input Leakage Current TIMER Pin High Threshold TIMER Pin Low Threshold TIMER Pin Pull-Up Current TIMER Pin Pull-Down Current TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) IMON Pin Current Gain IMON Pin Offset Current Gate Pull-Up Current Gate Pull-Down Current Gate Fast Pull-Down Current IOUT = 5A IOUT = 330mA Gate Drive On, VGATE = VOUT = 12V Gate Drive Off, VGATE = 18V, VOUT = 12V Fast Turn Off, VGATE = 18V, VOUT = 12V VDD = 5V, 15V ILOAD = 0mA, –10mA IOUT = 2mA VOUT = 30V VTIMER Rising VTIMER Falling VTIMER = 0V VTIMER = 1.2V l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. CONDITIONS l l l l l l l l l l l l l l l l l l l l l l MIN 2.9 TYP MAX 15 UNITS V mA V V V mV mV μA μA μA V/ms mΩ A A A μA kΩ kΩ V mV mV kΩ V V μA V V μA μA % μA/A μA μA μA mA DC Characteristics 1.6 2.65 10.2 4.2 127 53 50 26 0.15 15 5.0 1.2 2.6 2.73 10.5 4.35 170 71 0 70 36 0.3 33 5.6 1.5 2.9 0 13 20 1.21 50 10 19 2.8 18 29 1.235 80 20 20 3.0 0.4 0 1.2 0.1 –80 1.4 1.6 18.5 –19 190 1.235 0.21 –100 2 2 20 0 –24 250 140 3 2.85 10.8 4.5 213 89 ±150 90 46.5 0.55 50 6.1 1.8 3.3 ±1 23 37 1.26 110 30 21 3.2 0.8 ±10 1.28 0.3 –120 2.6 2.7 21.5 ±4.5 –29 340 EN1, EN2 Pin Input Current FB Pin Input Resistance EN1, EN2, FB Pin Threshold Voltage EN1, EN2 Pin Hysteresis FB Pin Power Good Hysteresis ISET Pin Output Resistor VIN = 1.2V LTC4219-12 LTC4219-5 VIN Rising 4219f 3 LTC4219 ELECTRICAL CHARACTERISTICS SYMBOL tPHL(GATE) tPHL(ILIM) tD(ON) tD(CB) PARAMETER Input High (EN1, EN2) to Gate Low Propagation Delay Short Circuit to Gate Low Turn-On Delay Circuit Breaker Filter Delay Time (Internal) AC Characteristics VGATE < 16.5V Falling VFB = 0, Step ISENSE to 3A, VGATE < 16.5V Falling Step VEN1 and VEN2 to 0V, VGATE > 13V VFB = 0V, Step ISENSE to 3A l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. CONDITIONS MIN TYP 8 1 50 1.5 100 2 MAX 10 5 150 2.7 UNITS μs μs ms ms Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above OUT. Driving this pin to voltages beyond the clamp may damage the device. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: TJ = TA + (PD • 43°C/W) TYPICAL PERFORMANCE CHARACTERISTICS IDD vs VDD 2.0 3.5 3.0 1.8 85°C IDD (mA) 1.6 25°C 1.4 –40°C 1.2 INTVCC (V) 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 VDD (V) 20 25 30 4219 G01 TA = 25°C, VDD = 12V unless otherwise noted. EN1, EN2 Low Threshold vs Temperature 1.234 INTVCC Load Regulation VDD = 5V UV LOW-HIGH THRESHOLD (V) 1.232 VDD = 3.3V 1.230 1.228 1.0 0 –2 –4 –8 ILOAD (mA) –6 –10 –12 –14 1.226 –50 –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G03 4219 G02 4219f 4 LTC4219 TYPICAL PERFORMANCE CHARACTERISTICS EN1, EN2 Hysteresis vs Temperature 0.10 TIMER PULL-UP CURRENT (μA) –110 CURRENT PROPAGATION DELAY (μs) TA = 25°C, VDD = 12V unless otherwise noted. Current Limit Delay (tPHL(ILIM) vs Overdrive) 1000 Timer Pull-Up Current vs Temperature –105 100 UV HYSTERESIS (V) 0.08 –100 10 0.06 –95 1 0.04 –50 –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G04 –90 –50 0.1 –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G05 0 20 10 OUTPUT CURRENT (A) 30 4219 G06 Current Limit Threshold Foldback, LTC4219-5 6 5 CURRENT LIMIT VALUE (A) 4 3 2 1 0 0 1 2 3 VOUT (V) 4 5 4219 G07 Current Limit Threshold Foldback, LTC4219-12 6 CURRENT LIMIT THRESHOLD VALUE (A) 5 CURRENT LIMIT VALUE (A) 4 3 2 1 0 0 3 6 VOUT (V) 4219 G08 Current Limit Adjustment (IOUT vs RSET) 6 5 4 3 2 1 0 9 12 1k 10k 100k RSET (Ω) 1M 10M 4219 G09 ISET Resistor vs Temperature 22 60 50 ISET RESISTOR (kΩ) 21 40 RON (mΩ) RON vs VDD and Temperature 10 MOSFET SOA Curve VDD = 3.3V, 12V 1 1ms ID (A) 30 20 10ms 0.1 TA = 25°C MULTIPLE PULSE DUTY CYCLE = 0.2 0.1 1 VDS (V) 4219 G11 20 100ms 1s 10s DC 10 100 4219 G12 19 10 18 –50 0 –50 0.01 –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G10 –25 0 25 50 TEMPERATURE (°C) 75 100 4219f 5 LTC4219 TYPICAL PERFORMANCE CHARACTERISTICS PG, FLT VOUT Low vs ILOAD 14 12 PG, FLT VOUT LOW (V) PG 10 8 6 4 85 2 0 0 2 4 6 8 ILOAD (mA) 10 12 4219 G13 TA = 25°C, VDD = 12V unless otherwise noted. GATE Pull-Up Current vs Temperature –26.0 IMON vs Temperature and VDD 105 VDD = 3.3V, 12V, 24V ILOAD = 5A FLT 100 IGATE PULL-UP (μA) –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G14 –25.5 IMON (μA) 95 –25.0 90 –24.5 80 –50 –24.0 –50 –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G15 Gate Pull-Up Current vs Gate Drive 7 GATE DRIVE (VGATE – VSOURCE) (V) 6 5 4 3 VDD = 3.3V 2 1 0 0 –5 –10 –15 –20 IGATE (μA) –25 –30 4219 G16 Gate Drive vs VDD 6.2 GATE DRIVE (VGATE – VSOURCE) (V) VDD = 12V 6.0 5.8 5.6 5.4 5.2 0 5 10 15 VDD (V) 20 25 30 4219 G17 Gate Drive vs Temperature 6.15 GATE DRIVE (VGATE – VSOURCE) (V) 0.9 0.8 0.7 VISET (V) –25 50 0 25 TEMPERATURE (°C) 75 100 4219 G18 VISET vs Temperature 6.14 6.13 0.6 0.5 6.12 6.11 0.4 0.3 –50 –25 6.10 –50 0 25 50 75 100 125 150 TEMPERATURE (°C) 4219 G19 4219f 6 LTC4219 PIN FUNCTIONS EN1: Inverted Enable 1 Input. Ground this pin to enable the MOSFET to turn on after 100ms debounce delay. If the voltage at this pin rises above 1.235V for longer than 10μs a turn-off command is detected, the overcurrent fault is cleared and the MOSFET gate is discharged with a 250μA current. Bringing this pin below 1.15V and EN2 low for 100ms begins GATE pin ramping. EN2: Inverted Enable 2 Input. Ground this pin to enable the MOSFET to turn on after 100ms debounce delay. If the voltage at this pin rises above 1.235V for longer than 10μs a turn-off command is detected and the MOSFET gate is discharged with a 250μA current. Bringing this pin below 1.15V and EN1 low for 100ms begins GATE pin ramping. Exposed Pad: SENSE. FB: Foldback and Power Good Input. The FB pin is driven from an internal resistive divider from OUT for both the LTC4219-12 and LTC4219-5. These versions preset 12V and 5V foldback and power good levels. If the OUT voltage falls below 2.5V (LTC4219-5) or 6V (LTC4219-12) the current limit is reduced using a foldback profile (see the Typical Performance Characteristics section). If the FB voltage falls below 1.21V the PG pin will pull high to indicate the power is bad. FLT: Overcurrent Fault Indicator. Open-drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips. GATE: Gate Drive for Internal N-channel MOSFET. An internal 24μA current source charges the gate of the N-channel MOSFET. At start-up the GATE pin ramps up at a 0.3V/ms rate determined by internal circuitry. During an undervoltage or overvoltage condition a 250μA pull-down current turns the MOSFET off. During a short-circuit or undervoltage lockout condition, a 140mA pull-down current source between GATE and OUT is activated. GND: Device Ground. IMON: Current Monitor Output. The current in the internal MOSFET switch is divided by 50,000 and sourced from this pin. Placing a 20k resistor from this pin to GND creates a 0V to 2V voltage swing when current ranges from 0A to 5A. INTVCC: Internal 3V Supply Decoupling Output. This pin must have a 0.1μF or larger bypass capacitor. ISET: Current Limit Adjustment Pin. For a 5.6A current limit value open this pin. This pin is driven by a 20k resistor in series with a voltage source. The pin voltage is used to generate the current limit threshold. The internal 20k resistor and an external resistor between ISET and ground create an attenuator that lowers the current limit value. In order to match the temperature variation of the sense resistor, the voltage on this pin increases at the same rate as the sense resistance increases. Therefore the voltage at ISET pin is proportional to temperature of the MOSFET switch. OUT: Output of Internal MOSFET Switch. Connect this pin directly to the load. An internal resistive divider is connected to this pin to drive the FB pin. PG: Power Good Indicator. Open-drain output releases the PG pin to go high when the FB pin drops below 1.21V indicating the power is bad. If the FB pin rises above 1.23V and the GATE to OUT voltage exceeds 4.2V, the open-drain output pulls low indicating power is good. SENSE: Current Sense Node and MOSFET Drain. The current limit circuit controls the GATE pin to limit the sense voltage between the VDD and SENSE pins to 42mV (5.6A) or less depending on the voltage at the FB pin. The exposed pad on the DHC package is connected to SENSE and must be soldered to an electrically isolated printed circuit board trace to properly transfer the heat out of the package. TIMER: Timer Input. Connect a capacitor between this pin and ground to set a 12ms/μF duration for current limit before the switch is turned off. If the EN1 pin is toggled first high then low while the MOSFET switch is off, the switch will turn on again following a cooldown time of 518ms/μF duration. Tie this pin to INTVCC for a fixed 2ms overcurrent delay and 100ms auto-retry time. VDD: Supply Voltage and Current Sense Input. This pin has an undervoltage lockout threshold of 2.73V. 4219f 7 LTC4219 FUNCTIONAL DIAGRAM VDD INTERNAL 7.5mΩ SENSE RESISTOR SENSE (EXPOSED PAD) INTERNAL 25mΩ MOSFET GATE OUT IMON CLAMP CS CHARGE PUMP AND GATE DRIVER INRUSH 0.3V/ms ISET 20k X1 – +– + 0.6V POSITIVE TEMPERATURE COEFFICIENT REFERENCE OUT FB CM FOLDBACK 0.6V OUT * 1.235V EN1 + EN1 PG LOGIC – 1.235V EN2 + EN2 0.2V + TM1 INTVCC 100μA – – 2μA + TM2 VDD VDD 3.1V GEN INTVCC – UVLO1 1.235V – TIMER UVLO2 GND 4219 BD * 100k (LTC4219-5) 150k (LTC4219-12) ** 40k (LTC4219-5) 20k (LTC4219-12) 8 – 2.73V + + ** – + 1.235V PG FLT 2.65V 4219f LTC4219 OPERATION The Functional Diagram displays the main circuits of the device. The LTC4219 is designed to turn a board’s supply voltage on and off in a controlled manner allowing the board to be safely inserted and removed from a live backplane. The LTC4219 includes a 25mΩ MOSFET and a 7.5mΩ current sense resistor. During normal operation, the charge pump and gate driver turn on the pass MOSFET’s gate to provide power to the load. The inrush current control is accomplished by the INRUSH circuit. This circuit limits the GATE ramp rate to 0.3V/ms and hence controls the voltage ramp rate of the output capacitor. The current sense (CS) amplifier monitors the load current using the voltage sensed across the current sense resistor. The CS amplifier limits the current in the load by reducing the GATE-to-OUT voltage in an active control loop. It is simple to adjust the current limit threshold using the current setting (ISET) pin. This allows a different threshold during other times such as start-up. A short circuit on the output to ground causes significant power dissipation during active current limiting. To limit this power, the foldback amplifier reduces the current limit value from 5.6A to 1.5A in a linear manner as the FB pin drops below 0.6V (see the Typical Performance Characteristics section). If an overcurrent condition persists, the TIMER pin ramps up with a 100μA current source until the pin voltage exceeds 1.2V (comparator TM2). This indicates to the logic that it is time to turn off the pass MOSFET to prevent overheating. At this point the TIMER pin ramps down using the 2μA current source until the voltage drops below 0.2V (Comparator TM1) which tells the logic to start an internal 100ms timer. After this delay, the pass transistor has cooled and it is safe to turn it on again. It is suitable for many applications to use an internal 2ms overcurrent timer with a 100ms cooldown period. Tying the TIMER pin to INTVCC sets this default timing. The fixed 5V and 12V versions, LTC4219-5 and LTC4219-12, use an internal divider from OUT to drive the FB pin. This divider also sets the foldback current limit profile. The output voltage is monitored using the FB pin and the PG comparator to determine if the power is available for the load. The power good condition is signaled by the PG pin using an open-drain pull-down transistor. The Functional Diagram also shows the monitoring blocks of the LTC4219. The two comparators on the left side include the EN1 and EN2 comparators. These comparators determine if the enable inputs are valid prior to turning on the MOSFET. But first the undervoltage lockout circuits UVLO1 and UVLO2 must validate the input supply and the internally generated 3.1V supply (INTVCC) and generate the power up initialization to the logic circuits. If the external conditions remain valid for 100ms the MOSFET is allowed to turn on. Other features include MOSFET current and temperature monitoring. The current monitor (CM) outputs a current proportional to the sense resistor current. This current can drive an external resistor or other circuits for monitoring purposes. A voltage proportional to the MOSFET temperature is output to the ISET pin. The MOSFET temperature allows external circuits to predict failure and shutdown the system. 4219f 9 LTC4219 APPLICATIONS INFORMATION The typical LTC4219 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. A complete application circuit is shown in Figure 1. External component selection is discussed in detail in the following sections. Turn-On Sequence Several conditions must be present before the internal pass MOSFET can be turned on. First the supply VDD must exceed its undervoltage lockout level. Next the internally generated supply INTVCC must cross its 2.65V undervoltage threshold. This generates a 25μs power-on-reset pulse which clears the fault register and initializes internal latches. Finally, the enable inputs EN1 and EN2 both must be below the 1.15V threshold. All of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during the insertion has ended. The MOSFET is turned on by charging up the GATE with a charge pump generated current source whose value is adjusted by shunting a portion of the pull-up current to ground. The charging current is controlled by the INRUSH circuit that maintains a constant slope of GATE voltage versus time (Figure 2). The voltage at the GATE pin rises with a slope of 0.3V/ms and the supply inrush current is set at: IINRUSH = CL • (0.3V/ms) This gate slope is designed to charge up a 1000μF capacitor to 12V in 40ms, with an inrush current of 300mA. This allows the inrush current to stay under the current limit threshold (1.5A) for capacitors less than 1000μF Included . in the Typical Performance Characteristics section is a graph of the Safe Operating Area for the MOSFET. It is evident from this graph that the power dissipation at 12V, 300mA for 40ms is in the safe region. VDD + 6.15 SLOPE = 0.3V/ms VDD OUT GATE t1 t2 4219 F02 Figure 2. Supply Turn-On 12V VDD EN1 EN2 12V R1 10k FLT OUT + GATE LTC4219DHC-12 RGATE 1k CGATE 0.1μF PG ISET RSET 20k CL 330μF VOUT 12V 2A 12V R4 10k TIMER CT 0.1μF INTVCC C1 0.1μF GND IMON RMON 20k 4219 F01 ADC Figure 1. 2A, 12V Card Resident Application 4219f 10 LTC4219 APPLICATIONS INFORMATION Adding a capacitor and a 1k series resistor from GATE to ground will lower the inrush current below the default value set by the inrush circuit. The GATE is then charged with a 24μA current source. The voltage at the GATE pin rises with a slope equal to 24μA/CGATE and the supply inrush current is set at: IINRUSH = CL CGATE • 24µA Turn-Off Sequence The switch can be turned off by a variety of conditions. A normal turn-off is initiated by either the EN1 or EN2 pins going above their 1.235V threshold. Additionally, several fault conditions will turn off the switch. These include overcurrent circuit breaker (SENSE pin) or overtemperature. Normally the switch is turned off with a 250μA current pulling down the GATE pin to ground. With the switch turned off, the OUT voltage drops which pulls the FB pin below its threshold. PG then goes high to indicate output power is no longer good. If VDD drops below 2.65V for greater than 5μs or INTVCC drops below 2.5V for greater than 1μs, a fast shutdown of the switch is initiated. The GATE is pulled down with a 170mA current to the OUT pin. Overcurrent Fault The LTC4219 features an adjustable current limit with foldback that protects against short circuits or excessive load current. To prevent excessive power dissipation in the switch during active current limit, the available current is reduced as a function of the output voltage sensed by the FB pin. A graph in the Typical Performance Characteristics curves shows the current limit versus FB voltage. An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time-out delay set by the TIMER. Current limiting begins when the MOSFET current reaches 1.5A to 5.6A (depending on the foldback). The GATE pin is then brought down with a 140mA GATEto-OUT current. The voltage on the GATE is regulated in order to limit the current to less than 5.6A. At this point, a circuit breaker time delay starts by charging the external timing capacitor from the TIMER pin with a 100μA pullup current. If the TIMER pin reaches its 1.2V threshold, the internal switch turns off (with a 250μA current from GATE to ground). Included in the Typical Performance Characteristics curves is a graph of the Safe Operating Area for the MOSFET. From this graph one can determine the MOSFET’s maximum time in current limit for a given output power. When the GATE voltage reaches the MOSFET threshold voltage, the switch begins to turn on and the OUT voltage follows the GATE voltage as it increases. Once OUT reaches VDD, the GATE will ramp up until clamped by the 6.15V Zener between GATE and OUT. As the OUT voltage rises, so will the FB pin which is monitoring it. Once the FB pin crosses its 1.235V threshold and the GATE to OUT voltage exceeds 4.2V, the PG pin pulls low indicating that the power is good. Parasitic MOSFET Oscillation When the N-channel MOSFET ramps up the output during power-up it operates as a source follower. The source follower configuration may self-oscillate in the range of 25kHz to 300kHz when the load capacitance is less than 10μF, especially if the wiring inductance from the supply to the VDD pin is greater than 3μH. The possibility of oscillation will increase as the load current (during power-up) increases. There are two ways to prevent this type of oscillation. The simplest way is to avoid load capacitances below 10μF. For wiring inductance larger than 20μH, the minimum load capacitance may extend to 100μF. A second choice is to connect an external gate capacitor CP >1.5nF as shown in Figure 3. GATE CP 2.2nF LTC4219 * OPTIONAL RC TO LOWER INRUSH CURRENT 4219 F03 Figure 3. Compensation for Small CLOAD 4219f 11 LTC4219 APPLICATIONS INFORMATION Tying the TIMER pin to INTVCC will force the part to use the internally generated (circuit breaker) delay of 2ms. In either case the FLT pin is pulled low to indicate an overcurrent fault has turned off the pass MOSFET. For a given circuit breaker time delay, the equation for setting the timing capacitor’s value is as follows: CT = tCB • 0.083(μF/ms) After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2μA pull-down current. When the TIMER pin reaches its 0.2V threshold, an internal 100ms timer is started. After the 100ms delay, the switch is allowed to turn on again if the overcurrent fault has been cleared. Bringing the EN1 pin above 1.235V and then low will clear the fault. If the TIMER pin is tied to INTVCC then the switch is allowed to turn on again (after an internal 100ms delay) if the overcurrent fault is cleared. The waveform in Figure 4 shows how the output latches off following a short-circuit. The current in the MOSFET is 1.4A as the timer ramps up. VOUT 10V/DIV temperature which corresponds to a 5.6A current limit at room temperature. An external resistor placed between the ISET pin and ground forms a resistive divider with the internal 20k sourcing resistor. The divider acts to lower the voltage at the ISET pin and therefore lower the current limit threshold. The overall current limit threshold precision is reduced to ±12% when using a 20k resistor to halve the threshold. Using a switch (connected to ground) in series with this external resistor allows the active current limit to change only when the switch is closed. This feature can be used when the start-up current exceeds the typical maximum load current. Monitor MOSFET Temperature The voltage at the ISET pin increases linearly with increasing temperature. The temperature profile of the ISET pin is shown in the Typical Performance Characteristics section. Using a comparator or ADC to measure the ISET voltage provides an indicator of the MOSFET temperature. There is an over-temp circuit in the LTC4219 that monitors an internal voltage similar to the ISET pin voltage. When the die temperature exceeds 145°C the circuit turns off the MOSFET until the temperature drops to 125°C. Monitor MOSFET Current IOUT 2A/DIV AVGATE 10V/DIV TIMER 2V/DIV 1ms/DIV 4219 F04 Figure 4. Short-Circuit Waveform Current Limit Adjustment The default value of the active current limit is 5.6A. The current limit threshold can be adjusted lower by placing a resistor between the ISET pin and ground. As shown in the Functional Diagram the voltage at the ISET pin (via the clamp circuit) sets the CS amplifier’s built-in offset voltage. This offset voltage directly determines the active current limit value. With the ISET pin open, the voltage at the ISET pin is determined by a positive temperature coefficient reference. This voltage is set to 0.618V at room The current in the MOSFET passes through an internal sense resistor. The voltage on the sense resistor is converted to a current that is sourced out of the IMON pin. The gain of ISENSE amplifier is 20μA/A referenced from the MOSFET current. This output current can be converted to a voltage using an external resistor to drive a comparator or ADC. The voltage compliance for the IMON pin is from 0V to INTVCC – 0.7V. A microcontroller with a built-in comparator can build a simple integrating single-slope ADC by resetting a capacitor that is charged with this current. When the capacitor voltage trips the comparator and the capacitor is reset, a timer is started. The time between resets will indicate the MOSFET current. 4219f 12 LTC4219 APPLICATIONS INFORMATION Power Good Indication In addition to setting the foldback current limit threshold, the FB pin is used to determine a power good condition. The LTC4219-12 and LTC4219-5 use an internal resistive divider on the OUT pin to drive the FB pin. On the LTC4219-12, the PG comparator indicates logic high when OUT pin rises above 10.5V. If the OUT pin subsequently falls below 10.3V, the comparator toggles low. On the LTC42195 the PG comparator drives high when the OUT pin rises above 4.35V and low when OUT falls below 4.27V. Once the PG comparator is high, the GATE pin voltage is monitored with respect to the OUT pin. Once the GATE minus OUT voltage exceeds 4.2V, the PG pin goes low. This indicates to the system that it is safe to load the OUT pin while the MOSFET is completely turned “on”. The PG pin goes high when the GATE is commanded off (using the EN1, EN2 or SENSE pins) or when the PG comparator drives low. Design Example Consider the following design example (Figure 5): VIN = , 12V, IMAX = 5A. IINRUSH = 100mA, CL = 330μF VPWRGD = 10.5V. The inrush current is defined by the current required to charge the output capacitor using the fixed 0.3V/ms GATE charge up rate. The inrush current is defined as: ⎛ 0.3V ⎞ ⎛ 0.3V ⎞ IINRUSH = CL • ⎜ ⎟ = 330µF • ⎜ ms ⎟ = 100mA ⎝ ms ⎠ ⎝ ⎠ As mentioned previously, the charge up time is the output voltage (12V) divided by the output rate of 0.3V/ms resulting in 40ms. The peak power dissipation of 12V at 100mA (or 1.2W) is within the SOA of the pass MOSFET for 40ms (see MOSFET SOA curve in the Typical Performance Characteristics section). Next the power dissipated in the MOSFET during overcurrent must be limited. The active current limit uses a timer to prevent excessive energy dissipation in the MOSFET. The worst-case power dissipation occurs when the voltage versus current profile of the foldback current limit is at the maximum. This occurs when the current is 6.1A and the voltage is one half of the 12V or 6V. See the Current Limit Sense Voltage vs FB Voltage in the Typical Performance Characteristics section to view this profile. In order to survive 36W, the MOSFET SOA dictates a maximum time of 10ms (see SOA graph). Use the internal 2ms timer invoked by tying the TIMER pin to INTVCC. 12V VDD EN1 EN2 12V R3 10k FLT TIMER INTVCC C1 0.1μF GND OUT + CL 330μF VOUT 12V 5A LTC4219DHC-12 PG 12V R1 10k IMON R2 20k ADC 4219 F05 Figure 5. 5A, 12V Card Resident Application 4219f 13 LTC4219 APPLICATIONS INFORMATION The power good threshold using the internal resistive divider on the FB pin matches the 10.5V requirement. The final schematic in Figure 5 results in very few external components. The pull-up resistors, R1 and R3, connect to the FLT and PG pins while the 20k (R2) converts the IMON current to a voltage at a ratio: VIMON = 20 ⎡µA/A ⎤ • 20k •IOUT = 0.4 ⎡ V/A ⎤ •IOUT ⎣ ⎦ ⎣ ⎦ In addition there is a 0.1μF bypass (C1) on the INTVCC pin. Layout Considerations In Hot Swap applications where load currents can be 5A, narrow PCB tracks exhibit more resistance than wider tracks and operate at elevated temperatures. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 0.5mΩ/square. Small resistances add up quickly in high current applications. There are two VDD pins on opposite sides of the package that connect to the sense resistor and MOSFET. The PCB layout should be balanced and symmetrical to each VDD pin to balance current in the MOSFET bond wires. Figure 6 shows a recommended layout for the LTC4219. Although the MOSFET is self protected from overtemperature, it is recommended to solder the backside of the package to a copper trace to provide a good heat sink. Note that the backside is connected to the SENSE pin and cannot be soldered to the ground plane. During normal loads 5V VDD EN1 EN2 5V R1 10k FLT TIMER INTVCC CT 0.1μF GND IMON RMON 20k ADC 4219 F07 the power dissipated in the package is as high as 1.9W. A 10mm × 10mm area of 1oz copper should be sufficient. This area of copper can be divided in many layers. It is also important to put C1, the bypass capacitor for the INTVCC pin as close as possible between the INTVCC and GND. HEAT SINK VDD OUT VIA TO SINK C GND 4217 F06 Figure 6. Recommended Layout Additional Applications The LTC4219 has a wide operating range from 2.9V to 15V. The PG threshold is set with an internal resistive divider. All other functions are independent of supply voltage. Figure 7 shows a 5V application with a PG threshold of 4.35V. In addition to Hot Swap applications, the LTC4219 also functions as a backplane resident switch for removable load cards (see the Typical Application section). OUT VOUT 5V 5A + CL 100μF 5V LTC4219DHC-5 PG R2 10k Figure 7. 5V, 5A Card Resident Application 4219f 14 LTC4219 PACKAGE DESCRIPTION DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 0.65 ± 0.05 3.50 ± 0.05 1.65 ± 0.05 2.20 ± 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.40 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 ± 0.10 (2 SIDES) R = 0.20 TYP 3.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 8 0.200 REF 0.75 ± 0.05 4.40 ± 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1 0.25 ± 0.05 0.50 BSC 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH (DHC16) DFN 1103 R = 0.115 TYP 9 16 0.40 ± 0.10 0.00 – 0.05 4219f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC4219 TYPICAL APPLICATION 12V, 5A Backplane Resident Application with Insertion Activated Turn-On 12V VDD OUT LTC4219DHC-12 EN1 PG FLT EN2 TIMER INTVCC 0.1μF GND ISET IMON 20k ADC 4219 TA02 12V 10k 12V 10k 12V 10k LOAD VOUT 12V 5A RELATED PARTS PART NUMBER LTC1421 LTC1422 LTC1642A LTC1645 LTC1647-1/LTC1647-2/ LTC1647-3 LTC4210 LTC4211 LTC4212 LTC4214 LTC4215 LTC4217 LTC4218 LT4220 LTC4221 LTC4230 LTC4352 DESCRIPTION Dual Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Dual Channel, Hot Swap Controller Dual Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Negative Voltage, Hot Swap Controller Hot Swap Controller with I2C Compatible Monitoring 2A, Hot Swap Controller Single Channel, Hot Swap Controller Positive and Negative Voltage, Dual Channels, Hot Swap Controller Dual Hot Swap Controller/Sequencer Triple Channels, Hot Swap Controller 0V to 18V Ideal Diode Controller Operates from 2.9V to 26.5V, Integrated MOSFET and RSENSE, SSOP-20 or 5mm × 3mm DFN-16 Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16 Operates from ±2.7V to ±16.5V, SSOP-16 Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20 Operates from 2.9V to 18V, 3mm × 3mm DFN-12 COMMENTS Operates from 3V to 12V, Supports –12V, SSOP-24 Operates from 2.7V to 12V, SO-8 Operates from 3V to 16.5V, Overvoltage Protection up to 33V, SSOP-16 Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14 Operates from 2.7V to 16.5V, SO-8 or SSOP-16 Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 Operates from –6V to –16V, MSOP-10 Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage, SSOP-16 4219f 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0610 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010