LTC4221IGN

LTC4221 Dual Hot Swap Controller/ Power Sequencer with Dual Speed, Dual Level Fault Protection FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Safe Board Insertion and Removal from a Live Backplane Configurable Power Supply Sequencing Soft-Start with Current Foldback Limits Inrush Current No External Gate Capacitor Required Adjustable Dual Level Circuit Breaker Protection Controls Supply Voltages from 1V to 13.5V Independent N-Channel MOSFET High Side Drivers FB Pin Monitors VOUT for Overvoltage Protection Latch Off or Automatic Retry on Current Fault FAULT and PWRGD Outputs Narrow 16-Pin SSOP Package The LTC®4221 is a 2-channel Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using two independent high side gate drivers to control two external N-channel pass transistors, the output voltages can be ramped up with current foldback to limit the inrush current during the start-up period. No external compensation capacitors are required at the GATE pins. The two channels can be configured to ramp up and down separately or simultaneously for supply voltages ranging from 2.7V to 13.5V and 1V to 13.5V for channels 1 and 2 respectively. Each channel has two current limit comparators that provide dual level and dual speed overcurrent circuit breaker protection after the start-up period. If any current sense voltage exceeds 100mV for 1µs or 25mV for the timeout delay (set by the CFILTER at the FILTER pin), then the FAULT latch is set and both GATE pins are pulled low. The FB pins monitor the respective channel output voltages and provide the inputs for the PWRGD comparators as well as overvoltage protection. APPLICATIO S ■ ■ ■ ■ Electronic Circuit Breaker Power Supply Sequencing Live Board Insertion and Removal Industrial High Side Switch/Circuit Breaker , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG 2-Channel Hot Swap Controller VCC1 3.3V VCC2 2.5V 0.004Ω 10Ω 100nF * 100nF 10Ω IRF7413 0.004Ω IRF7413 LONG * SHORT 21k 10k VCC1 ON1 SENSE1 GATE1 VCC2 SENSE2 GATE2 14.3k FB2 5.11k 10k 10k SHORT 13.3k ON2 10k LTC4221 FAULT GND TIMER 470nF FAULT GND SHORT LONG *SMAJ10 (OPTIONAL) FILTER 1nF U VOUT1 3.3V/5A VOUT2 2.5V/5A PWRGD2 PWRGD1 20k U U PWRGD2 PWRGD1 FB1 5.11k 4221 TA01 4221f 1 LTC4221 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW ON1 VCC1 SENSE1 GATE1 FB1 PWRGD1 FAULT FILTER 1 2 3 4 5 6 7 8 16 ON2 15 VCC2 14 SENSE2 13 GATE2 12 FB2 11 PWRGD2 10 GND 9 TIMER Supply Voltage (VCCn) ............................................ 17V SENSEn Pins ............................ – 0.3V to (VCCn + 0.3V) FB, ON Pins .............................. – 0.3V to (VCC1 + 0.3V) TIMER Pin .................................................. – 0.3V to 2V GATE Pins (Note 3) ................................... – 0.3V to 21V PWRGD, FAULT, FILTER Pins ................... – 0.3V to 17V Operating Temperature Range LTC4221C ............................................... 0°C to 70°C LTC4221I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC4221CGN LTC4221IGN GN PART MARKING 4221 4221I GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL VCC1 VCC2 ICC1 ICC2 VCC1(UVL) ∆VCC1(HYST) VCC2(UVL) ∆VCC2(HYST) ISENSE1(IN) ISENSE2(IN) VSENSE(FC) VSENSE(SC) VSENSE(ACL) IGATE(UP) IGATE(DN) IGATE(FSTDN) ∆VGATE PARAMETER Supply Voltage Channel 1 Supply Voltage Channel 2 VCC1 Supply Current VCC2 Supply Current Undervoltage Lockout for Channel 1 Undervoltage Lockout Hysteresis Undervoltage Lockout for Channel 2 Undervoltage Lockout Hysteresis SENSE1 Pin Input Current SENSE2 Pin Input Current SENSEn Threshold Voltage SENSEn Threshold Voltage SENSEn Voltage at Active Current Limit GATEn Output Current GATEn Output Current GATEn Output Current External N-Channel Gate Drive The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted. CONDITIONS ● MIN 2.7 1 ● ● ● ● ● ● ● ● ● TYP MAX 13.5 13.5 UNITS V V mA mA V mV V mV µA µA µA mV mV mV mV mV VCC2 ≤ VCC1 ON1, ON2 = 2V ON1, ON2 = 2V VCC1 Rising VCC2 Rising 0V ≤ VSENSE1 ≤ VCC1 VSENSE2 = VCC2 VSENSE2 = 0V Channeln Fast Comparator Threshold Channeln Slow Comparator Threshold VFBn = 0 VFBn = 0.65V VON1 = VON2 = 2V, VGATEn = 0V VON1 = VON2 = 0.6V, VGATEn = 3.3V UVLO with VGATEn = 3.3V or FAULT Latched with VGATEn = 3.3V VGATEn – VCC1 for VCC1 = 2.7V, VCC2 = 1V VGATEn – VCC1 for VCC1 = 3.3V, VCC2 = 2.5V VGATEn – VCC1 for VCC1 = 5V, VCC2 = 3.3V VGATEn – VCC1 for VCC1 = 12V, VCC2 = 12V 0V ≤ VONn ≤ VCC1 VON1 Falling 2.2 0.05 2.1 0.65 2.5 110 0.8 25 ±0.03 ±0.2 1000 85 22.5 20.5 100 25 25 9 25 3 0.15 2.675 0.975 ±5 ±5 115 27.5 29.5 ● ● –7 75 –9.5 100 16 –12 125 ● ● ● ● ● ● ● 4.5 5 8 7 0.4 ±0.01 0.375 0.4 25 13 16 16 18 0.5 ±1 0.425 VGATE(OV) ION(IN) VON(RESET) ∆VON(RESETHYST) GATEn Overvoltage Lockout Threshold ONn Pin Input Current ON1 Reset Threshold ON1 Reset Threshold Hysteresis 2 U W U U WW W µA µA mA V V V V V µA V mV 4221f LTC4221 ELECTRICAL CHARACTERISTICS SYMBOL VON(OFF) ∆VON(OFFHYST) IFB(IN) VFB(UV) ∆VFB(UVHYST) ∆VFB(LREG) VFB(OV) IFILTER(UP) IFILTER(DN) VFILTER(TH) ∆VFILTER(HYST) ITMR(UP1) ITMR(UP2) ITMR(FSTDN) VTMR(H) VTMR(L) IFAULT(UP) VFAULT(TH) ∆VFAULT(HYST) VFAULT(OL) IPWRGD(LK) VPWRGD(OL) tP(FC-GATE) tP(SC-FAULT) tP(FAULT-GATE) tP(OV-GATE) tP(FILTER-GATE) tRESET tP(ON-GATE) PARAMETER ONn Off Threshold ONn Off Threshold Hysteresis FBn Input Current FBn Undervoltage Threshold FBn Undervoltage Threshold Hysteresis FBn Threshold Line Regulation FBn Overvoltage Threshold FILTER Pull-Up Current FILTER Pull-Down Current FILTER Threshold FILTER Threshold Hysteresis TIMER Pull-Up Current 1 TIMER Pull-Up Current 2 TIMER Pull-Down Current TIMER High Threshold TIMER Low Threshold FAULT Pull-Up Current FAULT Threshold FAULT Hysteresis FAULT Output Low Voltage PWRGDn Leakage Current PWRGDn Output Low Voltage Fast Comparator Trip to GATEn Discharging Slow Comparator Trip to FILTER High and FAULT Latched FAULT Low to GATEn Discharging FBn OV Comparator Trip to GATEn Discharging Filter Comparator Trip to GATEn Discharging Circuit Breaker Reset Delay Time Turn Off Propagation Delay The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted. CONDITIONS High to Low, GATEn Turns Off by 100µA Pull-Down 0V ≤ VFBn ≤ VCCn FBn Falling 2.7V ≤ VCC1 ≤ 13.5V FBn Rising During Current Fault Condition During Normal Cycle Latched Off Threshold, FILTER Rising Initial Timing Cycle Start-Up Cycle VTIMER = 1.5V, End of Initial Timing Cycle TIMER Rising TIMER Falling FAULT Falling IFAULT = 1.6mA, VCC1 = 5V VPWRGDn = VCC1, VFBn = 0.7V, Normal Cycle IPWRGDn = 1.6mA, VCC1 = 5V, VFBn = 0V, Normal Cycle VSENSEn = VCCn to (VCCn – 200mV) Step VSENSEn = VCCn to (VCCn – 50mV) Step. FILTER Open VFAULT = 3.3V to 0V VFBn = 0V to 1V VFILTER = 0V to 1.5V VON1 < 0.4V to FAULT High VONn ≤ 0.821V to GATEn Discharging ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN 0.796 TYP 0.821 30 MAX 0.846 UNITS V mV ● ● ±0.01 0.605 0.617 3 2 0.805 –80 1.15 1.18 –1.2 –15 1.172 0.1 –2.5 0.791 0.822 –105 1.8 1.24 105 –1.9 –20 9 1.234 0.4 –3.8 0.816 35 0.14 ±0.01 0.14 1 15 15 18 15 15 15 ±1 0.629 µA V mV mV 0.838 –132 2.45 1.30 –2.6 –25 1.27 0.5 –5 0.841 0.4 ±10 0.4 1.5 35 35 35 35 30 35 V µA µA V mV µA µA mA V V µA V mV V µA V µs µs µs µs µs µs µs Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All current into device pins are positive. All voltages are referenced to ground unless otherwise specified. Note 3: An internal zener on each GATE pin clamps the charge pump voltage to a typical maximum operating voltage of 26V. External overdrive of either GATE pin beyond its internal zener voltage may damage the device. 4221f 3 LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS ICC1 vs Temperature 6 5 4 ICC1 (mA) VCC2 = 1V VCC1 = 13.5V ICC2 (mA) 0.125 0.100 0.075 0.050 0.025 0 – 50 – 25 0 VCC1(UVL) (V) VCC1 = 12V 3 VCC1 = 5V 2 VCC1 = 2.7V 1 0 –50 –25 50 25 75 0 TEMPERATURE (°C) VCC2(UVL) vs Temperature 0.815 0.810 0.805 RISING TIMER = 0.3V |ISENSE2(IN)| (µA) VCC2(UVL) (V) 10 1 0.1 0.01 VSENSE(FC) (mV) 0.800 0.795 0.790 0.785 0.780 0.775 0.770 –50 –25 FALLING 0 25 50 75 TEMPERATURE (°C) VSENSE(FC) vs Temperature 102.0 101.5 VSENSE(SC) (mV) VSENSE(FC) (mV) VCC1 = 5V VCC2 = 3.3V VSENSE(SC) (mV) 101.0 100.5 100.0 99.5 99.0 –50 –25 50 25 75 0 TEMPERATURE (°C) 4 UW 100 100 ICC2 vs Temperature 0.200 0.175 0.150 VCC2 = 12V VCC1 = 13.5V VCC2 = 13.5V 2.52 2.50 2.48 2.46 2.44 2.42 2.40 2.38 50 75 25 TEMPERATURE (°C) 100 125 VCC1(UVL) vs Temperature TIMER = 0.3V RISING VCC2 = 5V VCC2 = 3.3V VCC2 = 1V FALLING 125 2.36 – 50 – 25 0 50 75 25 TEMPERATURE (°C) 100 125 4221 G01 4221 G02 4221 G03 |ISENSE2(IN)| vs VSENSE2 10000 1000 100 101.5 101.0 102.0 VSENSE(FC) vs VCC1 VCC2 = VCC1 TA = 25°C 100.5 0.001 0.0001 125 VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V 0 2 4 6 8 10 12 4221 G05 100.0 99.5 0 2 4 6 8 VCC1 (V) 4221 G06 10 12 14 16 VSENSE2 (V) 4221 G04 VSENSE(SC) vs VCC1 25.6 25.4 25.2 25.0 24.8 24.6 24.4 24.2 100 125 0 2 4 6 8 VCC1 (V) 4221 G07 4221 G08 VSENSE(SC) vs Temperature VCC2 = VCC1 TA = 25°C 26.0 VCC1 = 5V 25.8 VCC2 = 3.3V 25.6 25.4 25.2 25.0 24.8 24.6 10 12 14 16 24.4 – 50 – 25 0 50 75 25 TEMPERATURE (°C) 100 125 4221 G09 4221f LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS VSENSE(ACL) vs VFB 30 VCC1 = 5V VCC2 = 3.3V 25 TA = 25°C VSENSE(ACL) (mV) IGATE(DN) (µA) IGATE(UP) (µA) 20 15 10 5 0 0 0.1 0.2 0.3 0.4 VFB (V) 0.5 0.6 0.7 IGATE(FSTDN) vs Temperature 60 50 IGATE(FSTDN) (mA) VCC2 = 1V VGATE = 3.3V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 40 ∆VGATE1 (V) VGATEn (V) 30 20 10 0 –50 –25 50 25 75 0 TEMPERATURE (°C) ∆VGATE2 (VGATE2 – VCC1) vs Temperature 16 14 12 ∆VGATE2 (V) VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V VON(RESET) (V) VGATE(OV) (V) 10 8 6 4 –50 –25 50 25 75 0 TEMPERATURE (°C) UW 100 100 IGATE(UP) vs Temperature –6 –7 –8 –9 –10 –11 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (°C) 100 125 VCC2 = 1V VGATE = 0V 104 103 102 101 100 99 98 IGATE(DN) vs Temperature VCC2 = 1V VGATE = 3.3V –12 –50 –25 97 –50 –25 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (°C) 100 125 4221 G10 4221 G11 4221 G12 ∆VGATEn (VGATEn – VCC1) vs VCC1 15 14 13 12 11 10 9 8 7 VCC2 = VCC1 – 1.5V TA = 25°C ∆VGATE1 ∆VGATE1 (VGATE1 – VCC1) vs Temperature 18 16 14 VCC1 = 2.7V, VCC2 = 1V VCC1 = 5V, VCC2 = 3.3V VCC1 = 13.5V, VCC2 = 13.5V ∆VGATE2 12 10 8 6 4 –50 –25 125 6 0 2 4 6 8 VCC1 (V) 10 12 14 50 25 75 0 TEMPERATURE (°C) 100 125 4221 G13 4221 G14 4221 G15 VGATE(OV) vs Temperature 0.420 0.415 0.410 0.405 0.400 0.395 0.390 0.385 0.380 VCC2 = 1V TIMER = 0.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V VON(RESET) vs VCC1 0.430 0.425 RISING 0.420 0.415 0.410 0.405 FALLING 0.400 0.395 VCC2 = 1V, TA = 25°C 125 0.375 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 125 0 2 4 6 8 VCC1 (V) 10 12 14 16 4221 G16 4221 G17 4221 G18 4221f 5 LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS VON(RESET) vs Temperature 0.440 0.435 0.430 VCC1 = 5V VCC2 = 3.3V RISING VON(RESET) (V) 0.425 VON(OFF) (V) 0.420 0.415 0.410 0.405 FALLING 0.400 0.395 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 125 0.840 0.835 0.830 0.825 FALLING 0.820 0.815 0 2 4 6 8 VCC1 (V) VON(OFF) (V) VFB(UV) vs VCC1 0.622 0.623 VCC2 = 1V 0.621 TA = 25°C 0.620 VFB(UV) (V) RISING VFB(UV) (V) VFB(OV) (V) 0.619 0.618 0.617 0.616 0.615 0.614 0 2 4 6 8 VCC1 (V) 4221 G22 FALLING 10 VFB(OV) vs Temperature 0.825 VCC1 = 5V 0.824 VCC2 = 3.3V 0.823 0.822 VFB(OV) (V) 0.821 0.820 0.819 0.818 0.817 0.816 0.815 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 IFILTER(DN) (µA) IFILTER(UP) (µA) 6 UW 12 14 VON(OFF) vs VCC1 0.860 0.855 RISING 0.850 0.845 0.85 0.84 0.83 VCC2 = 1V TA = 25°C 0.87 0.86 VON(OFF) vs Temperature VCC1 = 5V VCC2 = 3.3V RISING FALLING 0.82 0.81 –50 –25 10 12 14 16 50 25 75 0 TEMPERATURE (°C) 100 125 4221 G19 4221 G20 4221 G21 VFB(UV) vs Temperature VCC1 = 5V 0.622 VCC2 = 3.3V 0.621 0.620 0.619 0.618 0.617 0.616 0.615 0.614 FALLING VFB(OV) vs VCC1 0.8225 0.8220 0.8215 0.8210 0.8205 0.8200 0.8195 0.8190 0 2 4 6 8 VCC1 (V) 4221 G23 4221 G24 RISING VCC2 = 1V TA = 25°C 16 0.613 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 10 12 14 16 IFILTER(UP) vs Temperature –88 –93 –98 –103 –108 –113 –118 –50 –25 VCC2 = 1V VFILTER = 1V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 2.00 1.95 1.90 1.85 1.80 1.75 1.70 IFILTER(DN) vs Temperature VCC2 = 1V VFILTER = 1V 50 25 75 0 TEMPERATURE (°C) 100 125 1.65 –50 –25 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (°C) 100 125 4221 G25 4221 G26 4221 G27 4221f LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS VFILTER(TH) vs Temperature 1.246 VCC2 = 1V 1.244 V GATE1 = 0.2V 1.242 1.240 VFILTER(TH) (V) ITMR(UP1) (µA) ITMR(UP2) (µA) 1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 –50 –25 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 0 75 TEMPERATURE (°C) 100 125 ITMR(FSTDN) vs Temperature 25 VCC2 = 1V VTMR = 1.5V 20 1.240 1.238 1.236 1.234 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V ITMR(FSTDN) (mA) 1.230 1.228 1.226 VTMR(L) (V) 15 VTMR(H) (V) 10 5 0 –50 –25 50 25 0 75 TEMPERATURE (°C) IFAULT(UP) vs Temperature –3.1 –3.3 –3.5 VCC2 = 1V VFAULT = 1.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 0.860 0.855 0.850 0.845 VFAULT(TH) (V) 0.840 0.835 0.830 0.825 0.820 IFAULT(UP) (µA) –3.7 –3.9 –4.1 –4.3 –4.5 –50 –25 VFAULT(TH) (V) 50 25 75 0 TEMPERATURE (°C) UW 100 ITMR(UP1) vs Temperature –1.6 –1.7 –1.8 –1.9 –2.0 –2.1 –2.2 –50 –25 ITMR(UP2) vs Temperature –17.0 VCC2 = 1V –17.5 VTMR = 0.25V –18.0 –18.5 –19.0 –19.5 –20.0 –20.5 –21.0 –21.5 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V VCC2 = 1V VTMR = 0.25V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (°C) 100 125 –22.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 4221 G28 4221 G29 4221 G30 VTMR(H) vs Temperature VCC2 = 1V VTMR(L) vs Temperature 0.404 0.403 0.402 0.401 0.400 0.399 0.398 VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V VCC2 = 1V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 1.232 1.224 1.222 125 1.220 –50 –25 0.397 0.396 – 50 – 25 0 50 75 25 TEMPERATURE (°C) 100 125 50 25 0 75 TEMPERATURE (°C) 100 125 4221 G31 4221 G32 4221 G33 VFAULT(TH) vs VCC1 RISING VCC2 = 1V TA = 25°C VFAULT(TH) vs Temperature 0.87 0.86 0.85 0.84 0.83 0.82 FALLING VCC1 = 5V VCC2 = 3.3V RISING FALLING 0.815 0.810 0.81 0.80 –50 –25 100 125 0 2 4 6 8 VCC1 (V) 10 12 14 16 50 25 75 0 TEMPERATURE (°C) 100 125 4221 G34 4221 G35 4221 G36 4221f 7 LTC4221 TYPICAL PERFOR A CE CHARACTERISTICS VPWRGD(OL)/VFAULT(OL) vs Temperature 0.500 0.450 VCC2 = 1V, IPWRGD/IFAULT = 1.6mA VCC1 = 2.7V VCC1 = 5V 0.400 VCC1 = 13.5V 0.350 tp(SC-FAULT) (V) VOL (V) 0.300 0.250 0.200 0.150 0.100 0.050 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 15 14 13 12 –50 –25 tp(FC-GATE) (V) PI FU CTIO S ON1 (Pin 1): System/Channel 1 On Input. Both GATE pins are pulled low by internal 100µA pull-downs and the FAULT latch is reset when VON1 < 0.4V. When 0.425V < VON1 < 0.821V, the FAULT latch is released from reset. When VON1 > 0.851V, GATE1 ramps up after an initial timing cycle. VCC1 (Pin 2): Channel 1 Positive Supply Input. It powers all the internal circuitry. VCC1 can range from 2.7V to 13.5V for normal operation but it must be ≥ VCC2. An undervoltage lockout circuit disables both channels whenever the voltage at VCC1 is less than 2.5V. SENSE1 (Pin 3): Channel 1 Current Sense Input. A sense resistor RSENSE1 is placed in the supply path between VCC1 and SENSE1 to sense channel 1 load current. If VRSENSE1 exceeds 100mV for more than 1µs or 25mV for an adjustable time (set by the CFILTER), the FAULT latch is set and fast pull-down circuits are triggered to discharge both GATEs low. During the start-up cycle, GATE1 ramp-up is controlled to servo VRSENSE1 ≤ VSENSE(ACL). VSENSE(ACL) increases from 9mV to 25mV as VFB1 ramps from 0V to 0.5V. To disable the current limit and circuit breaker function for channel 1, tie SENSE1 to VCC1. GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high side gate drive of an external N-channel MOSFET. When VON1 < 0.821V, GATE1 is held low by a 100µA current source. When VON1 > 0.851V, an initial timing cycle is followed by a start-up cycle when an internal charge pump provides a 9.5µA pull-up to ramp up GATE1 with inrush current limiting. UVLO, overvoltage, overcurrent and externally generated faults override the ON1 pin and pull GATE1 low. FB1 (Pin 5): VOUT1 Feedback Input. FB1 monitors the channel 1 output voltage with an external resistive divider. When VFB1 < 0.617V, the PWRGD1 pin is pulled low. When VFB1 > 0.822V, overvoltage is detected, the FAULT latch is set and both GATEs are pulled low. The FB1 pin is also used to control the channel 1 current limit during its start-up cycle. PWRGD1 (Pin 6): Channel 1 Power Good Output. PWRGD1 is pulled low when VFB1 < 0.617V, during the initial timing cycle or when the chip is in UVLO. An external pull-up is required to generate a logic high at the open-drain PWRGD1 pin. 8 UW tp(SC-FAULT) vs Temperature 18 17 16 VCC2 = 1V TIMER = 0.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 1.8 1.6 1.4 1.2 1.0 0.8 tp(FC-GATE) vs Temperature VCC2 = 1V TIMER = 0.5V VCC1 = 2.7V VCC1 = 5V VCC1 = 13.5V 50 25 75 0 TEMPERATURE (°C) 100 125 0.6 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 4221 G37 4221 G38 4221 G39 U U U 4221f LTC4221 PI FU CTIO S FAULT (Pin 7): Fault Status Input/Output. FAULT is a bidirectional pin. As an input, pulsing VFAULT < 0.816V will set the FAULT latch and bring the LTC4221 into the fault state. As an output, FAULT is pulled high by an internal 3.8µA pull-up under normal operating conditions. When an overcurrent fault is detected by a SENSE pin or a overvoltage fault detected by an FB pin, the FAULT latch is set and the LTC4221 goes into the fault state. The FAULT latch is reset by a UVLO or the ON1 pin being driven below 0.4V. FILTER (Pin 8): Overcurrent Fault Timing Filter. The FILTER pin requires an external capacitor to ground to adjust the response time of the two slow comparators. The FILTER pin can be left unconnected for a default slow comparator response time of 15µs. TIMER (Pin 9): Analog System Timer. The TIMER pin requires an external capacitor to ground to generate timing delay cycles during start-up. The LTC4221’s initial and start-up timing cycles are controlled by CTIMER and the internal current sources connected to the TIMER pin. GND (Pin 10): Ground. Connect to a ground plane for optimum performance. PWRGD2 (Pin 11): Channel 2 Power Good Output. Similar functionality as PWRGD1. Controlled by FB2. FB2 (Pin 12): VOUT2 Feedback Input. Similar functionality as FB1. Monitors channel 2 output voltage, controls PWRGD2 output and channel 2 start-up current limit. GATE2 (Pin 13): Channel 2 Gate Drive. Similar functionality as GATE1. Controls the gate drive of the channel 2 external N-channel MOSFET. ON2 controls GATE2 in the same manner as ON1 controls GATE1. VON1 < 0.4V overrides conditions at ON2 and GATE2 is held low by a 100µA current source. UVLO, overvoltage, overcurrent and externally generated faults override conditions at ON1 and ON2, and pull GATE2 low. SENSE2 (Pin 14): Channel 2 Current Sense Input. Similar functionality as SENSE1. Monitors channel 2 load current through RSENSE2 placed in the supply path between VCC2 and SENSE2. To disable the current limit and circuit breaker function for channel 2, tie SENSE2 to VCC2. VCC2 (Pin 15): Channel 2 Positive Supply Input. VCC2 can range from 1V to 13.5V for normal operation but it must be ≤ VCC1. An undervoltage lockout circuit disables both channels whenever the voltage at VCC2 is less than 0.8V. ON2 (Pin 16): Channel 2 On Input. GATE2 is pulled to ground by a 100µA current source when VON2 < 0.821V. When VON2 > 0.851V, GATE2 ramps up after an initial timing cycle. U U U 4221f 9 LTC4221 BLOCK DIAGRA OSCILLATOR VCC1 ON1 1 0.821V 0.4V ON2 16 CHARGE PUMP 2 CPO2 VCC1 VCC1 0.821V 105µA FILTER 8 1.24V 1.8µA VCC1 3.8µA 0.816V FAULT 7 VCC1 VCC1 2 + – VCC1 9mV TO 25mV + – SENSE1 3 100mV 0.617V FB1 5 VCC2 VCC2 15 + – VCC2 9mV TO 25mV + – SENSE2 14 100mV 0.617V FB2 12 10 W CHARGE PUMP 1 CPO1 VCC1 VCC2 UVLO VCC1 20µA ON1 COMPARATOR VCC1 1.9µA – + – + 9 TIMER ON2 COMPARATOR + – FTRHI FILTER COMPARATOR SYSTEM CONTROL LOGIC TMRHI + 1.234V 0.4V – TMRHI COMPARATOR TMRLO + – TMRLO COMPARATOR + – FAULT_LO FAULT COMPARATOR 12V 10 GND CPO1 9.5µA 4 GATE1 VCC1 26V + – + SLOWHI1 CUR_LIMIT1 SLOW COMPARATOR 1 FPD1 109.5µA FASTHI1 CHANNEL 1 CONTROL – FAST LOGIC COMPARATOR 1 + 0.822V GATELO1 OV1 COMPARATOR GATELO1 COMPARATOR + – 0.4V – + FB1 COMPARATOR 6 PWRGD1 – CPO2 12V CHANNEL ONE 9.5µA 13 GATE2 VCC2 26V + – + SLOWHI2 CUR_LIMIT2 SLOW COMPARATOR 2 FPD2 109.5µA FASTHI2 CHANNEL 2 CONTROL – FAST LOGIC COMPARATOR 2 + 0.822V GATELO2 OV2 COMPARATOR GATELO2 COMPARATOR + – 0.4V – + FB2 COMPARATOR 11 PWRGD2 – CHANNEL TWO 4221 BD 4221f LTC4221 OPERATIO Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current may damage the connector pins and glitch the power bus, causing other boards in the system to reset. The LTC4221 is designed to turn on and off a circuit board’s supply voltages in a controlled manner, allowing insertion or removal without glitches or connector damage. The LTC4221 can reside on the backplane or on the removable circuit board for hot insertion applications. It controls the path between the backplane power bus and the daughter board load with an external MOSFET switch. Both inrush control and short-circuit protection are provided by the external MOSFET. Each LTC4221 controls two channels, each with its individual MOSFET for supplies from 1V to 13.5V. Overview The timing diagram in Figure 1 shows some typical waveforms of the LTC4221. The VCC and GND pins receive power through the longest connector pins and are the first to connect when the board is inserted. During the undervoltage lockout (UVLO) state before time point 1, both GATE pins are held low by internal N-channel MOSFET pull-downs, turning the external MOSFETs off. Once both VCC pins are valid at time point 1, the LTC4221 enters into a reset state as ON1 is below its reset threshold. At time point 2, ON1 clears its reset threshold and the device goes from the reset state to an off state. When either ON1 or ON2 clears its off threshold, both GATE pins are < 0.4V and TIMER < 0.4V (time points 3 and 4), the TIMER pin sources 1.9µA and an initial timing cycle starts. Any transition of ON1 and ON2 through their off thresholds will reset the initial timing cycle. At time point 5, TIMER reaches its high threshold and is pulled down by an internal N-channel MOSFET to its low threshold at time point 6. The LTC4221 then checks that FILTER pin voltage is low and FAULT pin voltage is high. If both conditions are met, the electronic circuit breaker is armed. The channel 1 start-up timing cycle starts at time point 6 since ON1 has cleared its off threshold and ON2 has not. U During the start-up cycle, TIMER sources 20µA and GATE1 sources 9.5µA. As GATE1 ramps up, MOSFET1 starts to turn on and current flows through to charge up the load capacitance. As VOUT1 and FB1 ramp up, the load current is monitored through the external SENSE1 resistor. Between time points 7 and 8, the GATE1 9.5µA pull-up is controlled to servo the voltage across RSENSE1 to be less than the SENSE1 active current limit voltage, which has a component controlled by the FB1 voltage (see Applications Information: Start-Up Cycle with Current Limit). In this way, inrush current is limited and MOSFET1 does not overheat during the start-up cycle. When FB1 clears its undervoltage threshold, PWRGD1 asserts high. At time point 9, TIMER reaches its high threshold and is pulled down by an internal N-channel MOSFET to its low threshold at time point 10. Channel 1’s slow comparator is armed at time point 9 and enters a fault monitor mode, bringing the channel 1 start-up cycle to an end. At time point 10, ON2 voltage is monitored and since ON2 has cleared its off threshold, the start-up timing cycle repeats for channel 2. The inrush current is low and GATE2 ramps up without need for current limiting. Channel 2’s slow comparator is armed at time point 11 and enters a fault monitor mode, ending the channel 2 start-up cycle. Overcurrent faults translate to an increase in either VRSENSE. At time point 13, VRSENSE1 > 25mV (slow comparator threshold). The 1.8µA pull-down on the FILTER changes to a 105µA pull-up. When the FILTER pin hits its threshold at time point 14, it triggers a fault state when FAULT is latched low and both GATE pins are pulled low by internal N-channel MOSFETs, turning off the external MOSFETs. As each channel output discharges, its FB pin goes below the undervoltage threshold and the PWRGD pin deasserts. Higher overcurrents when either VRSENSE > 100mV (fast comparator threshold) for more than 1µs will trigger the same condition. This fault state can only be cleared by a UVLO at either VCC pin or a hard reset at the ON1 pin, as at time point 15, when ON1 is pulled below its reset threshold. The LTC4221 then reverts back to its reset state as between time points 1 and 2. 4221f 11 LTC4221 OPERATIO VCCn CLEARS VCCn(UVL) ON1 > VON(RESET) + ∆VON(RESETHYST) ON2 > VON(OFF), + ∆VON(OFFHYST), CHECK GATE < VGATE(OV), TIMER < 0.4V ON1 > VON(OFF) + ∆VON(OFFHYST), CHECK GATE < VGATE(OV), TIMER < 0.4V 1 VCCn 2 VCCn(UVL) VTMR(H) TIMER 1.9µA VTMR(L) 20µA 20µA 3 4 56 7 8 ELECTRONIC CIRCUIT BREAKER ARMED, CHECK FILTER < VFILTER(TH), FAULT > VFAULT(TH) + ∆VFAULT(HYST) CHANNEL 1 SLOW COMPARATOR ARMED CHANNEL 2 SLOW COMPARATOR ARMED 9 10 11 12 13 14 15 FAULT VFILTER(TH) 105µA 1.8µA FILTER VON(OFF) + ∆VON(OFFHYST) VON(RESET) + ∆VON(RESETHYST) VON(OFF) + ∆VON(OFFHYST) ON2 VON(OFF) ON1 GATE1 100µA VGATE(OV) GATE2 SENSE1 SENSE2 FB1 > VFB(UV) + ∆VFB(HYST) VOUT1 VOUT2 PWRGD1 PWRGD2 4221 F01 UVLO RESET 12 U VON1(RESET) 9.5µA 9.5µA 100µA VGATE(OV) 25mV 9mV VSENSE(FC) VSENSE(SC) 9mV FB1 < VFB(UV) FB2 > VFB(UV) + ∆VFB(HYST) FB2 < VFB(UV) OFF INITIAL TIMING CHANNEL 1 CHANNEL 2 NORMAL START-UP START-UP FAULT RESET Figure 1. LTC4221 Operation 4221f LTC4221 APPLICATIO S I FOR ATIO Undervoltage Lockout An internal undervoltage lockout (UVLO) occurs if either VCC supply is too low for normal operation. The LTC4221 is kept in lockout mode in which the internal charge pumps are off, the GATE pins, TIMER are held low by internal N-channel MOSFET pull-downs and the FAULT latch reset, cutting off both channels. VCC1 has a low-to-high UVLO threshold of 2.5V with 110mV hysteresis. VCC2 has a lowto-high UVLO threshold of 0.8V with 25mV hysteresis. Both UVLOs have glitch filters that filter out dips that are less than 30µs, allowing for bus supply transients. An additional requirement for normal operation is VCC1 ≥ VCC2. ON Pin Functions The ON1 pin serves as a global reset for the LTC4221. It has an internal reset comparator with a high-to-low threshold of 0.4V, a 25mV hysteresis and a high-to-low glitch filter of 15µs. Pulling ON1 below this threshold will put the LTC4221 into a reset state in which the TIMER is pulled low by an internal N-channel MOSFET pull-down, the GATE pins are pulled low by separate internal 100µA pull-downs and the FAULT latch resets. A low-to-high transition on the ON1 pin past the reset threshold releases the reset on the FAULT latch and both channels go into an off state. BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC1 VCC2 LONG LONG Z1 RX1 10Ω CX1 100nF 1 16 R1 10k LONG Z1 = SMAJ10 * ADDITIONAL DETAILS OMITTED FOR CLARITY 10 ON1 VCC1 RSENSE1 Q1 0.004Ω IRF7413 R2 SHORT 10k ON2 SENSE1 LTC4221* GATE1 GND 9 FB1 RF2 15k CTIMER 1µ F TIMER RF1 56k (2a) Circuit Figure 2. Simultaneous Power On/Off 4221f U In addition to its global reset function, ON1 also serves as an on/off switch for channel 1. ON2 performs the same role for channel 2. Both pins have an off comparator with a high-to-low threshold of 0.821V and 30mV hysteresis. With these, ON1 and ON2 can be used to force a simultaneous or sequential power-up/power-down of the two channels. A simultaneous power-up and power-down is shown in Figure 2b. Both VCC pins clear their respective UVLO at time point 1 and both channels enter reset state. When ON1 clears its reset threshold, either ON1 or ON2 clears its off threshold, both GATEs < 0.4V and TIMER < 0.4V (time point 2), an initial timing cycle starts. At time point 4, the initial timing cycle completes and the LTC4221 checks that FILTER is low and FAULT is high. If both conditions are met, it then monitors the voltage of ON1 and ON2. As long as its ON pin has cleared its off threshold, each channel powers up regardless of the state of the other channel. Similarly, if its ON pin goes below its off threshold, each channel pulls its GATE pin down with an internal 100µA pull-down and turns off its external MOSFET regardless of the state of the other channel. As the circuit in Figure 2a has its two ON pins shorted together, a simultaneous power-up is programmed at time points 4 to 5 and a simultaneous power down is programmed between time points 7 and 8. The timing waveforms in Figure 3 show a 1 2 34 56 78 VCCn VCCn(UVL) ONn VOUT1 3.3V 5A VOUT2 2.5V 5A 0.851V 0.821V 1.234V 1.9µA 20µA TIMER W UU + CLOAD1 GATEn 9.5µA VTH 100µA VOUTn UVLO 4221 F02a DISCHARGE BY LOAD 4221 F02b INITIAL CHANNEL NORMAL TIMING START-UP RESET RESET STATE (2b) Timing Waveforms 13 LTC4221 APPLICATIO S I FOR ATIO 12 VCCn VCCn(UVL) 34 ON1 0.851V TIMER 1.234V 1.9µA GATE1 VOUT1 PWRGD1 ON2 GATE2 VOUT2 UVLO RESET INITIAL TIMING CHANNEL 1 START-UP CHANNEL 2 START-UP NORMAL Figure 3. Sequential Power On/Off Timing Waveforms sequential power up from time points 4 to 8 and a sequential power-down programmed from time points 9 to 11. To achieve this the circuit requires the functionality of the PWRGD1 pin and will be featured in the next section. The circuit in Figure 2a sits on a daughter board with staggered pins on its edge connectors. Supply voltage and ground connections are wired to long-edge connector pins while both ON pins are connected to a short-edge connector pin through a resistive divider. Until the connectors are fully mated, ON1 is pulled low and holds both channels in the reset state. When the connectors have properly seated, the ON pins are pulled above 0.851V and an initial timing cycle starts. This cycle is restarted by any transitions on the ON pins across their off thresholds and adds a further delay for the plug-in transients to die off before allowing a start-up cycle. The Typical Application circuit on the first page of this data sheet shows similar 14 U 5 67 8 9 10 11 0.821V 0.4V 20µA 20µA 9.5µA VTH VFB1 = 0.620V VFB1 = 0.617V DISCHARGE BY LOAD 100µA 0.851V 0.821V 9.5µA VTH DISCHARGE BY LOAD 4221 F03 W UU 100µA OFF CHANNEL 1 OFF CHANNEL 2 NORMAL considerations in the design of its PCB edge connectors, and the resistive dividers connected to ON1 and ON2 act as an external UVLO to override the internal one. An RC filter can be added at the ON1 pin to increase the delay time at card insertion to allow bus supply transients to stabilize. FB and PWRGD Pin Functions Each FB pin is used to detect undervoltage and overvoltage in its channel output voltage (VOUT) through a resistive divider. Each FB pin has an undervoltage comparator with a high-to-low threshold of 0.617V and 3mV hysteresis. The output of this comparator controls the channel’s open-drain PWRGD output. During UVLO, both PWRGD pins are pulled low by internal N-channel MOSFET pulldowns. As both channels come out of UVLO, control of PWRGD1 is passed to FB1and control of PWRGD2 to FB2. Each PWRGD pin can be connected to a pull-up resistor to 4221f LTC4221 APPLICATIO S I FOR ATIO generate a logic high output to indicate that VOUT is valid. An internal high-to-low glitch filter helps to prevent negative voltage transients on each FB pin from deasserting its PWRGD. The relationship between glitch filter time and an FB pin transient voltage is shown in Figure 4. Using the functionality of the PWRGD1 pin, the LTC4221 can be configured to do sequential power-up and power-down as shown by the circuit in Figure 5. Referring back to Figure 3, ON2 is held low until VOUT1 ramps high enough for FB1 to exceed its undervoltage threshold at time point 5 when PWRGD1 ramps up, pulling ON2 high. At time point 7, the control logic sees ON2 exceeding its off threshold and so commences a start-up cycle for channel 2. Similarly, when ON1 is forced low by Q2 at time point 9, GATE1 is pulled low by its 100µA pull-down while ON2 is held high by the 80 70 TA = 25°C GLITCH FILTER TIME (µs) 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 180 200 FEEDBACK TRANSIENT (mV) 4221 F04 Figure 4. FB Comparator Glitch Filter Time vs Feedback Transient Voltage BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) VCC1 VCC2 LONG LONG SHORT R3 10k R6 10k ON/OFF SHORT R5 10Ω Q2 R1 10k R2 2k R4 10k LONG Q2: 2N7002LT1 Z1: SMAJ10 * ADDITIONAL DETAILS OMITTED FOR CLARITY Figure 5. Using PWRGD1 to Configure Sequential Power-Up/Power-Down 4221f U R4 pull-up on PWRGD1. Its is only when channel 1 is powered off and VOUT1 discharges below its undervoltage threshold at time point 10 that PWRGD1’s internal N-channel MOSFET pull-down is triggered and ON2 goes low. At time point 11, ON2 trips its off threshold and GATE2 pulls low with a 100µA pull-down, powering off channel 2. For VOUT overvoltage detection, each FB pin has an overvoltage comparator with a low-to-high threshold of 0.822V and a low-to-high glitch filter of 18µs. This threshold is designed to be 33% higher than the undervoltage threshold. If either FB pin trips this threshold, the fault latch is set, all GATE pins are pulled low with internal NFET pull-downs and the LTC4221 goes into a fault state. In the third function, each FB pin is used to control its channel’s current limit during its start-up cycle. This will be featured in the Start-Up Cycle with Current Limit section. GATE Pin Functions Each GATE pin controls the gate of its channel’s external N-channel MOSFET. Individual internal charge pumps powered by VCC1 guarantee a gate drive of minimum 4.5V and maximum 18V (internally clamped) for GATE1 and GATE2. During UVLO, the internal charge pumps are off and both GATE pins are pulled low by internal N-channel MOSFET pull-downs. Outside UVLO, when ON1 is below its off threshold, the charge pumps are on and GATE1 is held low by an internal 100µA current pull-down. Once RSENSE1 Q1 0.004Ω IRF7413 Z1 RX1 10Ω CX1 100nF VCC1 SENSE1 RF1 56k RF2 15k CTIMER 1µF 4221 F05 W UU VOUT1 3.3V 5A VOUT2 2.5V 5A 1 16 6 10 ON1 ON2 + CLOAD1 LTC4221* PWRGD1 GATE1 GND TIMER 9 FB1 15 LTC4221 APPLICATIO S I FOR ATIO ON1 clears its off threshold and the initial timing cycle is complete, the GATE1 pin is pulled up by a 9.5µA current source connected to the charge pump output during the channel start-up cycle. GATE1 can be servoed by adjusting the ramp up current to