LTC4242CUHF

LTC4242 Dual Slot Hot Swap Controller for PCI Express FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Live Insertion into PCI Express® Backplane Controls Two Independent PCI Express Slots Independent Control of Main and Auxiliary Supplies 20V Rating for 12V Supply Input Pins Integrated 0.25Ω AUX Switches Limits Fault Current in ≤1µs Force On Test Mode Adjustable Supply Voltage Power-Up Rate High Side Drivers for N-Channel MOSFETs Thermal Shutdown Protection Available in 38-Lead QFN and 36-Lead SSOP Packages The LTC®4242 Hot SwapTM controller allows safe board insertion and removal for two independent slots on a PCI Express backplane. External N-channel transistors control the 12V and 3.3V supplies while integrated switches control the 3.3V auxiliary supplies. Both 12V and 3.3V supplies can be ramped up at an adjustable rate. Dual level circuit breakers and fast active current limiting protect all supplies against overcurrent faults. A supply filter at the VCC pin allows the LTC4242 to endure supply transients. The EN input detects the presence of a card in the PCI Express slot. The FAULT and AUXFAULT outputs alert the system of overcurrent conditions on the main and auxiliary supplies, respectively. PGOOD and AUXPGOOD outputs indicate proper main and auxiliary supply outputs. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ PCI Express-Based PC and Servers Hot Swap Application for Triple Supply Systems TYPICAL APPLICATIO 12V 3.3V PCI Express Application 12VOUT 3.3VOUT 12VIN1 12VSENSE1 12VGATE1 12VOUT1 3VIN1 VCC 3VSENSE1 3VGATE1 3VOUT1 AUXOUT1 3.3VOUT BD_PRST1 ENn 5V/DIV AUXOUTn 5V/DIV 3.3V AUXIN1 AUXON1 ON1 FAULT1 AUXFAULT1 PGOOD1 PGOOD2 AUXFAULT2 FAULT2 ON2 AUXON2 AUXIN2 12VIN2 12VSENSE2 12VGATE2 12VOUT2 3VIN2 PCI EXPRESS HOT PLUG CONTROLLER LTC4242G FON1 EN1 GND EN2 FON2 PCIe PLUG-IN CONNECTOR CARD 12VOUTn 5V/DIV 3VOUTn 5V/DIV BD_PRST2 AUXOUT2 3VOUT2 3VSENSE2 3VGATE2 3.3VOUT PGOODn 5V/DIV 3.3V 3.3V 12V PCIe PLUG-IN CONNECTOR CARD 3.3VOUT 12VOUT 4242 TA01a U Normal Power-Up Sequence 10ms/DIV 4242 F04 U U 4242f 1 LTC4242 ABSOLUTE AXI U RATI GS Supply Voltages VCC........................................................... –0.3V to 7V 12VINn.................................................... –0.3V to 20V 3VINn...................................................... –0.3V to 10V AUXINn .................................................. –0.3V to 10V Input Voltages ONn, AUXONn, FONn ............................... –0.3V to 7V ENn .......................................................... –0.3V to 7V Output Voltages FAULTn, PGOODn, AUXFAULTn, AUXPGOODn ........................................... –0.3V to 7V Analog Voltages 12VSENSEn .............................................. –0.3V to 20V PACKAGE/ORDER I FOR ATIO TOP VIEW EN1 FON1 ON1 AUXON1 3VOUT1 3VGATE1 3VSENSE1 3VIN1 AUXIN1 1 2 3 4 5 6 7 8 9 36 FAULT1 35 AUXFAULT1 34 PGOOD1 33 12VIN1 32 12VSENSE1 31 12VGATE1 30 12VOUT1 29 AUXOUT1 28 GND 27 AUXOUT2 26 12VOUT2 25 12VGATE2 24 12VSENSE2 23 12VIN2 22 PGOOD2 21 AUXFAULT2 20 FAULT2 19 EN2 38 37 36 35 34 33 32 AUXON1 1 3VOUT1 2 3VGATE1 3 3VSENSE1 4 3VIN1 5 AUXIN1 6 VCC 7 AUXIN2 8 3VIN2 9 3VSENSE2 10 3VGATE2 11 3VOUT2 12 13 14 15 16 17 18 19 AUXFAULT2 AUXON2 FAULT2 PGOOD2 FON2 ON2 EN2 39 31 12VIN1 30 12VSENSE1 29 12VGATE1 28 12VOUT1 27 AUXOUT1 26 GND 25 AUXOUT2 24 12VOUT2 23 12VGATE2 22 12VSENSE2 21 12VIN2 20 AUXPGOOD2 VCC 10 AUXIN2 11 3VIN2 12 3VSENSE2 13 3VGATE2 14 3VOUT2 15 AUXON2 16 ON2 17 FON2 18 G PACKAGE 36-LEAD PLASTIC SSOP UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 95°C/W TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 39) IS GND, PCB ELECTRICAL CONNECTION OPTIONAL ORDER PART NUMBER LTC4242CG LTC4242IG Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ ORDER PART NUMBER LTC4242CUHF LTC4242IUHF UHF PART MARKING* 4242 4242 *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. 4242f 2 AUXPGOOD1 AUXFAULT1 PGOOD1 FAULT1 FON1 ON1 EN1 U U W WW U W (Note 1) 12VGATEn ................................................ –0.3V to 25V 12VOUTn (Note 3) .. 12VGATEn – 5V to 12VGATEn + 0.3V AUXOUTn, 3VSENSEn .............................. –0.3V to 10V 3VGATEn .................................................. –0.3V to 14V 3VOUTn (Note 3) ....... 3VGATEn – 5V to 3VGATEn + 0.3V Operating Temperature Range LTC4242C ................................................ 0°C to 70°C LTC4242I ............................................. –40°C to 85°C Storage Temperature Range SSOP ................................................. –65°C to 150°C QFN .................................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C TOP VIEW LTC4242 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2) SYMBOL Supplies VIN Operating Voltage VCC 12VINn 3VINn AUXINn VAUXONn = 2V, VONn = 2V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN 2.7 10.1 3.0 3.0 TYP MAX 6.0 14.4 6.0 6.0 UNITS V V V V mA mA mA V V V V mV mV mV mV IDD Input Supply Current VCC 12VINn 3VINn Supply Undervoltage Lockout 1.6 0.5 0.35 2.3 9.48 2.57 2.57 30 90 20 20 2.45 9.78 2.67 2.67 100 130 35 35 4 1 1 2.6 10.08 2.77 2.77 200 170 50 50 VUVL VCC Rising 12VINn Rising 3VINn Rising AUXINn Rising VCC 12VINn 3VINn AUXINn ΔVLKO(HYST) Supply Undervoltage Lockout Hysteresis Current Limit ΔVSENSE(CB) ΔVSENSE(ACL) Circuit Breaker Trip Sense Voltage 12VINn – 12VSENSEn 3VINn – 3VSENSEn Active Current Limit Sense Voltage 12VINn – 12VSENSEn 3VINn – 3VSENSEn Circuit Breaking Current for AUX Supply Circuit Breaker Response Time Internal Switch Resistance RAUX = (VAUXINn – VAUXOUTn)/I External N-Channel Gate Pull-Up Current (Note 4) I = 375mA Gate Drive On V12VGATEn = 1V V3VGATEn = 1V Gate Drive Off V12VGATEn = 17V, V12VOUTn = 12V V3VGATEn = 8.3V, V3VOUTn = 3.3V Fast Turn Off V12VGATEn = 17V, V12VOUTn = 12V V3VGATEn = 8.3V, V3VOUTn = 3.3V IGATE = 1µA (Note 3) ● ● ● ● ● ● 45 45 75 75 385 10 50 50 100 100 550 20 55 55 125 125 715 40 mV mV mV mV mA µs ICBAUX tCB RAUX Switch Resistance ● 0.25 0.4 Ω External Gate Drive IGATE(UP) ● ● ● ● ● ● ● ● ● ● ● ● ● ● –5 –5 0.5 0.5 150 150 4.5 4.5 10.08 2.772 2.772 20 5 5 –9 –9 1 1 250 250 5.5 5.5 10.38 2.855 2.855 70 20 20 –13 –13 2 2 400 400 7.9 7.9 10.68 2.937 2.937 110 30 30 µA µA mA mA mA mA V V V V V mV mV mV 4242f IGATE(DN) External N-Channel Gate Pull-Down Current IGATE(FPD) ΔVGATE External N-Channel Gate Fast Pull-Down Current External N-Channel Gate Drive 12VGATEn – 12VOUTn 3VGATEn – 3VOUTn Power Good Threshold Voltage Input Pins VPG(TH) 12VOUTn Falling 3VOUTn Falling AUXOUTn Falling (Note 5) 12VOUTn 3VOUTn AUXOUTn (Note 5) VPG(HYST) Power Good Hysteresis 3 LTC4242 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2) SYMBOL VON(TH) ΔVON(TH) VON(RTH) ION(IN) VEN(TH) ΔVEN(HYST) IEN(UP) VFON ISENSE PARAMETER ONn, AUXONn Pin Threshold Voltage ONn, AUXONn Pin Hysteresis ONn, AUXONn Pin Reset Threshold Voltage ONn, AUXONn Pin Input Current ENn Pin Threshold Voltage ENn Pin Hysteresis ENn Pull-Up Current FONn Pin Logic Threshold SENSE Pin Input Current 12VSENSEn 3VSENSEn OUT Pin Input Current 12VOUTn 3VOUTn OUT Pin Discharge Resistance 12VOUTn 3VOUTn AUXOUTn Output Low Voltage FAULTn, AUXFAULTn, PGOODn, AUXPGOODn (Note 5) Pull-Up Current FAULTn, AUXFAULTn, PGOODn, AUXPGOODn (Note 5) AUXOUTn Slew Rate Input High (ONn) to GATEs High Prop Delay Input Supply Low (12VINn, 3VINn) to GATEs Low Prop Delay Out Low (12VOUTn, 3VOUTn) to PGOOD High Prop Delay Sense Voltage High to GATE Low ΔVSENSE = 200mV, CGATE = 10nF V12VSENSEn = 12V V3VSENSEn = 3.3V Gate Drive On V12VOUTn = 12V V3VOUTn = 3.3V Gate Drive Off V12VOUTn = 6V V3VOUTn = 2V VAUXOUTn = 2V IPIN = 3mA VENn = 1V Falling Edge VONn = VAUXONn = 1.2V ENn Rising CONDITIONS Rising Edge ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN 1.173 30 0.5 1.173 30 –5 0.7 TYP 1.235 70 0.6 1.235 70 –9 MAX 1.297 120 0.7 ±1 1.297 120 –13 2.6 UNITS V mV V µA V mV µA V µA µA µA µA Ω Ω Ω 40 40 45 27 350 165 375 700 330 750 100 100 90 60 1400 660 1500 IOUT ROUT(DIS) Output Pins VOL ● 0.14 0.4 V IPU VPIN = 1.5V ● –5 –9 –13 µA Slew Rate SRAUXOUT Delays tPLH(GATE) tPLH(UVL) tPLH(PG) tPHL(SENSE) ● ● ● ● ● 1.25 7 18 20 0.4 1.7 14 36 40 1 V/ms µs µs µs µs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All current into device pins is positive, all current out of the device pins is negative. All voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pins to a minimum of 5V above VOUT. Driving this pin to voltages beyond the clamp may damage the device. Note 4: For the QFN package, the AUX FET on resistance is guaranteed by correlation to wafer level measurements. Note 5: Available on QFN package only. 4242f 4 LTC4242 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2) VCC, 12VINn and 3VINn Supply Current vs Temperature 1.8 VCC SUPPLY CURRENT (mA) 2.5 IDD (mA) 1.5 10.2 12VINn UV RISING THRESHOLD (V) IDD vs VCC 3.0 1.0 1.5 1.0 3 4 5 VCC (V) 3VINn, AUXINn Rising Threshold vs Temperature 2.72 3VINn AUXINn UV RISING THRESHOLD (V) 10.6 12VOUTn POWER GOOD THRESHOLD (V) 3VOUTn AUXOUTn POWER GOOD THRESHOLD (V) 2.70 2.68 2.66 2.64 –50 –25 0 25 50 TEMPERATURE (°C) OUT Discharge Resistance vs Temperature ONn, AUXONn, ENn LOW-HIGH THRESHLD (V) 1000 OUT DISCHARGE RESISTANCE (Ω) AUXOUTn 800 12VOUTn 600 1.242 1.240 ONn, AUXONn, ENn HYSTERESIS (mV) 400 3VOUTn 200 –50 –25 0 25 50 TEMPERATURE (°C) UW 6 4242 G01 12VINn UV Rising Threshold vs Temperature 10.0 1.2 9.8 0.9 12VINn 3VINn 9.6 0.6 7 0.3 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G02 9.4 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G03 12VOUTn Power Good Threshold vs Temperature 2.92 3VOUTn, AUXOUTn Power Good Threshold vs Temperature 10.4 2.90 10.2 2.88 10.0 2.86 75 100 4242 G04 9.8 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G05 2.84 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G06 ONn, AUXONn, ENn Low-to-High Threshold vs Temperature 90 ONn, AUXONn, ENn Hysteresis vs Temperature 80 1.238 70 1.236 60 1.234 75 100 4242 G07 1.232 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G08 50 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G09 4242f 5 LTC4242 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2) FONn Low-to-High Threshold vs VCC 5 FONn HIGH-LOW THRESHOOLD (V) FONn LOW-HIGH THRESHOLD (V) 3 4 2 1 0.20 1 0 0 2 3 4 VCC (V) 4242 G10 5 6 7 2 3 4 VCC (V) 5 6 7 4242 G11 RON (Ω) 3 RON vs AUXINn CURRENT LIMIT PROPAGATION DELAY (µs) 0.35 100 0.30 10 CIRCUIT BREAKER TRIP SENSE VOLTAGE (mV) RON (Ω) 0.25 0.20 0.15 3 3.5 4 4.5 5 AUXINn (V) 5.5 6 6.5 4242 G13 Aux Circuit Breaker Trip Current vs Temperature AUX CIRCUIT BREAKER TRIP CURRENT (mA) 650 25.0 CIRCUIT BREAKER TRIP FILTER TIME (µs) 600 550 20.0 GATE DRIVE (V) 500 450 –50 –25 0 25 50 TEMPERATURE (°C) 6 UW 75 4242 G14 FONn High-to- Low Threshold vs VCC 0.35 RON vs Temperature 0.30 2 0.25 0.15 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G12 Current Limit Propagation Delay vs Sense Voltage 52 Circuit Breaker Trip Sense Voltage vs Temperature 51 1 50 0.1 49 0.01 0 50 100 150 200 SENSE VOLTAGE (mV) 250 300 4242 G14 48 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G14 Circuit Breaker Trip Filter Time vs Temperature 6 5 4 3 2 1 0 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G17 Gate Drive vs IGATE 22.5 17.5 100 15.0 –50 2 4 6 IGATE (µA) 8 10 4242 G18 4242f LTC4242 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2) Gate Drive vs Temperature 6.0 –15 5.8 IGATE PULL-UP (µA) GATE DRIVE (V) –10 5.6 5.4 5.2 5.0 –50 –25 0 25 50 TEMPERATURE (°C) IGATE Off Current vs Temperature 1.2 GATE FAST PULL-DOWN CURRENT (mA) 300 IGATE OFF CURRENT (mA) 1.1 1.0 0.9 0.8 0.7 –50 –25 0 25 50 TEMPERATURE (°C) UW IGATE Pull-Up vs Temperature –5 75 100 4242 G19 0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G20 Gate Fast Pull-Down Current vs Temperature 275 250 225 74 100 4242 G21 200 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4242 G22 4242f 7 LTC4242 PI FU CTIO S 12VGATE1/12VGATE2: Gate Drive for 12V Supply External N-Channel MOSFET. An internal charge pump provides a 9µA pull-up current to ramp up 12VGATEn. During turn off, a 1mA pull-down current source discharges 12VGATEn to ground. 12VGATEn is internally clamped to 5.5V above 12VOUTn. During an overcurrent fault, a 250mA pull-down current source between 12VGATEn and 12VOUTn is activated. An external RC network is required at the pin for optimum current limit response. 12VSENSE1/12VSENSE2: 12V Supply Current Limit Sense Input. A sense resistor is placed in the supply path between 12VINn and 12VSENSEn to sense the 12V channel’s load current. The voltage across the sense resistor is monitored for active current limit and circuit breaker fault detection. To disable the circuit breaker function for the 12V channel, connect 12VSENSEn to 12VINn. 12VIN1/12VIN2: 12V Supply Input. An undervoltage lockout circuit disables the 12V and 3.3V supplies when 12VINn voltage is less than 9.78V. 12VOUT1/12VOUT2: 12V Output Connection. Connect this pin to the source of the 12V supply external N-channel MOSFET for gate drive return. PGOOD1/PGOOD2 cannot pull low until this pin goes above 10.38V. A 700Ω active pull-down discharges 12VOUTn to ground when the external MOSFET is turned off. 3VGATE1/3VGATE2: Gate Drive for 3.3V Supply External N-Channel MOSFET. An internal charge pump provides a 9µA pull-up current to ramp up 3VGATEn. During turn off, a 1mA pull-down current source discharges 3VGATEn to ground. 3VGATEn is internally clamped to 5.5V above 3VOUTn. During an overcurrent fault, a 250mA pull-down current source between 3VGATEn and 3VOUTn is activated. An external RC network is required at the pin for optimum current limit response. 3VSENSE1/3VSENSE2: 3.3V Supply Current Limit Sense Input. A sense resistor is placed in the supply path between 3VINn and 3VSENSEn to sense 3.3V channel’s load current. The voltage across the sense resistor is monitored for active current limit and circuit breaker fault detection. To disable the circuit breaker function for the 3.3V channel, connect 3VSENSEn to 3VINn. 3VIN1/3VIN2: 3.3V Supply Input. An undervoltage lockout circuit disables the 3.3V and 12V supplies when 3VINn voltage is less than 2.67V. 3VOUT1/3VOUT2: 3.3V Output Connection. Connect this pin to the source of the 3.3V supply external N-channel MOSFET for gate drive return. PGOOD1/PGOOD2 cannot pull low until this pin goes above 2.855V. A 375Ω active pull-down discharges 3VOUTn to ground when the external MOSFET is turned off. AUXFAULT1/AUXFAULT2: AUX Supply Fault Status Output. AUXFAULTn is normally pulled high by an internal 9µA pull-up. It asserts low if the AUX channel shuts off due to an overcurrent fault or due to the device temperature rising above 150°C. Indicates switch ON status when FONn and ENn are high. AUXON1/AUXON2: AUX Supply On Control Input. A rising edge turns on the internal FET, while a falling edge turns it off. Pulling this pin below 0.6V for more than 3.5µs clears the fault on the AUX channel. AUXIN1/AUXIN2: AUX Supply Input. An undervoltage lockout circuit disables the AUX supply when the voltage at AUXINn is less than 2.67V. AUXINn is the input to the internal pass FET. AUXOUT1/AUXOUT2: AUX Supply Output. AUXOUTn is the output from the internal pass FET. AUXPGOOD1/ AUXPGOOD2 cannot pull low until this pin goes above 2.855V. A 750Ω active pull-down discharges AUXOUTn to ground when the internal FET is turned off. 8 U U U 4242f LTC4242 PI FU CTIO S AUXPGOOD1/AUXPGOOD2 (QFN): AUX Supply Power Status Output. This open-drain pin is pulled high by an internal 9µA pull-up when AUXOUTn is below power good threshold, when ENn is high, during thermal shutdown, AUXONn is low or when VCC or AUXINn are in UVLO. EN1/EN2: Card Presence/Slot Insert Detect Input. ENn pin must be pulled below 1.235V to enable the system. An internal 9µA pull-up current source is present on this pin. Exposed Pad (QFN): Power Ground. PCB electrical connection is optional. FAULT1/FAULT2: Main Supplies Fault Status Output. FAULTn is pulled high by an internal 9µA pull-up. When an overcurrent fault occurs at either the 12V or 3.3V supply, FAULTn is latched low. FON1/FON2: Force On Digital Input. For diagnostic purposes, a high input overrides undervoltage and overcurrent faults on 12V, 3.3V and AUX channels and input commands on the ONn and AUXONn pins. However, UVLO on VCC would shut off the switches. Caution! There is no current limit mechanism in this mode. Connect FONn to ground to disable the fault override feature. GND: Device Ground. Connect to a ground plane. ON1/ON2: Main Supply On Control Input. A rising edge turns on the external MOSFETs for the 12V and 3.3V supplies, while a falling edge turns them off. Pull this pin below 0.6V to clear the faults on 12V and 3.3V channels. PGOOD1/PGOOD2: Main Supply Power Status Output. This open-drain pin is pulled high by an internal 9µA pull-up when 12VOUTn or 3VOUTn is below power good threshold, when ENn is high, ONn is low or when VCC or any of the main supplies are in UVLO. VCC: Device Supply Input. Operates from 2.7V to 6V. An internal undervoltage lockout circuit disables the part until the voltage at VCC exceeds 2.45V. U U U 4242f 9 LTC4242 FU CTIO AL DIAGRA OSCILLATOR ENn 1.235V ONn 0.6V 1.235V FONn AUXONn 0.6V 1.235V 12VINn 12VSENSEn 100mV 12VOUTn 7.4R R 3VINn 3VSENSEn 100mV 3VOUTn 1.31R R AUXINn THERMAL SHUTDOWN 10 W CHARGE PUMP VCC 10µA EN BOARD PRSNT ON1 MAIN ON SYSTEM CONTROL FORCE ON PGOODn VCC 9µA CP12V CP3V CPAUX VCC 12VIN 3VIN AUXIN 4 FAULTn UVLO VCC 9µA VCC GND U U + – + – – FON + – – ON2 AUX ON 3 3 SYSTEM CONTROL CP12V +– 50mV + – + – ACL1 9µA 12VGATEn ECB1 +– 12V SUPPLY CONTROL GATE DRIVER 5.5V 1.235V + – PG1 12V PWR GOOD 1mA 12V SUPPLY CP3V 12VOUTn +– 50mV + – + – ACL2 9µA 3VGATEn ECB2 +– 3.3V SUPPLY CONTROL GATE DRIVER 5.5V 1.235V + – PG2 3.3V PWR GOOD 1mA 3.3V SUPPLY VCC 9µA AUXFAULTn 3VOUTn CPAUX AUX SUPPLY CONTROL VCC 9µA AUXPGOODn AUX FET AUXOUTn AUX SUPPLY 4242 FD 4242f LTC4242 OPERATIO The Functional Diagram displays the main functional elements of this device. The LTC4242 is designed to control the power for two independent slots on a PCI Express backplane, allowing two boards to be safely inserted and removed. During normal operation, the charge pump sources 9µA to turn on the gate of the external N-channel MOSFETs to pass power to the load. The gates of the external MOSFETs are clamped about 5.5V above their sources. The gates of the AUX FETs rise at a slew rate of about 1.25V/ms to control the inrush current. The electronic circuit breaker (ECB) comparator and analog current limit (ACL) amplifier monitor the load current using the difference between the VIN and SENSE voltage. The threshold of the ACL is set at 2x the ECB threshold. The ACL amplifier limits the current in the load by reducing the gate-to-source voltage of the external MOSFETs in an active control loop. When an overcurrent condition persists for more than 20µs, the MOSFETs are shut off to prevent overheating. FAULT is latched low to signal that an overcurrent condition has occurred on the external MOSFETs controlling the main channels. The AUX FET’s control circuitry has a circuit breaker that trips at 550mA after 20µs. It also incorporates an active current limit amplifier that would limit the current flowing in the AUX FET to about 1.65A. A thermal shutdown circuit shuts off the AUX FET when the die temperature rises above 150°C. AUXFAULT is latched low to signal APPLICATIO S I FOR ATIO The typical LTC4242 application is in a backplane or motherboard that controls power to two PCI Express slots. The device reports fault and power good status to the system hot plug controller (HPC). The basic LTC4242 application circuit is shown in Figure 1. Discussion begins with board presence detection in a PCI Express system, the normal turn on and off sequence, the various fault conditons and recovery from fault situations. The force on operation is discussed next followed by the considerations for PCB layout. External component selection is discussed in detail in the Design Example section. U W U U U an overcurrent conditon on the internal FET or thermal shutdown has occurred. When the switches are off (both internal and external), the OUT pins are discharged to ground through internal N-channel transistors. The output voltages are monitored using the OUT pins and the PG comparators to determine if the voltage is valid. The power good conditon is signaled by the PGOOD/AUXPGOOD pins using open-drain pull-down transistors. The Functional Diagram shows the monitoring blocks of the LTC4242. The group of comparators in the system control includes the UVLO, ON and EN comparators. These comparators are used to determine if the external conditions are valid prior to turning on the switches. But first the undervoltage lockout circuit (UVLO) must validate the input supplies and the main supply VCC and generate the power up initialization to the logic circuits. The FON inverter in the system control is used for operating the LTC4242 in diagnostic mode. In this mode of operation, all pass transistors are forced to turn on, ignoring the undervoltage, circuit breaker/current limiting status and input commands. However, if VCC drops below its UVLO voltage, all switches would be shut off, regardless of FON. Board Presence Detect In PCI Express systems, the system board connector uses two signals, PRSNT1 and PRSNT2, to detect the presence of a board and ensure a fully inserted board in the connector as shown in Figure 2. PRSNT2 is routed to the system HPC. Upon a board insertion into the connector, a turn-on command is generated by the HPC to LTC4242 after a programmed HPC debounce delay, as shown in Figure 1. Another method to generate the debounce delay is through the delay network shown in Figure 3. 4242f 11 LTC4242 APPLICATIO S I FOR ATIO R1 8mΩ 12V R5 10Ω RG1 47Ω CG1 15nF 33 RS 33Ω C1 1µF 9 MRL1 4 10 32 31 30 8 7 12VIN1 12VSENSE1 12VGATE1 12VOUT1 3VIN1 VCC 29 BD_PRST1 2 1 28 19 18 PCIe CONNECTOR ×1 3.3V 375mA PRSNT2 PRSNT1 R2 13mΩ Q2 Si7336ADP 3 R6 10Ω 6 5 RG2 18Ω SMBus CG2 47nF 3 Q1 Si7336ADP 3.3V 3.3V AUXIN1 AUXON1 3 PWREN1 BD_PRST1 PWRFLT1 AUXPWRFLT1 HPC PGOOD1 PWRFLT2 AUXPWRFLT2 PGOOD2 BD_PRST2 36 35 34 20 21 22 ON1 FAULT1 AUXFAULT1 PGOOD1 FAULT2 AUXFAULT2 PGOOD2 LTC4242G PWREN2 17 ON2 BD_PRST2 PRSNT2 PRSNT1 MRL2 3.3V 16 11 AUXON2 AUXIN2 AUXOUT2 12VIN2 12VSENSE2 12VGATE2 12VOUT2 3VIN2 RG3 47Ω CG3 15nF 23 24 25 26 12 R7 10Ω 3.3V R4 13mΩ 12V R3 8mΩ Q3 Si7336ADP PCIe CONNECTOR ×1 4242 F01 Figure 1. Typical PCI Express Application 12 U SLOT A 12V 5.5A 3.3V 3A SMBus 3VSENSE1 3VGATE1 3VOUT1 AUXOUT1 FON1 EN1 GND EN2 FON2 SLOT B 27 3.3V 375mA 3 SMBus 3 SMBus 3VSENSE2 3VGATE2 3VOUT2 13 14 15 RG4 18Ω R8 10Ω CG4 47nF 3.3V 3A Q4 Si7336ADP 12V 5.5A 4242f W U U LTC4242 APPLICATIO S I FOR ATIO U PCI EXPRESS ADD-IN CARD TRACE ON THE ADD-IN CARD (ACTUAL TRACE ROUTING IS LEFT UP TO THE BOARD DESIGNER) MATE LAST/BREAK FIRST PULL-UP SYSTEM BOARD CONNECTOR PRSNT2 SYSTEM BOARD 4242 F02 OUT LTC4242 VOUT 9µA ENn RD 47k BD_PRSNT LOAD CD 33nF Figure 3. RC Network to Generate Delay During Card Plug-In When PRSNT2 pulls low after insertion of a board, the ENn pin goes low after a delay as determined by the values of CD and RD. For plug-in debounce delay of 1ms and RD of 47k: CD = tDELAY1 (ms) µF = 0.023µF 43.5 Choose CD to be 33nF. W U U GOLD FINGERS PRSNT1 HOT PLUG CONTROL LOGIC Figure 2. Plug-In Card Insertion/Removal + – GND 1.235V 4242 F03 MOTHERBOARD CONNECTOR PLUG-IN CARD When the board is removed, the power to the slot is disabled after a delay of: tDELAY 2 = 0.765CD s = 2.8ms 9 Turn-On Sequence The PCI Express power supplies are controlled by the external N-channel pass transistors, Q1 through Q4, in the 12V and 3.3V power paths, and internal pass transistors 4242f 13 LTC4242 APPLICATIO S I FOR ATIO for the 3.3V auxiliary power paths. Sense resistors R1 to R4 provide input for current fault detection. Resistors RG1 to RG4 and capacitors CG1 to CG4 compensate the current control loops. Capacitors CG1 to CG4 also control the output power-up rate and the inrush current while resistors R5 to R8 prevent high frequency oscillations in N-channel MOSFETs, Q1 to Q4 respectively. The following conditions must be satisfied before the external and internal switches can be turned on. 1. The device’s power supply, VCC, must exceed its undervoltage lockout threshold. To turn on the external/internal switches, the main/auxiliary input supplies must exceed their UVLO thresholds. 2. The EN pin must be pulled low to begin the start-up sequence. When these initial conditions are satisfied, the ON pins are checked. The LTC4242 features per slot ON pins, the AUXON and ON, to allow independent control of the main input supplies (12V and 3.3V) and the 3.3V auxiliary supplies. If the ON pin is high, the switches turn on. If ON is low, the switches turn on when the ON pin is brought high. Figure 4 shows all supplies turning on after EN goes low. Each of the external switches is turned on by charging the GATE with a 9µA current source. The voltage at the GATE pins rises with a slope equal to 9µA/CG and the supply inrush current is set at CL/CG • 9µA, where CL is the capacitance at the supply output. The gate of the internal switch is slewed resulting in the 3.3VAUX supply output powering up at an internally set rate of about 1.25V/ms. The circuit breaker (ECB) of the input supplies is armed after the input supplies clear UVLO. Once the supplies have been turned on and the outputs are within tolerance, PGOOD for the main input supplies and AUXPGOOD for the auxiliary input supplies (available for the QFN only) are pulled low. 14 U ENn 5V/DIV AUXOUTn 5V/DIV 12VOUTn 5V/DIV 3VOUTn 5V/DIV PGOODn 5V/DIV 10ms/DIV 4242 F04 W U U Figure 4. Normal Power-Up Sequence Turn-Off Sequence The switches can be turned off by a variety of conditions. 1. The ON/AUXON pin going low would turn off the main/ internal switches. 2. EN going high turns off all switches. 3. A variety of fault conditions will turn off the switches. These include supply undervoltage and overcurrent circuit breaker faults. 4. When thermal shutdown activates, the internal switch is shut off. When ON goes low, the main switches are turned off with a 1mA current pulling down the gate to ground. When the main supplies are shut off, the PGOOD signal pulls high and the outputs are discharged to ground through internal switches. Similarly, when an auxiliary supply is turned off, the AUXPGOOD signal pulls high and its output is discharged to ground through internal switches. Figure 5 shows all supplies being turned off by EN going high. 4242f LTC4242 APPLICATIO S I FOR ATIO ENn 5V/DIV AUXOUTn 5V/DIV 12VOUTn 5V/DIV 3VOUTn 5V/DIV PGOODn 5V/DIV 100ms/DIV 4242 F05 Figure 5. Normal Power-Down Sequence Thermal Shutdown Each of the two internal switches for the 3.3V auxiliary supplies is protected by an independent thermal shutdown circuit. If the temperature of an internal switch reaches 150°C, the switch shuts down immediately and AUXFAULT is latched low. All other power switches are not affected. The switch is allowed to turn on again by recycling the AUXON pin low then high with the temperature falling below 120°C. Overcurrent Fault The LTC4242 features dual level glitch tolerant protection against overcurrent faults for all the supplies. The sense resistor (both internal and external) voltage drop is monitored by an electronic circuit breaker (ECB) comparator and an active current limit (ACL) amplifier. In the event that a supply’s current exceeds the ECB threshold, an internal timer is started. If the supply is still overcurrent after 20µs, the ECB trips and the MOSFET turns off immediately, as shown in Figure 6. During start-up, a supply output could be shorted to ground in the worst case. The inrush current would be limited to the ACL threshold, which is 2x the ECB threshold, and the part will latch off after 20µs. U FAULTn 5V/DIV 3VOUTn 5V/DIV 3VGATEn 5V/DIV ILOAD 3A/DIV 5µs/DIV 4242 F06 W U U Figure 6. Overcurrent Fault on 3.3V Output FAULTn 5V/DIV 3VOUTn 5V/DIV 3VGATEn 5V/DIV ILOAD 10A/DIV 5µs/DIV 4242 F07 Figure 7. Short-Circuit Fault on 3.3V Output During an output short circuit, the surge current must be brought to a controlled level within the shortest amount of time to protect the system. The LTC4242’s active current limit enters a high current protection mode that immediately turns off the output MOSFET by pulling its gate-to-source voltage to zero. Current in the output MOSFET drops from tens of amps to zero in a few hundred nanoseconds. The input voltage drops during the high current and then spikes upwards due to lead parasitic inductances as the 4242f 15 LTC4242 APPLICATIO S I FOR ATIO AUXFAULTn 5V/DIV AUXOUTn 5V/DIV AUXINn 5V/DIV ILOAD 5A/DIV 5µs/DIV 4242 F08 Figure 8. Short-Circuit Fault on 3.3VAUX Output MOSFET shuts off (see Supply Transients). The compensation network RG/CG assists the gate voltage recovery. The ACL limits the current level to 2x the ECB threshold by regulating the gate voltage. For the internal switch, the ACL limits the supply current to about 3x the circuit breaker current level of 550mA. The ECB has a 20µs filter delay before latching off to prevent unnecessary resets of the system due to minor transient surges. An overcurrent fault on any of the main outputs (12V or 3.3V) latches off both main outputs without affecting the 3.3V auxiliary output. Similarly, an overcurrent fault on the 3.3V auxiliary output latches off the auxiliary output, without affecting the main outputs. When there is a shorted load with significant supply lead inductance, the supply pin voltage could collapse before the ACL brings down the gate of the external MOSFET. In this case, the undervoltage lockout circuit, with 18µs filter time, turns off the pass MOSFETs. Undervoltage Fault An undervoltage fault occurs when any of the input supplies, 12VIN, 3VIN or AUXIN, falls below its undervoltage threshold for more than 18µs. This turns off the switches immediately. An undervoltage on the 3.3V auxiliary supply will not cause the main supplies to shut off and vice versa. An undervoltage fault on any of the main supplies shuts off both main supply switches. If VCC falls below 16 U its UVLO threshold for more than 38µs, all switches are turned off. The switches are allowed to turn on when the supply voltages and VCC rise above their respective undervoltage thresholds. Power Good Fault A power good fault occurs when any supply output drops below its power good threshold for more than 20µs. A power good fault on the main/AUX supplies causes the PGOOD/AUXPGOOD to be pulled high. There are a variety of conditions which must be satisfied for PGOOD/ AUXPGOOD to be asserted low: 1. The output voltage is above power good threshold 2. EN pin is low 3. The input voltage is above the undervoltage threshold 4. ON pin is high 5. Thermal shutdown not activated Resetting Faults To reset an overcurrent fault on the main outputs, bring ON low or the faulting supply below its undervoltage lockout (UVLO) threshold. To reset an overcurrent or thermal shutdown fault on the auxiliary output, bring AUXON low or the auxiliary suppy below its UVLO threshold. Bringing VCC below its UVLO threshold resets all overcurrent and thermal shutdown faults. The part cannot be reset when fault overide, FON, is high. Auto-Retry After a Fault As shown in Figure 9, the LTC4242 can be configured to automatically retry after a fault condition by connecting both the FAULT and ON pins together with an RC network. The auto-retry circuit will attempt to restart the LTC4242 after a circuit breaker trip, as shown in the timing diagram of Figure 10. tOFF ≈ R AUTO • C AUTO • (1.235 – VOL ) 2.065 + R AUTO • 9µA For the component values shown, tOFF = 3.3ms. Since the duration of a short is less than 40µs in the worst case, the auto-retry duty cycle is 1.3%. 4242f W U U LTC4242 APPLICATIO S I FOR ATIO 3.3V R2 13mΩ Q2 Si7336ADP 3VGATE 3VSENSE RAUTO 200k CAUTO 0.1µF 3VIN LTC4242* FAULT ON GND 4242 F09 3VOUT EN BD_PRST *ADDITIONAL DETAILS OMITTED FOR CLARITY Figure 9. Auto-Retry Application 3VIN 1.235V 0.6V VOL VTH ON/FAULT 3VGATE 3VIN – 3VSENSE VCB tOFF tCB 4242 F10 Figure 10. Auto-Retry Timing GATE Pin Voltage The minimum gate drive voltage is 4.5V, therefore, logic level N-channel MOSFETs should be used for the external switches to maintain adequate gate enhancement. The GATE pins are clamped at a typical value of 5.5V above the respective OUT pins. Compensating the Active Current Loop The active current limit circuit is compensated using the resistor RG and the slew rate control capacitor CG. The value of CG is selected based on the inrush current allowed. The RG value should be experimentally determined. A suggested value range for RG is between 10Ω and 100Ω. U VCC Power Supply The LTC4242 derives its power from VCC. A bypass capacitor of 1µF should be connected between this pin and ground. If VCC is derived from the input supplies of 3VIN or AUXIN, a lowpass filter shown in Figure 11 should be used. This RC network allows the LTC4242 to ride through a 3VIN/AUXIN short-circuit transient without collapsing below the VCC UVLO threshold. AUXIN or 3VIN may have narrow but high glitches due to parasitic inductance. Since the absolute maximum rating for VCC is 7V compared to 10V for AUXIN and 3VIN, the RS and C1 values should be chosen to damp the peak voltage seen by VCC below 7V. AUXIN OR 3VIN RS 33W C1 1mF 4242 F11 W U U LOAD VCC Figure 11. RC Network for VCC Filtering Force ON Operation When the FON pin is pulled high and EN is low, the LTC4242 operates in the diagnostic mode. All the input supplies’ power switches are forced to turn on, regardless of undervoltage conditions on the input supplies, status of the ON pins and the fault latch. The contents in the fault latch would be preserved during this time and no change of state would occur after the part is configured to operate in the diagnostic mode. If the output current exceeds the ECB threshold, FAULT/AUXFAULT is pulled low immediately, but does not latch. The undervoltage lockout on VCC turns off all the switches, regardless of the status of FON. During thermal shutdown, the internal switch is shut off to prevent overheating, even if FON is high. The main power switches remain on as FON is high. Care must be taken to ensure the outputs are not short circuited since there is no current limit mechanism in diagnostic mode. 4242f 17 LTC4242 APPLICATIO S I FOR ATIO Yet another mode of operation is the Force ON with current limit mode. To enter this mode, pull both FON and EN high. In this mode of operation, the ACLs are enabled with the 20µs filter time disabled. The fault latch of the AUX supply can be latched if the AUX’s ICBAUX is exceeded. AUXFAULT indicates whether the AUX channel FET is on or off. To enter normal operation, pull FON and EN low and recycle the ON and AUXON pins. PCB Layout Considerations For proper operation of the LTC4242’s circuit breaker, a Kelvin connection to the sense resistors is required. The Kelvin sense PCB layout traces should be minimum length, closed together, balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for optimal device power dissipation. A recommended PCB layout for the 12V sense resistor and the power MOSFET is illustrated in Figure 12. CURRENT FLOW TO LOAD SENSE RESISTOR 12VIN1 12V W TRACK WIDTH W: 0.03" PER AMPERE ON 1OZ Cu FOIL C1 33 32 31 LTC4242G* 30 GND W *ADDITIONAL DETAILS OMITTED FOR CLARITY, DRAWING NOT TO SCALE! Figure 12. Recommended Layout for Power MOSFET, Sense Resistor and GATE Components for the 12V Rail 4242f 18 U In Hot Swap applications where load currents can be 10A, narrow PCB tracks exhibit more resistance than wider tracks and hence, operate at higher temperatures. Since the sheet resistance of 1oz copper foil is approximately 0.5mΩ/square, track resistances and voltage drops add up quickly in high current applications. Thus, to keep PCB track resistance, voltage drop and temperature rise to a minimum, the suggested trace width in these applications for 1oz copper foil is 0.03" for each ampere of DC current. In the majority of applications, it will be necessary to use plated-through vias to make circuitry connections from components layers to power and ground layers internal to the PCB. For 1oz copper foil plating, a general rule is 1A of DC current per via making sure the via is properly dimensioned so that solder completely fills any void. Check with your PCB fabrication facility for via current specifications. POWER PAK SO-8 CURRENT FLOW TO LOAD W 12VOUT1 12V R5 12VGATE1 RG1 CG1 W U U • VIA PATH TO GND CURRENT FLOW TO SOURCE VIA TO GND PLANE • GND 4242 F12 LTC4242 APPLICATIO S I FOR ATIO In system board applications, large bypass capacitors (≥10µF) are recommended at each of the system input supplies to minimize supply glitches as a result of large inrush or fault currents. It is important to put C1, the bypass capacitor for the VCC pin as close as possible between the VCC and GND pins. Design Example Consider a PCI Express Hot Swap application example with the following power supply requirements: Table 1. PCI Express Power Supply Requirements SUPPLY VOLTAGE 12V 3.3V 3.3VAUX MAXIMUM SUPPLY CURRENT 5.5A 3.0A 375mA MAXIMUM LOAD CAPACITANCE 2000µF 1000µF 150µF 1. Select an RSENSE value for each supply. Calculate the RSENSE value based on the maximum load current and the lower circuit breaker threshold limit, ΔVSENSE(CB)(MIN). In a PCI Express connector, five pins are allocated for the 12V supply, three pins for the 3.3V supply and one pin for 3.3VAUX. The current rating of a connector pin is 1.1A. If a 1% tolerance is assumed for the sense resistors, then the following values of resistances should suffice: Table 2. Sense Resistance Values VOLTAGE SUPPLY 12V 3.3V RSENSE (1%) 8mΩ 13mΩ ITRIP(MIN) 5.6A 3.4A ITRIP(MAX) 6.9A 4.3A 2. Assume no load current at start-up and the inrush current charges the load capacitance. Compute gate capacitance with: CGATE = IGATE(UP) • t1 VOUT (2) t1 is the time to charge up the load capacitor. With IGATE(UP)(MAX) = 13µA and t1 = 10ms: a. For 12V Supply, CGATE = 11nF b. For 3.3V Supply, CGATE = 39nF U So a value of 15nF and 47nF (±10%) should suffice for the 12V and 3.3V supplies respectively. The worst-case t1 and inrush currents are tabulated in Table 3. Table 3. Worst-Case t1 and Inrush Current VOLTAGE SUPPLY 12V 3.3V t1(MIN) 13ms 11ms t1(MAX) 40ms 34ms MAX IINRUSH 2.4A 0.4A W U U For the internal switch, the slew rate (SR) at the 3.3VAUX supply output is limited to 1.7V/ms max. The inrush current can then be calculated according to: IINRUSH(MAX) = CLOAD • SRMAX (3) The inrush current must be lower than 385mA (ICBAUX(MIN)) for proper start-up. Assuming a tolerance of 30% for the load capacitance, the value of CLOAD should not exceed 170µF. 3. Next is the selection of MOSFETs for the 12V and 3.3V main input supplies. The Si7336ADP’s on resistance is less than 4mΩ at VGS = 4.5V, 25°C and it is a good choice for 3.3V and 12V main supplies. Since the maximum load for the 3.3V supply is 3A, the MOSFET may dissipate up to 36mW. The Si7336ADP has a maximum junction-to-ambient thermal resistance of 50°C/W. This gives a junction temperature of 51.8°C when operating at a case temperature of 50°C. According to the Si7336ADP’s Normalized On-Resistance vs Junction Temperature curve, the device’s on resistance can be expected to increase by about 12% over its room temperature value. Recalculation for steady-state RON and junction temperature yield approximately 4.5mΩ and 52°C, respectively. The voltage drop across the 3.3V sense resistor and series MOSFET at 3A and at 50°C PCB temperature is less than 53mV. The MOSFET dissipates power during inrush charging of the output load capacitor. Assuming no load current, the MOSFET’s dissipated power equals the final load capacitor stored energy. Therefore, average MOSFET dissipated power is: PON = 2 CL • VOUT 2 • t1 (4) 4242f 19 LTC4242 APPLICATIO S I FOR ATIO Using PON and t1 to look up the MOSFETs’ single pulse θJA(MAX) from the manufacturer’s Transient Thermal Impedance Graph, the worst-case junction-to-ambient temperature rise occurs for the 12V MOSFET. Table 4. MOSFET Power-Up Temperature Rise Calculation VOLTAGE SUPPLY 12V 3.3V PON 11W 0.5W θJA(MAX) 0.75°C/W 0.6°C/W ΔT 8.3°C 0.3°C There is a 20µs filter time when large current of 2x circuit breaker’s threshold can flow in the switches. This time is 20 U short enough to cause minimal increase in the junctionto-ambient temperature of the MOSFETs, in the event of powering up into short circuit or short circuiting after power up. Therefore, in these events, it can be safely assumed that the MOSFETs would have minimal thermal stress on them. If the LTC4242 operates in the diagnostic mode, user must ensure a safe joule heating limit of the external MOSFET. The internal switch will be disabled once the temperature reaches 150°C, thereby preventing overheating. 4242f W U U Standalone Hot Swap Application for Four Supplies: 12V, 5V, 3.3V and 3.3V Standby 12VIN 12V 4mΩ Si7336ADP + SMAJ15A 100nF 10Ω 8mΩ Si7336ADP 3.3V 5A 1000µF 10Ω 2000µF 12V 10A 3.3VIN 3.3V + SMAJ5.0A 100nF 15nF 33Ω 1µF AUXIN1 AUXIN2 VCC 12VIN2 12VIN1 12VSENSE2 12VSENSE1 12VGATE1 12VOUT2 12VOUT1 3VIN1 3VSENSE1 3VGATE1 3VOUT1 10Ω 18Ω 47nF 10Ω 47Ω VSTANDBY 3.3V SMAJ5.0A 100nF 10Ω AUXOUT1 AUXOUT2 + 3.3V STANDBY 385mA 150µF PGOOD1 PGOOD2 ON LTC4242 10k EN1 EN2 10k 10k AUXON1 AUXON2 ON1 ON2 FON1 FON2 12VGATE2 NC 2N2222 4.7µF AUXFAULT AUXFAULT2 AUXFAULT1 FAULT1 FAULT2 GND FAULT BD_PRST 3VIN2 3VSENSE2 3VGATE2 3VOUT2 18Ω 10Ω 47nF 5VIN 5V SMAJ7.0A 100nF 10Ω 8mΩ Si7336ADP + 5V 5A 1000µF 4242 TA02 BACKPLANE PLUG-IN CARD U LTC4242 TYPICAL APPLICATIO 21 4242f LTC4242 PACKAGE DESCRIPTIO U G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ± 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) MAX 0° – 8° 7.8 – 8.2 0.42 ± 0.03 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 0.22 – 0.38 (.009 – .015) TYP 0.05 (.002) MIN G36 SSOP 0204 4242f 22 LTC4242 PACKAGE DESCRIPTIO U UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.15 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 0.00 – 0.05 3.15 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 37 38 0.40 ± 0.10 1 2 5.15 ± 0.10 (2 SIDES) 0.40 ± 0.10 0.200 REF 0.25 ± 0.05 0.75 ± 0.05 0.200 REF 0.00 – 0.05 0.50 BSC R = 0.115 TYP (UH) QFN 0205 5.50 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 3.15 ± 0.05 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 7.00 ± 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4242f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC4242 TYPICAL APPLICATIO PAYLOAD POWER SOURCE MANAGEMENT POWER SOURCE 10Ω Hot Swap Application for Two Advanced Mezzanine Cards (AMC) MODULE 1 0.008Ω Si7336ADP 12V 5.6A 0.4Ω Si2306DS 3.3V 100mA BD_PRSNT1 22Ω 33nF 33Ω 1µF 12VIN1 12VSENSE1 12VGATE1 12VOUT1 3VIN1 VCC 10Ω 33nF 3VSENSE1 3VGATE1 3VOUT1 AUXFAULT1 AUXFAULT2 AUXIN1 AUXIN2 ON1 PGOOD1 ON2 PGOOD2 FAULT1 FAULT2 BD_PRSNT1 BD_PRSNT2 3VIN2 AUXOUT1 AUXOUT2 LTC4242G FON1 FON2 AUXON1 AUXON2 EN1 EN2 GND 3VSENSE2 3VGATE2 3VOUT2 12VIN2 12VSENSE2 12VGATE2 12VOUT2 22Ω 33nF 10Ω 10Ω 33nF BD_PRSNT2 0.008Ω 0.4Ω Si7336ADP PS0 PS1 12V 5.6A 3.3V 100mA CARRIER AMC CARD 4242 TA03 INTELLIGENT PLATFORM MANAGEMENT CONTROLLER PAYLOAD POWER SOURCE MANAGEMENT POWER SOURCE RELATED PARTS PART NUMBER LTC4210 LTC4213 LTC4214 LTC4215 LTC4216 LT®4220 LTC4221 LTC4241 DESCRIPTION Hot Swap Contoller No RSENSETM Electronic Circuit Breaker Negative Low Voltage Hot Swap Controller Hot Swap Controller with I2C Compatible Monitoring Ultralow Voltage Hot Swap Controller Dual Supply Hot Swap Controller Dual Hot Swap Controller PCI-Bus Hot Swap Controller COMMENTS 6-Lead SOT-23 Package Three Selectable Circuit Breaker Thresholds Controls Supplies from 0V to –16V 2.9V to 15V, 8-Bit ADC Monitors Current and Voltages Load Voltages from 0V to 6V ±2.7V to ±16V Operation Power Sequencer with Dual Speed, Dual Level Fault Protection 3.3V Auxiliary Supply 4242f No RSENSE is a trademark of Linear Technology Corporation. 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006 U PS1 PS0 CARRIER AMC CARD NC MODULE 2 Si2306DS LT 1106 • PRINTED IN USA