LTC4245

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LTC4245 Multiple Supply Hot Swap Controller with I2C Compatible Monitoring DESCRIPTIO The LTC®4245 Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane in multiple supply systems such as CompactPCI and PCI Express. Using four external N-channel pass transistors, the board supply voltages can be ramped up at an adjustable rate and in any desired sequence. An I2C interface and onboard ADC allow monitoring of board current, voltage and fault status for each supply. The device features adjustable dI/dt controlled soft start and foldback limited inrush current. A dual-level timed circuit breaker and fast current limit protect each supply against overcurrent faults. A power good input with timeout allows a downstream supply monitor to disconnect the board supplies. The device can be configured to function without a –12V supply or with an extra 3.3V supply instead of a 5V supply. The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up in either the on or off state. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Allows Safe Insertion into Live CompactPCITM or PCI ExpressTM Backplane 8-Bit ADC Monitors Current and Voltage I2CTM/SMBus Interface dI/dt Controlled Soft Start Simultaneous or Sequenced Turn-On ±20V Absolute Maximum Rating for ±12V Supplies No External Gate Capacitor Required Dual-Level Circuit Breaker and Current Limit Bus Precharge Output Power Good Input with Timeout Optional Latchoff or Autoretry After Faults Alerts Host After Faults Integrated LOCAL_PCI_RST# Logic 36-Pin SSOP and 38-Pin (5mm × 7mm) QFN Packages APPLICATIO S ■ ■ Live Board Insertion CompactPCI, CompactPCI Express, CompactTCA, PCI Express Systems TYPICAL APPLICATIO BACKPLANE CONNECTOR CARD CONNECTOR CompactPCI Application Sequenced Turn-On Waveform 5VOUT 12VOUT BD_SEL# 10V/DIV 12VOUT OUTPUT VOLTAGE 5V/DIV VEEOUT 5VOUT 3VOUT 12VIN 12VSENSE 12VGATE 12VOUT 5VIN 5VSENSE 5VGATE 5VOUT BD_SEL# ON HEALTHY# SDA SCL ALERT# PCI_RST# GND PRECHARGE LTC4245 LOCAL_PCI_RESET# PGI SUPPLY MONITOR RESET BOARD RESET TO BUS LOCAL_PCI_RST# 5V/DIV TIME (50ms/DIV) –12VOUT 4245 TA01b 3VOUT VEEIN VEESENSE VEEGATE VEEOUT 3VIN 3VSENSE 3VGATE 3.3VOUT U U U 4245fa 1 LTC4245 ABSOLUTE (Notes 1, 2) AXI U RATI GS VEEGATE – VEEIN (Note 4) .......................... –0.3V to 5V 12VSENSE ........... –0.3V or 12VIN – 6V to 12VIN + 0.3V nSENSE...........................................–0.3V to nIN + 0.3V VEESENSE ..................................... VEEIN – 0.3V to 0.3V 12VOUT – 12VGATE (Note 4)...................... –5V to 0.3V nOUT – nGATE (Note 4) .............................. –5V to 0.3V VEEOUT (Note 5)...................................... –20V to 0.3V PRECHARGE .............................. –0.3V to 3VIN + 0.3V Operating Temperature Range LTC4245C ................................................ 0°C to 70°C LTC4245I ............................................. –40°C to 85°C Storage Temperature Range G Package .......................................... –65°C to 150°C UHF Package...................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) G Package ......................................................... 300°C Supply Voltages 12VIN ..................................................... –0.3V to 20V 5VIN, 3VIN .............................................. –0.3V to 10V VEEIN ...................................................... –20V to 0.3V INTVCC .................................................. –0.3V to 6.5V Input Voltages BD_SEL#, ON, PGI ................................. –0.3V to 12V ADR0-3, CFG, SS, TIMER ...... –0.3V to INTVCC + 0.3V PCI_RST#, SCL, SDA ............................ –0.3V to 6.5V Output Voltages ALERT#, GPIO1-3, HEALTHY#, LOCAL_PCI_RST# ................................ –0.3V to 6.5V Analog Voltages (n is 5V, 3V) 12VGATE ................................................. –0.3V to 25V nGATE (Note 3)............... –0.3V to 12VIN + 0.3V or 14V PACKAGE/ORDER I FOR ATIO TOP VIEW HEALTHY# TIMER ON SS 12VIN 12VSENSE 12VGATE 12VOUT GND 1 2 3 4 5 6 7 8 9 36 5VIN 35 5VSENSE 34 5VGATE 33 5VOUT 32 ADR3 31 ADR2 30 ADR1 29 ADR0 28 INTVCC 27 GPIO1 26 PGI 25 PCI_RST# 24 LOCAL_PCI_RST# 23 PRECHARGE 22 3VIN 21 3VSENSE 20 3VGATE 19 3VOUT HEALTHY# 5VSENSE 5VGATE TIMER 38 37 36 35 34 33 32 SS 1 12VIN 2 12VSENSE 3 12VGATE 4 12VOUT 5 GND 6 BD_SEL# 7 CFG 8 SDA 9 SCL 10 ALERT# 11 VEESENSE 12 13 14 15 16 17 18 19 3VOUT VEEIN 3VGATE VEEOUT 3VSENSE VEEGATE 3VIN 39 31 ADR3 30 ADR2 29 ADR1 28 ADR0 27 INTVCC 26 GPIO3 25 GPIO2 24 GPIO1 23 PGI 22 PCI_RST# 21 LOCAL_PCI_RST# 20 PRECHARGE BD_SEL# 10 CFG 11 SDA 12 SCL 13 ALERT# 14 VEESENSE 15 VEEIN 16 VEEGATE 17 VEEOUT 18 G PACKAGE 36-LEAD PLASTIC SSOP UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 95°C/W TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 39) PCB GND CONNECTION OPTIONAL ORDER PART NUMBER LTC4245CG LTC4245IG ORDER PART NUMBER LTC4245CUHF LTC4245IUHF UHF PART MARKING* 4245 4245 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. 4245fa 2 5VOUT 5VIN ON U U W WW U W TOP VIEW LTC4245 ELECTRICAL CHARACTERISTICS SYMBOL Supplies IDD Input Supply Current 12VIN 5VIN 3VIN, PRECHARGE Open VEEIN 12VIN 5VIN, VCFG = 0V, Open 5VIN When VCFG = VCC, 3VIN VEEIN, VCFG = 0V VCC Falling ● ● ● ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, V5VIN = 5V, V3VIN = 3.3V, VVEEIN = –12V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP 3 0.5 0.6 –0.5 10.2 4.25 2.7 –10.2 3.4 5 10.5 4.38 2.8 –10.5 3.8 5.5 MAX 5 1 1 –1 10.8 4.5 2.9 –10.8 4.2 6 UNITS mA mA mA mA V V V V V V VUVL Supply Undervoltage Lockout VCC Current Limit ΔVSNS(CB) Internal Regulator Voltage Circuit Breaker Trip Sense Voltage (V12VIN – V12VSENSE) (V5VIN – V5VSENSE) (V3VIN – V3VSENSE) (VVEESENSE – VVEEIN) Active Current Limit Sense Voltage (V12VIN – V12VSENSE) (V5VIN – V5VSENSE) (V3VIN – V3VSENSE) (VVEESENSE – VVEEIN) Foldback Current Limit Sense Voltage (V12VIN – V12VSENSE) (V5VIN – V5VSENSE) (V3VIN – V3VSENSE) (VVEESENSE – VVEEIN) After Start-Up ● ● ● ● 45 22.5 22.5 40 130 60 60 130 10 40 4 22 4 22 11 40 5 –16 0.9 1.7 125 155 32 1.21 70 –7 50 25 25 50 150 75 75 150 15 50 7.5 25 7.5 25 16 50 6.2 –20 1.3 3.5 250 310 65 1.235 120 –10 55 27.5 27.5 60 170 90 90 170 20 60 11 29 11 29 21 60 7.5 –24 1.7 5.3 375 465 98 1.26 170 –16 mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV V μA mA mA mA mA mA V mV µA ΔVSNS(ACL) After Start-Up ● ● ● ● ΔVSNS(FBL), ΔVSNS(FBH) Start-Up, VTIMER = 0V V12VOUT = 0V V12VOUT = 12V V5VOUT = 0V V5VOUT = 5V V3VOUT = 0V V3VOUT = 3.3V VVEEOUT = 0V VVEEOUT = –12V Gate to Source Gate Drive On, ΔVGATE = 0V Gate Drive Off, ΔVGATE = 5V VOUT = VIN VVEEGATE = –7V Fast Turn Off, ΔVGATE = 5V V12VGATE = 17V, V5VGATE = 10V V3VGATE = 8.3V VVEEGATE = –7V VON Rising, VBD_SEL# Rising VBD_SEL# = 0V ● ● ● ● ● ● ● ● Gate Drive ΔVGATE IGATE(UP) IGATE(DN) Gate Drive Gate Pull-Up Current Gate Pull-Down Current 12VGATE, 5VGATE, 3VGATE, VEEGATE Gate Fast Pull-Down Current 12VGATE, 5VGATE 3VGATE VEEGATE ON, BD_SEL# Pin Threshold Voltage BD_SEL# Pull-Up Current ● ● ● ● ● ● ● IGATE(FST) Input/Output Pins VON, BD_SEL#(TH) IBD_SEL#(UP) ● ● ● ΔVON, BD_SEL#(HYST) ON, BD_SEL# Pin Hysteresis 4245fa 3 LTC4245 ELECTRICAL CHARACTERISTICS SYMBOL VPB(TH) PARAMETER Power Bad Threshold Voltage The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, V5VIN = 5V, V3VIN = 3.3V, VVEEIN = –12V, unless otherwise noted. CONDITIONS 12VOUT 5VOUT, VCFG = 0V, Open 5VOUT When VCFG = VCC, 3VOUT VEEOUT, VCFG = 0V PGI, PCI_RST#, GPIOn SDA, SCL ON, PGI, PCI_RST#, V = 1.2V SDA, SCL, ALERT#, GPIOn, HEALTHY#, LOCAL_PCI_RST#, V = 6V SDA, ALERT#, I = 5mA; GPIOn, HEALTHY#, LOCAL_PCI_RST#, I = 3mA ● ● ● ● ● ● ● MIN 10.8 4.5 2.8 –10.8 0.8 1.6 TYP 11.1 4.63 2.9 –11.1 1.0 1.8 0 MAX 11.4 4.75 3.0 –11.4 1.2 2.0 ±1 UNITS V V V V V V μA VIN(TH) IIN Logic Input Threshold Pin Input Current VOL VTRI(H) VTRI(L) ITRI(IN,HL) ITRI(IN,Z) IADR01(IN) ISENSE Output Low Voltage ADR2, ADR3, CFG Input High Threshold ADRn, CFG Input Low Threshold ADR2, ADR3, CFG High, Low Input Current ADR2, ADR3, CFG High Z Input Current ADR0, ADR1 Input Current Sense Pin Input Current 12VSENSE, 5VSENSE, 3VSENSE VEESENSE OUT Pin Input Current ● ● ● 0.2 VCC –0.8 0.2 0.4 V V V μA μA VCC –0.4 VCC –0.2 0.4 0.8 ±80 V = 0V, VCC V = 0.8V, VCC –0.8V VADR0, VADR1 = 0V, VCC After Start-Up VSENSE = VIN VVEESENSE = –12V V12VOUT = 12V, VON = 2V V5VOUT = 5V, VON = 2V V3VOUT = 3.3V, VON = 2V VVEEOUT = –12V, VON = 2V V12VOUT = 6V, VON = 0V V5VOUT = 3V, VON = 0V V3VOUT = 2V, VON = 0V VVEEOUT = –6V, VON = 0V VVEEOUT = 0V IPRECHARGE = Open, –70mA (Note 6) VTIMER Rising VTIMER Falling During Start-Up, VTIMER = 0V During PGI Timeout, VTIMER = 0V During Auto-Retry, VTIMER = 0V (ITIMER(RTRY)/ITIMER(START)) ((VTIMER(H) – VTIMER(L))/ITIMER(START)) Fast Ramp, VSS = 0V Slow Ramp, VSS = 2V VTIMER = 1.2V, VSS = 1.2V 12VIN, VEEIN 5VIN, 3VIN ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ±10 –30 0.3 –30 200 275 75 –200 650 125 130 1300 0.95 2.5 0.1 –80 –8 –1.5 1.6 20 –16 –1.5 1000 180 190 1800 –36 1 2.56 0.23 –100 –10 –2 2 23.3 –20 –2 225 46 23 1 1 –45 280 390 105 –280 1800 325 340 3200 –54 1.05 2.62 0.4 –120 –12 –2.5 2.7 26 –24 –2.5 400 μA μA μA μA μA μA μA Ω Ω Ω Ω μA V V V μA μA μA % ms/μF μA μA Ω mV/V mV/V IOUT(ON) ROUT(DIS) OUT Pin Discharge Resistance IVEEOUT(UP) VPXG Timer, Soft-Start VTIMER(H) VTIMER(L) ITIMER VEEOUT Pull-Up Current PRECHARGE Voltage TIMER Pin High Threshold TIMER Pin Low Threshold TIMER Pin Pull-Up Current ● ● ● ● ● ● ● ● ● ● KTMRATIO KTMCAP ISS RTS(DIS) GSS TIMER Pin Current Ratio Start-Up Time per TIMER Capacitance SS Pin Pull-Up Current TIMER, SS Discharge Resistance Gain from SS Pin to Foldback Current Limit (ΔVSNS(FB)/ΔVSS) 4245fa 4 LTC4245 ELECTRICAL CHARACTERISTICS SYMBOL ADC RES VFS Resolution (No Missing Codes) Full-Scale Voltage (VFS = 255LSB) 12VIN, 12VOUT 12VIN – 12VSENSE, VEESENSE – VEEIN 5VIN, 5VOUT 5VIN – 5VSENSE, 3VIN – 3VSENSE 3VIN, 3VOUT VEEIN, VEEOUT GPIO INL OE Integral Nonlinearity Offset Error ΔVSENSE (Note 8) Other 9 Channels ΔVSENSE (Note 6) VEEIN, VEEOUT Other 7 Channels (Note 7) ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, V5VIN = 5V, V3VIN = 3.3V, VVEEIN = –12V, unless otherwise noted. PARAMETER CONDITIONS MIN 8 13.744 62.47 5.5 3.75 31.24 3.75 –13.744 2.5 14.025 14.306 65.03 63.75 5.72 5.61 3.9 3.825 32.51 31.875 3.9 3.825 –14.025 –14.306 2.6 2.55 ±0.5 ±0.2 ±0.5 ±0.5 ±0.3 ±2 ±1.25 ±1.5 ±1.25 ±1 ±5 ±5 665 70 35 ● TYP MAX UNITS Bits V mV V V mV V V V LSB LSB LSB LSB LSB LSB LSB ms ms ms (Note 6) VCFG = 0V, Open VCFG = VCC FSE TUE tADC Full-Scale Error Total Unadjusted Error Conversion Time All 13 Channels Once ΔVSENSE, VEEIN, VEEOUT Other 7 Channels Delays tD tPLH(GATE) tPHL(GATE) tPHL(UVL) tCB tACL Turn-On Delay Input High (ON) to Gates High Delay Input High (BD_SEL#), Input Low (ON) to Gates Low Propagation Delay Supply Low to Gates Low Delay Circuit Breaker Filter Delay Time Active Current Limit Delay ΔV12VSENSE = 300mV, C12VGATE = 10nF ΔV5VSENSE = 150mV, C5VGATE = 10nF ΔV3VSENSE = 150mV, C3VGATE = 10nF ΔVVEESENSE = 300mV, CVEEGATE = 10nF CGATE = 1pF 12VOUT, 5VOUT, 3VOUT, VPCI_RST# = 2V VEEOUT, VPCI_RST# = 2V SS Open CGATE = 1pF 12VIN, 5VIN, 3VIN, CGATE = 1pF VEEIN, CVEEGATE = 1pF 60 100 15 0.3 2.1 3.3 16 3.5 5.5 22 0.9 0.85 0.7 2 12 9 10.2 20 15 17 60 400 0.12 10 140 10 1.3 600 600 600 150 30 1 4.9 7.7 28 2.3 2.1 1.8 5 28 21 23.8 200 ms μs μs μs μs μs μs μs μs μs μs μs μs ns kHz μs ns ns ns ● ● ● ● ● ● ● ● ● ● ● ● ● tPHL(PGI) tPHL(RST) tP(RST) fSCL(MAX) tBUF(MIN) tSU, STA(MIN) tHD, STA(MIN) tSU, STO(MIN) PGI Low to Gates Low Output Low to LOCAL_PCI_RST# Low PCI_RST# to LOCAL_PCI_RST# Delay Maximum SCL Clock Frequency Min. Bus Free Time Between Stop/Start Minimum Repeated Start Set-Up Time Min. Hold Time After (Repeated) Start Minimum Stop Condition Set-Up Time I2C Interface Timing (Note 7) Operates with fSCL ≤ fSCL(MAX) 4245fa 5 LTC4245 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V12VIN = 12V, V5VIN = 5V, V3VIN = 3.3V, VVEEIN = –12V, unless otherwise noted. SYMBOL tSU, DAT(MIN) tHD, DATI(MIN) tHD, DATO(MIN) tSP(MAX) CX tof PARAMETER Minimum Data Set-Up Time Input Minimum Data Hold Time Input Minimum Data Hold Time Output Maximum Suppressed Spike Pulse Width SCL, SDA Input Capacitance Data Output Fall Time (Note 9) 20 + 0.1Cb 300 50 CONDITIONS MIN TYP 0 –100 500 110 5 MAX 100 0 900 250 10 250 UNITS ns ns ns ns pF ns ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: The 5VGATE and 3VGATE pins should not be driven beyond the lower of 12VIN + 0.3V and 14V. Note 4: An internal clamp limits the GATE pins to a minimum of 5V above VOUT (VEEIN for VEEGATE). Driving this pin to voltages beyond the clamp may damage the device. Note 5: The device pulls up the VEEOUT pin to 0.6V when pin is in open state. Note 6: UHF package specification limits are identical to G package limits and guaranteed by design and by correlation to wafer test measurements. Note 7: Guaranteed by design and not subject to test. Note 8: Integral Nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size and the single shot measurement. Typical specifications are measured from 1/4, 1/2, 3/4 areas of the quantization band. Note 9: Cb = total capacitance of one bus line in pF. TI I G DIAGRA SDA SCL tHD, STA tof START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION 4245 TDO1 6 W tSU, DAT tHD, DATO, tHD, DATI tSU, STA tSP tHD, STA tSP tBUF tSU, STO 4245fa UW LTC4245 TYPICAL PERFOR A CE CHARACTERISTICS ADC INL vs Code (GPIO1 Pin) 0.5 0.5 0.25 ADC DNL (LSB) ADC INL (LSB) 0.25 ADC FULL-SCALE ERROR (LSB) 0 –0.25 –0.5 0 64 128 CODE 12V and –12V Circuit Breaker Trip Voltage vs Temperature 50.25 CIRCUIT BREAKER TRIP VOLTAGE (mV) CIRCUIT BREAKER TRIP VOLTAGE (mV) 25.50 CIRCUIT BREAKER FILTER DELAY (µs) 50.00 –12V 49.75 49.50 12V 49.25 –50 –25 0 25 50 TEMPERATURE (°C) Active Current Limit Delay vs Sense Voltage 100 CGATE = 10nF ACTIVE CURRENT LIMIT DELAY (µs) FOLDBACK CURRENT LIMIT (mV) 60 FOLDBACK CURRENT LIMIT (mV) 10 –12V 5V 3.3V 12V 1 0.1 0 300 100 200 SENSE VOLTAGE (mV) 400 4245 G07 UW 192 75 ADC DNL vs Code (GPIO1 Pin) 1 ADC Full-Scale Error vs Temperature (GPIO1 Pin) 0.5 0 0 –0.25 –0.5 256 4245 G01 –0.5 0 64 128 CODE 192 256 4245 G02 –1 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4245 G03 5V and 3.3V Circuit Breaker Trip Voltage vs Temperature 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 Circuit Breaker Filter Delay vs Temperature 25.25 3.3V 25.00 5V 24.75 100 4245 G04 24.50 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4245 G05 18.0 –50 –25 0 50 25 TEMPERATURE (°C) 75 100 4245 G06 12V and –12V Foldback Current Limit vs Output Voltage 30 5V and 3.3V Foldback Current Limit vs Output Voltage 3.3V 50 40 30 –12V 20 10 0 12V 25 20 15 10 5 0 0 1 2 3 4 5VOUT/3VOUT VOLTAGE (V) 5 4245 G09 5V CFG = H 5V CFG = L 0 10 4 6 8 2 12VOUT/–VEEOUT VOLTAGE (V) 12 4245 G08 4245fa 7 LTC4245 TYPICAL PERFOR A CE CHARACTERISTICS INTVCC Voltage vs Load Current 6 5 GATE PULL-UP CURRENT (µA) INTVCC VOLTAGE (V) 4 3 2 1 0 0 5 10 LOAD CURRENT (mA) 15 4245 G10 4245 G12 4245 G13 GATE DRIVE (∆VGATE) (V) CAUTION: DRAWING CURRENT FROM INTVCC INCREASES POWER DISSIPATION AND TJ. LIMIT DC LOAD CURRENT TO 3mA Gate Drive vs IGATE 7 GATE FAST PULL-DOWN CURRENT (mA) 6 GATE DRIVE (∆VGATE) (V) 5 4 3 2 1 0 0 12VGATE 5VGATE 3VGATE VEEGATE –4 –8 –12 –16 –20 4245 G14 300 250 200 150 100 50 0 –50 –25 50 25 TEMPERATURE (°C) 0 75 100 4245 G15 5VGATE 12VGATE PRECHARGE VOLTAGE (V) IGATE (µA) PRECHARGE Voltage vs Load Current 1.01 OUTPUT DISCHARGE RESISTANCE (Ω) 2500 PRECHARGE VOLTAGE (V) 1.005 1 VOL (mV) 0.995 0.99 0 –10 –20 –30 –40 –50 LOAD CURRENT (mA) –60 –70 8 UW 4245 G17 Gate Pull-Up Current vs Temperature –21 –20.5 VEEGATE –20.0 5VGATE –19.5 12VGATE –19.0 3VGATE –18.5 –18.0 –50 6.40 6.35 Gate Drive vs Temperature VEEGATE 6.30 6.25 3VGATE 6.20 12VGATE 6.15 6.10 –50 5VGATE –25 0 25 50 TEMPERATURE (°C) 75 100 –25 0 25 50 TEMPERATURE (°C) 75 100 Gate Fast Pull-Down Current vs Temperature 400 350 3VGATE 1.013 PRECHARGE Voltage vs Temperature PRECHARGE OPEN 1.012 1.011 1.010 VEEGATE 1.009 1.008 – 50 – 25 0 25 50 TEMPERATURE (°C) 75 100 4245 G16 Output Discharge Resistance vs Temperature 400 350 2000 VEEOUT 300 250 200 150 VOL vs Current 1500 GPI0n, HEALTHY#, LOCAL_PCI_RST# 1000 12VOUT SDA, ALERT# 100 500 5VOUT 0 – 50 3VOUT – 25 0 25 50 TEMPERATURE (°C) 75 100 4245 G18 50 0 0 1 2 4 3 CURRENT (mA) 5 6 4245 G21 4245fa LTC4245 PI FU CTIO S 12VGATE: Gate Drive for 12V Supply External N-Channel MOSFET. An internal 20μA current source charges the gate of the external N-channel MOSFET. An internal clamp limits the gate voltage to 6.2V above 12VOUT. During turn-off a 1.3mA pull-down current discharges 12VGATE to ground. During short-circuit a 250mA pull-down current between 12VGATE and 12VOUT is activated. 12VIN: 12V Supply, Current Sense and ADC Input. The internal low voltage supply VCC is generated from 12VIN. An undervoltage lockout circuit, with 38mV hysteresis, prevents any external MOSFET from turning on when this pin is below 10.5V. 12VOUT: 12V Gate Drive Return; Foldback, ADC and Power Bad Input. Connect this pin to the source of the 12V supply external N-channel MOSFET switch for gate drive return. Power is considered bad if this pin drops below 11.1V. The comparator on this pin has a built-in hysteresis of 40mV. This pin is also an input to the ADC and the current limit foldback circuit. A 1000Ω active pull-down discharges 12VOUT to ground when the external MOSFET is turned off. 12VSENSE: 12V Supply Current Sense and ADC Input. Connect this pin to the output of the 12V current sense resistor. The current limit circuit controls the 12VGATE pin to limit the sense voltage between the 12VIN and 12VSENSE pins to 50mV or less during start-up and 150mV thereafter. During start-up a foldback feature reduces the current limit to 15mV as the 12VOUT pin approaches ground. A circuit breaker, enabled after start-up, trips when the sense voltage exceeds 50mV for 22μs. To disable current limit, connect this pin to 12VIN. 3VGATE: Gate Drive for 3.3V Supply External N-Channel MOSFET. An internal 20μA current source charges the gate of the external N-channel MOSFET. An internal clamp limits the gate voltage to 6.2V above 3VOUT. During turn-off a 1.3mA pull-down current discharges 3VGATE to ground. During short-circuit a 310mA pull-down current between 3VGATE and 3VOUT is activated. 3VIN: 3.3V Supply, Current Sense and ADC Input. The 1V precharge circuit draws its power and reference voltage from 3VIN. An undervoltage lockout circuit, with 10mV hysteresis, prevents any external MOSFET from turning on when this pin is below 2.8V. 3VOUT: 3.3V Gate Drive Return; Foldback, ADC and Power Bad Input. Connect this pin to the source of the 3.3V supply external N-channel MOSFET switch for gate drive return. Power is considered bad if this pin drops below 2.9V. The comparator on this pin has a built-in hysteresis of 11mV. This pin is also an input to the ADC and the current limit foldback circuit. A 190Ω active pull-down discharges 3VOUT to ground when the external MOSFET is turned off. 3VSENSE: 3.3V Supply Current Sense and ADC Input. Connect this pin to the output of the 3.3V current sense resistor. The current limit circuit controls the 3VGATE pin to limit the sense voltage between the 3VIN and 3VSENSE pins to 25mV or less during start-up and 75mV thereafter. During start-up a foldback feature reduces the current limit to 7.5mV as the 3VOUT pin approaches ground. A circuit breaker, enabled after start-up, trips when the sense voltage exceeds 25mV for 22μs. To disable current limit, connect this pin to 3VIN. 5VGATE: Gate Drive for 5V Supply External N-Channel MOSFET. An internal 20μA current source charges the gate of the external N-channel MOSFET. An internal clamp limits the gate voltage to 6.2V above 5VOUT. During turn-off a 1.3mA pull-down current discharges 5VGATE to ground. During short-circuit a 250mA pull-down current between 5VGATE and 5VOUT is activated. 5VIN: 5V Supply, Current Sense and ADC Input. An undervoltage lockout circuit, with 16mV or 10mV of hysteresis, prevents any external MOSFET from turning on when this pin is below 4.38V or 2.8V depending on the state of the CFG pin. U U U 4245fa 9 LTC4245 PI FU CTIO S 5VOUT: 5V Gate Drive Return; Foldback, ADC and Power Bad Input. Connect this pin to the source of the 5V supply external N-channel MOSFET switch for gate drive return. Power is considered bad if this pin drops below 4.63V or 2.9V depending on the CFG pin. The comparator on this pin has a built-in hysteresis of 17mV or 11mV. This pin is also an input to the ADC and the current limit foldback circuit. A 180Ω active pull-down discharges 5VOUT to ground when the external MOSFET is turned off. 5VSENSE: 5V Supply Current Sense and ADC Input. Connect this pin to the output of the 5V current sense resistor. The current limit circuit controls the 5VGATE pin to limit the sense voltage between the 5VIN and 5VSENSE pins to 25mV or less during start-up and 75mV thereafter. During start-up a foldback feature reduces the current limit to 7.5mV as the 5VOUT pin approaches ground. A circuit breaker, enabled after start-up, trips when the sense voltage exceeds 25mV for 22μs. To disable current limit, connect this pin to 5VIN. ADR0 to ADR3: Serial Bus Address Inputs. ADR0 and ADR1 are two-state inputs; ADR2 and ADR3 are threestate inputs. Tying these pins to ground, open or INTVCC configures one of 32 possible addresses. The addressing scheme is compatible with the CompactPCI geographic addressing for slot identification. See Table 5 in Applications Information. ALERT#: Fault Alert Output. Open-drain logic output that can be pulled to ground, when a fault occurs, to alert the host controller. A fault alert is enabled by the ALERT register. This device is compatible with SMBus alert protocol. See Applications Information. Tie to ground if unused. BD_SEL#: Board Present Input. Ground this pin to enable the N-channel MOSFETs to turn on. When this pin is high, the MOSFETs are off. An internal 10μA current source pulls up this pin to INTVCC. Transitions on this pin will be recorded in the FAULT2 register. A high-to-low transition activates the logic to read the state of the ON pin and clear faults. See Applications Information. CFG: Supply Configuration Three-State Input. When this pin is grounded, all four supply inputs must satisfy their undervoltage lockout levels to allow the external MOSFETs to turn on. Floating this pin disables VEE undervoltage lockout and power bad functions, allowing other supplies to turn-on even when –12V supply is absent. Tying this pin to INTVCC not only disables VEE, but also converts the 5VIN undervoltage, power bad and ADC levels to 3.3V levels. This allows using an extra 3.3V supply instead of a 5V supply as in a PCI Express application. EXPOSED PAD (Pin 39, UHF Package): Exposed Pad may be left open or connected to device ground. GND: Device Ground. GPIO1 to GPIO3 (GPIO2, GPIO3 on UHF package only): General Purpose Input/Output and ADC Input. Open-drain logic outputs and logic inputs. Any one of the three pins can be multiplexed to the GPIO channel of the internal ADC. GPIO1 has a state change fault associated with it. The GPIO register (Table 13) contains status and control bits for these pins. HEALTHY#: Board Power Status Output. This pin is pulled low by an open-drain output when all supply outputs are above their power bad thresholds and when all external N-channel MOSFETs are on. When any supply output falls below its power bad threshold voltage, this pin will go high after a 15μs deglitching time. INTVCC: Internal Low Voltage Supply Decoupling Output. Connect a 0.1μF capacitor from this pin to ground. When this pin falls below 3.8V, the internal registers are reset. LOCAL_PCI_RST#: Reset Output. This pin is pulled low by an open-drain output whenever HEALTHY# is high or when the PCI_RST# input is low. Tie to ground if unused. ON: On Control Input. A rising edge turns on the external N-channel MOSFETs and a falling edge turns them off. This pin is also used to configure the state of the FET On control bits (and hence the external FETs) in the ON register. For example, if the ON pin is tied high, then one or all (depending on the Sequence control bit) FET On control bits will go high 100ms after power-up. Likewise if the ON pin is tied low then the part will remain off after power-up until the FET On control bits are set high using the I2C bus. If the Sequence control bit is set, taking ON pin high turns on the supplies in a 12V, 5V, 3.3V, –12V sequence. A high-to-low transition on this pin will clear faults. 4245fa 10 U U U LTC4245 PI FU CTIO S PCI_RST#: Reset Input. Pulling this pin low causes LOCAL_PCI_RST# to pull low. When high, LOCAL_PCI_RST# is the logical inverse of HEALTHY#. Tie to INTVCC if unused. PGI: Power Good Input. Tie this pin to the ⎯R⎯E⎯S⎯E⎯T output of an external supply monitor or power good output of a DC/DC converter. When all supplies have been turned on, a timing cycle is started at the end of which the PGI pin is sampled. If it is low, all external MOSFETs are shut off. If the PGI Disable control bit C3 is not set, pulling this pin low for more than 20μs during normal operation will also shut off all MOSFETs. Tie to INTVCC if unused. PRECHARGE: Bus Precharge Output. This pin can source 70mA at 1V as soon as 3VIN is powered-up. Leave it open if unused. SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller. SDA: Serial Bus Data Input and Output. This is a high impedance input when address, command or data bits are shifted in. It is an open-drain output when sending data back to the master controller or acknowledging a write operation. An external pull-up resistor or current source is required. SS: Soft-Start Input. Connect a capacitor between this pin and ground to set the rate of increase of current limit during start-up for dI/dt limited inrush current. When an external MOSFET is turned on, a 20μA pull-up current charges the capacitor. The voltage ramp on the capacitor is converted into an internal current limit increasing linearly with time. Leave it open if dI/dt limited inrush is not required. TIMER: Timer Input. A capacitor between this pin and ground sets the duration of the start-up, PGI and auto-retry timing cycles to be 23.3ms/μF, 233ms/μF and 1.17s/μF respectively. A timing cycle consists of TIMER being charged to 2.56V with an internal pull-up current source and then being reset by a switch to ground. The timing cycle ends when TIMER falls below 0.23V. The start-up, PGI and auto-retry timing cycles use 100μA, 10μA and 2μA pull-up current sources respectively. VEEGATE: Gate Drive for –12V Supply External N-Channel MOSFET. An internal 20μA current source charges the gate of the external N-channel MOSFET. An internal clamp limits the gate voltage to 6.2V above VEEIN. During turn-off, a 3.5mA pull-down current discharges VEEGATE to VEEIN. During short-circuit a 65mA pull-down current between VEEGATE and VEEIN is activated. If a –12V supply is not available, connect VEEGATE to ground and use the CFG pin appropriately. VEEIN: –12V Supply, Current Sense and ADC Input. An undervoltage lockout circuit, with 38mV hysteresis, prevents any external MOSFET from turning on when this pin is above –10.5V. The VEEIN undervoltage lockout can be disabled by using the CFG pin. If a –12V supply is not available, connect VEEIN to ground and use the CFG pin appropriately. VEEOUT: –12V Supply Foldback, ADC and Power Bad Input. Connect this pin to the drain of the –12V supply external N-channel MOSFET switch. Power is considered bad if this pin rises above –11.1V. The comparator on this pin has a built-in hysteresis of 54mV. The VEEOUT power bad function can be disabled by using the CFG pin. This pin is also an input to the ADC and the current limit foldback circuit. A 1800Ω active pull-up discharges VEEOUT to ground when the external MOSFET is turned off. If a –12V supply is not available, connect VEEOUT to ground and use the CFG pin appropriately. VEESENSE: –12V Supply Current Sense and ADC Input. Connect this pin to the output of the –12V current sense resistor. The current limit circuit controls the VEEGATE pin to limit the sense voltage between the VEESENSE and VEEIN pins to 50mV or less during start-up and 150mV thereafter. During start-up a foldback feature lowers the current limit to 16mV as the VEEOUT pin approaches ground. A circuit breaker, enabled after start-up, trips when the sense voltage exceeds 50mV for 22μs. To disable current limit, connect this pin to VEEIN. If a –12V supply is not available, connect VEESENSE to ground and use the CFG pin appropriately. U U U 4245fa 11 LTC4245 BLOCK DIAGRA 12VOUT 12VIN INTVCC 5.5V GEN 25mV 5VIN 5VSENSE RAMP5 HI: 15mV LO: 0mV 12VIN SS RAMP12 HI: 30mV LO: 0mV SS D[6] ECB12 SS 20µA 5VGATE 5V ACL ON LOGIC ECB3 GATE DRIVER 5VOUT 4 RAMPXX 20µA 2µA M2 VCC R ISS D[5] VCC 10µA PGI BD_SEL# 1.235V ON 12VOUT A[6] 4 POWER BAD MONITOR 5VOUT 3VOUT VEEOUT FOLDBACK 4 RAMPXX CFG 12VIN 4 CPTL CPTH UVL MONITOR 5VIN 3VIN VEEIN TIMER CONTROL M3 VCC 3.8V SCL SDA IC ALERT# 2 + – + – 0.23V VCC ITMR 100µA, 10µA, 2µA 2.56V +– +– TIMER M1 RESET 8 A[3] 4 8 REGISTER ARRAY A TO U 8 ADC 4 1 OF 13 4 MUX VIN VIN-VSENSE VOUT GPIO1 GPIO2 –12V ECB TRIP TO LOGIC ADDRESS SELECT 1 OF 32 5 ECBEE 50mV GPIO3 RAMPEE –12V ACL ON, TO LOGIC HI: 0 TO 80mV LO: 150mV D[7] ACLEE G[1] G[4] M6 G[0] G[3] M5 B[3] ADR0 ADR1 ADR2 ADR3 + – RAMPEE HI: 30mV LO: 0mV SS GATE DRIVER VCC 20µA GND * UHF PACKAGE ONLY A[6], D[7], etc. REFER TO REGISTER BITS VEESENSE VEEIN VEEGATE 12 + – + – – + RAMP5 40mV – HI: 0 TO LO: 75mV 5V ECB TRIP ACL5 RESET 3.3V ECB TRIP 25mV 2.3R + – G[2] G[5] M7 VEEOUT EXPOSED PAD* + – 12V ACL ON 50mV RAMP12 HI: 0 TO 80mV LO: 150mV 12V ECB TRIP RAMP3 HI: 15mV LO: 0mV A[4] M4 + – + – + – ECB5 + – + – + – + – + – + – W 12VGATE 12VSENSE 12VIN 3VOUT 3VGATE 12VIN CHARGE PUMP GATE DRIVER GATE DRIVER 20µA 3.3V ACL ON D[4] ACL12 ACL3 RAMP3 HI: 0 TO 40mV LO: 75mV 3VSENSE 3VIN –+ + – + – + + – PRECHARGE SS HEALTHY# LOCAL_PCI_RST# PCI_RST# GPI01 GPI02* GPI03* + – + – 4245fa LTC4245 OPERATIO Start-Up The LTC4245 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane slot. When a supply turn-on command is received, current sources start pulling up the TIMER and SS pins. The 100μA ITMR current and the external TIMER capacitor determine the time a supply can be in current limit during start-up. The gate of a supply’s external N-channel MOSFET is servoed by an amplifer (ACLn) so that the current, as indicated by the sense resistor voltage drop, never exceeds an internal current limit. This current limit rises at a rate determined by ISS and the capacitor at the SS pin. A foldback circuit determines the maximum value of the current limit and reduces it to 30% of the maximum when a supply’s output is shorted to ground. When the TIMER pin crosses 2.56V it is reset to ground and the start-up timing cycle ends. If a supply is still in current limit all gates are turned off, an overcurrent fault is logged and the TIMER goes through a cool-down timing cycle using 2μA for ITMR. Otherwise, its circuit breaker (ECBn) is armed and the current limit is raised to 3 times the circuit breaker threshold. The SS pin is then reset by switch M2. Any combination of the four supplies can be turned on together or one after another. Whenever a supply is ramping up, its output voltage will affect, through the foldback circuit, where the internal current limit ramp stops. The default configuration turns on all supplies together. If sequence control bit C6 (Table 9) is set, the supplies turn on in a 12V, 5V, 3.3V, –12V sequence. With this bit set, the end of a supply ramp-up triggers the start of the next one in the sequence. The I2C interface allows independent on and off control for each supply through its On control bit. Turn-off is simultaneous under fault conditions and when using the ON or BD_SEL# pins. At the end of the last start-up timing cycle, HEALTHY# is pulled low by M3 if all supply outputs are above their power bad thresholds. LOCAL_PCI_RST# which was held low (M4), now follows PCI_RST#. The TIMER pin goes through a PGI timeout cycle using 10μA for ITMR. The PGI pin is sampled at the end of the cycle. If it is low, then all external MOSFETs are shut-off, a PGI fault is logged and TIMER goes through a cool-down cycle using 2μA U for ITMR. If PGI is high, the part enters the normal mode of operation. Normal Operation During normal operation, the gates of the MOSFETs are clamped about 6.2V above their sources. The 12V gate driver uses a charge pump, the 5V and 3.3V gate drive is derived from 12VIN and the –12V gate drive from INTVCC. Each supply is continuously monitored for undervoltage, overcurrent and power bad conditions. Overcurrent monitoring consists of an electronic circuit breaker comparator (ECBn) and an active current limit circuit (ACLn) set at 3x the ECB threshold. Undervoltage and overcurrent faults cause all MOSFETs to be shut off. A power bad condition causes HEALTHY# to go high impedance and LOCAL_PCI_RST# to pull low, without shutting off the MOSFETs. If the PGI pin is not disabled (register bit C3 not set), then PGI pin going low will also shut off all MOSFETs. ADC Included in the LTC4245 is an 8-bit A/D converter. The converter has a 13-input multiplexer to select between input, output and current sense voltage of each supply, and the GPIO channel. The ADC can either cycle through all channels or measure a channel on-demand. Serial Interface An I2C interface is provided to read from or write to the status, control and A/D registers. It allows the host to poll the device and determine if faults have occurred. If the ALERT# line is used as an interrupt, the host can respond to a fault in real time. The LTC4245 I2C interface slave address is decoded using the ADR0 to ADR3 pins. Configuration, GPIO and Precharge The three-state CFG pin can be used to disable the VEE undervoltage lockout, power bad and foldback functions. It can also convert the 5V undervoltage, power bad and ADC levels to 3.3V levels. The GPIO1 to GPIO3 pins can be used as general purpose inputs or outputs (M5 to M7). One of the pins can also be multiplexed to the GPIO channel of the ADC. A 1V reference voltage derived from 3VIN is provided at the PRECHARGE pin. This can be used to pre-charge I/O lines on the board so as not to corrupt the backplane bus. 4245fa 13 LTC4245 36 5VIN 10 BD_SEL# TIMER 1 HEALTHY# SS 12 SDA SCL CFG ALERT# R12 10k 29 ADR0 ADR1 ADR2 ADR3 PCI_RST# GND 22 R7 10Ω 21 20 19 3VIN 3VSENSE 3VGATE 3VOUT VEEIN 16 PGI LOCAL_PCI_RST# PRECHARGE 30 31 32 25 9 10nF C7 PER PIN C3 10nF Z3 R3 2.5mΩ Z4 R19 1.74Ω R11 1Ω R13 10k R14 10k R15 10k LTC4245G ON INTVCC 3 28 C1 0.1 µF 26 TO RESET OF SUPPLY MONITOR 24 23 R9 18Ω VEESENSE VEEGATE VEEOUT 15 17 18 3VOUT 11 13 14 CSS 220nF 4 C9 10nF CT 2.2 µF 2 GPIO1 ADC INPUT 27 R16 10k R17 1.2k 5VSENSE 5VGATE 5VOUT 12VIN 12VSENSE 12VGATE 12VOUT 35 R6 10Ω 34 33 5 6 7 8 LONG V(I/0) BD_SEL# HEALTHY# SDA APPLICATIO S I FOR ATIO SCL 3VIN GA[0] GA[1] GA[2] R24 10k GA[3] PCI_RST# GROUND C6 LONG 3.3V MEDIUM 3.3V Q3, Si7880DP R8 10Ω + 3.3V 7A CL (3VOUT) 2200 µF –12V 300mA –12V R20 10Ω R4 100mΩ • • • R21 10Ω Q4, Si4872 I/O PIN 1 • • • I/O PIN 128 Z1 , Z4: DIODES INC. SMAJ12A Z2 , Z3: DIODES INC. SMAJ5.0A I/O DATA LINE 128 RESET PCI BRIDGE CHIP BACKPLANE CONNECTOR (MALE) BOARD CONNECTOR (FEMALE) Figure 1. CompactPCI Application + I/O DATA LINE 1 R23 10k R22 10k CL(VEEOUT) 100 µF 4245 FO1 U ALERT# W U U 14 C2 10nF R10 1Ω R1 50mΩ Q1, IRF7413 12V + CL(12VOUT) 100 µF 12V 600mA R2, 3.5mΩ Q2, Si788ODP R18, 2.74Ω Z2 C4 10nF C5 PER PIN R5 10Ω Z1 CL(5VOUT) 2200 µF MEDIUM 5V C8 2.2nF + 5V 5A LONG 5V 4245fa LTC4245 APPLICATIO S I FOR ATIO The typical LTC4245 application is in a high availability system where boards using multiple supplies are hot plugged. The device enables the system to periodically monitor board power consumption and fault status over the I2C interface. Boards in CompactPCI and PCI Express systems typically utilize three to four supplies. Figure 1 shows the LTC4245 being used in a CompactPCI application. The following sections describe the turn on, turn off and fault response behavior of the LTC4245. The ADC and I2C interface are discussed next. External component selection is discussed in detail in the Design Example section. CPCI Connection Pin Sequence The staggered lengths of the CPCI male connector pins on the backplane ensures that all power supplies are physically connected to the LTC4245 before back-end power is allowed to ramp up (BD_SEL# asserted low). The long pins, which include 5V, 3.3V, V(I/O) and GND, mate first. The short BD_SEL# pin mates last. At least one long 3.3V power pin must be connected to the LTC4245 in order for the PRECHARGE pin voltage to be available before the CPCI bus pins mate. The following is a typical hot plug sequence. 1. ESD clips make contact. 2. Long power and ground pins make contact and Early Power is established. The 1V precharge voltage becomes valid at this stage. Power is also applied to the pull-up resistors connected to the HEALTHY# and BD_SEL# signals. LOCAL_PCI_RST# is held in reset. All power switches are held off at this stage of insertion. 3. Medium length pins make contact. The 12V and –12V connector pins make contact at this stage. The internal low voltage supply of the LTC4245 (INTVCC) powers up from the 12V supply. An internal 10μA pull-up from INTVCC to BD_SEL# turns on. Other connector pins that mate are HEALTHY#, PCI_RST# and the bus I/O pins (which are precharged to 1V). 4. Short pins make contact. If the BD_SEL# signal is grounded on the backplane, the plug-in board power-up cycle may begin immediately. If the ON pin U is tied high then turn-on is automatic, else the LTC4245 waits for a serial bus turn-on command. System backplanes that do not ground the BD_SEL# signal will instead have circuitry that detects when BD_SEL# makes contact with the plug-in board. The system logic can then control the power up process by pulling BD_SEL# low. The precharge potential may be optionally disconnected from the CPCI bus signals at this stage. Turn-On The back-end power planes are isolated from the input power planes by external N-channel pass transistors Q1 through Q4. Sense resistors R1 to R4 provide current fault detection. Resistors R5 to R8 prevent high frequency oscillations in MOSFETs Q1 to Q4 respectively. The following conditions must be satisfied for a duration of 100ms before the external switches can be turned on. 1. All input supplies and the internally generated supply, INTVCC, must exceed their undervoltage lockout thresholds. The VEE undervoltage lockout can be disabled by not tying the CFG pin low. 2. No undervoltage, overcurrent or PGI fault bits must be set unless the corresponding auto-retry is enabled. When 12VIN powers up for the first time, INTVCC rises above its undervoltage threshold which generates a 60μs to 120μs internal power-on-reset pulse. During reset, the fault registers are cleared and the control bits are initialized. If INTVCC is already up, then the I2C interface can be used to clear the fault bits or set the auto-retry bits. 3. The BD_SEL# pin must be pulled low. When these initial conditions are satisfied, the ON pin is checked. If it is high, the four FET On control bits (D0 to D3) are set either simultaneously (the default state) or in a 12V, 5V, 3.3V, –12V sequence (register bit C6 set). If ON is low, the external switches turn on when the ON pin is brought high or if a serial bus turn-on command is received. Figure 2 shows all supplies turning on after BD_SEL# goes low. 4245fa W U U 15 LTC4245 APPLICATIO S I FOR ATIO When a switch is to be turned on, an internal 100μA current source is connected to the TIMER pin and a 20μA current to SS pin. The gate of each ramping supply’s pass transistor is servoed by an internal amplifier, so the supply current never exceeds an internal current limit. This internal current limit starts off with a negative value, which makes the amplifier pull the gate low. The voltage ramp on the SS pin is converted to a current limit rising linearly with time. The amplifier releases the gate as the current limit crosses zero. An internal current source starts charging up the gate. When the gate voltage reaches the MOSFET threshold voltage, the switch begins to turn on. The amplifier once again starts modulating the gate pull-up current so that the sense resistor voltage drop follows the internally set current limit. The rate of rise of the inrush current is given by: dIINRUSH G dV = SS • SS dt RSENSE dt (1) dVSS ISS = dt CSS (2) GSS is the ratio of the change in current limit to the change in SS pin voltage. The rising current limit will stop at a level depending on the foldback circuit. The foldback circuit monitors the outputs of all supplies which are ramping. In the worst case, a supply output could be shorted to ground. In this case the foldback circuit reduces the current limit to 30% of the maximum as shown in the Typical Performance Curves. To set an inrush current lower than the foldback level, a series R-C network can be connected between the gate pin and ground (VEEOUT for –12V supply) (Figure 3). This allows charging the output load beyond the time dictated by the TIMER capacitor. When the rising internal current limit exceeds the dV/dt set inrush current, the current limit amplifier goes open loop. If any ramping supply’s amplifier is open loop the SS pin current drops to 2μA from 20μA, thus slowing the current limit rise. This would affect the other supplies ramp-up in case of simultaneous turn-on. A 100kΩ resistance ensures that the capacitor charge is decoupled during a fast gate turnoff. The capacitor value is determined by: IGATE(UP) CGATE = • CLOAD IINRUSH (3) 16 U Meanwhile the TIMER pin ramps up to 2.56V, when it is reset to ground. Current limit faults on the ramping supplies are ignored during this time period. The start-up timing cycle ends when the TIMER pin falls below 0.23V. The SS pin is reset, the circuit breaker for the supply is armed and its current limit raised to 3x the circuit breaker threshold. In a sequenced turn-on the part will start another TIMER and SS cycle to ramp up the next supply. If supplies are being turned on through the serial bus, it will wait for the next turn-on command. Once all supplies have been turned on and all their outputs are within tolerance, HEALTHY# will pull low and LOCAL_PCI_RST#, which was low, will now follow PCI_RST#. The TIMER pin is now pulled up by a 10μA current source while SS pin remains in reset. When TIMER reaches 2.56V, it is reset to ground. As it crosses 0.23V the PGI pin is sampled. If it is low then all switches are turned off. BD_SEL# 5V/DIV TIMER 2.5V/DIV SS 2.5V/DIV 12VOUT, 5VOUT 3VOUT, VEEOUT, 10V/DIV HEALTHY# 5V/DIV LOCAL_PCI_RST# 5V/DIV TIME 50ms/DIV 4245 F02 W U U Figure 2. Normal Turn-On Waveform Q2, Si7880DP R6 10Ω R26 100k CGATE(5V) 34 5VGATE LTC4245G* VEEGATE 17 R27 100k CGATE(VEE) R8 10Ω VEEOUT 18 *ADDITIONAL DETAILS OMITTED FOR CLARITY Q4, Si4872 4245 F03 Figure 3. CGATE for dV/dt Limited Inrush Current 4245fa LTC4245 APPLICATIO S I FOR ATIO BD_SEL# 5V/DIV 12VOUT, 5VOUT 3VOUT, VEEOUT, 10V/DIV HEALTHY# 5V/DIV LOCAL_PCI_RST# 5V/DIV TIME 100ms/DIV 4245 F04 Figure 4. Normal Turn-Off Waveform Turn-Off The switches can be turned off by a variety of conditions. 1. ON pin going low or BD_SEL# going high turns off all switches. 2. Individual switches can be turned off by resetting the particular FET On control bit (D0 to D3) through the serial bus. 3. A variety of fault conditions will turn off all switches together. These include supply undervoltage, overcurrent circuit breaker and PGI faults. 4. Writing a logic one into the undervoltage, overcurrent or PGI fault bits will turn off all switches, if the corresponding autoretry is not enabled. Normally the 12V, 5V and 3.3V switches are turned off with a 1.3mA current pulling down the gate to ground. VEEGATE is pulled through a resistive switch to VEEIN. All supply outputs are also discharged to ground through internal switches. When any MOSFET is shut off, the HEALTHY# signal pulls high and LOCAL_PCI_RST# will be asserted low. Figure 4 shows all supplies being turned off by BD_SEL# going high. ON Register and Sequencing The LTC4245 features an ON register (Table 10) consisting of four On control bits (D0 to D3) and four On status bits (D4 to D7). D0 to D3 provide independent on/off control for each supply through the I2C bus. Bits D4 to D7 report U the on status of each supply. Even though a supply may be commanded to turn-on by setting its On control bit, it may remain off (On status bit low) because the conditions to turn on, as listed in the Turn-On section, may not be present. The sequence control bit, C6, determines whether the four supply MOSFETs turn-on together or in a fixed sequence. The default state is no sequencing. In this case taking the ON pin high sets all the four On control bits. If the start-up conditions are satisfied, all switches will turn on under the control of a single TIMER and SS cycle. Due to different input voltage offsets in the current limit amplifier of each supply, the gate turn-on of all MOSFETs will not occur at the same moment but will happen in random order depending on amplifier offset and soft-start ramp rate. The gate turn-ons will be truly simultaneous only if SS pin is left open. If bit C6 is set, then the ON pin going high sets only the 12V On control bit, D0. The 12V back-end supply ramps up. The end of the TIMER and SS cycle sets the 5V On control bit, D1, starting the ramp of the 5V supply output. The end of the 5V timing cycle sets bit D2 and the end of the 3.3V ramp sets bit D3. In this way, the four On control BD_SEL# 5V/DIV TIMER 2.5V/DIV SS 2.5V/DIV 12VOUT, 5VOUT 3VOUT, VEEOUT, 10V/DIV HEALTHY# 5V/DIV LOCAL_PCI_RST# 5V/DIV TIME 50ms/DIV 4245 F05 W U U Figure 5. Sequential Turn-On Waveform bits get set one after another, leading to a 12V, 5V, 3.3V, –12V start-up sequence. Figure 5 illustrates this. If C6 is set and any of the start-up conditions goes bad, all switches turn-off, and all On control bits except D0 are reset. This ensures that the part goes through a sequenced turn-on during auto-retry. D1 to D3 are also reset when BD_SEL# goes low with C6 set. 4245fa 17 LTC4245 APPLICATIO S I FOR ATIO When the sequence bit C6 is set, setting the On control bit of a supply, through the I2C interface, starts the supply turn-on sequence from that supply onwards. For example, setting bit D1 will turn-on 5V, 3.3V, –12V supplies, in that order. A logic one can then be written to bit D0 to ramp the 12V supply. At the end of this ramp-up, bit D1 is set. But since 5V is already powered-up, the sequence stops there. The I2C interface provides the most flexibility in turning supplies on and off. With bit C6 cleared, any supply or supplies can be turned on by setting their On control bits. The On control bits cannot be set when any supply is ramping (therefore using TIMER and SS pins). The SS busy bit, A1, indicates this blanking period. The On control bits can be reset though, even when a supply is ramping. Two or more On control bits may be set at the same time to ramp multiple supplies in the same timing cycle. When all supplies are turned on the LTC4245 goes through the PGI timing cycle. Supply Voltage Configuration The CFG pin enables the LTC4245 to be used in non-CPCI applications. It is a three-state input pin. In a CPCI application with all four supplies, the CFG pin is tied to ground. Floating the CFG pin disables the VEE undervoltage lockout (UVLO), start-up foldback and power bad functions. It also makes the ±12V turn-ons coincident by using the 12V FET On control bit, D0, to control the –12V supply MOSFET. This allows the three positive supplies to power-up and HEALTHY# to assert, even when a negative supply is either unavailable or does not meet the required thresholds. If unused the VEEIN, VEESENSE, VEEGATE and VEEOUT pins should be tied to ground. Since the circuit breaker and active current limit circuits are not disabled, a lower negative supply could be hot plugged. It would turn on whenever the 12V supply turns on. Care should be taken that the supply does not collapse under overcurrent conditions. At low supplies, the ECB and ACL circuits stop functioning. With the UVLO already disabled, the LTC4245 may not detect a fault condition on the VEE supply. Large currents, limited only by MOSFET and sense resistances, could flow, potentially damaging the board traces and connector pins. 18 U If the CFG pin is tied high, the 5V supply thresholds change to 3.3V levels, while keeping the floating state functionality. The 5V supply UVLO, power bad thresholds and foldback profile become similar to those of the 3.3V supply. The 5VIN and 5VOUT inputs to the ADC use the same LSB and full-scale as the 3VIN and 3VOUT pins. This allows the use of an extra 3.3V supply instead of a 5V supply as in a PCI Express application. Overcurrent Fault The LTC4245 has different current limiting behavior during start-up, when supply ramps up under TIMER and SS control, and normal operation. As such it can generate an overcurrent fault during both phases of operation. Both set the faulting supply’s overcurrent fault bit (bits E4 to E7) and shut off all external FETs. During start-up when both TIMER and SS are ramping, the current limit is a function of SS pin voltage and the ramping supplies’ output voltages. A supply could power up entirely in current limit depending on the bypass capacitor at the outputs of the ramping supplies. The TIMER pin sets the time duration for current limit during start-up. This time involves the TIMER charging up to 2.56V with a 100μA current source and then resetting to 0.23V with a switch. At the end of the timing cycle if the supply is still in current limit, i.e., the gate of it’s external MOSFET is still being actively controlled, an overcurrent fault is declared for that supply and all MOSFETs are shut off (Figure 6). Therefore the maximum time a supply can stay in current limit at start-up is given by: t START = CT • K TMCAP = CT • 23.3 ⎣ms / µF ⎦ ⎡ ⎤ (4) ON 5V/DIV TIMER 2.5V/DIV SS 2.5V/DIV 3VGATE 2.5V/DIV 3.3V SUPPLY CURRENT 2.5A/DIV 12VOUT, 5VOUT 3VOUT, VEEOUT, 10V/DIV HEALTHY# 5V/DIV TIME 10ms/DIV 4245 F06 W U U Figure 6. Start-Up Into a Short on 3.3V Output 4245fa LTC4245 APPLICATIO S I FOR ATIO After the switches are turned off, the TIMER pin begins charging up with a 2μA pull-up current. When it reaches 2.56V it is reset to ground with a switch. During this cooldown cycle, the overcurrent fault bit cannot be reset. After this cycle, the switches will be allowed to turn on again if the overcurrent fault bit is cleared. However, if the overcurrent autoretry bit, C1, has been set then the switches turn on again automatically after the 100ms turn-on delay (without resetting the overcurrent fault). After start-up, a supply has dual-level glitch-tolerant protection against overcurrent faults. The sense resistor voltage drop is monitored by an electronic circuit breaker (ECB) and an active current limit (ACL). In the event that a supply’s current exceeds the ECB threshold, an internal timer is started. If the supply is still overcurrent after 22μs, the ECB trips and all supplies are turned off (Figure 7). An analog current limit loop prevents the supply current from exceeding 3x the ECB threshold in the event of a short circuit (Figure 8). The 22μs filter delay and the higher ACL threshold prevents unnecessary resets of the board due to minor current surges. The LTC4245 will stay in the latched off state unless bit C1 is set, in which case the switches turn on after a 100ms delay. Note that foldback is not active after start-up. Undervoltage Fault An undervoltage fault occurs when any of the input supplies falls below its undervoltage threshold for more than 3.5μs (5.5μs for VEEIN). This turns off all switches immediately and sets the undervoltage present bit A0 and the corresponding undervoltage fault bit (bits E0 to E3). 5V SUPPLY CURRENT 5A/DIV 5VGATE 2V/DIV 12VGATE 5V/DIV 5VOUT 2V/DIV 12VOUT 5V/DIV TIME 10µs/DIV 4245 F07 Figure 7. Overcurrent Fault on 5V Output U If the supply subsequently rises above the threshold for 100ms, the switches will turn on again unless the undervoltage auto-retry has been disabled by clearing bit C0. When power is first applied to the device, if any supply is below its threshold after INTVCC crosses its undervoltage lockout threshold, an undervoltage fault will be logged in the FAULT1 register. PGI Fault The PGI pin can be used to shut off the board’s input supplies in case downstream supplies fail to enter regulation in time. It can be tied to the reset output of a monitor IC or the powergood pin of a DC/DC converter. After all supply outputs have been powered up, a timing cycle is started with a 10μA current pulling up the TIMER pin. When TIMER reaches 2.56V it is reset to ground by a switch. As TIMER falls below 0.23V, the PGI pin is sampled. If it is low, the PGI fault bit F4 is set and all external FETs are shut off. A cool-down timing cycle is started using a 2μA pull-up current on TIMER pin. Bit F4 cannot be reset during this time. After this cycle, the switches will be allowed to turn on again if the PGI fault bit is cleared. However, if the PGI autoretry bit, C4, has been set then the switches turn on again automatically after the 100ms turn-on delay. By default, the PGI pin is ignored during normal operation. It can be enabled by clearing PGI disable bit C3. Now, if PGI pin goes low for more than 20μs, all FETs will be shut off. If bit C4 is set, the switches will turn on after the 100ms turn-on delay. 12V SUPPLY CURRENT 2A/DIV TIME 5µs/DIV 4245 F08 W U U Figure 8. Short-Circuit Fault on 12V Output 4245fa 19 LTC4245 APPLICATIO S I FOR ATIO Power Bad Fault A power bad condition exists when any supply output drops below its power bad threshold for more than 15μs (17μs for VEEOUT). This sets bit A2 in the STATUS register. The HEALTHY# output goes high impedance, and LOCAL_PCI_RST# pin is pulled low. If the gate of the supply’s MOSFET is enhanced, a power bad fault is logged in bits F0 to F3 of the FAULT2 register. A circuit will prevent power bad fault bits being set if the external MOSFET gate-to-source voltage is low, eliminating false power bad faults during power-up or power-down. If the supply output subsequently rises back above the threshold, bit A2 will be cleared, HEALTHY# will pull low and LOCAL_PCI_RST# will follow PCI_RST#. BD_SEL# Change of State Whenever the BD_SEL# pin toggles, bit F6 is set to indicate a change of state. When the BD_SEL# pin goes high, indicating board removal, all switches turn off immediately. Bit A6 reports the current state of this pin. If the BD_SEL# pin is pulled low, indicating a board insertion, all fault bits except F6 will be cleared. If the sequence bit C6 is set, then On control bits D1 to D3 are also cleared. If the BD_SEL# pin remains low for 100ms the state of the ON pin will be captured in either D0 to D3 or only D0, depending on sequence bit C6. This turns on the switches if ON pin is tied high. There is an internal 10μA pull-up current source on the BD_SEL# pin from INTVCC. If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4245 and the switches reside on a backplane or midplane (as in a PCI Express application) and the load resides on a plug-in card, the BD_SEL# pin can be used to detect when the plug-in card is removed (see Figure 9). Once the plug-in card is reinserted the two fault registers are cleared (except for F6). After 100ms the state of ON pin is latched into bits D0 to D3. At this point the system will start up again. If a connection sense on the plug-in card is driving the BD_SEL# pin, the insertion or removal of the card may cause the pin voltage to bounce. This will result in clearing the fault register when the card is removed. The pin 20 U can be debounced using a filter capacitor, CBD_SEL# , on the BD_SEL# pin as shown in Figure 9. The filter time is given by: tFILTER = CBD _ SEL # • 123 [ms / µF ] FET Short Fault A FET short fault will be reported if the data converter measures a supply’s current sense voltage greater than 7 LSB while the supply’s pass transistor is turned off. This condition sets the FET short present bit, A5, and the FET short fault bit F5. Reading the On status bits (D4 to D7) and the ADC current sense voltage data registers (J, M, P, S) can help debug which supply’s MOSFET might be potentially shorted. A false FET short fault might be reported if an input supply power-up is delayed by more than 500ms after INTVCC is up. Fault Alerts When any of the bits in fault registers E and F are set, an optional bus alert can be generated by setting the appropriate bit in the ALERT register B. This allows only selected faults to generate alerts. At power-up the default state is not to alert on faults. If an alert is enabled, the corresponding fault will cause the ALERT# pin to pull low. See the Alert Response Protocol section for more information. (5) LTC4245G* 10µA BD_SEL# 10 CBD_SEL# W U U + – GND 9 1.235V CONNECTOR MOTHERBOARD *ADDITIONAL DETAILS OMITTED FOR CLARITY PLUG-IN CARD 4245 F09 Figure 9. Plug-In Card Insertion/Removal 4245fa LTC4245 APPLICATIO S I FOR ATIO Resetting Faults The two fault registers E and F can be reset in any of the following ways: 1. Writing zeros to the registers using the I2C bus. 2. Taking the ON pin high to low resets both registers. 3. INTVCC falling below its undervoltage lockout threshold. 4. Bringing BD_SEL# from high to low clears all fault bits except bit F6. Bit F6, which indicates a BD_SEL# change of state, will be set. Note that faults that are still present cannot be cleared. Overcurrent and PGI faults are continuously set during their cool-down timing cycles and hence cannot be reset for that duration. The fault registers will not be cleared when auto-retrying. When autoretry is disabled the existence of an undervoltage (E0 to E3), overcurrent (E4 to E7) or PGI (F4) fault keeps the switches off. As soon as the fault is cleared, the switches will turn on. BACKPLANE CONNECTOR 5V LONG 5V BD_SEL# C4 Z2 10nF PER PIN GROUND R24 51k 5% C10 100Ω Q5 0.1µF MMBT3906 OE R20 10Ω 5% R21 10Ω 5% CARD CONNECTOR C5 10nF PER PIN 5VIN R18 2.74Ω R17 1.2k 5% 36 5V IN LTC4245G* 10 BD_SEL# GND 9 R9 18Ω 5% I/O PIN 1 ••• I/O PIN 128 Z2: SMAJ5.0A *ADDITIONAL DETAILS OMITTED FOR CLARITY DATA BUS Figure 10. Precharge Bus Switch Application Circuit for 3.3V and Universal Hot Swap Boards U Precharge The PRECHARGE pin provides a 1V voltage (using a divided down 3VIN as the reference) that is used to bias the CPCI bus connector pins during board insertion and extraction. The pin can source 70mA without losing regulation. An external 18Ω resistor from this pin to ground provides the current sink capability. At least one long 3.3V connector pin must be connected to 3VIN to provide early power to the precharge circuit. Resistors are used to connect the 1V bias voltage to the CPCI bus signals. For 5V signaling this resistance must be greater than 10kΩ - 5% (Figure 1). For 3.3V signaling if the leakage current on the I/O line is greater than 2µA, the precharge resistors need to be disconnected during normal operation. Figure 10 shows a circuit that uses a bus switch to accomplish this. The connection is made when the voltage on the BD_SEL# pin is pulled up to 5V, which occurs just after the long pins have made contact. The resistors are disconnected when the short BD_SEL# connector pin makes contact and the BD_SEL# voltage drops below 4.4V thus causing ⎯O⎯E to be pulled high by PRECHARGE 23 R25 75k 5% IN VDD BUS SWITCH OUT OUT R22 R23 10k 10k 5% 5% ••• ••• UP TO 128 I/O LINES I/O PCI BRIDGE CHIP 4245 F10 W U U I/O 4245fa 21 LTC4245 APPLICATIO S I FOR ATIO Q5. The CPCI specification assumes that there is a diode to 3.3V on the circuit that is driving the BD_SEL# pin. If the BD_SEL# pin is being driven high, the actual voltage on the pin will fall to approximately 3.9V from 5V. This is still above the threshold of the LTC4245 BD_SEL# pin, but low enough for Q5 to pull ⎯O⎯E high. Since the bus switch is powered off an early power plane, a 100Ω resistor should be placed in series with its VDD . When the plug-in card is removed from the backplane, the BD_SEL# connection is broken first, and the BD_SEL# voltage pulls up to 5V. This causes Q5 to turn off, which re-enables the bus switch, and the precharge resistors are again connected to the PRECHARGE pin for the remainder of the extraction process. Data Converter The LTC4245 incorporates an 8-bit data converter that continuously converts thirteen different channels. Twelve of these channels are used for each supply’s input, current sense and output voltages. One of the three GPIO pins can be multiplexed to the thirteenth channel using bits G6 and G7. The results from each conversion are stored in registers I through U and are updated once every 665ms. Since the ADC is powered off INTVCC, which is derived from 12VIN, it is not possible to convert 12VIN below about 8V as the ADC and serial bus are held in reset. The ADC can also measure a particular channel on-demand. First the ADC needs to be taken out of it’s free-running mode by setting control bit C7. The ADC enters a quiescent state, which is indicated by the ADC busy bit, A7, going to logic zero. Writing the address of a channel to ADCADR register triggers the start of one conversion of that channel’s voltage. Bit A7 goes high to indicate ADC activity. It goes low again after the ADC finishes the conversion and writes the result to the channel’s data register. The same or different address can be written again to start a new conversion. The quiescent state of the ADC can also be used to read and write from the ADC data registers for software testing purposes. Resetting bit C7 allows the ADC to again start cycling through the thirteen channels starting with the first one. 22 U Digital Interface The LTC4245 communicates with a bus master using a 2-wire interface compatible with the I2C bus and the SMBus, an I2C extension for low power devices. The LTC4245 is a read-write slave device and supports SMBus Read Byte, Write Byte, Read Word and Write Word commands. The second word in a Read Word command will be identical to the first word. The second word in a Write Word command is ignored. The data formats for these commands are shown in Figures 12 to 15. START and STOP Conditions When the bus is idle, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. I2C Device Addressing Thirty-two distinct bus addresses are configurable using the two-state ADR0, ADR1 pins and the three-state ADR2, ADR3 pins. Table 5 shows the correspondence between pin states and addresses. Note that address bits B7 and B6 are internally configured to (01)b. The first 16 addresses are compatible with the geographic addressing scheme used in CompactPCI to encode physical slot addresses. In addition, the LTC4245 will respond to two special addresses. Address (0010 111)b is a mass write address used to write to all LTC4245, regardless of their individual address settings. The mass write can be masked by setting register bit C5 to zero. Address (0001 100)b is the SMBus Alert Response Address. If the LTC4245 is pulling low on the ALERT# pin, it will acknowledge this address using the SMBus Alert Response Protocol. Acknowledge The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the 4245fa W U U LTC4245 APPLICATIO S I FOR ATIO SDA a6 - a0 SCL S 1-7 8 9 START CONDITION ADDRESS R/W ACK Figure 11. Data Transfer over I2C or SMBus S ADDRESS 0 1 a4:a0 W 0 A 0 COMMAND xxx b4:b0 A 0 DATA b7:b0 A 0 P FROM MASTER TO SLAVE FROM SLAVE TO MASTER Figure 12. LTC4245 Serial Bus SDA Write Byte Protocol S ADDRESS 0 1 a4:a0 W 0 A 0 COMMAND xxx b4:b0 A 0 DATA b7:b0 A 0 DATA xxxxxxxx A 0 4245 F13 Figure 13. LTC4245 Serial Bus SDA Write Word Protocol S ADDRESS 0 1 a4:a0 W 0 A 0 COMMAND xxx b4:b0 A 0 S ADDRESS 0 1 a4:a0 R 1 A 0 DATA b7:b0 A 1 4245 F14 Figure 14. LTC4245 Serial Bus SDA Read Byte Protocol S ADDRESS 0 1 a4:a0 W 0 A 0 COMMAND xxx b4:b0 A 0 S ADDRESS 0 1 a4:a0 R 1 A 0 DATA b7:b0 A 0 DATA b7:b0 A 1 P Figure 15. LTC4245 Serial Bus SDA Read Word Protocol ALERT RESPONSE ADDRESS 0001100 DEVICE ADDRESS 01 a4:a0 0 S Figure 16. LTC4245 Serial Bus SDA Alert Response Protocol U b7 - b0 b7 - b0 1-7 8 9 1-7 8 9 P DATA ACK DATA ACK STOP CONDITION 4245 F11 W U U A : ACKNOWLEDGE (LOW) A : NOT ACKNOWLEDGE (HIGH) R : READ BIT (HIGH) W : WRITE BIT (LOW) S : START CONDITION P : STOP CONDITION 4245 F12 P P R 1 A 0 A 1 P 4245 F16 4245fa 23 LTC4245 APPLICATIO S I FOR ATIO SDA line during the acknowledge clock pulse. When the slave is the receiver, it must pull down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA HIGH, then the master can abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master must pull down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received, the master will leave the SDA line HIGH (not acknowledge) and issue a STOP condition to terminate the transmission. Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/⎯W bit set to zero. The addressed LTC4245 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4245 acknowledges this and then latches the lower five bits of the command byte into its internal Register Address Pointer. The master then delivers the data byte and the LTC4245 acknowledges once more and latches the data into its internal register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte will be acknowledged by the LTC4245 but ignored. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address and the R/⎯W bit set to zero. The addressed LTC4245 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to read. The LTC4245 acknowledges this and then latches the lower five bits of the command byte into its internal Register Address Pointer. The master then sends a repeated START condition followed by the same seven bit address with the R/⎯W bit now set to one. The LTC4245 acknowledges and sends the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command, the LTC4245 will repeat the requested register as the second data byte. 24 U Note that the Register Address Pointer is not cleared at the end of the transaction. Thus the Receive Byte protocol can be used to repeatedly read a specific register. Alert Response Protocol The LTC4245 implements the SMBus Alert Response Protocol as shown in Figure 16. If enabled to do so through the ALERT register B, the LTC4245 will respond to faults by pulling the ALERT# pin low. Multiple LTC4245s can share a common ALERT# line and the protocol allows a master to determine which LTC4245s are pulling the line low. The master begins by sending a START bit followed by the special Alert Response Address (0001 100)b with the R/⎯W bit set to one. Any LTC4245 that is pulling its ALERT# pin low will acknowledge and begin sending back its individual slave address. An arbitration scheme ensures that the LTC4245 with the lowest address will have priority; all others will abort their response. The successful responder will then release its ALERT# pin while any others will continue to hold their ALERT# pins low. Polling may also be used to search for any LTC4245 that have detected faults. Any LTC4245 pulling its ALERT# pin low will have bit B3 in the ALERT register set. Writing a zero to this bit will release the ALERT# pin. The ALERT# signal will not be pulled low again until the FAULT1 or FAULT2 register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated fault register bit has been cleared. Also, a fault on one supply will not generate an alert if a fault bit of the same kind (undervoltage, overcurrent, power bad) is set for any other supply. General Purpose Input/Outputs (GPIOs) The G36 package of the LTC4245 has one GPIO (GPIO1) pin while the UHF package has three (GPIO1 to GPIO3). Bits G0 to G2 in the GPIO register (Table 13) indicate whether a pin is above or below the 1V threshold voltage. Bits G3 to G5 control whether the open-drain output on a GPIO pin pulls low or is high impedance. This can be used to drive external pull-up resistors or LEDs. Register bits G6 and G7 control which one of the three pins is multiplexed to the GPIO channel of the ADC. Whenever the GPIO1 pin 4245fa W U U LTC4245 APPLICATIO S I FOR ATIO toggles, bit F7 is set to indicate a change of state. If the GPIO1 alert bit B7 is enabled, this feature can be used to alert the host system to a change in state of the board’s ejector handles. Compensating the Active Current Loop The four active current limit circuits of the LTC4245 are compensated internally and therefore do not require any RC network on the gate pins. The internal compensation should work for most pass transistors. If the gate capacitance is very small then the best method to compensate the loop is to add a 1nF to 5nF capacitor between the gate and source of the external MOSFET. Supply Collapse During Transients The LTC4245 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is significant, there is a chance that the supply could collapse before the active current limit circuit brings down the gate of the external MOSFET. In this case the undervoltage lockout circuit, which has a 3.5μs (5.5μs for VEEIN) filter time, turns off the pass transistors. Input Overvoltage Transient Protection Hot-plugging a board into a backplane generates inrush currents from the backplane power supplies due to the charging of the plug-in board capacitance. To reduce this transient current to a safe level, the CPCI Hot Swap specification restricts the amount of unswitched capacitance used on the input side of the plug-in board. Each medium or long power pin connected to the CPCI female connector on the plug-in board is required to have a 10nF ceramic bypass capacitor to ground. Bulk capacitors are allowed on the switched output side of the LTC4245. Some bulk capacitance is allowed on the Early Power planes, but only because a current limiting resistor is assumed to decouple the connector pin from the bulk capacitance (e.g., see 100Ω to Bus Switch VDD in Figure 10). Disallowing bulk capacitors on the input power pins tends to create a resonant circuit formed by the inductance of the backplane power supply trace and the parasitic capacitance of the plug-in board (mainly due to the large power U MOSFET). Upon board insertion, the ringing of this circuit can exhibit a peak overshoot of 2.5 times the steady-state voltage (>30V for 12VIN). There are two methods for abating the effects of these high voltage transients: using voltage limiters to clip the transient to a safe level and snubber networks. Snubber networks are series RC networks whose time constants are experimentally determined based on the board’s parasitic resonance circuits. As a starting point, the capacitors in these networks are chosen to be 10× to 100× the power MOSFET’s COSS under bias. The series resistor is a value determined experimentally that ranges from 1Ω to 50Ω, depending on the parasitic resonance circuit. Note that in all LTC4245 circuit schematics, both transient voltage limiters and snubber networks have been added to the 12VIN and VEEIN supply rails and should always be used. Snubber networks are not necessary on the 3VIN or the 5VIN supply lines since their absolute maximum ratings are 10V. Transient voltage limiters, however, are recommended as these devices provide large-scale transient protection for the LTC4245 in the event of abrupt changes in supply current. All protection networks should be mounted very close to the LTC4245’s supply pins using short lead lengths to minimize the trace resistance and inductance. A recommended layout of the 5V and 12V transient protection devices around the LTC4245 is shown in Figure 18. Design Example As a design example, consider a Hot Swap application with the following power supply requirements: Table 1. Example Power Supply Requirements VOLTAGE SUPPLY 12V 5V 3.3V –12V MAXIMUM LOAD CURRENT 600mA 5A 7A 300mA MAXIMUM INRUSH dI/dt 150mA/ms 1.5A/ms 1.5A/ms 150mA/ms LOAD CAPACITANCE 100μF 2200μF 2200μF 100μF W U U 1. Select the appropriate values of RSENSE for the supplies. Calculating the value of RSENSE is based on ILOAD(MAX) and the lower limit for the circuit breaker threshold voltage, ΔVSNS(CB)(MIN). If a 1% tolerance is assumed for the sense resistors, then the following values of resistances should suffice: 4245fa 25 LTC4245 APPLICATIO S I FOR ATIO Table 2. Sense Resistance Values SUPPLY 12V 5V 3.3V –12V RSENSE(1%) 50mΩ 3.5mΩ 2.5mΩ 100mΩ ITRIP(MIN) 891mA 6.4A 8.9A 396mA ITRIP(MAX) 1.1A 7.9A 11.1A 606mA If necessary, two resistors with the same tolerance can be connected in parallel to yield the 3.5mΩ and 2.5mΩ values. 2. Select the SS capacitor for limiting the rate of rise of inrush current. Equations 1 and 2 lead to the following design equation: CSS(MIN) ≥ GSS • ISS(MAX ) RSENSE(MIN) •(dI / dt)(MAX ) (6) Applying Equation 6 to the 12V supply, with GSS of 46mV/V, ISS(MAX) of 24μA, RSENSE(MIN) of 49.5mΩ, and (dI/dt)(MAX) of 150mA/ms yields a CSS(MIN) greater than 149nF. This capacitance value satisfies the dI/dt requirements of the other supplies too. Hence, a 220nF (±10%) capacitor is chosen for CSS. 3. To determine the TIMER capacitance, the time required to completely power-up all supply outputs simultaneously needs to be calculated. There are three parts to this time: time for the internal current limit to cross zero (t1), time for the gate to slew to the MOSFET threshold voltage (t2) and the time for the current flow to charge up the load capacitors (t3) (see Figure 17). t1: The time for the internal current limit to rise above zero is simply: t1 = 4 • IFBL(MIN) (dI / dt)(MIN) (7) t2: The maximum time for the gate of the external MOSFET to rise to the threshold voltage depends on IGATE(UP)(MIN) and the gate charge required to turn on the external MOSFET. A typical value for this time is 1ms. This can be verified after the MOSFETs are selected. Since the current limit ramp is almost stopped while any MOSFET is turning on, t2 is 4 times 1ms or 4ms, since in the worst case none of the four MOSFET turn-ons overlaps in time. 26 U t3: Under simultaneous power-up each output voltage affects the inrush current profile. To simplify calculations, the inrush current profile shown in Figure 17 is chosen. All the current is assumed to charge the load capacitor, i.e., there is no load current. There are four parts to t3 as shown. Equations 8 to 11 are used to determine t31 to t34: IFBL(MIN) t 31 = (dI / dt)(MIN) (8) CL • VFB t 32 = – 0.5 • t 31 IFBL(MIN) (9) ⎞ ⎛ IFBH(MIN) – IFBL(MIN) , ⎟ ⎜ (dI / dt) (MIN) ⎜ ⎟ t 33 = min ⎜ 2 • C • (V ⎟ L OUT – VFB ) + t 2 − t ⎟ ⎜ 31 31⎟ ⎜ (dI / dt)(MIN) ⎠ (10) ⎝ t 34 = max ⎞ ⎛ 0, ⎟ ⎜ C • (V OUT – VFB ) – 0.5 • t 33 • (IFBL(MIN) + IFBH(MIN) ) ⎟ ⎜L ⎟ ⎜ IFBH(MIN) ⎠ ⎝ (11) VOUT = VIN (LARGE CL) IFBH VOUT = VIN (SMALL CL) VGATE = VTH IFBL VOUT = VFB VGATE = 0 0 INEG t1 t2 t31 t32 t33 OR t33 t34 4245 F17 W U U INTERNAL CURRENT LIMIT INRUSH CURRENT FOR LARGER CL INRUSH CURRENT FOR SMALLER CL Figure 17. Inrush Current Profile for Design Example 4245fa LTC4245 APPLICATIO S I FOR ATIO Table 3. t3 Calculation Inputs SUPPLY 12V 5V 3.3V –12V VOUT 12V 5V 3.3V 12V VFB 6V 3V 2V 6V (dI/dt)(MIN) 60mA/ms 430mA/ms 602mA/ms 30mA/ms IFBL(MIN) 198mA 1.13A 1.58A 109mA IFBH(MIN) 792mA 6.22A 8.71A 396mA The inputs to the above equations are pre-calculated in Table 3. Equations 8 to 11, when applied to the four supplies yields: Table 4. t3 Calculation Results SUPPLY 12V 5V 3.3V –12V t31 3.3ms 2.6ms 2.6ms 3.6ms t32 1.4ms 4.5ms 1.5ms 3.7ms t33 2.3ms 2.6ms 1.4ms 3.7ms t34 0 0 0 0 TOTAL(t3) 7ms 9.7ms 5.5ms 11ms Therefore the TIMER capacitance value is constrained by the –12V supply inrush current. The total time (t1 + t2 + t3) is approximately 30ms. Equation 4 gives the capacitor value to be: (12) CT(MIN) ≥ 30ms / KTMCAP(MIN) = 1.5μF So a value of 2.2μF (±10%) should suffice. 4. The next step is to select MOSFETs for the four supplies. The IRF7413 is selected for 12V, Si7880DP for 5V and 3.3V, and Si4872 for –12V Supply. The Si7880DP’s on resistance is less than 4.25mΩ for VGS = 4.5V and a junction temperature of 25°C. Since the maximum load current requirement for the 3.3V supply is 7A, the steady-state power the MOSFET may be required to dissipate is 208mW. The Si7880DP has a maximum junction-to-ambient thermal resistance of 65°C/W. If a maximum ambient temperature of 50°C is assumed, this yields a junction temperature of 63.5°C. According to the Si7880DP’s Normalized On-Resistance vs Junction Temperature curve, the device’s on-resistance can be expected to increase by about 15% over its room temperature value. Recalculation of the steady-state values of RON and junction temperature yields approximately 4.9mΩ and 67°C, respectively. The I • R drop across the 3.3V sense resistor and series MOSFET at maximum load current under these conditions will be less than 52mV. U The energy dissipated in the MOSFET during power-up is the same as that stored into the load capacitor. The average power dissipated in the MOSFET is: C • V2 PON = L OUT 2 • t3 (13) The 12V MOSFET’s single-pulse θJA(MAX), as read from its Transient Thermal Impedance Graph, is 3°C/W for a time, t3, of 7ms. PON is calculated to be 1W and therefore the 12V MOSFET temperature rise during power-up is 3°C. The other supplies show a smaller rise in MOSFET temperature than this value. When a supply powers-up into a short-circuit at the output, the supply current rises linearly to the lower foldback level and stays there till the timer expires and the MOSFETs are shut-off. To simplify calculations it will be assumed that the MOSFET conducts the lower foldback current from the moment it turns on. This time (tSC) is the actual time the MOSFET is conducting current minus a correction for the assumption, which is half of the time required for the current to rise from zero to the lower foldback level. Therefore: t SC(MAX ) = CT(MAX ) • K TMCAP(MAX ) – (1.5 • ∆VSNS(FBL )(MAX ) ) • CSS(MIN) (14) The 1.5 • ΔVSNS(FBL)(MAX) term is due to the correction factor and the time spent in ramping the starting negative current limit to zero. tSC(MAX) turns out to be about 58ms for all four supplies. The maximum power dissipated in the MOSFET is given by: PSC(MAX ) = IFBL(MAX ) • VOUT (15) GSS • ISS(MAX ) PSC(MAX) for the 5V supply is 3.2A • 5V, or 16W. θJA(MAX) for the 5V MOSFET is 3.25°C/W. Therefore the MOSFET temperature rise during power-up into a 5VOUT shortcircuit is 52°C. Similar calculations show that the other supplies experience a smaller MOSFET temperature rise. The θJA(MAX) value is read from the MOSFET datasheet’s Transient Thermal Impedance Graph for a duty cycle of 0.02, which is the case when the LTC4245 is configured for auto-retry on overcurrent faults. 4245fa W U U 27 LTC4245 APPLICATIO S I FOR ATIO PCB Layout Considerations For proper operation of the LTC4245’s circuit breaker, Kelvin connection to the sense resistors is strongly recommended. The PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistors and the power MOSFETs should include good thermal management techniques for optimal device power dissipation. A recommended PCB layout for the 5V sense resistor and the power MOSFET around the LTC4245 is illustrated in Figure 18. In Hot Swap applications where load currents can be 10A, narrow PCB tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. Since the sheet resistance of 1 ounce copper foil is approximately 0.5mΩ/o, track resistances and voltage drops add up quickly in high current applications. Thus, to keep PCB track resistance, voltage CURRENT FLOW TO LOAD R2 SENSE RESISTOR D 5VIN D W D D R6 TRACK WIDTH W: 0.03" PER AMPERE ON 1 OZ Cu FOIL 36 35 34 33 32 31 30 29 INTVCC 28 VIA TO GND PLANE C1 27 Z2 5VSENSE 5VGATE 5VOUT 5VIN 12VIN GND CURRENT FLOW TO SOURCE Z1 R10 C2 GND GND W 10 1 2 3 4 5 6 7 8 9 *ADDITIONAL DETAILS OMITTED FOR CLARITY DRAWING IS NOT TO SCALE! Figure 18. Recommended Layout for R2, Q2, R6, Z2, C1, Z1, R10 and C2 4245fa 28 U drop and temperature rise to a minimum, the suggested trace width in these applications for 1oz copper foil is 0.03” for each ampere of DC current. In the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the PCB. For 1oz copper foil plating, a general rule is 1A of DC current per via, making sure the via is properly dimensioned so that solder completely fills any void. For other plating thicknesses, check with your PCB fabrication facility. It is also important to put C1, the bypass capacitor for the INTVCC pin as close as possible between INTVCC and GND. The surge suppressors, Z1 and Z2, are placed between the supply inputs and ground using wide traces. Q2 SO-8 G S S S W 5VOUT CURRENT FLOW TO LOAD LTC4245G* VIA TO GND PLANE 4245 F18 W U U LTC4245 APPLICATIO S I FOR ATIO Table 5. LTC4245 I2C Device Addressing DESCRIPTION Mass Write Alert Response 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 HEX DEVICE ADDRESS H 2E 19 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 7A 7C 7E 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BINARY DEVICE ADDRESS 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R/⎯W 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ADR3 X X L L L L L L L L NC NC NC NC NC NC NC NC L L L L NC/H NC/H NC/H NC/H H H H H H H H H LTC4245 ADDRESS PINS* ADR2 X X L L L L NC NC NC NC L L L L NC NC NC NC H H H H H H H H L L L L NC NC NC NC ADR1 X X L L NC NC L L NC NC L L NC NC L L NC NC L L NC NC L L NC NC L L NC NC L L NC NC ADR0 X X L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC L NC * L = Low, H = High, NC = Not Connected, X = Don’t Care U 4245fa W U U 29 LTC4245 APPLICATIO S I FOR ATIO Table 6. LTC4245 Register Address and Contents REGISTER ADDRESS* DECIMAL 0, 8 1, 9 2, 10 3, 11 4, 12 5, 13 6, 14 7, 15 16 17 18 19 20 21 22 23 24 25 26 27 28 to 31 HEX 00h, 08h 01h, 09h 02h, 0Ah 03h, 0Bh 04h, 0Ch 05h, 0Dh 06h, 0Eh 07h, 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch to 1Fh STATUS (A) ALERT (B) CONTROL (C) ON (D) FAULT1 (E) FAULT2 (F) GPIO (G) ADCADR (H) 12VIN (I) 12VSENSE (J) 12VOUT (K) 5VIN (L) 5VSENSE (M) 5VOUT (N) 3VIN (O) 3VSENSE (P) 3VOUT (Q) VEEIN (R) VEESENSE (S) VEEOUT (T) GPIOADC (U) R R/W R/W D3:D0 R/W**, D7:D4 R R/W R/W G2:G0 R, G7:G3 R/W R/W R/W† R/W† R/W† R/W† R/W† R/W† R/W† R/W† R/W† R/W† R/W† R/W† R/W† System Status Information Controls Which Faults Cause ALERT# Pin to be Pulled Low Controls Part Behavior Such As Auto-Retry, Sequencing, etc. Sets State and Reports Status of Switches Fault Log for Undervoltage and Overcurrent Fault Log for Power Bad, PGI, FET Short, BD_SEL#, GPIO1 Sets State and Reports Status of GPIO1 to GPIO3 pins, Control Which Pin is Multiplexed to the GPIO Channel of ADC 4-Bit ADC Channel Address for On-Demand ADC Measurement ADC 12VIN Voltage Data ADC 12V Current Sense Voltage Data ADC 12VOUT Voltage Data ADC 5VIN Voltage Data ADC 5V Current Sense Voltage Data ADC 5VOUT Voltage Data ADC 3VIN Voltage Data ADC 3.3V Current Sense Voltage Data ADC 3VOUT Voltage Data ADC VEEIN Voltage Data ADC –12V Current Sense Voltage Data ADC VEEOUT Voltage Data ADC GPIO Voltage Data REGISTER NAME READ/WRITE DESCRIPTION All registers are 8-bit wide. * Register address MSBs b7 – b5 are ignored. ** Cannot set D3:D0 high if bit A1 set. † Set bit C7 before writing. Table 7. STATUS Register A (00h)- Read Only BIT A7 A6 A5 A4 A3 A2 A1 A0 NAME ADC Busy BD_SEL# Input FET Short Present LOCAL_PCI_RST# Output PCI_RST# Input Power Bad SS Busy Undervoltage OPERATION Indicates State of ADC; 1 = ADC Busy Measuring, 0 = ADC Quiescent State of the BD_SEL# Pin; 1 =BD_SEL# High, 0 = BD_SEL# Low Indicates Potential FET Short on at Least One Supply, if ADC Current Sense Voltage Measurement Exceeds 7 LSB While FET is Off; 1 = FET is Shorted, 0 = FET is Not Shorted LOCAL_PCI_RST# Pin Open-Drain Output State; 1 = High Impedance, 0 = Pulls Low State of the PCI_RST# Pin; 1 = PCI_RST# High, 0 = PCI_RST# Low Indicates Power Bad Present on at Least One of the Supply Outputs; 1 = Power Bad, 0 = No Power Bad Indicates SS Pin is Being Used to Ramp Up a Supply, Affects Writing to D3:D0 Bits 1 = SS Pin Ramping, Cannot Set D3:D0 High, 0 = SS Pin Reset Indicates Undervoltage Present on at Least One of the Input Supply; 1 = Undervoltage, 0 = Not Undervoltage 30 U 4245fa W U U LTC4245 APPLICATIO S I FOR ATIO Table 8. ALERT Register B (01h) – Read/Write BIT B7 B6 B5 B4 B3 B2 B1 B0 NAME GPIO1 State Change Alert BD_SEL# State Change Alert FET Short Alert PGI Fault Alert Alert Present Power Bad Alert Overcurrent Alert Undervoltage Alert OPERATION Enables Alert When GPIO1 Changes State; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert When BD_SEL# Changes State; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert for FET Short Condition; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert When a PGI Fault Occurs; 1 = Enable Alert, 0 = Disable Alert (Default) ALERT# Pin Open-Drain Output State; 1 = Pulls Low, 0 = High Impedance (Default) Enables Alert When Output Power is Bad; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert for Overcurrent Condition; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert for Undervoltage Condition; 1 = Enable Alert, 0 = Disable Alert (Default) Table 9. CONTROL Register C (02h) – Read/Write BIT C7 C6 C5 C4 C3 C2 C1 C0 NAME ADC Free-Run Disable Sequencing Enable Mass Write Enable PGI Fault Autoretry PGI Pin Disable Reserved Overcurrent Autoretry Undervoltage Autoretry OPERATION Disable ADC Free Running Operation to Allow On-Demand Measurement and Writes to ADC Registers; 1 = Halt ADC Free Running, 0 = ADC Free Running (Default) Enables Supplies to Turn-On in a Set Sequence 1 = Sequencing Enabled, 0 = Sequencing Disabled (Default) Enables Mass Write Using Address (0010 111)b 1 = Mass Write Enabled (Default), 0 = Mass Write Disabled Enables Autoretry After a PGI Fault; 1 = Retry Enabled, 0 = Retry Disabled (Default) Enables PGI Pin Going Low During Normal Operation to Shut Off Switches 1 = PGI Pin Disabled (Default), 0 = PGI Pin Enabled Not Used Enables Autoretry After an Overcurrent Fault; 1 = Retry Enabled, 0 = Retry Disabled (Default) Enables Autoretry After an Undervoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled Table 10. ON Register D (03h) – Read/Write BIT D7 D6 D5 D4 D3 D2 D1 D0 NAME –12V FET On Status 3.3V FET On Status 5V FET On Status 12V FET On Status –12V FET On Control 3.3V FET On Control 5V FET On Control 12V FET On Control OPERATION Indicates State of –12V FET. Read Only Bit; 1 = FET On, 0 = FET Off Indicates State of 3.3V FET. Read Only Bit; 1 = FET On, 0 = FET Off Indicates State of 5V FET. Read Only Bit; 1 = FET On, 0 = FET Off Indicates State of 12V FET. Read Only Bit; 1 = FET On, 0 = FET Off Turns –12V FET On and Off. Not used if CFG Pin is Not Low. Cannot Write 1 if Bit A1 Set 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay Turns 3.3V FET On and Off. Cannot Write 1 if Bit A1 Set 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay Turns 5V FET On and Off. Cannot Write 1 if Bit A1 Set 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay Turns 12V FET On and Off. Also Turns –12V FET On and Off if CFG Pin is Not Low. Cannot Write 1 if Bit A1 Set 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay U 4245fa W U U 31 LTC4245 APPLICATIO S I FOR ATIO Table 11. FAULT1 Register E (04h) – Read/Write BIT E7 E6 E5 E4 E3 E2 E1 E0 NAME –12V Overcurrent Fault Occurred 3.3V Overcurrent Fault Occurred 5V Overcurrent Fault Occurred 12V Overcurrent Fault Occurred –12V Undervoltage Fault Occurred 3.3V Undervoltage Fault Occurred 5V Undervoltage Fault Occurred 12V Undervoltage Fault Occurred OPERATION Indicates Overcurrent Fault Occurred on –12V Supply 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults Indicates Overcurrent Fault Occurred on 3.3V Supply 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults Indicates Overcurrent Fault Occurred on 5V Supply 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults Indicates Overcurrent Fault Occurred on 12V Supply 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults Indicates –12V Supply Undervoltage Fault Occurred When VEEIN Went High 1 = VEEIN was High, 0 = No Undervoltage Faults Indicates 3.3V Supply Undervoltage Fault Occurred When 3VIN Went Low 1 = 3VIN was Low, 0 = No Undervoltage Faults Indicates 5V Supply Undervoltage Fault Occurred When 5VIN Went Low 1 = 5VIN was Low, 0 = No Undervoltage Faults Indicates 12V Supply Undervoltage Fault Occurred When 12VIN Went Low 1 = 12VIN was Low, 0 = No Undervoltage Faults Table 12. FAULT2 Register F (05h) – Read/Write BIT F7 F6 F5 F4 F3 F2 F1 F0 NAME GPIO1 Changed State BD_SEL# Changed State FET Short Fault Occurred PGI Fault Occurred –12V Power Bad Fault Occurred 3.3V Power Bad Fault Occurred 5V Power Bad Fault Occurred 12V Power Bad Fault Occurred OPERATION Indicates that GPIO1 Pin Changed State; 1 = GPIO1 Changed State, 0 = GPIO1 Unchanged Indicates that BD_SEL# Pin Changed State; 1 = BD_SEL# Changed State, 0 = BD_SEL# Unchanged Indicates Potential FET Short was Detected on at Least One Supply, When ADC Measured Current Sense Voltage Exceeded 7 LSB While FET was Off; 1 = FET was Shorted, 0 = FET is Good Indicates PGI Fault Occurred; 1 = PGI Fault Occurred, 0 = No PGI faults Indicates –12V Power was Bad When VEEOUT Went High 1 = VEEOUT was High, 0 = No Power Bad Faults Indicates 3.3V Power was Bad When 3VOUT Went Low 1 = 3VOUT was Low, 0 = No Power Bad Faults Indicates 5V Power was Bad When 5VOUT Went Low 1 = 5VOUT was Low, 0 = No Power Bad Faults Indicates 12V Power was Bad When 12VOUT Went Low 1 = 12VOUT was Low, 0 = No Power Bad Faults Table 13. GPIO Register G (06h) – Read/Write (GPIO2, GPIO3 Bits Apply Only to the UHF Package) BIT G7:6 NAME GPIO Select OPERATION Control Which GPIO Pin is Multiplexed to the GPIO Channel of ADC G7 0 0 1 1 G5 G4 G3 G2 G1 G0 GPIO3 Output GPIO2 Output GPIO1 Output GPIO3 Input GPIO2 Input GPIO1 Input G6 0 1 0 1 GPIO GPIO1 (Default) GPIO1 GPIO2 GPIO3 GPIO3 Pin Open-Drain Output State; 1 = High Impedance (Default), 0 = Pulls Low GPIO2 Pin Open-Drain Output State; 1 = High Impedance (Default), 0 = Pulls Low GPIO1 Pin Open-Drain Output State; 1 = High Impedance (Default), 0 = Pulls Low State of the GPIO3 Pin, Read Only Bit; 1 = GPIO3 High, 0 = GPIO3 Low State of the GPIO2 Pin, Read Only Bit; 1 = GPIO2 High, 0 = GPIO2 Low State of the GPIO1 Pin, Read Only Bit; 1 = GPIO1 High, 0 = GPIO1 Low 4245fa 32 U W U U LTC4245 APPLICATIO S I FOR ATIO Table 14. ADCADR Register H (07h) – Read/Write BIT H7:4 H3:0 NAME Reserved ADC Channel Address OPERATION Not Used Selects Which ADC Channel to Measure On-Demand H3 0 0 0 0 0 0 0 0 1 1 1 1 1 H2 0 0 0 0 1 1 1 1 0 0 0 0 1 H1 0 0 1 1 0 0 1 1 0 0 1 1 X H0 0 1 0 1 0 1 0 1 0 1 0 1 X ADC CHANNEL 12VIN Voltage (Default) 12V Current Sense Voltage 12VOUT Voltage 5VIN Voltage 5V Current Sense Voltage 5VOUT Voltage 3VIN Voltage 3.3V Current Sense Voltage 3VOUT Voltage VEEIN Voltage –12V Current Sense Voltage VEEOUT Voltage GPIO Voltage Table 15. ADC Data Registers I to U (10h to 1Fh) – Read/Write BIT I7:0 J7:0 K7:0 L7:0 M7:0 N7:0 O7:0 P7:0 Q7:0 R7:0 S7:0 T7:0 U7:0 NAME 12VIN Voltage Data 12VSENSE Voltage Data 12VOUT Voltage Data 5VIN Voltage Data 5VSENSE Voltage Data 5VOUT Voltage Data 3VIN Voltage Data 3VSENSE Voltage Data 3VOUT Voltage Data VEEIN Voltage Data VEESENSE Voltage Data VEEOUT Voltage Data GPIO Voltage Data OPERATION 12VIN Pin Voltage Data. 8-Bit Data with 55mV LSB and 14.025V Full Scale 12VIN to 12VSENSE Current Sense Voltage Data. 8-Bit Data with 250µV LSB and 63.75mV Full Scale 12VOUT Pin Voltage Data. 8-Bit Data with 55mV LSB and 14.025V Full Scale 5VIN Pin Voltage Data. 8-Bit Data with 22mV (or 15mV) LSB and 5.61V (or 3.825V) Full Scale 5VIN to 5VSENSE Current Sense Voltage Data. 8-Bit Data with 125µV LSB and 31.875mV Full Scale 5VOUT Pin Voltage Data. 8-Bit Data with 22mV (or 15mV) LSB and 5.61V (or 3.825V) Full Scale 3VIN Pin Voltage Data. 8-Bit Data with 15mV LSB and 3.825V Full Scale 3VIN to 3VSENSE Current Sense Voltage Data. 8-Bit Data with 125µV LSB and 31.875mV Full Scale 3VOUT Pin Voltage Data. 8-Bit Data with 15mV LSB and 3.825V Full Scale VEEIN Pin Voltage Data. 8-Bit Data with –55mV LSB and –14.025V Full Scale VEESENSE to VEEIN Current Sense Voltage Data. 8-Bit Data with 250µV LSB and 63.75mV Full Scale VEEOUT Pin Voltage Data. 8-Bit Data with –55mV LSB and –14.025V Full Scale GPIOn Pin Voltage Data. 8-Bit Data with 10mV LSB and 2.55V Full Scale U 4245fa W U U 33 LTC4245 PACKAGE DESCRIPTIO U G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ± 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) MAX 0° – 8° 7.8 – 8.2 0.42 ± 0.03 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 0.22 – 0.38 (.009 – .015) TYP 0.05 (.002) MIN G36 SSOP 0204 4245fa 34 LTC4245 PACKAGE DESCRIPTIO U UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.15 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 0.00 – 0.05 3.15 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 37 38 0.40 ± 0.10 1 2 5.15 ± 0.10 (2 SIDES) 0.40 ± 0.10 0.200 REF 0.25 ± 0.05 0.75 ± 0.05 0.200 REF 0.00 – 0.05 0.50 BSC R = 0.115 TYP (UH) QFN 0205 5.50 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 3.15 ± 0.05 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 7.00 ± 0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4245fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC4245 TYPICAL APPLICATIO 8mΩ VIN 12V VIN 3.3V VAUX 3.3V 12VIN PWREN PWREN 12VSENSE BD_SEL# ON PWRGD PCI EXPRESS HOT-PLUG CONTROLLER PWRGD PWRFLT SYSTEM MANAGEMENT BUS CONTROLLER HEALTHY# LOCAL_PCI_RESET# ALERT# SDA SCL SS TIMER ADR0 ADR1 ADR2 ADR3 PGI PCI_RESET# INTVCC CFG GND PRECHARGE PRST#1 N/C 10nF 2.2µF 0.1µF N/C BACKPLANE CONNECTOR CARD CONNECTOR 4245 TA02 RELATED PARTS PART NUMBER LTC1421 LT®1641-1/LT1641-2 LTC1642A DESCRIPTION Hot Swap Controller Positive High Voltage Hot Swap Controllers Fault Protected Hot Swap Controller COMMENTS Dual Supplies from 3V to 12V, Additional –12V 9V to 80V, Latch Off/Autoretry, SO-8 3V to 16.5V, Overvoltage Protection Up to 33V 3.3V, 5V, ±12V Supplies for PCI Bus Operates from 1.2V to 12V, SO-8 3.3V, 5V Supplies Only Dual ON Pins, 2.7V to 16.5V Single Supply, 2.5V to 16.5V, MSOP 3.3V, 5V, ±12V Supplies, Control and Status over I2C 3.3V, 5V, ±12V and 3.3VAux Supplies for PCI Bus 3.3V, 5V, ±12V, Local Reset Logic and Precharge Fast Active Current Limiting with Drain Accelerated Response, Supply from –15V Provides Capacitive Buffering, SDA and SCL Precharge and Level Shifting, Enabled by 2-Wire Bus Commands 4245fa LTC1643AL/LTC1643AL-1, PCI Bus Hot Swap Controllers LTC1643AH LTC1645 LTC1646 LTC1647 LTC4211 LTC4240 LTC4241 LTC4244/LTC4244-1 LTC4252A LTC4260 LTC4302-1/LTC4302-2 Dual-Channel Hot Swap Controller/Power Sequencer CompactPCI Dual Hot Swap Controller Dual Hot Swap Controller Hot Swap Controller with Multifunction Current Control CompactPCI Hot Swap Controller with I2C I/O PCI-Bus with 3.3V Auxiliary Hot Swap Controller Rugged CompactPCI Bus Hot Swap Controllers –48V Hot Swap Controller in MSOP Positive High Voltage Hot Swap Controller with I2C, ADC I2C Interface and 8-bit ADC for Board Power Monitoring, 8.5V to 80V Addressable 2-Wire Bus Buffers 36 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006 U PCI Express Backplane Resident Application PRST#2 Si7880DP VOUT 12V 5.5A 10Ω 7mΩ Si7880DP VOUT 3.3V 3A 10Ω 60mΩ IRF7413 AUX OUTPUT 3.3V 375mA 10Ω 12VGATE 12VOUT 3VIN 3VSENSE 3VGATE 3VOUT 5VIN 5VSENSE 5VGATE 5VOUT GPI01 GPI02 GPI03 LTC4245 VEEIN VEESENSE VEEGATE VEEOUT A/D INPUT LT 0406 REV A • PRINTED IN USA