LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 Negative Voltage Hot Swap Controllers
FEATURES
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
DESCRIPTIO
Allows Safe Board Insertion and Removal from a Live – 48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit With Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Programmable Soft-Start Current Limit Programmable Timer with Drain Voltage Accelerated Response ±1% Undervoltage/Overvoltage Threshold Accuracy (LTC4252A) Adjustable Undervoltage/Overvoltage Protection LTC4252-1/LTC4252A-1: Latch Off After Fault LTC4252-2: Automatic Retry After Fault Available in 8-Pin and 10-Pin MSOP Packages
The LTC®4252 negative voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. Adjustable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4252’s supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial startup and controls the circuit breaker’s response time. The circuit breaker’s response time is accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within its safe operating area (SOA). An adjustable softstart circuit controls MOSFET inrush current at start-up. The LTC4252-1/LTC4252A-1 latch off after a circuit breaker fault times out. The LTC4252-2 provides automatic retry after a fault. The LTC4252A-1/LTC4252A-2 feature tight ±1% undervoltage/overvoltage threshold accuracy. The LTC4252 is available in either an 8-pin or 10-pin MSOP.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
APPLICATIO S
■ ■ ■ ■ ■ ■ ■
Hot Board Insertion Electronic Circuit Breaker – 48V Distributed Power Systems Negative Power Supply Control Central Office Switching High Availability Servers ATCA
TYPICAL APPLICATIO
GND
– 48V/2.5A Hot Swap Controller
RIN 3× 1.8k IN SERIES 1/4W EACH CIN 1µF R1 402k 1% VIN LTC4252-1 OV UV R2 32.4k 1% C1 10nF TIMER CT 0.33µF SS CSS 68nF VEE PWRGD DRAIN GATE SENSE RC 10Ω CC 18nF RS 0.02Ω
PWRGD 10V/DIV
4252-1/2 TA01
+
CL 100µF LOAD EN
GATE 5V/DIV
GND (SHORT PIN)
R3 5.1k * RD 1M VOUT
SENSE 2.5A/DIV
Q1 IRF530S
VOUT 20V/DIV
–48V * M0C207
U
Start-Up Behavior
1ms/DIV
4252-1/2 TA01a
U
U
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
ABSOLUTE
AXI U RATI GS
Current into VIN (100µs Pulse) ........................... 100mA VIN, DRAIN Pin Minimum Voltage ....................... – 0.3V Input/Output Pins (Except SENSE and DRAIN) Voltage ..........– 0.3V to 16V SENSE Pin Voltage ................................... – 0.6V to 16V Current Out of SENSE Pin (20µs Pulse) ........... – 200mA Current into DRAIN Pin (100µs Pulse) ................. 20mA Maximum Junction Temperature .......................... 125°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW VIN SS SENSE VEE 1 2 3 4 8 7 6 5 TIMER UV/OV DRAIN GATE VIN PWRGD SS SENSE VEE 1 2 3 4 5
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W
ORDER PART NUMBER LTC4252-1CMS8 LTC4252-2CMS8 LTC4252-1IMS8 LTC4252-2IMS8
MS8 PART MARKING LTWM LTWP LTRQ LTRR
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
U
U
W
WW
U
W
All Voltages Referred to VEE (Note 1)
Operating Temperature Range LTC4252-1C/LTC4252-2C LTC4252A-1C/LTC4252A-2C ................... 0°C to 70°C LTC4252-1I/LTC4252-2I LTC4252A-1I/LTC4252A-2I ............... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW 10 9 8 7 6 TIMER UV OV DRAIN GATE
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W
ORDER PART NUMBER LTC4252-1CMS LTC4252-2CMS LTC4252A-1CMS LTC4252A-2CMS LTC4252-1IMS LTC4252-2IMS LTC4252A-1IMS LTC4252A-2IMS
MS PART MARKING LTWN LTWQ LTAFX LTAGE LTRS LTRT LTAFY LTAGF
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL VZ rZ IIN VLKO VLKH VCB VACL VACL VCB VFCL VSS RSS ISS PARAMETER VIN – VEE Zener Voltage VIN – VEE Zener Dynamic Impedance VIN Supply Current VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis Circuit Breaker Current Limit Voltage Analog Current Limit Voltage Analog Current Limit Voltage Circuit Breaker Voltage Fast Current Limit Voltage SS Voltage SS Output Impedance SS Pin Current UV = OV = 4V, VSENSE = VEE, VSS = 0V (Sourcing) UV = OV = 0V, VSENSE = VEE, VSS = 2V (Sinking) VOS Analog Current Limit Offset Voltage VACL+VOS Ratio (VACL + VOS) to SS Voltage VSS IGATE GATE Pin Output Current UV = OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV = OV = 4V, VSENSE – VEE = 0.15V, VGATE = 3V (Sinking) UV = OV = 4V, VSENSE – VEE = 0.3V, VGATE = 1V (Sinking) VGATE VGATEH VGATEL VUVHI VUVLO VUV VUVHST VOVHI VOVLO VOV VOVHST ISENSE IINP VTMRH VTMRL External MOSFET Gate Drive Gate High Threshold Gate Low Threshold UV Pin Threshold HIGH UV Pin Threshold LOW UV Pin Threshold UV Pin Hysteresis OV Pin Threshold HIGH OV Pin Threshold LOW OV Pin Threshold OV Pin Hysteresis SENSE Pin Input Current UV, OV Pin Input Current TIMER Pin Voltage High Threshold TIMER Pin Voltage Low Threshold Low-to-High Transition (● for LTC4252A Only) UV = OV = 4V, VSENSE = 50mV UV = OV = 4V Low-to-High Transition (● for LTC4252A Only) VGATE – VEE, IIN = 2mA VGATEH = VIN – VGATE, IIN = 2mA, for PWRGD Status (MS Only) (Before Gate Ramp-Up)
● ● ● ● ● ● ● ● ● ● ● ●
ELECTRICAL CHARACTERISTICS
CONDITIONS IIN = 2mA IIN = 2mA to 30mA UV = OV = 4V, VIN = (VZ – 0.3V) Coming Out of UVLO (Rising VIN) VCB = (VSENSE – VEE) VACL = (VSENSE – VEE), SS = Open or 2.2V VACL = (VSENSE – VEE), SS = Open or 1.4V VFCL = (VSENSE – VEE) After End of SS Timing Cycle
● ● ● ● ● ● ●
LTC4252-1/-2 MIN TYP MAX 11.5 13 5 0.8 9.2 1 40 80 50 100 60 120 2 11.5 14.5
LTC4252A-1/-2 MIN TYP MAX 11.5 13 5 0.9 9 0.5 45 50 55 2 10 14.5
UNITS V Ω mA V V mV mV
1.05 150 200 2.2 100 22 28 10 0.05 40 58 17 190 10 12 2.8 0.5 3.075 3.225 3.375 2.775 2.925 3.075 3.05 300 5.85 5.25 6.15 5.55 600 – 15 ± 0.1 4 1 –30 ±1 6.45 5.85 5.04 82 292 VZ 10 80 40 300 150
1.20 200 1.4 50 28 28 10 0.05 58 17 190 12 2.8 0.5
1.38 300
V/V mV V kΩ µA mA mV V/V
80
µA mA mA
VZ
V V V V V
3.08 324
3.11 356
V mV V V
5.09 102 –15 ± 0.1 4 1
5.14 122 –30 ±1
V mV µA µA V V
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL ITMR PARAMETER TIMER Pin Current CONDITIONS Timer On (Initial Cycle/Latchoff/ Shutdown Cooling, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 0µA), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 50µA), VTMR = 2V Timer Off (Circuit Breaker/ Shutdown Cooling, Sinking), VTMR = 2V ∆ITMRACC [(ITMR at IDRN = 50µA) – (ITMR at IDRN = 0µA)] ∆IDRN ∆IDRN VDRNL IDRNL VDRNCL VPGL IPGH tSS DRAIN Pin Voltage Low Threshold DRAIN Leakage Current DRAIN Pin Clamp Voltage PWRGD Output Low Voltage PWRGD Pull-Up Current SS Default Ramp Period Timer On (Circuit Breaker with IDRN = 50µA) For PWRGD Status (MS Only) VDRAIN = 5V (4V for LTC4252A) IDRN = 50µA IPG = 1.6mA (MS Only) IPG = 5mA (MS Only) SS pin floating, VSS ramps from 0.2V to 2V SS pin floating, VSS ramps from 0.1V to 0.9V tPLLUG tPHLOG UV Low to Gate Low OV High to Gate Low 0.4 0.4
● ●
ELECTRICAL CHARACTERISTICS
LTC4252-1/-2 MIN TYP MAX 5.8
LTC4252A-1/-2 MIN TYP MAX 5.8
UNITS µA
28 230 630 5.8
28 230 630 5.8
mA µA µA µA
8 2.385 ± 0.1 7 0.2 40 58 180 0.4 1.1 80 40 ±1
8 2.385 ± 0.1 6 0.2 58 0.4 1.1 80 ±1
µA/µA V µA V V V µA µs
VPWRGD = 0V (Sourcing) (MS Only) ●
230 0.4 0.4
µs µs µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 TYPICAL PERFOR A CE CHARACTERISTICS
VZ vs Temperature
14.5 IIN = 2mA
14.0
6 5 4
IIN (µA)
13.5
VZ (V)
rZ (Ω)
13.0
12.5
12.0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G04
IIN vs VIN
1000 TA = – 40°C 100 TA = 25°C
VLKO (V)
10
TA = 85°C TA = 125°C
10.0 9.5
VLKH (V)
IIN (mA)
1
0.1
0
2
4
6
8 10 12 14 16 18 20 22 VIN (V)
4252-1/2 G02
Circuit Breaker Current Limit Voltage VCB vs Temperature
60 58 56 54
VACL (mV)
50 48 46 44 42 40 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G07
100 95 90 85 80 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G08
VFCL (mV)
VCB (mV)
52
UW
rZ vs Temperature
10 9 8 7 IIN = 2mA
2000 1800 1600 1400 1200 1000 800 600 400 200
IIN vs Temperature
VIN = (VZ – 0.3V)
3 2 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G03
0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G01
Undervoltage Lockout VLKO vs Temperature
12.0 11.5 11.0 10.5
Undervoltage Lockout Hysteresis VLKH vs Temperature
1.5
1.3
1.1
0.9
9.0
0.7
8.5 8.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G05
0.5 –55 –35 –15
5 25 45 65 95 105 125 TEMPERATURE (°C)
4252-1/2 G06
Analog Current Limit Voltage VACL vs Temperature
120 115 110 105 250 225 200 175 300 275
Fast Current Limit Voltage VFCL vs Temperature
150 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G09
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 TYPICAL PERFOR A CE CHARACTERISTICS
VSS vs Temperature
2.40 2.35 2.30 RSS (kΩ) 2.25 110 108 106 104 ISS (mA) 102 100 98 96 2.10 2.05 2.00 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G26
VSS (V)
2.20 2.15
VOS vs Temperature
11.0 10.8 10.6 10.4 VOS (mV) 10.2 10.0 9.8 9.6 9.4 9.2 9.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G29
(VACL + VOS) / VSS (V/V)
0.052 0.050 0.048 0.046 0.044 0.042 0.040 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G30
IGATE (µA)
IGATE (ACL, Sinking) vs Temperature
30 25 20
IGATE (mA)
IGATE (mA)
UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.15V VGATE = 3V
VGATE (V)
15 10 5 0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G11
6
UW
RSS vs Temperature
45 40 35 30 25 20 15 10 5
ISS (Sinking) vs Temperature
UV = OV = VSENSE = VEE IIN = 2mA VSS = 2V
94 92 90 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G28
0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G39
(VACL + VOS)/VSS vs Temperature
0.060 0.058 0.056 0.054
70
IGATE (Sourcing) vs Temperature
UV/0V = 4V TIMER = 0V 65 VSENSE = VEE VGATE = 0V 60 55 50 45 40 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G10
IGATE (FCL, Sinking) vs Temperature
400 350 300 250 200 150 100 50 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G12
VGATE vs Temperature
14.5 UV/0V = 4V 14.0 TIMER = 0V VSENSE = VEE 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G13
UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.3V VGATE = 1V
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 TYPICAL PERFOR A CE CHARACTERISTICS
VGATEH vs Temperature
3.6 3.4 3.2 VGATEH (V) VGATEL (V) 3.0 2.8 2.6 2.4 2.2 2.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G31
VGATEH = VIN – VGATE, IIN = 2mA (MS ONLY)
UV THRESHOLD (V)
OV Threshold vs Temperature
6.45 6.25 6.05 OV THRESHOLD (V)
ISENSE (µA)
VOVH
–18 –20 –22 –24 UV/0V = 4V TIMER = 0V GATE = HIGH VSENSE – VEE = 50mV 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G17
–ISENSE (mA)
5.85 5.65 5.45 5.25 5.05 4.85 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G16
VOVL
VOV
TIMER Threshold vs Temperature
5.0 4.5 4.0
TIMER THRESHOLD (V)
VTMRH
3.5
ITMR (mA)
ITMR (µA)
3.0 2.5 2.0 1.5 1.0 0.5 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G19
VTMRL
UW
VGATEL vs Temperature
0.8 UV/0V = 4V 0.7 TIMER = 0V GATE THRESHOLD 0.6 BEFORE RAMP-UP 0.5 0.4 0.3 0.2 0.1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G14
UV Threshold vs Temperature
3.375 3.275 3.175 3.075 2.975 2.875 2.775 –55 –35 –15 VUV
VUVH
VUVL
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G15
ISENSE vs Temperature
–10 –12 –14 –16 1.0 0.1 0.01
ISENSE vs (VSENSE – VEE)
10 UV/0V = 4V TIMER = 0V GATE = HIGH TA = 25°C 1.5 2.0
–26 –28
100
–30 –55 –35 –15
1000 –1.5 –1.0 –0.5 0 0.5 1.0 (VSENSE – VEE) (V)
4252-1/2 G18
ITMR (Initial Cycle, Sourcing) vs Temperature
10 9 8 7 6 5 4 3 2 1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G20
ITMR (Initial Cycle, Sinking) vs Temperature
50 TIMER = 2V 45 40 35 30 25 20 15 10 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G21
TIMER = 2V
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 TYPICAL PERFOR A CE CHARACTERISTICS
ITMR (Circuit Breaker, Sourcing) vs Temperature
280 690 TIMER = 2V IDRN = 0µA 670 650
ITMR (µA)
ITMR (µA)
260
630 610 590
ITMR (µA)
240
220
200 570 180 –55 –35 –15 550 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G22
ITMR vs IDRN
10 9.0 8.8 ∆ITMRACC/∆IDRN (µA/µA) 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 0.1 0.001 0.01 0.1 IDRN (mA) 1 10
4252-1/2 G33
ITMR (mA)
IDRN (mA)
1
VDRNL vs Temperature
2.60 FOR PWRGD STATUS (MS ONLY) 2.55 2.50
VDRNCL (V)
VDRNL (V)
2.45 2.40 2.35 2.30 2.25 2.20 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G35
7.0 6.8 6.6 6.4 6.2 6.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G36
VPGL (V)
8
UW
ITMR (Circuit Breaker, IDRN = 50µA, Sourcing) vs Temperature
TIMER = 2V IDRN = 50µA
10 9 8 7 6 5 4 3 2 1
ITMR (Cooling Cycle, Sinking) vs Temperature
TIMER = 2V
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G32
0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G23
∆ITMRACC/∆IDRN vs Temperature
100
TIMER ON (CIRCUIT BREAKING, IDRN = 50µA)
IDRN vs VDRAIN
IIN = 2mA
10 1 0.1 0.01 TA = 125°C TA = 85°C 0.001 0.0001 0.00001 TA = 25°C 0 2 4 6
TA = – 40°C 8 10 VDRAIN (V) 12 14 16
7.0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G34
4252-1/2 G25
VDRNCL vs Temperature
8.0 7.8 7.6 7.4 7.2 2.5 2.0 1.5 1.0 0.5 IDRN = 50µA 3.0
VPGL vs Temperature
(MS ONLY)
IPG = 10mA
IPG = 5mA
IPG = 1.6mA 5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G37
0 –55 –35 –15
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 TYPICAL PERFOR A CE CHARACTERISTICS
IPGH vs Temperature
62 61 60 VPWRGD = 0V (MS ONLY)
tSS (µs)
59 58 57 56 55 –55 –35 –15
190 180 170 160 150 –55 –35 –15
DELAY (µs)
IPGH (µA)
5 25 45 65 85 105 125 TEMPERATURE °(C) 4252-1/2 G38
PI FU CTIO S
(MS/MS8)
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO, overriding UV and OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE rampup. If VIN drops below approximately 8.2V, GATE pulls low immediately. PWRGD (Pin 2/Not Available): Power Good Status Output (MS only). At start-up, PWRGD latches low if DRAIN is below 2.385V and GATE is within 2.8V of VIN. PWRGD status is reset by UV, VIN (UVLO) or a circuit breaker fault timeout. This pin is internally pulled high by a 58µA current source. SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20x attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the beginning of a start-up cycle, the SS capacitor (CSS) is ramped by a 22µA (28µA for the LTC4252A) current
UW
tSS vs Temperature
220 210 200 SS PIN FLOATING, VSS RAMPS FROM 0.2V TO 2V
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
tPLLUG and tPHLOG vs Temperature
tPLLUG tPHLOG
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G27
0 –55 –35 –15
5 25 45 65 85 105 125 TEMPERATURE (°C)
4252-1/2 G24
U
U
U
source. The GATE pin is held low until SS exceeds 20 • VOS = 0.2V. SS is internally shunted by a 100k resistor (RSS) which limits the SS pin voltage to 2.2V(50k resistor and 1.4V for the LTC4252A). This corresponds to an analog current limit SENSE voltage of 100mV (60mV for the LTC4252A). If the SS capacitor is omitted, the SS pin ramps up in about 180µs. The SS pin is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (230µA + 8 • IDRN) TIMER pull-up current. If SENSE exceeds VACL, the analog current limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic shortcircuit, SENSE may overshoot. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
PI FU CTIO S
VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, or a circuit breaker fault timeout. GATE is actively servoed to control the fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp-up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects if GATE is within 2.8V of VIN before PWRGD is set (MS package only). DRAIN (Pin 7/Pin 6): Drain Sense Input. Connecting an external resistor, RD, between this pin and the MOSFET’s drain (VOUT) allows voltage sensing below 6.15V (5V for LTC4252A) and current feedback to TIMER. A comparator detects if DRAIN is below 2.385V and together with the GATE high comparator sets the PWRGD flag. If VOUT is above VDRNCL, DRAIN clamps at approximately VDRNCL. The current through RD is internally multiplied by 8 and added to TIMER’s 230µA pullup current during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV (Pin 8/Pin7): Overvoltage Input. The active high threshold at the OV pin is set at 6.15V with 0.6V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns below 5.55V, GATE start-up begins without an initial timing cycle. The LTC4252A OV pin is set at 5.09V with 102mV hysteresis. If OV > 5.09V, GATE pulls low. When OV returns below 4.988V, GATE start-up begins without an initial timing cycle. If an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. An overvoltage condition does not reset the PWRGD flag. The internal UVLO at VIN always overrides OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE pin.
10
U
U
U
(MS/MS8)
UV (Pin 9/Pin 7): Undervoltage Input. The active low threshold at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V, PWRGD pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The LTC4252A UV pin is set at 3.08V with 324mV hysteresis. If UV < 2.756V, PWRGD pulls high, both GATE and TIMER pull low. If UV rises above 3.08V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at VIN always overrides UV. A low at UV resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin. TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to generate an initial timing delay at start-up and to delay shutdown in the event of an output overload (circuit breaker fault). TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE is lower than VGATEL, SS < 0.2V, and VSENSE – VEE < VCB. A pull-up current of 5.8µA then charges CT, generating a time delay. If CT charges to VTMRH (4V), the timing cycle terminates, TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 230µA pull-up current charging CT. If DRAIN is approximately 7V (6V for LTC4252A) during this cycle, the timer pull-up has an additional current of 8 • IDRN. If SENSE drops below 50mV before TIMER reaches 4V, a 5.8µA pull-down current slowly discharges the CT. In the event that CT eventually integrates up to the VTMRH threshold, the circuit breaker trips, GATE quickly pulls low and PWRGD pulls high. The LTC4252-1 TIMER pin latches high with a 5.8µA pull-up source. This latched fault is cleared by either pulling TIMER low with an external device or by pulling UV below VUVLO. The LTC4252-2 starts a shutdown cooling cycle following an overcurrent fault. This cycle consists of 4 discharging ramps and 3 charging ramps. The charging and discharging currents are 5.8µA and TIMER ramps between its 1V and 4V thresholds. At the completion of a shutdown cooling cycle, the LTC4252-2 attempts a startup cycle.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
BLOCK DIAGRA
VIN
VEE
6.15V (5.09V) OV *
– +
UV *
– (+)
2.925V (3.08V) 230µA VIN 5.8µA 4V
VEE
+ (–) –
LOGIC
VIN
– +
TIMER
–
VEE 5.8µA VIN 22µA (28µA) SS 95k (47.5k) RSS 5k (2.5k) VEE VOS = 10mV VEE 1V
FCL
+
+
ACL
–+ +
VEE CB
–
50mV
+–
VEE
VEE *OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE ** ONLY AVAILABLE IN THE MS PACKAGE FOR COMPONENTS, CURRENT AND VOLTAGE WITH TWO VALUES, VALUES IN PARENTHESES REFER TO THE LTC4252A. VALUES WITHOUT PARENTHESES REFER TO THE LTC4252
+
+
–
–
+
–
+
–
W
DRAIN 2.385V VIN 8× 1× VIN 58µA PWRGD ** VIN 58µA VEE GATE 2.8V 6.15V (5V) 1× 1× VEE
–+
VIN
0.5V
200mV
+–
VEE
VEE SENSE
4252-1/2 BD
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11
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
OPERATIO
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4252 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Initial Start-Up The LTC4252 resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic for the LTC4252A is shown in Figure 2. – 48V and – 48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV and OV determine whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV and OV do double duty by also monitoring whether or not the connector is seated. The top of the divider detects – 48RTN by way of a short connector pin that is the last to mate during the insertion sequence.
LONG –48RTN
PLUG-IN BOARD
LTC4252 LONG –48V BACKPLANE
Figure 1. Basic LTC4252 Hot Swap Topology
R2 30.1k 1% LONG –48V CSS 68nF CT 0.68µF
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Interlock Conditions A start-up sequence commences once these “interlock” conditions are met. 1. The input voltage VIN exceeds VLKO (UVLO). 2. The voltage at UV > VUVHI. 3. The voltage at OV < VOVLO. 4. The (SENSE – VEE) voltage is < 50mV (VCB). 5. The voltage at SS is < 0.2V (20 • VOS). 6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL). 7. The voltage at GATE is < 0.5V (VGATEL). The first three conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5.8µA into CT. If VIN, UV or OV falls out of range, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 58µA (IGATE), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits VSENSE to control the inrush current. PWRGD pulls active low when GATE is within 2.8V of VIN and DRAIN is lower than VDRNL.
LONG –48RTN RIN 3 × 1.8k IN SERIES 1/4W EACH SHORT R1 390k 1% C1 10nF CIN 1µF OV UV VIN
+ +
CLOAD
+
LOW VOLTAGE CIRCUITRY
ISOLATED DC/DC CONVERTER MODULE
CLOAD 100µF
+
–
–
4252-1/2 F01
LTC4252A-1 TIMER SS VEE SENSE DRAIN GATE
CC 10nF RS 0.02Ω
RC 10Ω
RD 1M
Q1 IRF530S
4252-1/2 F02
Figure 2. –48V, 2.5A Hot Swap Controller
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
OPERATIO
Two modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to –48V and the LTC4252 will fully enhance the MOSFET. A second possibility is that the load current exceeds the softstart current limit threshold of [VSS(t)/20 – VOS]/RS. In this case the LTC4252 will ramp the output by sourcing softstart limited current into the load capacitance. If the softstart voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4252-1 may shut down after one circuit breaker delay time whereas the LTC4252-2 may continue to autoretry. Board Removal If the board is withdrawn from the card cage, the UV and OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate, there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop (60mV for the LTC4252A); and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, owing to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 230µA into CT. CT eventually charges to a 4V threshold and the LTC4252 shuts off. If the overload goes away before CT reaches 4V and SENSE measures less than 50mV, CT slowly discharges (5.8µA). In this way the LTC4252’s circuit breaker function responds to low duty cycle overloads and accounts for fast heating and slow cooling characteristics of the MOSFET.
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Higher overloads are handled by an analog current limit loop. If the drop across RS reaches VACL, the current limiting loop servos the MOSFET gate and maintains a constant output current of VACL/RS. In current limit mode, VOUT typically rises and this increases MOSFET heating. If VOUT > VDRNCL, connecting an external resistor, RD, between VOUT and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 • IDRN. Note that because SENSE > 50mV, TIMER charges CT during this time and the LTC4252 will eventually shut down. Low impedance failures on the load side of the LTC4252 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/µs. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The VACL/RS current limit loop then takes over and servos the current as previously described. As before, TIMER runs and shuts down the LTC4252 when CT reaches 4V. If CT reaches 4V, the LTC4252-1 latches off with a 5.8µA pull-up current source whereas the LTC4252-2 starts a shutdown cooling cycle. The LTC4252-1 circuit breaker latch is reset by either pulling UV momentarily low or dropping the input voltage VIN below the internal UVLO threshold or pulling TIMER momentarily low with a switch. The LTC4252-2 retries after its shutdown cooling cycle. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot-swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4252 to “ride out” temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
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13
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
SHUNT REGULATOR A fast responding regulator shunts the LTC4252 VIN pin. Power is derived from – 48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1µF decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. RIN should be chosen to accommodate both VIN supply current and the drive required for an optocoupler if the PWRGD function on the 10-pin MS package is used. Higher current through RIN results in higher dissipation for RIN and the LTC4252. An alternative is a separate NPN buffer driving the optocoupler as shown in Figure 3. Multiple 1/4W resistors can replace a single higher power RIN resistor. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) A hysteretic comparator, UVLO, monitors VIN f or undervoltage. The thresholds are defined by VLKO and its hysteresis, VLKH. When VIN rises above VLKO the chip is enabled; below (VLKO – VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV/OV pin(s). These are completely separate functions.
GND RIN 10k 1/2W R4 22k Q2 GND (SHORT PIN) 1 R1 432k 1% R2 4.75k 1% R3 38.3k 1% CT 330nF C2 10nF VIN LTC4252-1 9 8 10 3 UV OV TIMER SS CSS 68nF VEE 5 PWRGD DRAIN GATE SENSE 2 7 6 4 RC 10Ω CC 18nF RD 1M Q1 IRF530S RS 0.02Ω
4252-1/2 F03
–48V * M0C207 Q2: MMBT5551LT1
Figure 3. – 48V/2.5A Application with Different Input Operating Range
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UV/OV COMPARATORS (LTC4252) An UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds: UV low-to-high (VUVHI) = 3.225V UV high-to-low (VUVLO) = 2.925V An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds: OV low-to-high (VOVHI) = 6.150V OV high-to-low (VOVLO) = 5.550V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 82V when connected together as in the typical application. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 82.5V. The undervoltage shutdown and overvoltage recovery thresholds are then 39.2V and 74.4V. 1% divider resistors are recommended to preserve threshold accuracy. The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100µA and define an impedance at UV/OV of 30kΩ. In most applicaCL 100µF R5 2.2k *
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U
+
CIN 1µF
LOAD EN
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
tions, 30kΩ impedance coupled with 300mV UV hysteresis makes the LTC4252 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. Separate UV and OV pins are available in the 10-pin MS package and can be used for a different operating range such as 35.5V to 76V as shown in Figure 3. Other combinations are possible with different resistor arrangements. UV/OV COMPARATORS (LTC4252A) A UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds: UV low-to-high (VUV) = 3.08V UV high-to-low (VUV – VUVHST) = 2.756V An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds: OV low-to-high (VOV) = 5.09V OV high-to-low (VOV – VOVHST) = 4.988V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 71V when connected together as in Figure 2. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 390k and R2 = 30.1k
GND
GND (SHORT PIN)
R1 464k 1% R2 10k 1% R3 34k 1% CT 0.68µF C2 10nF
–48V * M0C207 Q2: MMBT5551LT1
Figure 4. – 48V/2.5A Application with Wider Input Operating Range
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gives a typical operating range of 43V to 71V. The undervoltage shutdown and overvoltage recovery thresholds are then 38.5V and 69.6V respectively. 1% divider resistors are recommended to preserve threshold accuracy. The R1-R2 divider values shown in Figure 2 set a standing current of slightly more than 100µA and define an impedance at UV/OV of 28kΩ. In most applications, 28kΩ impedance coupled with 324mV UV hysteresis makes the LTC4252A insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. The UV and OV pins can be used for a wider operating range such as 35.5V to 76V as shown in Figure 4. Other combinations are possible with different resistor arrangements. UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4252, pulls the MOSFET gate low and resets the latched PWRGD high.
RIN 10k 1/2W R4 22k Q2 1 VIN LTC4252A-1 9 8 10 3 UV OV TIMER SS CSS 68nF VEE 5 PWRGD DRAIN GATE SENSE 2 7 6 4 RC 10Ω CC 10nF RD 1M Q1 IRF530S RS 0.02Ω CIN 1µF R5 2.2k * LOAD EN CL 100µF
W
U
U
+
4252-1/2 F04
15
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load. However, it will not reset the circuit breaker TIMER, PWRGD flag or shutdown cooling timer. Returning the supply voltage to an acceptable range restarts the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does an OV condition reset the TIMER. DRAIN Connecting an external resistor, RD, to the dual function DRAIN pin allows VOUT sensing* without it being damaged by large voltage transients. Below 5V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less than 2.385V (VDRNL). This condition, together with the GATE low comparator, sets the PWRGD flag. If VOUT > VDRNCL, the DRAIN pin is clamped at about VDRNCL and the current flowing in RD is given by:
IDRN ≈ VOUT − VDRNCL RD
This current is scaled up 8 times during a circuit breaker fault and is added to the nominal 230µA TIMER current. This accelerates the fault TIMER pull-up when the MOSFET’s drain-source voltage exceeds VDRNCL and effectively shortens the MOSFET heating duration. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at TIMER to provide timing for the LTC4252. Four different charging and discharging modes are available at TIMER: 1) A 5.8µA slow charge; initial timing and shutdown cooling delay. 2) A (230µA + 8 • IDRN) fast charge; circuit breaker delay. 3) A 5.8µA slow discharge; circuit breaker "cool off" and shutdown cooling.
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4) Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing. For initial start-up, the 5.8µA pull-up is used. The low impedance switch is turned off and the 5.8µA current source is enabled when the interlock conditions are met. CT charges to 4V in a time period given by:
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t=
4V • C T 5.8µA
(2)
When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than a 50mV drop across RS, the TIMER pin charges CT with (230µA + 8 • IDRN). If CT charges to 4V, the GATE pin pulls low and the LTC4252-1 latches off while the LTC4252-2 starts a shutdown cooling cycle. The LTC4252-1 remains latched off until the UV pin is momentarily pulsed low or TIMER is momentarily discharged low by an external switch or VIN dips below UVLO and is then restored. The circuit breaker timeout period is given by:
t= 4V • C T 230µA + 8 • IDRN
(1)
(3)
If VOUT < 5V, an internal PMOS device isolates any DRAIN pin leakage current, making IDRN = 0µA in Equation (3). If VOUT > VDRNCLduring the circuit breaker fault period, the charging of CT accelerates by 8 • IDRN of Equation (1). Intermittent overloads may exceed the 50mV threshold at SENSE, but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4252 will not shut the external MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5.8µA pull-down whenever the SENSE voltage is less than 50mV. Therefore, any intermittent overload with VOUT > 5V and an aggregate duty cycle
*VOUT as viewed by the MOSFET; i.e., VDS.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
10 IDRN = 0µA
NORMALIZED RESPONSE TIME (s/µF)
1 t CT(µF) 0.1 = 4 [(235.8 + 8 • IDRN) • D – 5.8]
0.01 0 20 40 60 80 FAULT DUTY CYCLE (%) 100
4252-1/2 F05
Figure 5. Circuit-Breaker Response Time
of 2.5% or more will eventually trip the circuit breaker and shut down the LTC4252. Figure 5 shows the circuit breaker response time in seconds normalized to 1µF for IDRN = 0µA. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. The normalized circuit response time is estimated by
t 4 = C T (µF ) (235.8 + 8 • IDRN ) • D − 5.8
[
]
SHUTDOWN COOLING CYCLE For the LTC4252-1 (latchoff version), TIMER latches high with a 5.8µA pull-up after the circuit breaker fault TIMER reaches 4V. For the LTC4252-2 (automatic retry version), a shutdown cooling cycle begins if TIMER reaches the 4V threshold. TIMER starts with a 5.8µA pull-down until it reaches the 1V threshold. Then, the 5.8µA pull-up turns back on until TIMER reaches the 4V threshold. Four 5.8µA pull-down cycles and three 5.8µA pull-up cycles occur between the 1V and 4V thresholds, creating a time interval given by:
tSHUTDOWN = 7 • 3V • C T 5.8µA
At the 1V threshold of the last pull-down cycle, a GATE ramp-up is attempted.
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SOFT-START Soft-start limits the inrush current profile during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET’s SOA rating if powering up into an active load. If SS floats, an internal current source ramps SS from 0V to 2.2V for the LTC4252 or 0V to 1.4V for the LTC4252A in about 230µs. Connecting an external capacitor CSS from SS to ground modifies the ramp to approximate an RC response of:
⎞⎞ ⎛ t ⎛ ⎜ − R •C ⎟ VSS( t) ≈ VSS • ⎜ 1− e⎝ SS SS ⎠ ⎟ ⎜ ⎟ ⎝ ⎠
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(6)
An internal resistive divider (95k/5k for the LTC4252 or 47.5k/2.5k for the LTC4252A) scales VSS(t) down by 20 times to give the analog current limit threshold: VACL (t) = VSS (t) − VOS 20 (7)
(4)
This allows the inrush current to be limited to VACL(t)/RS. The offset voltage, VOS (10mV), ensures CSS is sufficiently discharged and the ACL amplifier is in current limit before GATE start-up. SS is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. When GATE turns on, a 58µA current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN
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(5)
17
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (≥ 10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing or a GATE start-up cycle; the GATE high comparator looks for < 2.8V relative to VIN and, together with the DRAIN low comparator, sets PWRGD status during GATE startup. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When SENSE exceeds 50mV, the CB comparator activates the 230µA TIMER pull-up. At 100mV (60mV for the LTC4252A), the ACL amplifier servos the MOSFET current and, at 200mV, the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation 3), the LTC4252 shuts down and pulls GATE low. If the SENSE pin encounters a voltage greater than VACL, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover.
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SHORT-CIRCUIT OPERATION Circuit behavior arising from a load side low impedance short is shown in Figure 6 for the LTC4252. Initially, the current overshoots the fast current limit level of VSENSE = 200mV (Trace 2) as the GATE pin works to bring VGS under control (Trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/RS, the backplane responds by glitching in the positive direction. TIMER commences charging CT (Trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, PWRGD pulls high, the load current drops to zero and the backplane rings up to over 100V. The transient associated with the GATE turn off can be controlled with a snubber to reduce ringing and a transient voltage suppressor (such as Diodes Inc. SMAT70A) to clip off large spikes. The choice of RC for the snubber is usually done experimentally. The value of the snubber capacitor is usually chosen between 10 to 100 times the MOSFET COSS. The value of the snubber resistor is typically between 3Ω to 100Ω.
SUPPLY RING OWING TO CURRENT OVERSHOOT –48RTN 50V/DIV SUPPLY RING OWING TO MOSFET TURN OFF ONSET OF OUTPUT SHORT-CIRCUIT SENSE 200mV/DIV GATE 10V/DIV TIMER 5V/DIV FAST CURRENT LIMIT ANALOG CURRENT LIMIT LATCH OFF
4252-1/2 F06
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CTIMER RAMP 0.5ms/DIV
Figure 6. Output Short-Circuit Behavior of LTC4252
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 6 Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4252s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. POWER GOOD, PWRGD PWRGD latches low if GATE charges up to within 2.8V of VIN and DRAIN pulls below VDRNL during start-up. PWRGD is reset in UVLO, in a UV condition or if CT charges up to 4V. An overvoltage condition has no effect on PWRGD status. A 58µA current pulls this pin high during reset. Due to voltage transients between the power module and PWRGD, optoisolation is recommended. This pin provides sufficent drive for an optocoupler. Figure 19 shows an alternative NPN configuration with a limiting base resistor for the PWRGD interface. The module enable input should have protection from the negative input current. MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite may not be true. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a 3-step process by assuming the absense of a soft-start capacitor. First, RS is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum short-circuit current and maximum input voltage defines an operating point that is checked against the MOSFET’s SOA curve.
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To begin a design, first specify the required load current and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY(MIN). RS is given by:
RS = VCB(MIN) IL(MAX)
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(8)
where VCB(MIN) = 40mV (45mV for LTC4252A) represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4252 may operate the MOSFET in current limit, forcing (VACL) between 80mV to 120mV (VACL is 54mV to 66mV for LTC4252A) across RS. The minimum inrush current is given by:
IINRUSH(MIN)=
80mV RS
(9)
Maximum short-circuit current limit is calculated using the maximum VACL. This gives
ISHORTCIRCUIT(MAX)=
120mV RS
(10)
The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by:
tCL(CHARGE) =
C • V C L• V SUPPLY(MAX) = I IINRUSH(MIN)
(11)
The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) = V SUPPLY(MAX)− V DRNCL RD (12)
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
Approximating a linear charging rate as IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation (3) can be approximated with 0.5 • IDRN(MAX). Rearranging equation, TIMER capacitor CT is given by: CT = tCL(CHARGE) • (230µA + 4 • IDRN(MAX) ) 4V (13)
Returning to Equation (3), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) a nd ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS = 40mΩ; Equation (13) gives CT = 441nF. To account for errors in RS, CT, TIMER current (230µA), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT = 680nF. If a short-circuit occurs, a current of up to 120mV/ 40mΩ = 3A will flow in the MOSFET for 5.6ms as dictated by CT = 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the RSSCSS response. An overly conservative but simple approach begins with the maximum circuit breaker current, given by: VCB(MAX) (14) RS where VCB(MAX) = 60mV (55mV for the LTC4252A). I CB(MAX)= From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by:
tSOA(MAX) (15) 0.916 • RSS In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX) for the IRF530S is 40ms. From Equation (15), CSS = 437nF. Actual board evaluation showed that CSS = 100nF C SS =
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was appropriate. The ratio (RSS • CSS) to tCL(CHARGE) is a good gauge as a large ratio may result in the time-out period expiring. This gauge is determined empirically with board level evaluation. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2 with the LTC4252A. It was designed for 80W. Calculate the maximum load current: 80W/43V = 1.86A; allowing for 83% converter efficiency, IIN(MAX) = 2.2A. Calculate RS: from Equation (8) RS = 20mΩ. Calculate ISHORTCIRCUIT(MAX): from Equation (10) ISHORTCIRCUIT(MAX) = 66mV = 3.3A 20mΩ Select a MOSFET that can handle 3.3A at 71V: IRF530S. Calculate CT: from Equation (13) CT = 322nF. Select CT = 680nF, which gives the circuit breaker time-out period t = 5.6ms. Consult MOSFET SOA curves: the IRF530S can handle 3.3A at 100V for 8.2ms, so it is safe to use in this application. Calculate CSS: using Equations (14) and (15) select CSS = 68nF. FREQUENCY COMPENSATION The LTC4252A typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected to VEE. Figure 7 depicts the relationship between the compensation capacitor CC and the MOSFET’s CISS. The line in Figure 7 is used to select a starting value for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
60
COMPENSATION CAPACITANCE CC (nF)
NTY100N10 50
40 30 20 10 0 0 2000 6000 4000 MOSFET CISS (pF) 8000
4252-1/2 F07
IRF540S
IRF3710
4252-1/2 F08
IRF530S IRF740
TO SENSE TO VEE
Figure 7. Recommended Compensation Capacitor CC vs MOSFET CISS
As seen in Figure 6 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4252’s VEE and SENSE pins are strongly recommended. The drawing in Figure 8 illustrates the correct way of making connections between the LTC4252 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. TIMING WAVEFORMS System Power-Up Figure 9 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At
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CURRENT FLOW FROM LOAD CURRENT FLOW TO –48V BACKPLANE SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER W
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Figure 8. Making PCB Connections to the Sense Resistor
time point 1, the supply ramps up, together with UV/OV, VOUT and DRAIN. VIN and PWRGD follow at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < V GATEL , SENSE < V CB a nd SS < 20 • VOS must be satisfied before a GATE ramp-up cycle begins. SS ramps up as dictated by RSS • CSS (as in Equation 6); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 • VOS. Upon releasing GATE, 58µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches the SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) (Equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE – VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT, is charged by a (230µA + 8 • IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 GND – VEE OR (–48RTN) – (–48V) 2 3 4 56 7 8 9 10 11
UV/OV
VIN
VLKO VTMRH 230µA + 8 • IDRN VTMRL 58µA
TIMER
5.8µA
GATE
VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS
SS
SENSE
VOUT VDRNCL DRAIN VDRNL
PWRGD INITIAL TIMING GATE START-UP
4252-1/2 F09
Figure 9. System Power-Up Timing (All Waveforms are Referenced to VEE)
At time point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB, the fault TIMER cycle ends, followed by a 5.8µA discharge cycle (cool off). The duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid a fault time out during GATE ramp-up. When GATE ramps past the VGATEH threshold at time point 10, PWRGD pulls low. At time point 11, GATE reaches its maximum voltage as determined by VIN. Live Insertion with Short Pin Control of UV/OV In the example shown in Figure 10, power is delivered through long connector pins whereas the UV/OV divider
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5.8µA 5.8µA 58µA VIN – VGATEH VACL VCB
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makes contact through a short pin. This ensures the power connections are firmly established before the LTC4252 is activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL, SENSE < VCB and SS < 20 • VOS must be satisfied before
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 GND – VEE OR (–48RTN) – (–48V) 2 3 4 56 7 8 9 1011
UV/OV
VUVHI
VIN
VLKO VTMRH 230µA + 8 • IDRN
TIMER
5.8µA VTMRL
GATE VGATEL SS 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS
SENSE
VOUT VDRNCL DRAIN VDRNL
PWRGD INITIAL TIMING GATE START-UP
4252-1/2 F10
Figure 10. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
a GATE start-up cycle begins. SS ramps up as dictated by RSS • CSS; GATE is held low by the analog current limit amplifier until SS crosses 20 • VOS. Upon releasing GATE, 58µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches the SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE – VEE) reaches the
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5.8µA 5.8µA 58µA 58µA VIN – VGATEH VACL VCB
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VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT, is charged by a (230µA + 8 • IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB and the fault TIMER cycle ends, followed by a 5.8µA discharge cycle (cool off). When GATE ramps past VGATEH threshold at time point 10, PWRGD pulls low. At time point 11, GATE reaches its maximum voltage as determined by VIN.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
Undervoltage Timing In Figure 11 when UV pin drops below VUVLO (time point 1), the LTC4252 shuts down with TIMER, SS and GATE all pulling low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV recovers and clears VUVHI (time point 2), an initial timer cycle begins followed by a GATE start-up cycle. VIN Undervoltage Lockout Timing The VIN undervoltage lockout comparator, UVLO, has a similar timing behavior as the UV pin timing except it looks for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to start. In an undervoltage lockout condition, both UV and OV comparators are held off. When VIN exits undervoltage lockout, the UV and OV comparators are enabled. Undervoltage Timing with Overvoltage Glitch In Figure 12, both UV and OV pins are connected together. When UV clears VUVHI (time point 1), an initial timing cycle
UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 VUVHI VUVLO VTMRH TIMER 5.8µA VTMRL 58µA GATE VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL 58µA 230µA + 8 • IDRN 2 3 4 56 7 8 9 10 11
UV
SS
PWRGD INITIAL TIMING GATE START-UP
4252-1/2 F11
Figure 11. Undervoltage Timing (All Waveforms are Referenced to VEE)
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starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts, followed by a GATE start-up cycle. Overvoltage Timing During normal operation, if the OV pin exceeds VOVHI as shown at time point 1 of Figure 13, the TIMER and PWRGD status are unaffected. Nevertheless, SS and GATE pull down and the load is disconnected. At time point 2, OV recovers and drops below the VOVLO threshold. A GATE start-up cycle begins. If the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle as shown between time points 4 through 7 may occur. Circuit Breaker Timing In Figure 14a, the TIMER capacitor charges at 230µA if the SENSE pin exceeds VCB but VDRN is less than 5V. If the SENSE pin drops below VCB before TIMER reaches the
5.8µA 5.8µA VIN – VGATEH
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 VOVHI UV/OV VUVHI VTMRH TIMER 5.8µA VTMRL 58µA GATE VGATEL SS 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL 58µA 230µA + 8 • IDRN 2 3 VOVLO 4 5 67 8 10 12 9 11
PWRGD INITIAL TIMING GATE START-UP
4252-1/2 F12
Figure 12. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 VOVHI 2 34 5 67 8 9
OV
VOVLO VTMRH
TIMER
230µA + 8 • IDRN 58µA
GATE
VGATEL
58µA
SS
20 • (VCB + VOS) 20 • VOS VACL VCB GATE START-UP
4252-1/2 F13
SENSE
Figure 13. Overvoltage Timing (All Waveforms are Referenced to VEE)
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5.8µA 5.8µA VIN – VGATEH
5.8µA 5.8µA VIN – VGATEH 20 • (VACL + VOS)
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
1 VTMRH TIMER 5.8µA 230µA + 8 • IDRN 2
GATE
SS VACL SENSE VCB
VOUT
DRAIN
PWRGD CB FAULT
(14a) Momentary Circuit-Breaker Fault
(14b) Circuit-Breaker Time Out
Figure 14. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to VEE)
VTMRH threshold, TIMER is discharged by 5.8µA. In Figure 14b, when TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. In Figure 14c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH. GATE pull down follows and the LTC4252 shuts down. During shutdown, the LTC4252-1 latches TIMER high with a 5.8µA pull-up current source; the LTC4252-2 activates a shutdown cooling cycle. Resetting a Fault Latch (LTC4252-1) The latched circuit breaker fault of LTC4252-1 benefits from long cooling time. It is reset by pulling the UV pin below VUVLO with a switch. Reset is also accomplished by pulling the VIN pin momentarily below (VLKO – VLKH). A third reset method involves pulling the TIMER pin below VTMRL as shown in Figure 15. An initial timing cycle is skipped if TIMER is used for reset. An initial timing cycle is generated if reset by the UV pin or the VIN pin. The duration of the TIMER reset pulse should be smaller than the time taken to reach 0.2V at SS pin. With a single
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CB TIMES OUT 1 VTMRH TIMER 230µA + 8 • IDRN 2 VTMRH TIMER 1 2 5.8µA 3 CB TIMES OUT 4 230µA + 8 • IDRN 230µA + 8 • IDRN GATE GATE SS VACL SENSE VCB SENSE SS VACL VCB VOUT VDRNCL DRAIN DRAIN VOUT VDRNCL PWRGD CB FAULT PWRGD CB FAULT CB FAULT
4252-1/2 F14
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(14c) Multiple Circuit-Breaker Fault
pole mechanical pushbutton switch, this may not be feasible. A double pole, single throw pushbutton switch removes this restriction by connecting the second switch to the SS pin. With this method, both the SS and TIMER pins are released at the same time (see Figure 24). Shutdown Cooling Cycle (LTC4252-2) Figure 16 shows the timer behavior of the LTC4252-2. At time point 2, TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. TIMER starts a shutdown cooling cycle by discharging TIMER with 5.8µA to the VTMRL threshold. TIMER then charges with 5.8µA to the VTMRH threshold. There are four 5.8µA discharge phases and three 5.8µA charge phases in this shutdown cooling cycle spanning time points 2 and 3. At time point 3, the LTC4252 automatic retry occurs with a start-up cycle. Good thermal management techniques are highly recommended; power and thermal dissipation must be carefully evaluated when implementing the automatic retry scheme.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
1 SWITCH RESETS LATCHED TIMER SWITCH RELEASES SS 2 34 5 67 8 9 5.8µA
5.8µA TIMER
VTMRH 230µA + 8 • IDRN VTMRL 58µA 58µA
GATE VGATEL SS
20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL
SENSE
DRAIN
PWRGD GATE START-UP MOMENTARY DPST SWITCH RESET
4252-1/2 F15
Figure 15. Pushbutton Reset of LTC4252-1’s Latched Fault (All Waveforms are Referenced to VEE)
CIRCUIT BREAKER TIMES OUT 1 230µA + 8 • IDRN TIMER 2 5.8µA 5.8µA VTMRL 5.8µA 5.8µA 5.8µA 5.8µA
GATE
SS
SENSE
VOUT VDRNCL DRAIN VDRNL
PWRGD SHUTDOWN COOLING CB FAULT GATE START-UP
4252-1/2 F16
Figure 16. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms are Referenced to VEE)
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5.8µA VIN – VGATEH VCB VDRNCL VDRNL
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RETRY 3 45 6 78 9 10 5.8µA
VTMRH 230µA + 8 • IDRN 5.8µA 58µA 58µA VGATEL
5.8µA
VIN – VGATEH
20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL VCB
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit In Figure 17a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 17b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier establishes control. If the severe fault causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows into the DRAIN pin and is multiplied by 8. This extra current is added to the TIMER pull-up current of 230µA. This accelerated TIMER current of [230µA+8 • IDRN] produces a shorter circuit breaker fault delay. Careful selection of CT, RD and MOSFET can help prevent SOA damage in a low impedance fault condition. Soft-Start If the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 180µs (or 0V to 1.4V in 230µs for the LTC4252A) at GATE start-up, as
12 230µA + 8 • IDRN TIMER
34 VTMRH 5.8µA 5.8µA VTMRH 230µA + 8 • IDRN TIMER
GATE
SS VACL SENSE VCB
VOUT
DRAIN
PWRGD
(17a) Analog Current Limit Fault
Figure 17. Current Limit Behavior (All Waveforms are Referenced to VEE)
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shown in Figure 18a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified from a linear ramp to an RC response (Equation 6), as shown in Figure 18b. This feature allows load current to slowly ramp-up at GATE start-up. Soft-start is initiated at time point 3 by a TIMER transition from VTMRH to VTMRL (time points 1 to 2) or by the OV pin falling below the VOVLO threshold after an OV condition. When the SS pin is below 0.2V, the analog current limit amplifier holds GATE low. Above 0.2V, GATE is released and 58µA ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET’s threshold, the MOSFET begins to conduct. Due to the MOSFET’s high gm, the MOSFET current quickly reaches the soft-start control value of VACL(t) (Equation 7). At time point 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB, at time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load
CB TIMES OUT 1 2 GATE SS SENSE VFCL VACL VCB VOUT VDRNCL DRAIN
4252-1/2 F17
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PWRGD
(17b) Fast Current Limit Fault
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
END OF INTIAL TIMING CYCLE 12 34 567 TIMER 7a 89 10 11 TIMER VTMRH 230µA + 8 • IDRN VTMRL 58µA GATE 58µA 20 • (VACL + VOS) SS 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL DRAIN SENSE SS 20 • VOS VACL VCB VDRNCL VDRNL VGS(th) VIN – VGATEH
5.8µA
PWRGD
(18a) Without External CSS
Figure 18. Soft-Start Timing (All Waveforms are Referenced to VEE)
current begins to decline below VACL(t). The current limit loop shuts off and GATE releases at time point 8. At time point 9, the SENSE voltage falls below VCB and TIMER deactivates. Large values of CSS can cause premature circuit breaker time out as VACL(t) may exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of large CSS values is SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER. Power Limit Circuit Breaker Figure 19 shows the LTC4252A-1 in a power limit circuit breaking application. The SENSE pin is modulated by the board supply voltage, VSUPPLY. The zener voltage, VZ is set to be the same as the low supply operating voltage, VSUPPLY(MIN) = 43V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 71V giving the same power at VSUPPLY(MIN), then resistors R4 and R6 are selected using the ratio:
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END OF INTIAL TIMING CYCLE 12 3 4 5 6 7 89 10 11 VTMRH 230µA + 8 • IDRN VTMRL 58µA GATE VGS(th) 58µA 20 • (VACL + VOS) 20 • (VCB + VOS) VIN – VGATEH 5.8µA PWRGD
4252-1/2 F18
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(18b) With External CSS
R6 VCB = R4 VSUPPLY(MAX)
(16)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power limit is:
POWERMAX
(VSUPPLY(MIN) + VSUPPLY(MAX) )2 =
4 • VSUPPLY(MIN) • VSUPPLY(MAX) • POWERSUPPLY(MIN) = 1.064 • POWERSUPPLY(MIN)
(17)
when VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 57V. The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is: POWERFAULT = VSUPPLY ⎛ R6 ⎞ • ⎜ VACL – (VSUPPLY – VZ ) • ⎟ ⎝ RS R4 ⎠ (18)
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
GND RIN 3× 1.8k 1/4W EACH CIN 1µF D1 BZV85C43 2 7 6 4 R6 27Ω RC 10Ω CC 10nF RD 1M Q1 IRF530S RS 0.02Ω R4 38.3k
GND (SHORT PIN)
R1 390k 1%
9 8 10
R2 30.1k 1%
3 CT SS 0.68µF C1 10nF CSS 68nF
–48V *FMMT493
Figure 19. Power Limit Circuit Breaking Application
Circuit Breaker with Foldback Current Limit Figure 20 shows the LTC4252A in a foldback current limit application. When VOUT is shorted to the –48V RTN supply, current flows through resistors R4 and R5. This results in a voltage drop across R5 and a corresponding reduction in voltage drop across the sense resistor, RS, as the ACL amplifier servos the sense voltage between the SENSE and VEE pins to about 60mV. The short-circuit current through RS reduces as the VOUT voltage increases during an output short-circuit condition. Without foldback current limiting resistor R5, the current is limited to 3A during analog current limit. With R5, the short-circuit current is limited to 0.5A when VOUT is shorted to 71V. Inrush Control Without a Sense Resistor During Power-Up Figure 21 shows the LTC4252A in an application where the inrush current is controlled without a sense resistor during power-up. This setup is suitable only for applications that don’t require short-circut protection from the LTC4252A. Resistor R4 and capacitor C2 act as a feedback network to accurately control the inrush current. The C2 capacitor can be calculated with the following equation:
IGATE • CL (19) IINRUSH where IGATE = 58µA and CL is the total load capacitance. C2 =
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+
CL 100µF 1 VIN LTC4252A-1 UV OV TIMER VEE 5 PWRGD DRAIN GATE SENSE R5 100k * VOUT LOAD EN
4252-1/2 F19
W
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Capacitor C3 and resistor R4 prevent Q1 from momentarily turning on when the power pins first make contact. Without C3 and R4, capacitor C2 pulls the gate of Q1 up to a voltage roughly equal to VEE • C2/CGS(Q1) before the LTC4252A powers up. By placing capacitor C3 in parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R4, the problem is solved. The value of C3 is given by:
C3 =
VSUPPLY(MAX) • C2 + CGD(Q1) VGS(TH),Q1
(
)
(20)
C3 ≈ 35 • C2 for VSUPPLY(MAX) = 71V where VGS(TH),Q1 is the MOSFET’s minimum gate threshold and VSUPPLY(MAX) is the maximum operating input voltage. Diode-ORing Figure 22 shows the LTC4252 used as diode-oring with Hot Swap capability in a dual – 48V power supply application. The conventional diode-OR method uses two high power diodes and heat sinks to contain the large heat dissipation of the diodes. With the LTC4252 controlling the external FETs Q2 and Q3 in a diode-OR manner, the small turn-on voltage across the fully enhanced Q2 and Q3 reduces the power dissipation significantly.
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
–48V RTN (LONG PIN)
–48V RTN (SHORT PIN)
R1 390k 1%
8 9 C1 10nF
OV UV
R2 30.1k 1%
TIMER 3 CT SS 0.68µF CSS 68nF
10
–48V
*MOC207
Figure 20. Circuit Breaker with Foldback Current Limit Application
–48V RTN (LONG PIN)
–48V RTN (SHORT PIN)
R1 390k 1%
8 9 C1 10nF
OV UV
R2 30.1k 1% –48V *MOC207
10 TIMER 3 CT SS 0.68µF CSS 68nF
Figure 21. Inrush Control Without a Sense Resistor Application
At power-up, Q5 and Q8 are held off low by the SS pin of the LTC4252; resistors R5 and R8 pull the SENSE pin closed to VEE. VEE is connected to the power supply with lower voltage through the body diodes Q2 or Q3 until Q2 or Q3 is turned on. This allows the LTC4252 to perform a start-up cycle and ramp up the SS and GATE voltage. As the SS voltage ramps up to 2.2V, it turns on Q5 and Q8 and pulls TIMER low through Q6 and Q9. The sense voltage rises as current flows into R5 and R8 through
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RIN 3× 1.8k 1/4W EACH CIN 1µ F R3 5.1k * 2 7 RD 1 M R4 38.3k R5 27Ω RC 10Ω CC 10nF VOUT
W
U
U
+
CL 100µF
LOAD EN
1 VIN LTC4252A-1 PWRGD DRAIN
GATE VEE 5 SENSE
6 4
Q1 IRF530S RS 0.02Ω
4252-1/2 F20
RIN 3× 1.8k 1/4W EACH CIN 1µ F R3 5.1k * 2 7 RD 1 M C2 10nF 100V R4 1k 1% VOUT
+
CL 100µF
LOAD EN
1 VIN LTC4252A-1 PWRGD DRAIN
GATE VEE 5 SENSE
6 4 C3 330nF 25V
Q1 IRF530S
4252-1/2 F21
resistors R3 and R6. The ACL amplifier of the LTC4252 servos the sense voltage to about 100mV as the GATE voltage regulates Q2 and Q3. Current flows into R4, Q4 and R7, Q7 as Q2 and Q3 turn on. The respective node voltages at the R3 and R4 connection and the R6 and R7 connection are always kept equal to their respective sense voltages by the Q4 and Q2 VDS drop and the Q7 and Q3 VDS drop assuming the Q5 and Q8 VDS drop is negligible.
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31
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
–48V RTN
Hot Swap SECTION RIN1 3× 1.8k IN SERIES 1/4W EACH R1 420k C1 10nF R2 32.4k 1 7 8 CT 0.33µF 2 UV/OV VIN DRAIN 6 5 RC1 10Ω CC1 22nF CIN 1µF RD 1M
DIODE-OR CIRCUIT FOR CHANNEL A –48V A RIN2 3× 1.8k IN SERIES 1/4W EACH 1 7 DRAIN UV 2 PWRGD LTC4252-2 4 10 SENSE TIMER 3 SS 6 8 GATE OV VEE 5 9 VIN R3 12k Q5 FDV301N R4 150Ω Q4 BSS131 R5 560Ω RC2 10Ω CC2 22nF Q2 IRF530S
CIN2 1µF Q6 FDV301N
DIODE-OR CIRCUIT FOR CHANNEL B –48V B RIN3 3× 1.8k IN SERIES 1/4W EACH 1 7 DRAIN UV PWRGD LTC4252-2 4 10 TIMER SENSE 3 SS 6 8 GATE OV VEE 2 5 9 VIN R6 12k Q8 FDV301N R7 150Ω Q7 BSS131 R8 560Ω RC3 10Ω CC3 22nF Q3 IRF530S
CIN3 1µF Q9 FDV301N
Figure 22. –48V/2.5A Diode-OR Application
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LOAD MODULE GATE TIMER LTC4252-1 Q1 IRF530S SS CSS 68nF VEE SENSE 4 3 RS 0.02Ω
4252-1/2 F22
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
APPLICATIO S I FOR ATIO
The internal fault latches of the LTC4252 are disabled as the TIMER pin is always held low by the SS voltage when Q2 and Q3 are in analog current limit. If both power supplies from channel A and B are exactly equal, then equal load current will flow through Q2 and Q3 to the load module via the Hot Swap section. If the channel A supply is greater than the channel B by more than 100mV, the sense voltage will rise above the fast comparator trip threshold of 200mV, the GATE will be pulled low and Q2 is turned off. The GATE ramps up and regulates Q2 when the channel A supply is equal to the channel B supply. Likewise, if the channel B supply is greater than channel A by more than 100mV, it trips the fast comparator and GATE is pulled low and Q3 is turned off. The GATE ramps up and regulates Q3 when the channel B supply is equal to the channel A supply. Resistors R4, R7 and external FETs Q4 and Q7 limit the current flow into Q5 and Q8 during their respective supply source short. When the channel A supply is shorted to the – 48V RTN (or GND), large current flows into Q4 momentarily and creates a voltage drop across R4, which in turn reduces the gate-to-source voltage of Q4, limiting the
–48V RTN (LONG PIN)
RIN 3× 1.8k 1/4W CIN 1µF R3 5.1k * 2 7 RD 1M VIN C2 LUCENT 0.1µF 100V FLTR100V10 VIN
– +
–48V RTN (SHORT PIN)
1 R1 390k 1% VIN
LTC4252A-1 8 9 C1 10nF OV UV PWRGD DRAIN
10
TIMER VEE 5
GATE SENSE
6 4
R2 30.1k 1%
3 CT SS 0.68µF CSS 68nF
RC 10Ω CC 10nF
–48V
Figure 23. Typical Application Using a Filter Module
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current flow. The sense voltage is lifted up and causes the fast comparator of LTC4252 to trip and pull the GATE low instantly. The channel A supply short will not cause Q3 of channel B diode-OR circuit to turn off. Similarly, when the channel B supply is shorted to the – 48V RTN (or GND), large current flows into Q7 momentarily and creates a voltage drop across R7, which in turn reduces the gate-to-source voltage of Q7, thus limiting the current flow. The increase in sense voltage will trip the fast comparator of LTC4252 and pull the GATE low instantly. The channel B supply short will not cause Q2 of channel A diode-OR circuit to turn off. The load short at the output of Q1 is protected by the Hot Swap section. Using an EMI Filter Module Many applications place an EMI filter module in the power path to prevent switching noise of the module from being injected back onto the power supply. A typical application using the Lucent FLTR100V10 filter module is shown in Figure 23. When using a filter, an optoisolator is required to prevent common mode transients from destroying the PWRGD and ON/OFF pins.
1 VIN+ VOUT+ SENSE 2 ON/OFF LUCENT JW050A1-E C3 0.1µF 100V 9 5V
+8
W
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TRIM
7
+
VOUT+
C6 100µF 16V
+
Q1 IRF530S RS 0.02Ω
1N4003
C4 100µF 100V
VOUT–
C5 0.1µF 100V 4
SENSE– VIN– VOUT 3
6
–5
CASE
CASE
4252-1/2 F20
*MOC207
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33
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.42 ± 0.038 (.0165 ± .0015) TYP
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A” 0° – 6° TYP
4.90 ± 0.152 (.193 ± .006)
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.127 ± 0.076 (.005 ± .003)
MSOP (MS8) 0204
0.65 (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
34
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MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127 (.035 ± .005) 3.20 – 3.45 (.126 – .136) 0.65 (.0256) BSC
3.00 ± 0.102 (.118 ± .004) (NOTE 3) 8 7 65 0.52 (.0205) REF 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.53 ± 0.152 (.021 ± .006) DETAIL “A”
1 23 4
1.10 (.043) MAX
0.86 (.034) REF
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LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
PACKAGE DESCRIPTIO U
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127 (.035 ± .005) 3.20 – 3.45 (.126 – .136)
3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF
DETAIL “A” 0° – 6° TYP
5.23 (.206) MIN
0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
4.90 ± 0.152 (.193 ± .006)
3.00 ± 0.102 (.118 ± .004) (NOTE 4)
12345 0.53 ± 0.152 (.021 ± .006)
DETAIL “A” 0.18 (.007) SEATING PLANE
1.10 (.043) MAX
0.86 (.034) REF
0.50 (.0197) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27 (.007 – .011) TYP
0.127 ± 0.076 (.005 ± .003)
MSOP (MS) 0603
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2
TYPICAL APPLICATIO
GND
GND (SHORT PIN)
R1 402k 1% R2 32.4k 1% C1 10nF
–48V
RELATED PARTS
PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1642 LTC4214 LTC4220 LT4250 LTC4251/LTC4251-1 LTC4253 DESCRIPTION Negative High Voltage Hot Swap Controllers in SO-8 Positive High Voltage Hot Swap Controllers in SO-8 Fault Protected Hot Swap Controller Negative Voltage Hot Swap Controller Dual Supply Hot Swap Controller – 48V Hot Swap Controller in SO-8 – 48V Hot Swap Controllers in SOT-23 –48V Hot Swap Controller with Sequencer COMMENTS Negative High Voltage Supplies from –10V to – 80V Supplies from 9V to 80V, Latched Off/Autoretry 3V to 16.5V, Overvoltage Protection up to 33V Operates from –6V to –16V ±2.2V to ± 16.5V Operation Active Current Limiting, Supplies from – 20V to – 80V Fast Active Current Limiting, Supplies from –15V Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies from –15V
36
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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RIN 2× 5.1k IN SERIES 1/4W EACH 1 VIN LTC4252-1 7 8 CT 150nF PUSH RESET 2 UV/OV TIMER SS CSS 27nF VEE 4 DRAIN GATE SENSE 6 5 3 R3 22Ω RC 10Ω CC 22nF CIN 1µF RD 1M CL 100µF
+
LOAD
VOUT
Q1 IRF540S RS 0.01Ω
4252-1/2 F24
Figure 24. – 48V/5A Application
425212fb LT 0406 REV B • PRINTED IN USA
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