LTC4259ACGW-1

FEATURES ■ ■ LTC4259A-1 Quad IEEE 802.3af Power over Ethernet Controller with AC Disconnect DESCRIPTIO The LTC®4259A-1 is a quad –48V Hot SwapTM controller designed for use in IEEE 802.3af compliant Power Sourcing Equipment (PSE). It consists of four independent ports, each with output current limit, short-circuit protection, complete Powered Device (PD) detection and classification capability, and programmable PD disconnect using AC or DC sensing. Used with power MOSFETs and passives as in Figure 1, the LTC4259A-1 can implement a complete IEEE 802.3af-compliant PSE. The LTC4259A-1 can operate autonomously or be controlled by an I2C serial interface. Up to 16 LTC4259A-1s may coexist on the same data bus, allowing up to 64 powered Ethernet ports to be controlled with only two digital lines. Fault conditions are optionally signaled with a programmable INT pin to eliminate software polling. External power MOSFETs, current sense resistors and diodes allow easy scaling of current and power dissipation levels and provide protection against voltage and current spikes and ESD events. Linear Technology also provides solutions for 802.3af PD applications with the LTC4257, LTC4257-1 and LTC4267. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ ■ ■ ■ ■ Controls Four Independent – 48V Powered Ethernet Ports Each LTC4259A-1 Port Includes: – IEEE 802®.3af Compliant PD Detection and Classification – Output Current Limit with Foldback – Short-Circuit Protection with Fast Gate Pull-Down – PD Disconnect Using AC or DC Sensing – Improved AC Disconnect – Improved UVLO Operates Autonomously or Controlled by I2CTM Serial Interface 4-Bit Programmable Digital Address Allows Control of Up to 64 Ports Current and Duty Cycle Limits Protect External FETs IMPROVED UVLO Available in a 36-pin SSOP package. APPLICATIO S ■ ■ ■ IEEE 802.3af Compliant Endpoint and Midspan Power Sources IP Phone Systems DTE Power Distribution TYPICAL APPLICATIO INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 3.3V 0.1µF 0.1µF 100V X7R SHDN1 SHDN2 SHDN3 SHDN4 VDD OSCIN AUTO BYP RESET DETECT1 DETECT2 DETECT3 DETECT4 LTC4259A-1 CMPD3003 ×4 1k ×4 0.47µF 100V × 4 X7R DGND AGND VEE SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4 RS1 –48V 0.1µF Q1 10k RS2 10k 10k 10k Q2 RS3 PORT3 Q3 RS4 Q4 PORT4 S1B × 4 4259A F01 RS1 TO RS4: 0.5Ω Q1 TO Q4: IRFM120A Figure 1. Complete 4-Port Powered Ethernet Power Source 4259a1fa U U U 0.1µF 100V ×4 SMAJ58A ×4 PORT1 PORT2 1 LTC4259A-1 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW RESET BYP INT SCL SDAOUT SDAIN AD3 AD2 AD1 1 2 3 4 5 6 7 8 9 36 OSCIN 35 AUTO 34 OUT1 33 GATE1 32 SENSE1 31 OUT2 30 GATE2 29 SENSE2 28 VEE 27 OUT3 26 GATE3 25 SENSE3 24 OUT4 23 GATE4 22 SENSE4 21 AGND 20 SHDN4 19 SHDN3 Supply Voltages VDD to DGND .......................................... – 0.3V to 5V VEE to AGND ......................................... 0.3V to – 70V DGND to AGND (Note 2) .................................... ±1V Digital Pins SCL, SDAIN, SDAOUT, INT, AUTO, RESET SHDNn, ADn ................. DGND – 0.3V to DGND + 5V Analog Pins GATEn (Note 3) ................... VEE – 0.3V to VEE + 12V DETECTn Peak Currents (Note 4) .................. ±80mA SENSEn ................................. VEE – 0.3V to VEE + 1V OUTn .................................... VEE – 70V to VEE + 70V OSCIN .......................... DGND – 0.3V to DGND + 5V BYP Current .................................................... ±1mA Operating Ambient Temperature Range LTC4259AC-1 .......................................... 0°C to 70°C LTC4259AI-1 ........................................ –40°C – 85°C Junction Temperature (Note 5) ............................ 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC4259ACGW-1 LTC4259AIGW-1 AD0 10 DETECT1 11 DETECT2 12 DETECT3 13 DETECT4 14 DGND 15 VDD 16 SHDN1 17 SHDN2 18 GW PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 80°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = – 48V unless otherwise noted (Note 6). SYMBOL PARAMETER Power Supplies VDD VDD Supply Voltage VEE VEE Supply Voltage IDD VDD Supply Current IEE VEE Supply Current VDDMIN VEEMINON VEEMINOFF Detection IDET VDD UVLO Voltage VEE UVLO Voltage (Turning On) VEE UVLO Voltage (Turning Off) Detection Current CONDITIONS ● ELECTRICAL CHARACTERISTICS MIN 3 –48 TYP 3.3 2.5 –2 2.7 –31 –28 MAX 4 –57 5 –5 100 UNITS V V mA mA mA V V V µA µA V kΩ kΩ V mA 4259a1fa To Maintain IEEE Compliant Output (Note 7) Normal Operation Classification Into a Short (VDETECTn = 0V) (Note 8) VEE – AGND VEE – AGND First Point, VDETECTn = – 10V Second Point, VDETECTn = – 3.5V Open Circuit, Measured at DETECTn Pin ● ● ● ● ● ● ● ● ● 235 145 15.2 26.7 –16.4 55 –20 17 29 VDET Detection Voltage Compliance RDETMIN Minimum Valid Signature Resistance RDETMAX Maximum Valid Signature Resistance Classification VCLASS Classification Voltage ICLASS Classification Current Compliance 300 190 –23 19 33 –21 75 0mA < ICLASS < 31mA Into Short (VDETECT = 0V) ● ● 2 U W U U WW W LTC4259A-1 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = – 48V unless otherwise noted (Note 6). SYMBOL ITCLASS PARAMETER Classification Threshold Current CONDITIONS Class 0-1 Class 1-2 Class 2-3 Class 3-4 Class 4-Overcurrent Gate On, VGATEn = VEE Gate Off, VGATEn = VEE + 5V VGATEn = VEE + 1V IGATEn = – 1µA (Note 3) VOUTn – VEE 0V > VOUTn > –10V –10V > VOUTn > –30V VOUTn = –48V VSENSEn – VEE, VOUTn = VEE (Note 9) VSENSEn – VEE, VOUTn = VEE VSENSEn – VEE, VOUTn = AGND – 30V VSENSEn – VEE, VOUTn = AGND – 10V VSENSEn – VEE VSENSEn = VEE 0.1V < VOSCIN < 3V, fOSCIN < 200Hz Port Powered, PD Not Present Port Powered, PD Not Present Port Powered, –6V < VDETECTn < 0V Port Powered, VDETECTn = – 3.4V (C grade) (I grade) ISDAOUT = 3mA, IINT = 3mA ISDAOUT = 5mA, IINT = 5mA SCL, SDAIN, RESET, SHDNn, AUTO, ADn SCL, SDAIN, RESET, SHDNn, AUTO, ADn ADn, RESET, SHDNn AUTO From Detect Command or Application of PD to Port to Detect Complete Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual Mode (Figure 2) (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = IGON (Note 10) ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN 5.5 13 21 31 45 –20 30 10 1 TYP 6.5 14.5 23 33 48 –50 50 13 2 MAX 7.5 16 25 35 51 –70 300 15 3 –6 –18 UNITS mA mA mA mA mA µA µA mA V V µA µA µA mV mV mV mV mV mV µA kΩ V/V V/V µA µA Gate Driver IGON GATE Pin Current IGOFF GATE Pin Current IGPD GATE Pin Short-Circuit Pull-Down ∆VGATE External Gate Voltage (VGATEn – VEE) Output Voltage Sense VPG Power Good Threshold Voltage IVOUT Out Pin Bias Current –20 166 201 201 30.2 2.52 187.5 212.5 199 224 224 4.97 Current Sense VCUT Overcurrent Detection Sense Voltage VLIM Current Limit Sense Voltage VMIN DC Disconnect Sense Voltage VSC Short-Circuit Sense Voltage ISENSE SENSE Pin Bias Current AC Disconnect (Note 10) ROSCIN Input Impedance of OSCIN Pin AVACD Voltage Gain OSCIN to DETECT1, 2 Voltage Gain OSCIN to DETECT3, 4 IACDMAX AC Disconnect DETECTn Output Current IACDMIN Remain Connected DETECT Pin Current Digital Interface VOLD Digital Output Low Voltage VILD Digital Input Low Voltage VIHD Digital Input High Voltage RPU Pull-Up Resistor to VDD RPD Pull-Down Resistor to DGND AC Characteristics tDETDLY Detection Delay tDET tCLSDLY Detection Duration Classification Delay 3.75 275 –50 500 –3 3 230 230 200 –2.7 2.7 190 180 –3.3 3.3 ±600 260 260 0.4 0.7 0.8 2.4 50 50 V V V V kΩ kΩ ms ms ms ms ms ms ms 4259a1fa ● ● ● ● ● ● ● 170 170 10.1 10.1 10.1 590 230 52 420 13 130 1 tCLASS tPON Classification Duration Power On Delay, Auto Mode 3 LTC4259A-1 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = – 48V unless otherwise noted (Note 6). SYMBOL tSTART PARAMETER Maximum Current Limit Duration During Port Start-Up CONDITIONS tSTART1 = 0, tSTART0 = 0 (Figure 3) tSTART1 = 0, tSTART0 = 1 (Figure 3) tSTART1 = 1, tSTART0 = 0 (Figure 3) tSTART1 = 1, tSTART0 = 1 (Figure 3) tICUT1 = 0, tICUT0 = 0 (Figure 3) tICUT1 = 0, tICUT0 = 1 (Figure 3) tICUT1 = 1, tICUT0 = 0 (Figure 3) tICUT1 = 1, tICUT0 = 1 (Figure 3) Reg16h = 00h tDIS1 = 0, tDIS0 = 0 (Figures 4, 5) tDIS1 = 0, tDIS0 = 1 (Figures 4, 5) tDIS1 = 1, tDIS0 = 0 (Figures 4, 5) tDIS1 = 1, tDIS0 = 1 (Figures 4, 5) VSENSEn – VEE > 5mV, VOUTn = – 48V (Figure 4) (Note 11) (Note 11) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) (Notes 11, 12, 13) (Notes 11, 12, 13) (Notes 11, 12) ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS tICUT Maximum Current Limit Duration After Port Start-Up DCCLMAX tDIS Maximum Current Limit Duty Cycle Disconnect Delay MIN 50 25 100 200 50 25 100 200 5.8 300 75 150 600 tVMIN I2C Timing fSCLK t1 t2 t3 t4 t5 t6 t7 t8 tr tf tFLTINT tSTOPINT tARAINT DC Disconnect Minimum Pulse Width Sensitivity Clock Frequency Bus Free Time Start Hold Time SCL Low Time SCL High Time Data Hold Time Data Set-Up Time Start Set-Up Time Stop Set-Up Time SCL, SDAIN Rise Time SCL, SDAIN Fall Time Fault Present to INT Pin Low Stop Condition to INT Pin Low ARA to INT Pin High Time TYP 60 30 120 240 60 30 120 240 6.3 360 90 180 720 0.02 MAX 70 35 140 280 70 35 140 280 6.7 400 100 200 800 1 UNITS ms ms ms ms ms ms ms ms % ms ms ms ms ms ● ● ● ● ● ● ● ● ● ● ● ● ● ● 400 1.3 600 1.3 600 150 200 600 600 20 20 20 60 20 300 150 150 200 300 kHz µs ns µs ns ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: DGND and AGND should be tied together in normal operation. Note 3: An internal clamp limits the GATE pins to a minimum of 12V above VEE. Driving this pin beyond the clamp may damage the part. Note 4: When a port powers on or off, the transient voltage on the port couples through CDET (Figure 18). The LTC4259A-1 contains internal protection circuitry to withstand transient currents of up to 80mA for 5ms. As long as the absolute value of the current remains below 80mA, the LTC4259A-1 will keep the voltage at the DETECTn pin within the absolute maximum voltage range. A properly sized RDET should limit the current to less than 60mA. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground (AGND and DGND) unless otherwise specified. Note 7: The LTC4259A-1 is designed to maintain a port voltage of –46.6V to –57V. The VEE supply voltage range accounts for the drop across the diode, MOSFET and sense resistor. Note 8: VEE supply current, while classifying a short, is measured indirectly by measuring the DETECTn pin current while classifying a short. Note 9: The LTC4259A-1 implements overload current detection per IEEE 802.3af. The minimum overload current (ICUT) is dependent on port voltage; ICUT_MIN = 15.4W/VPORT_MIN. An IEEE compliant system using the LTC4259A-1 should maintain port voltage above –46.6V. Note 10: Unless otherwise specified, AC disconnect specifications require the following conditions: the DETECT pin is connected to the port as shown in Figure 1, a valid sine wave is applied to OSCIN, the OSCFAIL bit is cleared and the AC Disconnect Enable bits are set. Note 11: Guaranteed by design, not subject to test. Note 12: Values measured at VILD and VIHD. Note 13: If fault occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. 4259a1fa 4 LTC4259A-1 TYPICAL PERFOR A CE CHARACTERISTICS Power On Sequence in Auto Mode PORT 1 VDD = 3.3V VEE = – 48V GND POWER ON PORT VOLTAGE 20V/DIV VEE VEE GATE +14V VOLTAGE 10V/DIV VEE PORT CURRENT 0mA 500mA/DIV GND PORT VOLTAGE 10V/DIV DETECTION DETECTION PHASE 1 PHASE 2 CLASSIFICATION VEE Current Limit Foldback 225 200 175 450 400 2.0 1.8 PULL-DOWN VOLTAGE (V) VSENSEn (mV) 150 125 100 75 50 25 VDD = 3.3V VEE = – 48V TA = 25°C –40 –32 –24 –16 –8 0 4259 G03 0 –48 VOUTn-AGND (V) Classification Transient Response to 40mA Load Step PORT VOLTAGE 1V/DIV –18V VDD = 3.3V VEE = – 48V TA = 25°C CLASSIFICATION VOLTAGE (V) –6 –8 –10 –12 –14 –16 –18 PORT VOLTAGE WITH TYPICAL CMPD3003 DETECTn PIN VOLTAGE 0 10 20 30 40 50 60 CLASSIFICATION CURRENT (mA) 70 SUPPLY CURRENT (mA) 40mA PORT CURRENT 20mA/DIV 0mA 50µs/DIV 4258 G05 UW 50ms/DIV Powering On a 180µF Load VDD = 3.3V VEE = – 48V FET ON LOAD FULLY CHARGED FOLDBACK 425mA CURRENT LIMIT 5ms/DIV 4259 G01 4259 G02 INT and SDAOUT Pull Down Voltage vs Load Current VDD = 3.3V TA = 25°C ILIMIT WITH RSENSE = 0.5Ω (mA) 350 300 250 200 150 100 50 0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 15 20 10 LOAD CURRENT (mA) 25 4259 G04 Classification Current Compliance 0 VDD = 3.3V –2 VEE = – 48V T = 25°C –4 A 3.0 2.5 2.0 1.5 1.0 0.5 VEE DC Supply Current vs Supply Voltage VDD = 3.3V REG 12h = 00h –50 –40 –30 –20 –10 VEE SUPPLY VOLTAGE (V) 0 –20 0 –70 –60 4258 G06 4258 G07 4259a1fa 5 LTC4259A-1 TEST TI I G PD INSERTED VPORTn 0V tDET VSENSEn TO VEE INT tVMIN tDIS 4259A F04 6 UW VCLASS VT VGATEn INT VEE PORT TURN ON (AUTO MODE) tCLSDLY tDETDLY tPON tCLASS 4259A F02 Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes VLIM VSENSEn TO VEE 0V VCUT tSTART, tICUT INT 4259A F03 Figure 3. Current Limit Timing VOSCIN VOUTn VMIN IACDMIN IDETECTn PD REMOVED INT tDIS 4259A F05 Figure 4. DC Disconnect Timing Figure 5. AC Disconnect Timing t3 t4 SCL t2 SDA t1 t5 tr tf t6 t7 t8 4259A F06 Figure 6. I2C Interface Timing 4259a1fa LTC4259A-1 TI I G DIAGRA S SCL SDA 0 1 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE W 0 SCL SDA UW AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK BY SLAVE ACK BY SLAVE FRAME 3 DATA BYTE ACK BY SLAVE STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 4259A F07 Figure 7. Writing to a Register A6 A5 A4 A3 A2 A1 A0 ACK 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK BY SLAVE ACK BY SLAVE REPEATED START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 4259A F08 Figure 8. Reading from a Register 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER 4259A F09 Figure 9. Reading the Interrupt Register (Short Form) SCL SDA 0 0 0 1 1 0 0 R/W ACK 0 1 0 AD3 AD2 AD1 AD0 1 ACK START BY MASTER FRAME 1 ALERT RESPONSE ADDRESS BYTE ACK BY SLAVE NO ACK BY MASTER STOP BY MASTER 4259A F10 FRAME 2 SERIAL BUS ADDRESS BYTE Figure 10. Reading from Alert Response Address 4259a1fa 7 LTC4259A-1 PI FU CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259A-1 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4259A-1 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1µs wide from resetting the LTC4259A-1. Pull RESET high with ≤ 10k or tie to VDD. BYP (Pin 2): Bypass Output. The BYP pin is used to connect the internally generated – 20V supply to an external 0.1µF bypass capacitor. Use a 100V rated 0.1µF, X7R capacitor. Do not connect the BYP pin to any other external circuitry. INT (Pin 3): Interrupt Output, Open Drain. INT will pull low when any one of several events occur in the LTC4259A-1. It will return to a high impedance state when bits 6 or 7 are set in the Reset PB register (1Ah). The INT signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. Individual INT events can be disabled using the Int Mask register (01h). See Register Functions and Applications Information for more information. The INT pin is only updated between I2C transactions. SCL (Pin 4): Serial Clock Input. High impedance clock input for the I2C serial interface bus. The SCL pin should be connected directly to the I2C SCL bus line. SDAOUT (Pin 5): Serial Data Output, Open Drain Data Output for the I2C Serial Interface Bus. The LTC4259A-1 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See Applications Information for more information. SDAIN (Pin 6): Serial Data Input. High impedance data input for the I2C serial interface bus. The LTC4259A-1 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See Applications Information for more information. AD3 (Pin 7): Address Bit 3. Tie the address pins high or low to set the I2C serial address to which the LTC4259A-1 responds. This address will be (010A3A2A1A0)b. Pull AD3 high or low with ≤10k or tie to VDD or DGND. AD2 (Pin 8): Address Bit 2. See AD3. AD1 (Pin 9): Address Bit 1. See AD3. AD0 (Pin 10): Address Bit 0. See AD3. DETECT1 (Pin 11): Detect Sense, Port 1. The LTC4259A1 Powered Device (PD) detection, classification and AC disconnect hardware monitors port 1 with this pin. Connect DETECT1 to the output port via a 0.47µF 100V X7R capacitor in series with a 1k resistor, both in parallel with a low leakage diode (see Figure 1). The resistor and capacitor may be eliminated if AC disconnect is not used. If the port is unused, the DETECT1 pin can be tied to DGND or allowed to float. DETECT2 (Pin 12): Detection Sense, Port 2. See DETECT1. DETECT3 (Pin 13): Detection Sense, Port 3. See DETECT1. DETECT4 (Pin 14): Detection Sense, Port 4. See DETECT1. DGND (Pin 15): Digital Ground. DGND should be connected to the return from the 3.3V supply. DGND and AGND should be tied together. VDD (Pin 16): Logic Power Supply. Connect to a 3.3V power supply relative to DGND. VDD must be bypassed to DGND near the LTC4259A-1 with at least a 0.1µF capacitor. SHDN1 (Pin 17): Shutdown Port 1, Active Low. When pulled low, SHDN1 shuts down port 1, regardless of the state of the internal registers. Pulling SHDN1 low is equivalent to setting the Reset Port 1 bit in the Reset Pushbutton register (1Ah). Internal filtering of the SHDN1 pin prevents glitches less than 1µs wide from reseting the LTC4259A-1. Pull SHDN1 high with ≤10k or tie to VDD. SHDN2 (Pin 18): Shutdown Port 2, Active Low. See SHDN1. SHDN3 (Pin 19): Shutdown Port 3, Active Low. See SHDN1. SHDN4 (Pin 20): Shutdown Port 4, Active Low. See SHDN1. 8 U U U 4259a1fa LTC4259A-1 PI FU CTIO S AGND (Pin 21): Analog Ground. AGND should be connected to the return from the – 48V supply. AGND and DGND should be tied together. SENSE4 (Pin 22): Port 4 Current Sense Input. SENSE4 monitors the external MOSFET current via a 0.5Ω sense resistor between SENSE4 and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up. If the voltage across the sense resistor reaches the current limit threshold VLIM (typically 25mV/50mA higher), the GATE4 pin voltage is lowered to maintain constant current in the external MOSFET. See Applications Information for further details. If the port is unused, the SENSE4 pin must be tied to VEE. GATE4 (Pin 23): Port 4 Gate Drive. GATE4 should be connected to the gate of the external MOSFET for port 4. When the MOSFET is turned on, a 50µA pull-up current source is connected to the pin. The gate voltage is clamped to 13V (typ) above VEE. During a current limit condition, the voltage at GATE4 will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE4 is pulled down with 50µA, turning the MOSFET off and recording a tICUT or tSTART event. If the port is unused, float the GATE4 pin or tie it to VEE. OUT4 (Pin 24): Port 4 Output Voltage Monitor. OUT4 should be connected to the output port through a 10k series resistor. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current limit threshold when the port voltage is within 18V of AGND. The port 4 Power Good bit is set when the voltage from OUT4 to VEE drops below 2V (typ). A 2.5MΩ resistor is connected internally from OUT4 to AGND. If the port is unused, the OUT4 pin can be tied to AGND or allowed to float. SENSE3 (Pin 25): Port 3 Current Sense Input. See SENSE4. GATE3 (Pin 26): Port 3 Gate Drive. See GATE4. OUT3 (Pin 27): Port 3 Output Voltage Monitor. See OUT4. VEE (Pin 28): – 48V Supply Input. Connect to a – 48V to – 57V supply, relative to AGND. SENSE2 (Pin 29): Port 2 Current Sense Input. See SENSE4. GATE2 (Pin 30): Port 2 Gate Drive. See GATE4. OUT2 (Pin 31): Port 2 Output Voltage Monitor. See OUT4. SENSE1 (Pin 32): Port 1 Current Sense Input. See SENSE4. GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4. OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4. AUTO (Pin 35): Auto Mode Input. Auto mode allows the LTC4259A-1 to detect and power up a PD even if there is no host controller present on the I2C bus. The voltage of the AUTO pin determines the state of the internal registers when the LTC4259A-1 is reset or comes out of VDD UVLO (see the Register map in Table 1). The states of these register bits can subsequently be changed via the I2C interface. The real-time state of the AUTO pin is read at bit 0 in the Pin Status register (11h). Pull AUTO high or low with ≤10k or tie to VDD or DGND. OSCIN (Pin 36): Oscillator Input. Connect to an oscillating signal source, preferably a sine wave, of approximately 100Hz with 2V peak-to-peak amplitude, negative peaks above – 0.3V and positive peaks below 2.5V. When a port is powered and AC disconnect is enabled, this signal is amplified and driven onto the appropriate DETECT pin to determine the AC impedance of the PD. U U U 4259a1fa 9 ADDRESS REGISTER NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE RESET STATE Auto Pin High 1000,0000 1110,0100 0000,0000 0000,0000 0000,0000 0000,0000 0011,0010* Auto Pin Low Supply Event tSTART Fault tICUT Fault Class Complete Detect Complete Disconnect Pwr Good Event Pwr Enable Event 1000,0000 1000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0011,0010* Mask 0 Pwr Enable Change 1 Mask 1 Pwr Enable Change 2 Mask 2 Pwr Enable Change 3 Mask 3 Pwr Enable Change 4 Mask 4 Pwr Good Change 1 Mask 5 Pwr Good Change 2 Mask 6 Pwr Good Change 3 Mask 7 Pwr Good Change 4 R/W PORT LTC4259A-1 TABLE 1. REGISTER 0Bh Supply Event CoR Reserved Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Detect Status 1 Detect Status 1 Detect Status 1 Power Enable 2 Reserved Port 1 Mode 1 DC Discon En 2 Detect Enable 2 Reserved tDIS1 Reserved Reserved Detect Status 2 Detect Status 2 Detect Status 2 Power Enable 3 AD0 Pin Status Port 2 Mode 0 DC Discon En 3 Detect Enable 3 Reserved tICUT0 Reserved Reserved Reserved Power Enable 4 AD1 Pin Status Port 2 Mode 1 DC Discon En 4 Detect Enable 4 Reserved tICUT1 Reserved Class Status 0 Class Status 0 Class Status 0 Power Good 1 AD2 Pin Status Port 3 Mode 0 AC Discon En 1 Class Enable 1 Reserved tSTART0 Reserved Class Status 1 Class Status 1 Class Status 1 Power Good 2 AD3 Pin Status Port 3 Mode 1 AC Discon En 2 Class Enable 2 Reserved tSTART1 Osc Fail Mask Restart Class 2 Restart Class 1 Power Off 1 Reset All Power Off 2 Reserved Restart Detect 4 Power On 4 Reset Port 4 Class Status 2 Class Status 2 Class Status 2 Power Good 3 Reserved Port 4 Mode 0 AC Discon En 3 Class Enable 3 Reserved Reserved Reserved Reserved Reserved Reserved Power Good 4 Reserved Port 4 Mode 1 AC Discon En 4 Class Enable 4 Reserved Reserved Interrupt Pin Enable Restart Class 4 Restart Class 3 Power Off 3 Clear Interrupt Pin Power Off 4 Clear All Interrupts Detect Status 0 Detect Status 0 Detect Status 0 Detect Status 0 Power Enable 1 Auto Pin Status Port 1 Mode 0 DC Discon En 1 Detect Enable 1 Reserved tDIS0 Reserved CoR 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 00A3A2,A1A000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 1010,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 00A3A2,A1A001 1111,1111 1111,0000 1111,1111 0000,0000 0000,0000 1010,0000 AP Status 0Ch Port 1 Status RO 1 0Dh Port 2 Status RO 2 0Eh Port 3 Status RO 3 0Fh Port 4 Status RO 4 10h Power Status RO 4321 11h Pin Status RO Global Configuration 12h Operating Mode R/W 4321 13h Disconnect Enable R/W 4321 14h Detect/Class Enable R/W 4321 15h Reserved R/W 16h Timing Config R/W Global 17h Misc Config R/W Global Pushbuttons Restart Detect 3 Power On 3 Reset Port 3 Restart Detect 2 Power On 2 Reset Port 2 Restart Detect 1 Power On 1 Reset Port 1 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 18h Det/Class Restart PB WO 4321 19h Power Enable PB WO 4321 1Ah Reset PB WO Global Encoding CLASS STATUS DETECT STATUS 000 Class Status Unknown 000 Detect Status Unknown 001 Class 1 001 Short Circuit (275mV, >550mA with a 0.5Ω sense resistor) and pulls the GATE pin down immediately if such an event occurs, shutting off the MOSFET in less than 1µs (with no external capacitor on GATE). Approximately 100µs later, GATE is allowed to rise back up and the normal current limit circuit will take over, allowing ILIM current to flow and causing the GND PORT VOLTAGE 20V/DIV VEE VEE GATE +15V VOLTAGE 10V/DIV VEE PORT CURRENT 0mA 20A/DIV VDD = 3.3V VEE = – 48V FAST PULL-DOWN ACTIVATED FET OFF SHORT APPLIED 250ns/DIV 4258 G04 Figure 15. Rapid Response to 1Ω Short U tICUT timer to count up. During a short circuit, ILIM will be reduced by the foldback feature to 1/7th of the nominal value. See Figures 15 and 16 for examples. Choosing External MOSFETs Power delivery to the ports is regulated with external power MOSFETs. These MOSFETs are controlled as previously described to meet the IEEE 802.3af specification. Under normal operation, once the port is powered and the PD’s bypass capacitor is charged to the port voltage, the external MOSFET dissipates very little power. This suggests that a small MOSFET is adequate for the job. Unfortunately, other requirements of the IEEE 802.3af mandate a MOSFET capable of dissipating significant power. When the port is being powered up, the port voltage must reach 30V or more before the PD turns on. The port voltage can then drop to 0V as the PD’s bypass capacitor is charged. According to the IEEE, the PD can directly connect a 180µF capacitor to the port and the PSE must charge that capacitor with a current limit of 400mA to 450mA for at least 50ms. An even more extreme example is a noncompliant PD that provides the proper signature during detection but then behaves like a low valued resistor, say 50Ω, in parallel with a 1µF capacitor. When the PSE has charged this noncompliant PD up to 20V, the 50Ω resistor will draw 400mA (the minimum IEEE prescribed ILIM current limit) keeping the port voltage at 20V for the remainder of tSTART. The external MOSFET sees 24V to 37V VDS at 400mA to 450mA, dissipating 9.6W to 16.7W for 60ms (typ). GND PORT VOLTAGE 20V/DIV VEE VEE +15V VEE CURRENT LIMIT VDD = 3.3V VEE = – 48V GATE VOLTAGE 10V/DIV FAST PULL-DOWN SHORT REMOVED SHORT APPLIED 100µs/DIV 4258 G05 W UU PORT CURRENT 0mA 500mA/DIV Figure 16. Rapid Response to Momentary 100Ω Short 4259a1fa 19 LTC4259A-1 APPLICATIO S I FOR ATIO The LTC4259A-1 implements foldback to reduce the current limit when the MOSFET VDS is high; see the Foldback section. Without foldback, the MOSFET could see as much as 25.7W for 60ms (typ) when powering a shorted or a noncompliant PD with only a few ohms of resistance. With foldback, the MOSFET sees a maximum of 18W for the duration of tSTART. The LTC4259A-1’s duty cycle protection enforces 15 times longer off time than on time, preventing successive attempts to power a defective PD from damaging the MOSFET. System software can enforce even longer wait times. When the LTC4259A-1 is operated in semiauto or manual mode—described in more detail under Operating Modes—it will not power on a port until commanded to do so by the host controller. By keeping track of tSTART and tICUT faults, the host controller can delay turning on the port again after one of these faults even if the LTC4259A1 reports a Detect Good. In this way the host controller implements a MOSFET cooling off period which may be programmed to protect smaller MOSFETs from repeated thermal cycling. The LTC4259A-1 has built-in duty cycle protection for tICUT and tSTART (see tICUT Timing and tSTART Timing sections) that is sufficient to protect the MOSFETs shown in Figure 1. Before designing a MOSFET into your system, carefully compare its safe operating area (SOA) with the worst case conditions (like powering up a defective PD) the device will face. Using transient suppressors, polyfuses and extended wait times after disconnecting a PD are effective strategies to reduce the extremes applied to the external MOSFETs. Surge Suppressors and Circuit Protection IEEE 802.3af Power over Ethernet is a challenging Hot Swap application because it must survive the (probably unintentional) abuse of everyone in the building. While hot swapping boards in a networking or telecom card cage is done by a trained technician or network administrator, anyone in the building can plug a device into the network. Moreover, in a card cage the physical domain being powered is confined to the card cage. With Power over Ethernet, the PSE supplies power to devices up to 100 meters away. Ethernet cables could potentially be cut, shorted together, and so on by all kinds of events from a contrac- 20 U tor cutting into walls to someone carelessly sticking a screwdriver where it doesn’t belong. Consequently, the Power over Ethernet power source (PSE) must be designed to handle these events. The most dramatic of these is shorting a powered port. What the PSE sees depends on how much CAT-5 cable is between it and the short. If the short occurs on the far end of a long cable, the cable inductance will prevent the current in the cable from increasing too quickly and the LTC4259A-1’s built-in short-circuit protection will take control of the situation and turn off the port. Some energy is stored in the cable, but the transient suppressor on the port clamps the port voltage when the cable inductance causes the voltage to fly back after the MOSFET is turned off. Because the cable only had 600mA or so going through it, an SMAJ58A or equivalent device can easily control the port voltage during flyback. With no cable connected at all, a powered port shorted at the PSE’s RJ-45 connector can reach high current levels before the port is shut down. There is no cable inductance to store energy so once the port is shut down the situation is under control. A short—hence low inductance—piece of CAT-5 will not limit the rapid increase of current when the port is shorted. Even though the LTC4259A-1 short-circuit shutdown is fast, the cable may have many amps flowing through it before the MOSFET can be turned off. Due to the high current, this short piece of cable flies back with significant energy behind it and must be controlled by the transient suppressor. Choosing a surge suppressor that will not develop more than a few volts of forward voltage while passing more than 10A is important. A positive port voltage may forward bias the detect diode (DDETn), bringing the LTC4259A-1’s DETECTn pin positive as well and engaging the DETECTn clamps. This will generally not damage the LTC4259A-1 but extreme cases can cause the LTC4259A-1 to reset. When it resets, the LTC4259A-1 signals an interrupt, alerting the host controller which can then return the LTC4259A-1 to normal operating mode. A substantial transient surge suppressor can typically protect the LTC4259A-1 and the rest of the PSE from these faults. Placing a polyfuse between the RJ-45 connector and the LTC4259A-1 and its associated circuitry can provide additional protection. To meet safety requirements, place the polyfuse in the ground leg of the PSE’s output. 4259a1fa W UU LTC4259A-1 APPLICATIO S I FOR ATIO DC DISCONNECT DC disconnect monitors the sense resistor voltage whenever the power is on to make sure that the PD is drawing the minimum specified current. The disconnect timer counts up whenever port current is below 7.5mA (typ). If the tDIS timer runs out, the corresponding port will be turned off and the disconnect bit in the fault register will be set. If the undercurrent condition goes away before the tDIS timer runs out, the timer will reset. The timer will start counting from the beginning if the undercurrent condition occurs again. The undercurrent circuit includes a glitch filter to filter out noise. The DC disconnect feature can be disabled by clearing the corresponding DC Discon Enable bits in the Disconnect register (13h). The tDIS timer duration can be programmed by bits 1 and 0 of register 16h. The LTC4259A-1 implements a variety of current sense and limit thresholds to control current flowing through the port. Figure 17 is a graphical representation of these thresholds and the action the LTC4259A-1 takes when currrent crosses the thresholds. 300mV 250mV 200mV 150mV 100mV 50mV 0mV SENSEn VOLTAGE 600mA 500mA 400mA 300mA 200mA 100mA 0mA CURRENT DC DISCUT RS = 0.5Ω CONNECT (ICUT) PORT OFF IN tDIS LIMIT (ILIM) SHORT CIRCUIT EFFECT 4259A F17 CURRENT LIMIT IN 1µs PORT OFF IN tICUT OR tSTART CURRENT LIMIT NORMAL OPERATION Figure 17. LTC4259A-1 Current Sense and Limits AC DISCONNECT AC disconnect is an alternate method of sensing the presence or absence of a PD by monitoring the port impedance. The LTC4259A-1 forces a signal, amplified from the OSCIN pin, out of the DETECT pins and onto the Power over Ethernet connection. It calculates the connection impedance from ohm’s law, ZPORT = VAC/IAC. Like DC disconnect, the AC disconnect sensing circuitry controls the disconnect timer. When the connection impedance rises (AC current U falls below IACDMIN) due to the removal of the PD, the disconnect timer counts up. If the impedance remains high (AC current remains below IACDMIN), the disconnect timer counts to tDIS, the port is turned off and the port’s disconnect bit in the Fault Register is set. If the impedance falls (AC current rises above IACDMIN) before the maximum count of the disconnect timer, the timer resets and the port remains powered. Like DC disconnect, AC disconnect can also be disabled by clearing the corresponding AC Discon Enable bits in the Disconnect register (13h). AC disconnect is also affected by the tDIS duration programmed in register 16h. Unlike DC disconnect, AC disconnect has no continuous time output to the timer. Rather, AC disconnect will reset the timer once every cycle, 1/fOSCIN, of the OSCIN signal if the port draws more than IACDMIN during that period. Because of this behavior, the time to turn off the port after PD removal, tDIS, may vary by up to one cycle of OSCIN (1/fOSCIN) from the delay programmed with the tDIS1 and tDIS0 bits. Note that AC disconnect and DC disconnect signals that reset the tDIS timer are ORed together. Thus on a port where both disconnect modes are enabled, either disconnect sensing method can keep the port powered even if the other reports that there is no PD connected. The LTC4259A-1 provides a higher AC disconnect threshold, IACDMIN (see Electrical Characteristics) than the LTC4259A. This reduces the port impedance that the LTC4259A-1’s AC disconnect circuitry senses as the absence of a PD. Consequently, in the same application circuit the LTC4259A-1 will have less sensitivity to parasitics like leakage and stray capacitance than an LTC4259A. Both the LTC4259A and LTC4259A-1 (used with the recommended application circuit) meet all the AC disconnect requirements of 802.3af standard. Because the LTC4259A-1 offers improved performance, Linear Technology recommends the LTC4259A-1 for new designs and as a replacement for the LTC4259A in existing designs. The AC disconnect circuitry senses the port and Power over Ethernet connection from the DETECT pins. Connect a 0.47µF 100V X7R capacitor (CDET) and a 1k resistor (RDET) from the port’s DETECT pin to the port’s output as shown in Figure 18. This provides an AC path for sensing 4259a1fa W UU 21 LTC4259A-1 APPLICATIO S I FOR ATIO U at their rated voltage. Operated at half their rated voltage, X7R capacitors exhibit more than 80% of their specified capacitance. With other ceramic dielectrics commonly used in 50V and 100V chip capacitors, capacitance falls much more dramatically with voltage. At their rated voltage, Y5V or Z5U capacitors exhibit less than 30% of their zero-bias capacitance. Ceramic capacitors can also have significantly less capacitance at elevated temperatures. In order to produce the desired capacitance at the operating bias, 100V or 250V X7R capacitors should be used with the LTC4259A-1. As illustrated in Figure 19, the Power over Ethernet connection between the PSE and PD includes a large amount of capacitance. Cable capacitance is particularly troubling because CAT-3 and CAT-5 pair-to-pair capacitance is not tightly specified by the IEEE 802.3 standard or well controlled by cable manufacturers. Considering that patch panels, additional connectors, old wiring, etc. are likely to be placed between the PSE and PD, pair-to-pair capacitance is a pretty nebulous quantity. Consequently, the cable’s contribution to the port impedance (at the frequency used for AC disconnect) can be a concern. PD OSCIN LEVEL 1/4 LTC4259A-1 SHIFT DGND AGND DETECT4 RDET4 1k CDET4 0.47µF 100V X7R 4259A F18 the port impedance. The 1k resistor, RDET, limits current flowing through this path during port power on and power off. Sizing of capacitors is critical to ensure proper function of AC disconnect. CPSE (Figure 18) controls the connection impedance on the PSE side. Its capacitance must be kept low enough for AC disconnect to be able to sense the PD. For operation near 100Hz, use a CPSE of 0.1µF. On the other hand, CDET has to be large enough to pass the signal at the frequency of OSCIN. For fOSCIN ≈ 100Hz, use at least a 0.47µF 100V X7R capacitor. The sizes of CPSE, CDET, RDET and the frequency, fOSCIN, are chosen to create an economical, physically compact and functionally robust system. Moreover, the complete Power over Ethernet AC disconnect system (PSE, transformers, cabling, PD, etc.) is complex; deviating from the recommended values of CDET, RDET and CPSE is discouraged. Contact the LTC Applications department for additional support. When choosing CDET and CPSE, carefully consider voltage derating of the capacitors. Capacitors built around an X7R dielectric will have about 60% of the specified capacitance GND VEE –48V SENSE4 GATE4 OUT4 ROUT4 10k RS4 0.5Ω 1% Figure 18. AC Disconnect Single Port Application Circuit (Port 4 Shown) OSCILLATOR INPUT CURRENT SENSE ~7k ~16k Figure 19. Simplified AC Disconnect Circuit with Impedances at 100Hz 4259a1fa 22 W UU CPSE4 0.1µF 100V X7R RPD_D ≤ 26.25k CPD_D ≥ 0.05µF DDET4 CMPD3003 Q4 DAC4 S1B RDET 1k CDET 0.47µF CPSE 0.10µF ZLINK < 14k ZPD < 14k PD ZCABLE < 32k CCABLE ≤ 0.05µF