LTC4261IGN-2

LTC4261/LTC4261-2 Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The LTC®4261/LTC4261-2 negative voltage Hot SwapTM controllers allow a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, the board supply voltage can be ramped at an adjustable rate. The devices feature independently adjustable inrush current and overcurrent limits to minimize stresses on the pass transistor during start-up, input step and output short conditions. The LTC4261 defaults to latch-off while the LTC4261-2 defaults to auto-retry on overcurrent faults. An I2C interface and onboard 10-bit ADC allow monitoring of board current, voltage and fault status. A single-wire broadcast mode is available to simplify the interface by eliminating two optoisolators. The controllers have additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a board and turn off the pass transistor if an external supply monitor fails to indicate power good within a timeout period. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. Patents pending. All other trademarks are the property of their respective owners. Allows Safe Insertion into Live –48V Backplanes 10-Bit ADC Monitors Current and Voltages I2C/SMBus Interface or Single-Wire Broadcast Mode Floating Topology Allows Very High Voltage Operation Independently Adjustable Inrush and Overcurrent Limits Controlled Soft-Start Inrush Adjustable UV/OV Thresholds and Hysteresis Sequenced Power Good Outputs with Delays Adjustable Power Good Input Timeout Programmable Latchoff or Auto-Retry After Faults Alerts Host After Faults Available in 28-Lead Narrow SSOP and 24-Lead (4mm × 5mm) QFN Packages APPLICATIONS ■ ■ ■ ■ AdvancedTCA Systems Telecom Infrastructure –48V Distributed Power Systems Power Monitors TYPICAL APPLICATION –48V/200W Hot Swap Controller with I2C and ADC –48V RTN 453k 1% 4× 1k IN SERIES 1/4W EACH –48V INPUT 50V/DIV Start-Up Behavior UV = 38.5V UV RELEASE AT 43V OV = 72.3V OV RELEASE AT 71V 16.9k 1% UVL UVH ADIN2 OV INTVCC ON SS 11.8k 1% 1µF PGI ALERT SDAO SDAI LTC4261CGN SCL ADIN PGIO TMR EN VEE SENSE GATE DRAIN RAMP PG 47nF 10Ω 1M 1k 10nF 100V 5% Q1 IRF1310NS VIN VIN+ LOAD ON VIN– + 330µF 100V VOUT 50V/DIV SENSE 0.5A/DIV PG 50V/DIV 10ms/DIV 42612 TA01b 220nF 0.1µF 47nF 0.008Ω 1% –48V INPUT VOUT 42612 TA01 42612fb 1 LTC4261/LTC4261-2 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) VIN (Note 3) ......................................... –0.3V to 10.65V Drain (Note 4) .......................................... –0.3V to 3.5V PGI, ON, ALERT, SDAO, SDAI, SCL, ADIN, ADIN2, OV, SENSE, ADR1, ADR0, FLTIN, TMR, SS, RAMP Voltages.................... –0.3V to INTVCC + 0.3V UVL, UVH, EN ............................................ –0.3V to 10V GATE Voltage .................................. –0.3V to VIN + 0.3V PG, PGIO Voltages .................................... –0.3V to 80V Supply Voltage (INTVCC) .......................... –0.3V to 5.5V Operating Temperature Range LTC4261C ................................................ 0°C to 70°C LTC4261I ............................................. –40°C to 85°C Storage Temperature Range SSOP ................................................. –65°C to 150°C QFN.................................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP Only ........................................................ 300°C PACKAGE/ORDER INFORMATION TOP VIEW PGI ON ALERT SDAO SDAI SCL INTVCC UVL UVH 1 2 3 4 5 6 7 8 9 28 PGIO 27 PG 26 EN 25 ADR1 24 ADR0 23 ADIN 22 FLTIN 21 VIN 20 TMR 19 SS 18 RAMP 17 NC 16 DRAIN 15 GATE SDAO 1 SDAI 2 SCL 3 INTVCC 4 UVL 5 UVH 6 OV 7 8 VEE 9 10 11 12 SENSE GATE DRAIN RAMP 25 ALERT TOP VIEW PGIO PGI ON PG 19 EN 18 ADR1 17 ADR0 16 ADIN 15 VIN 14 TMR 13 SS 24 23 22 21 20 ADIN2 10 OV 11 NC 12 VEE 13 SENSE 14 GN PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 85°C/W UFD PACKAGE 24-LEAD (4mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 45°C/W EXPOSED PAD (PIN 25) PCB VEE ELECTRICAL CONNECTION OPTIONAL ORDER PART NUMBER LTC4261CGN LTC4261IGN LTC4261CGN-2 LTC4261IGN-2 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ ORDER PART NUMBER LTC4261CUFD LTC4261IUFD LTC4261CUFD-2 LTC4261IUFD-2 UFD PART MARKING* 4261 4261 42612 42612 *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. 42612fb 2 LTC4261/LTC4261-2 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at IIN = 5mA, TA = 25°C. (Note 2) SYMBOL General VZ ΔVZ IIN VIN(UVLO) ΔVIN(UVLO) INTVCC Gate Drive VGATEH IGATE(UP) IGATE(OFF) tPHL(SENSE) tPHL(GATE) tPHLCB IRAMP VSS ISS(UP) ISS(DN) Input Pins VUVH(TH) VUVL(TH) ΔVUV(HYST) δVUV VUVLR(TH) ΔVUVLR(HYST) VOV(TH) ΔVOV(HYST) ΔVSENSE VINPUT(TH) ΔVINPUT(HYST) VPGIO(TH) ΔVPGIO(HYST) IINPUT UVH Threshold Voltage UVL Threshold Voltage Built-In UV Hysteresis UVH, UVL Minimum Hysteresis UVL Reset Threshold Voltage UVL Reset Hysteresis OV Pin Threshold Voltage OV Pin Hysteresis Current Limit Sense Voltage Threshold ON, EN, PGI, FLTIN Threshold Voltage ON, EN, PGI, FLTIN Hysteresis PGIO Pin Input Threshold Voltage PGIO Pin Input Hysteresis ON, EN, UVH, UVL, OV, SENSE, PGI, FLTIN Input Current ON, EN, UVH, UVL, OV, SENSE, PGI, FLTIN = 3V ● VPGIO Rising ● ELECTRICAL CHARACTERISTICS PARAMETER Shunt Regulator Voltage at VIN Shunt Regulator Load Regulation VIN Supply Current VIN Undervoltage Lockout Threshold VIN Undervoltage Lockout Hysteresis Internal Regulator Voltage GATE Pin Output High Voltage GATE Pin Pull-Up Current GATE Turn-Off Current SENSE High to Current Limit Propagation Delay GATE Off Propagation Delay Circuit Breaker Gate Off Delay RAMP Pin Current SS Pin Clamp Voltage SS Pin Pull-Up Current SS Pin Pull-Down Current CONDITIONS IIN = 5mA IIN = 5mA to 25mA VIN = VZ – 0.3V VIN Rising ILOAD = 1mA to 20mA, IIN = 25mA VIN = 10.65V VGATE = 4V VSENSE = 300mV, VGATE = 4V Gate Off, VGATE = 4V VSENSE = 100mV, CGATE = 1pF VSENSE = 300mV, CGATE = 1pF Input High (OV, EN, PGI), Input Low (ON, UVL), CGATE = 1pF VGATE < 2V, CGATE = 1pF VSS = 2.56V VSS = 0V VSS = 2.56V VUVH Rising VUVL Falling LTC4261C LTC4261I LTC4261C LTC4261I ● ● ● ● ● ● MIN 10.65 TYP 11.2 370 2 MAX 11.8 600 5 9.5 1 5.25 10.5 –15.5 140 140 1.5 0.5 0.5 620 –22 2.69 –13 20 2.586 2.598 2.319 2.328 282 1.30 1.796 1.805 62 55 2 1.40 ±2 UNITS V mV mA V V V V µA mA mA µs µs µs µs µA V µA mA V V mV mV V mV V mV mV V mV V mV µA 8.5 0.3 4.75 10 –7.5 60 60 9 0.7 5 10.25 –11.5 110 110 0.5 0.2 0.2 ● ● ● ● ● ● ● ● ● ● ● ● 440 –18 2.43 –7 6 2.534 2.522 2.263 2.254 256 1.12 1.744 1.735 18 45 0.8 1.10 530 –20 2.56 –10 12 2.56 2.56 2.291 2.291 269 15 1.21 60 1.770 1.770 37.5 50 1.4 170 1.25 100 0 ● ● ● ● ● UVH and UVL Tied Together VUVL Falling VOV Rising LTC4261C LTC4261I ● ● ● ● ● ● VSENSE – VEE ON, EN, PGI, FLTIN Falling or Rising 42612fb 3 LTC4261/LTC4261-2 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at IIN = 5mA, TA = 25°C. (Note 2) SYMBOL Timer VTMR(H) VTMR(L) ITMR(UP) TMR Pin High Threshold TMR Pin Low Threshold TMR Pin Pull-Up Current VTMR Rising VTMR Falling Turn-On and Auto-Retry (Except OC) Delays, VTMR = 0.2V Power Good, PGI Check and OC Auto-Retry Delays, VTMR = 0.2V ITMR(DN) TMR Pin Pull-Down Current Delays Except PGI Check or OC Auto-Retry, VTMR = 2.56V PGI Check and OC Auto-Retry Delays, VTRM = 2.56V Output Pins VPWRGD IPWRGD ADC Resolution (No Missing Codes) INL VOS Integral Nonlinearity Offset Error Full-Scale Voltage Total Unadjused Error Conversion Rate RADIN IADIN I2C Interface VADR(H) VADR(L) IADR(IN) VALERT(OL) VSDAO(OL) ISDAO,ALERT(IN) VSDAI,SCL(TH) ISDAI,SCL(IN) ADR0, ADR1 Input High Threshold ADR0, ADR1 Input Low Threshold ADR0, ADR1 Input Current ALERT Pin Output Low Voltage SDAO Pin Output Low Voltage SDAO, ALERT Input Current SDAI, SCL Input Threshold SDAI, SCL Input Current SDAI, SCL = 5V ADR0, ADR1 = 0V, 5V ADR0, ADR1 = 0.8V, (INTVCC – 0.8V) IALERT = 4mA ISDAO = 4mA SDAO, ALERT = 5V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN 2.43 40 –7 –3.5 6 3 TYP 2.56 75 –10 –5 12 5 MAX 2.69 110 –13 –6.5 20 7 UNITS V mV µA µA mA µA PG, PGIO Pins Output Low PG, PGIO Pins Leakage Current IPG, IPGIO = 3mA IPG, IPGIO = 500µA PG, PGIO = 80V (Note 5) SENSE ADIN2/OV, ADIN SENSE ADIN2/OV, ADIN SENSE ADIN2/OV, ADIN SENSE ADIN2/OV, ADIN ● ● ● 0.8 0.15 0 10 ±0.5 ±0.25 1.6 0.4 ±10 V V µA Bits ● ● ● ● ● ● ● ● ● ● ±2.5 ±1.25 ±1.75 ±1.25 LSB LSB LSB LSB mV V % % Hz MΩ µA V V µA µA V V µA V µA 62.8 2.514 64 2.560 65.2 2.606 ±1.8 ±1.6 5.5 2 7.3 10 0 9 ±2 INTVCC – 0.3 0.8 ±80 ADIN, ADIN2 Pins Input Resistance ADIN, ADIN2 Pins Input Current ADIN, ADIN2 = 1.28V ADIN, ADIN2 = 2.56V ● ● INTVCC – 0.8 0.3 ±10 INTVCC – 0.5 0.5 0.2 0.2 0 1.6 1.8 0 0.4 0.4 ±5 2 ±2 42612fb 4 LTC4261/LTC4261-2 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at IIN = 5mA, TA = 25°C. (Note 2) SYMBOL fSCL(MAX) tLOW tHIGH tBUF(MIN) tHD,STA(MIN) tSU,STA(MIN) tSU,STO(MIN) tHD,DATI(MIN) tHD,DATO(MIN) tSU,DAT(MIN) tSP(MAX) tRST CX PARAMETER Maximum SCL Clock Frequency Minimum SCL Low Period Minimum SCL High Period Minimum Bus Free Time Between Stop/Start Condition Minimum Hold Time After (Repeated) Start Condition Minimum Repeated Start Condition Set-Up Time Minimum Stop Condition Set-Up Time Minimum Data Hold Time Input Minimum Data Hold Time Output Minimum Data Set-Up Time Input Maximum Suppressed Spike Pulse Width Stuck-Bus Reset Time SCL,SDA Input Capacitance SCL or SDAI Held Low SDAI Tied to SDAO 50 25 300 CONDITIONS MIN 400 0.65 50 0.12 140 30 30 –100 600 30 110 66 5 10 1.3 600 1.3 600 600 600 0 900 100 250 TYP MAX UNITS kHz µs ns µs ns ns ns ns ns ns ns ms pF I2C Interface Timing (Note 5) ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to device GND (VEE) unless otherwise specified. Note 3: An internal shunt regulator limits the VIN pin to a minimum of 10.65V. Driving this pin to voltages beyond 10.65V may damage the part. The pin can be safely tied to higher voltages through a resistor that limits the current below 50mA. Note 4: An internal clamp limits the DRAIN pin to a minimum of 3.5V. Driving this pin to voltages beyond the clamp may damage the part. The pin can be safely tied to higher voltages through a resistor that limits the current below 2mA. Note 5: Guaranteed by design and not subject to test. 42612fb 5 LTC4261/LTC4261-2 TYPICAL PERFORMANCE CHARACTERISTICS Shunt Regulator Voltage vs Input Current 30 25 20 15 10 5 0 10.8 11.35 SHUNT REGULATOR VOLTAGE AT VIN (V) IIN = 5mA 5.04 INTVCC VOLTAGE (V) IIN = 5mA, TA = 25°C, unless otherwise noted Shunt Regulator Voltage vs Temperature 5.06 INTVCC vs Load Current IIN = 25mA VIN PIN INPUT CURRENT (mA) 11.30 11.25 5.02 11.20 5.00 11.15 4.98 11.8 11 11.2 11.4 11.6 SHUNT REGULATOR VOLTAGE AT VIN (V) 42612 G01 11.10 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 4.96 0 5 10 15 LOAD CURRENT (mA) 20 42612 G03 42612 G02 GATE Output High Voltage vs Temperature 10.5 VIN = 10.65V GATE OUTPUT HIGH VOLTAGE (V) 10.4 –12 GATE Pull-Up Current vs GATE Voltage 150 GATE TURN-OFF CURRENT (mA) 125 100 75 50 25 0 0 2 4 6 8 GATE VOLTAGE (V) 10 12 GATE Turn-Off Current vs GATE Voltage VSENSE = 300mV GATE PULL-UP CURRENT (µA) –10 –8 –6 –4 –2 0 10.3 10.2 10.1 10.0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 0 2 4 VGS (V) 6 8 10 42612 G06 42612 G04 42612 G05 RAMP Pin Current vs Temperature –22.0 –21.5 RAMP PIN CURRENT (µA) –21.0 –20.5 –20.0 2.575 UVH THRESHOLD VOLTAGE (V) UVH Threshold vs Temperature 2.305 UVH THRESHOLD VOLTAGE (V) 2.300 2.295 2.290 2.285 2.280 UVL Threshold vs Temperature 2.570 2.565 2.560 2.555 2.550 2.545 –50 –19.5 –19.0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 –25 0 25 50 TEMPERATURE (°C) 75 100 2.275 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 42612 G07 42612 G08 42612 G09 42612fb 6 LTC4261/LTC4261-2 TYPICAL PERFORMANCE CHARACTERISTICS OV Threshold vs Temperature 1.785 1.780 OV HYSTERESIS (mV) 1.775 1.770 1.765 1.760 1.755 –50 50 CURRENT LIMIT SENSE VOLTAGE (mV) IIN = 5mA, TA = 25°C, unless otherwise noted Current Limit Voltage vs Temperature 52.0 51.5 51.0 50.5 50.0 49.5 49.0 –50 OV Hysteresis vs Temperature OV THRESHOLD VOLTAGE (V) 45 40 35 30 –25 0 25 50 TEMPERATURE (°C) 75 100 25 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 –25 0 25 50 TEMPERATURE (°C) 75 100 42612 G08 42612 G11 42612 G08 Current Limit Propagation Delay (tPHL(SENSE)) vs VSENSE 1000 CGATE = 1pF PG OUTPUT LOW VOLTAGE (V) 6 5 PG, PGIO Output Low vs Load Current 1.0 ADC TOTAL UNADJUSTED ERROR (LSB) ADC Total Unadjusted Error vs Code (ADIN Pin) TA = 85°C 4 3 2 TA = –40°C 1 0 TA = 25°C 0.5 tPHL(SENSE) (ns) 0 –0.5 100 0 100 300 200 VSENSE (mV) 400 500 42612 G13 0 2 4 6 8 LOAD CURRENT (mA) 10 42612 G14 –1.0 0 256 512 CODE 768 1024 42612 G15 ADC Full-Scale Error vs Temperature (ADIN Pin) 3 ADC FULL-SCALE ERROR (LSB) 2 0.5 1.0 ADC INL vs Code (ADIN Pin) 1.0 ADC DNL vs Code (ADIN Pin) 0.5 ADC DNL (LSB) 0 256 512 CODE 768 1024 42612 G17 ADC INL (LSB) 1 0 –1 –2 –3 –50 0 0 –0.5 –0.5 –25 0 25 50 TEMPERATURE (°C) 75 100 –1.0 –1.0 0 256 512 CODE 768 1024 42612 G18 42612 G16 42612fb 7 LTC4261/LTC4261-2 PIN FUNCTIONS (SSOP/QFN) ADIN (Pin 23/Pin 16): ADC Input. A voltage between 0V and 2.56V applied to this pin is measured by the on-chip ADC. Tie to VEE if unused. ADIN2 (Pin 10/NA): Second ADC Input. Not available on QFN package. ADR0, ADR1 (Pins 24, 25/Pins 17, 18): Serial Bus Address Inputs. Tying these pins to VEE, OPEN or INTVCC configures one of nine possible addresses. See Table 1 in Applications Information. ALERT (Pin 3/Pin 24): Fault Alert Output. Open-drain logic output that pulls to VEE when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register. See Applications Information. Connect to VEE if unused. DRAIN (Pin 16/Pin 11): Drain Sense Input. Connect an external 1M resistor between this pin and the drain terminal (VOUT) of the N-channel FET. When the DRAIN pin voltage is less than 1.77V and the GATE pin voltage is above VZ – 1.2V the power good outputs are asserted after a delay. The voltage at this pin is internally clamped to 4V. EN (Pin 26/Pin 19): Device Enable Input. Pull low to enable the N-channel FET to turn-on after a start-up debounce delay set by the TMR pin. When this pin is pulled high, the FET is off. Transitions on this pin will be recorded in the FAULT register. A high-to-low transition activates the logic to read the state of the ON pin and clear faults. Requires external pull-up. Debouncing with an external capacitor is recommended when used to monitor board present. Connect to VEE if unused. Exposed Pad (Pin 25, QFN Only): Exposed Pad may be left open or connected to device ground (VEE). FLTIN (Pin 22/NA): General Purpose Fault Input. If this pin pulls low, the FAULT register bit B7 is latched to “1.” This pin is used to sense an external fault condition and its status does not affect the FET control functions of the LTC4261. Not available on the QFN package. Connect to INTVCC if unused. GATE (Pin 15/Pin 10): N-Channel FET Gate Drive Output. This pin is pulled up by an internal current source IGATE (11.5µA when the SS pin reaches its clamping voltage). GATE stays low until VIN and INTVCC cross the UVLO thresholds, UV and OV conditions are satisified and an adjustable timer delay expires. During turn-off, shortcircuit or undervoltage lockout (VIN or INTVCC), a 110mA pull-down current between GATE and VEE is activated. INTVCC (Pin 7/Pin 4): Low Voltage (5V) Supply Output. This is the output of the internal linear regulator with an internal UVLO threshold of 4.25V. This voltage powers up the data converter and logic control circuitry. Bypass this pin with a 0.1µF capacitor to VEE. ON (Pin 2/Pin 23): On Control Input. A rising edge turns on the external N-channel FET while a falling edge turns it off. This pin is also used to configure the state of the FET ON register bit D3 in the CONTROL register (and hence the external FET) at power-up. For example if the ON pin is tied high, then the register bit D3 goes high one timer cycle after power-up. Likewise, if the ON pin is tied low, then the device remains off after power-up until the register bit D3 is set high using the I2C bus. A high-to-low transition on this pin clears faults. OV (Pin 11/Pin 7): Overvoltage Detection Input. Connect this pin to an external resistive divider from VEE. If the voltage at the pin rises above 1.77V, the N-channel FET is turned off. The overvoltage condition does not affect the status of the power good outputs. On the QFN package, this pin is also measured by the on-chip ADC. Connect to VEE if unused. PG (Pin 27/Pin 20): Power Good Status Output. This open-drain pin pulls low and stays latched a timer delay after the FET is on (when GATE reaches VZ – 1.2V and DRAIN is within 1.77V of VEE). The power good output is reset in all GATE pull-down events except an overvoltage fault. Connect to VEE if unused. PGI (Pin 1/Pin 22): Power Good Input. This pin along with the PGI check timer serves as a watchdog to monitor the power-up of the DC/DC converter. The PGI pin must be low before the PGI check timer expires, otherwise the GATE pin pulls down and stays latched and a power bad fault is logged into the FAULT register. The PGI timer is started after the second power good is latched and its delay is equal to four times the start-up debounce delay. Connect to VEE if unused. 42612fb 8 LTC4261/LTC4261-2 PIN FUNCTIONS (SSOP/QFN) PGIO (Pin 28/Pin 21): General Purpose Input/Output. Opendrain logic output and logic input. Defaults to pull low a timer delay after the PG pin goes low to indicate a second power good output. Configure according to Table 6. RAMP (Pin 18/Pin 12): Inrush Current Ramp Control Pin. The inrush current is set by placing a capacitor (CR) between the RAMP pin and the drain terminal of the FET. At start-up, the GATE pin is pulled up by IGATE(UP) until the pass transistor begins to turn on. A current, IRAMP, then flows through CR to ramp down the output voltage VOUT. The value of IRAMP is controlled by the SS pin voltage. When the SS pin reaches its clamp voltage (2.56V), IRAMP = 20µA. The ramp rate of VOUT and the load capacitor CL set the inrush current: IINRUSH = (CL/CR) • IRAMP. SCL (Pin 6/Pin 3): Serial Bus Clock Input. Data at the SDAI pin is shifted in and data at the SDAO pin is shifted out on rising edges of SCL. This is a high impedance pin that is generally connected to the output of the incoming optoisolator driven by the SCL port of the master controller. An external pull-up resistor or current source is required. Pull up to INTVCC if unused. SDAI (Pin 5/Pin 2): Serial Bus Data Input. This is a high impedance input pin used for shifting in command or data bits. An external pull-up resistor or current source is required. Normally connected to the output of the incoming optoisolator that is driven by the SDA port of the master controller. Pull up to INTVCC if unused. SDAO (Pin 4/Pin 1): Serial Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. An external pull-up resistor or current source is required. Normally connected to the input of the outgoing optoisolator that outputs to the SDA port of the master controller. In the single-wire broadcast mode, the SDAO pin sends out selected data that is encoded with an internal clock. SENSE (Pin 14/Pin 9): Current Limit Sense Input. Load current through the external sense resistor (RS) is monitored and controlled by an active current limit amplifier to 50mV/RS. Once VSENSE reaches 50mV, a circuit breaker timer starts and turns off the pass transistor after 530µs. In the event of a catastrophic short circuit, if VSENSE crosses 150mV, a fast response comparator immediately pulls the GATE pin down to turn off the N-channel FET. SS (Pin 19/Pin 13): Soft-Start Input. Connect a capacitor to this pin to control the rate of rise of inrush current (dI/dt) during start-up. An internal 10µA current source charging the external soft-start capacitor (CSS) creates a voltage ramp. This voltage is converted to a current to charge the GATE pin up and to ramp the output voltage down. The SS pin is internally clamped to 2.56V limiting IGATE(UP) to 11.5µA and IRAMP to 20µA. If the SS capacitor is absent, the SS pin ramps from 0V to 2.56V in 220µs. TMR (Pin 20/Pin 14): Delay Timer Input. Connect a capacitor (CTMR) to this pin to create timing delays at start-up, when power good outputs pull down, during PGI check and when auto-retrying after faults (except overvoltage fault). Internal pull-up currents of 10µA and 5µA and pull-down currents of 5µA and 12mA configure the delay periods as multiples of a nominal delay of 256ms • CTMR/µF. Delays for start-up and auto-retry following undervoltage or power bad fault are the same as the nominal delay. Delays for sequenced power good outputs are twice of the nominal delay. Delays for PGI check and auto-retry following overcurrent fault are four times the nominal delay. UVH (Pin 9/Pin 6): Undervoltage High Level Input. Connect this pin to an external resistive divider from VEE. If the voltage at the UVH pin rises above 2.56V the pass transistor is allowed to turn on. A small capacitor at this pin prevents transients and switching noise from affecting the UVH threshold. Connect to INTVCC if unused. UVL (Pin 8/Pin 5): Undervoltage Low Level Input. Connect this pin to an external resistive divider from VEE. If the voltage at the UVL pin drops below 2.291V, the pass transistor is turned off and the power good outputs go high impedance. Pulling this pin below 1.21V resets faults and allows the pass transistor to turn back on. Connect to INTVCC if unused. VEE (Pin 13/Pin 8): Negative Supply Voltage Input and Device Ground. Connect this pin to the negative side of the power supply. VIN (Pin 21/Pin 15): Positive Supply Input. Connect this pin to the positive supply through a dropping resistor. An internal shunt regulator clamps VIN at 11.2V. An internal undervoltage lockout (UVLO) circuit holds the GATE low until VIN is above 9V. Bypass this pin with a 1µF capacitor to VEE. 42612fb 9 LTC4261/LTC4261-2 BLOCK DIAGRAM VIN 11.2V UVLO: VIN = 9V INTVCC = 4.25V VEE VCC GATE 20µA SSA VIN INTVCC 5V 10µA 50nA 3pF VEE SS SSC UVL 2.291V UVH 2.56V OV 1.77V 5µA 5µA 2.56V VEE VSENSE 40× PG + – + – + – UVL VEE UVH OV LOGIC TMR 2.56V 12mA 5µA + – TMR ADR0 ADR1 A0 • DECODER • A7 A8 8 I2C DEVICE ADDRESS SINGLE-WIRE ENABLE VREF = 2.56V 10 10 I2C INTERFACE REGISTER ADIN ADIN2/OV VSENSE MUX 10-BIT ADC 10 + – GC + – DC + – –+ + – VEE ACL RAMP SENSE +– 50mV VEE – + PGIO VEE FLTIN PGI EN ON DRAIN 1.77V VEE 4V VZ – 1.2V GATE SCL SDAI SDAO ALERT VEE 42612 BD 42612fb LTC4261/LTC4261-2 OPERATION The LTC4261/LTC4261-2 are designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live – 48V backplane. The devices also feature an onboard 10-bit ADC and I2C interface that allows monitoring board current, voltages and faults. The main functional circuits of the LTC4261/LTC4261-2 are illustrated in the Block Diagram. In normal operation after a start-up debounce delay, the GATE pin turns on the external N-channel FET passing power to the load. The GATE pin is powered by a shunt regulated 11.2V supply on the VIN pin that is derived from –48V RTN through a dropping resistor. The turn-on sequence starts by pulling the SS pin up. The voltage at the SS pin is converted to a current, IGATE(UP), pulling the GATE up. When the pass FET starts to turn on and charge the load capacitor, the inrush current flowing through the FET is a function of the capacitor at RAMP (CR), the load capacitor (CL) and the ramp current (IRAMP) that flows from the RAMP pin to CR: IINRUSH = IRAMP • CL CR The DRAIN and the GATE voltages are monitored to determine if power is available for the load. Two power good signals are sequenced on the PG pin (first power good signal) and the PGIO pin (second power good signal), each with a debounce delay that is twice the start-up delay. The PGIO pin can also be used as a general purpose input or output. The PGI pin serves as a watchdog to monitor the output of the DC/DC module. If the module output fails to come up, the LTC4261/LTC4261-2 shut down. The TMR pin generates delays for initial start-up, auto-retry following a fault, power good outputs and PGI check. The logic circuits a re powered by an internally generated 5V supply (available on the INTVCC pin). Prior to turning on the pass FET, both VIN and INTVCC voltages must exceed their undervoltage lockout thresholds. In addition, the control inputs UVH, UVL, OV, EN, ON and PGI are monitored by comparators. The FET is held off until all start-up conditions are met. A 10-bit analog-to-digital converter (ADC) is included in the LTC4261/LTC4261-2. The ADC measures SENSE resistor voltage as well as voltage at the ADIN2/OV (SSOP/QFN) and ADIN pins. The results are stored in on-board registers. An I2C interface is provided to read the ADC data registers. It also allows the host to poll the device and determine if a fault has occurred. If the ALERT line is used as an interrupt, the host can respond to a fault in real time. The SDA line is divided into SDAI (input) and SDAO (output) to facilitate opto coupling with the system host. Two three-state pins, ADR0 and ADR1, are used to decode eight device addresses. The interface can also be configured through the ADR0 and ADR1 pins for a single-wire broadcast mode, sending ADC data and faults status through the SDAO pin to the host without clocking the SCL line. This single-wire, one-way communication simplifies system design by eliminating two optocouplers on SCL and SDAI that are required by an I2C interface. IRAMP and IGATE(UP) are approximately proportional to the SS pin voltage and are limited to 20µA and 11.5µA, respectively when SS reaches its clamping voltage (2.56V). The ACL amplifier is used for overcurrent and short-circuit protection. It monitors the load current through the SENSE pin voltage and a sense resistor RS. In an overcurrent condition, the ACL amplifier limits the current to 50mV/RS by pulling down GATE in an active servo loop. After a 530µs timeout, the ACL amplifier turns off the pass FET. In the event of a catastrophic short circuit, when VSENSE crosses 150mV, a fast response comparator pulls the GATE pin down with a 110mA current. 42612fb 11 LTC4261/LTC4261-2 APPLICATIONS INFORMATION The LTC4261/LTC4261-2 are ideally suited for –48V distributed power systems and AdvancedTCA systems. A basic 200W application circuit using the LTC4261 is shown in Figure 1. A more complete application circuit with AdvancedTCA connections is shown in Figure 2. –48V RTN R3 453k 1% 7 UV = 38.5V UV RELEASE AT 43V OV = 72.3V OV RELEASE AT 71V R2 16.9k 1% 8 9 10 11 19 20 26 2 25 24 RIN 4× 1k IN SERIES 1/4W EACH 21 22 1 6 5 4 3 28 PWRGD2 27 PWRGD1 23 Input Power Supply Power for the LTC4261/LTC4261-2 is derived from the –48V RTN through an external current limiting resistor (RIN) to the VIN pin. An internal shunt regulator clamps VIN INTVCC UVL FLTIN UVH PGI ADIN2 SCL OV SDAI SS SDAO LTC4261CGN TMR ALERT EN PGIO ON ADR1 PG ADRO ADIN VEE SENSE GATE DRAIN RAMP 13 CG 47nF 14 RG 10Ω 15 16 RD 1M 18 RF 1k CR 10nF 100V 5% Q1 IRF1310NS + VIN+ MODULE2 ON VIN– VIN+ MODULE1 ON VIN– CL 330µF 100V CUV 100nF CIN 1µF R1 CVCC 11.8k 0.1µF 1% CSS 220nF CTMR 47nF –48V INPUT VEE CF RS 33nF 0.008Ω 1% R10 10k 1% VOUT R11 402k 1% 42612 F01 Figure 1. –48V/200W Hot Swap Controller Using LTC4261 with Current, Input Voltage and VDS Monitoring (5.6A Current Limit, 0.66A Inrush) 10A RTN A 10A RTN B UV TURN OFF = 34.2V UV RELEASE = 37.5V OV TURN OFF = 74.8V OV RELEASE = 73.2V RH 604Ω 1% R2 19.1k 1% CUV 100nF MBRM5100 R3 412k 1% MBRM5100 A ENABLE A R12 10k R13 10k Q9 2N5401 ENABLE B R10 100k R11 100k R14 100k 1N4148 ×2 Q10 2N5401 R15 100k 8 9 10 11 19 20 26 2 25 24 UVL UVH ADIN2 OV SS TMR EN ON ADR1 ADR0 VEE 13 LTC4261CGN SENSE GATE DRAIN RAMP 14 RG 10Ω 15 16 RD 1M 18 RF 1k CR 10nF 100V 5% Q1 IRF1310NS 42612 F02a CSS 330nF LTC4354 HZS5C1 7A –48V B BACKPLANE PLUG-IN CARD VEE R16 100k CEN 1µF R1 CTMR 10.5k 330nF 1% CG 47nF 7A –48V A CF 33nF RS 0.008Ω 5% B Figure 2a. 200W AdvancedTCA Hot Swap Controller with Input/Output Monitoring and Power Good Watchdog Using LTC4261 in I2C Mode (Part One) 42612fb 12 LTC4261/LTC4261-2 APPLICATIONS INFORMATION the voltage at VIN to 11.2V (VZ) and provides power to the GATE driver. The data converter and logic control circuits are powered by an internal linear regulator that derives 5V from the 11.2V supply. The 5V output is available at the INTVCC pin for driving external circuits (up to 20mA load current). Bypass capacitors of 1µF and 0.1µF are recommended at VIN and INTVCC, respectively. RIN should be chosen to accommodate the maximum supply current requirement of the LTC4261/LTC4261-2 (5mA) plus the supply current required by any external devices driven by the VIN and INTVCC pins at the minimum intended operation voltage. RIN ≤ V48 V(MIN) – VZ(MAX ) IIN(MAX ) + IEXTERNAL Initial Start-Up and Inrush Control Several conditions must be satisfied before the FET turn-on sequence is started. First the voltage at VIN must exceed its 9V undervoltage lockout level. Next the internal supply INTVCC must cross its 4.25V undervoltage lockout level. This generates a 100µs to 160µs power-on-reset pulse during which the FAULT register bits are cleared and the CONTROL register bits are set or cleared as described in the register section. After the power-on-reset pulse, the voltages at the UVH, UVL and OV pins must satisfy UVH > 2.56V, UVL > 2.291V and OV < 1.77V to indicate that the input power is within the acceptable range and the EN pin must be pulled low. All the above conditions must be satisfied throughout the duration of the start-up debounce delay that is set by an external capacitor (CTMR) connected to the TMR pin. CTMR is charged with a pull-up current of 10µA until the voltage at TMR reaches 2.56V. CTMR is then quickly discharged with a 12mA current. The initial delay expires when TMR is brought below 75mV. The duration of the start-up delay is given by: tD = 256ms • CTMR 1µF The maximum power dissipation in the resistor is: PMAX ( V48V(MAX) – VZ(MIN) )2 = RIN If the power dissipation is too high for a single resistor, use multiple low power resistors in series. –48V RTN OUTPUT A RIN 8 × 240Ω IN SERIES 1/4W EACH OUTPUT SENSE Q11 2N5401 R17 100k 1% R18 100k 1% Q12 2N5401 R4 20k VIN+ VOUT+ LUCENT FLTR100V10 VOUT– VIN– VOUT CASE 5V SUPPLY MONITOR VIN+ VOUT+ VDD MOC207 Q8 R21 1k LTC2900 RST GND CIN 1µF VEE VEE CVCC 0.1µF 7 INTVCC 21 VIN 23 ADIN 22 FLTIN 1 PGI 6 SCL 5 SDAI 28 PGIO 27 PG 4 SDAO 3 ALERT R6 100k R8 7.5k R7A 10k R7B 10k R7 100k R9 5.1k R19 R20 2.49k 2.49k 1% 1% VOUT VEE LUCENT JW050A1-E ON/OFF VIN– VOUT– CASE VEE 5V R22 1k VO R23 1k R24 5.1k CL 4000µF 100V 0V TRANSIENT RESEVOIR CAPACITOR LTC4261CGN Q5 + Q6 Q7 MOC207 Q3 VCC ANODE RL CATHODE VOUT GND HCPL-0300 Q4 VCC ANODE CATHODE GND 6N139 VO VCC ANODE VO CATHODE GND PS9113 VEE VCC ANODE CATHODE GND PS9113 VDD SCL SDA MICROCONTROLLER ALERT RST GND RL 343Ω 7 × 2.4k, 0805 EACH 28.7W VOUT B MBRM5100 42612 F02b Figure 2b. 200W AdvancedTCA Hot Swap Controller with Input/Output Monitoring and Power Good Watchdog Using LTC4261 in I2C Mode (Part Two) 42612fb 13 LTC4261/LTC4261-2 APPLICATIONS INFORMATION If any of the above conditions is violated before the start-up delay expires, CTMR is quickly discharged and the turn-on sequence is restarted. After all the conditions are validated throughout the start-up delay, the ON pin is then checked. If it is high, the FET will be turned on. Otherwise, the FET will be turned on when the ON pin is raised high or the FET ON bit D3 in the CONTROL register is set to “1” through the I2C interface. The FET turn-on sequence follows by charging an external capacitor at the SS pin (CSS) with a 10µA pull-up current and the voltage at SS (VSS) is converted to a current (IGATE(UP)) of 11.5µA· VSS/2.56V for GATE pull-up. When the GATE reaches the FET threshold voltage, the inrush current starts to flow through the FET and a current (IRAMP) of 20µA· VSS/2.56V flows out of the RAMP pin and through an external capacitor (CR) connected between RAMP and VOUT. The SS voltage is clamped to 2.56V, which corresponds to IGATE(UP) = 11.5µA and IRAMP = 20µA. The RAMP pin voltage is regulated at 1.1V and the ramp rate of VOUT determines the inrush current: IINRUSH = 20µA • CL CR Power Good Monitors When VDS of the pass transistor falls below 1.77V and GATE pulls above VZ – 1.2V, an internal power good signal is latched and a series of three delay cycles are started as shown in Figure 3. When the first delay cycle with a duration of 2tD expires, the PG pin pulls low as a power good signal to turn on the first module. When the second delay cycle (2tD) expires, the PGIO pin pulls low as a power good signal to turn on the second module. The third delay cycle with a duration of 4tD is for PGI check. Before the third delay cycle expires, the PGI pin must be pulled low by an external supply monitor (such as the LTC2900 in Figure 2) to keep the FET on. Otherwise, the FET is turned off and the power bad fault (PBAD) is logged in the FAULT register. The 2tD timer delay is obtained by charging CTMR with a 5µA current and discharging CTMR with a 12mA current when TMR reaches 2.56V. For the 4tD timer delay, the charging and discharging currents of CTMR are both 5µA. The power good signals at PG and PGIO are reset in all FET turn-off conditions except the overvoltage fault. Turn-Off Sequence and Auto-Retry In any of the following conditions, the FET is turned off by pulling down GATE with a 110mA current, and CSS and CTMR are discharged with 12mA currents. 1. The ON pin is low or the ON bit in the CONTROL register is set to 0. 2. The EN pin is high. 3. The voltage at UVL is lower than 2.291V and the voltage at UVH is lower than 2.56V (undervoltage fault). 4. The voltage at OV is higher than 1.77V (overvoltage fault). 5. The voltage at VIN is lower than 9V (VIN undervoltage lockout). The ramp rate of VSS determines dI/dt of the inrush current: dIINRUSH C 1µF = 20µA • L • dt CR 256ms • CSS If CSS is absent, an internal circuit pulls the SS pin from 0V to 2.56V in about 220µs. When VOUT is ramped down to VEE, IGATE returns to the GATE pin and pulls the GATE up to VGATEH. Figure 3 illustrates the start-up sequence of the LTC4261/ LTC4261-2. During board insertion and input power step, an internal clamp turns on to hold the RAMP pin low. Capacitor CF and resistor RF suppress the noise at the RAMP pin. For proper operation, RF • CR should not exceed 50µs. The recommended value of CF is 3 • CR. 42612fb 14 LTC4261/LTC4261-2 APPLICATIONS INFORMATION RTN_VEE UVH START-UP DELAY TMR 1x 2x 2x 4x PWRGD1 DELAY PWRGD2 DELAY PGI CHECK DELAY SS GATE VZ – 1.2V VOUT 1.77V 50mV LOAD 1 + LOAD 2 LOAD 1 SENSE INRUSH INTERNAL PWRGD LATCHED PG PWRGD1 READY PGIO PWRGD2 READY POWER BAD PGI NORMAL PGI 42612 F03 Figure 3. LTC4261 Turn-On Sequence 6. The voltage at INTVCC is lower than 4.25V (INTVCC undervoltage lockout). 7. VSENSE > 50mV and the condition lasts longer than 530µs (overcurrent fault). 8. The PGI pin is high when the PGI check timer expires (power bad fault). For conditions 1, 2, 5, 6, after the condition is cleared, the LTC4261/LTC4261-2 will automatically enter the FET turn-on sequence as previously described. For any of the fault conditions 3, 4, 7, 8, the FET off mode is programmable by the corresponding auto-retry bit in the CONTROL register. If the auto-retry bit is set to 0, the FET is latched off upon the fault condition. If the auto-retry bit is set to 1, after the fault condition is cleared, a delay timer is started. After the timer expires, the FET enters the auto-retry mode and GATE is pulled up. The auto-retry delay following the undervoltage fault or the power bad fault has a duration of tD. The autoretry delay following the overcurrent fault has a duration of 4tD for extra cooling time. The auto-retry following the overvoltage fault does not have a delay. The auto-retry control bits and their defaults at power up are listed in Table 6. Note that the LTC4261 defaults to latch-off while the LTC4261-2 defaults to auto-retry following the overcurrent fault. 42612fb 15 LTC4261/LTC4261-2 APPLICATIONS INFORMATION EN and ON Figure 4 shows a logic diagram for EN and ON as they relate to GATE, ALERT and internal registers A4, A7, B4, C4 and D3. Also affecting GATE is the status of UV, OV and several other fault conditions. The EN and ON pins have 0.8V to 2V logic thresholds relative to VEE with a maximum input leakage current of ±2µA. Register bit A4 indicates the present state of EN, and B4 is set high whenever EN changes state. Rising and falling edges at the ON pin set and clear FET-on control bit, D3. Another path allows a falling edge at EN to latch a high state at the ON pin (such as when ON is permanently pulled high) into D3 after a time delay. Both B4 and D3 can be set or cleared directly by I2C, and both are cleared low whenever INTVCC drops below its UVLO threshold. The condition of the GATE pin output is controlled by register bit A7, which is the AND of A4, D3 and the absence of UV, OV and other faults. Overcurrent Protection and Overcurrent Fault The LTC4261/LTC4261-2 feature two levels of protection from short-circuit and overcurrent conditions. Load current is monitored by the SENSE pin and resistor RS. There are two distinct thresholds for the voltage at SENSE: 50mV for engaging the active current limit loop and starting a 530µs circuit breaker timer and 150mV for a fast GATE pull-down to limit peak current in the event of a catastrophic short circuit or an input step. In an overcurrent condition, when the voltage drop across RS exceeds 50mV, the current limit loop is engaged and an internal 530µs circuit breaker timer is started. The current limit loop servos the GATE to maintain a constant output current of 50mV/RS. When the circuit breaker timer expires, the FET is turned off by pulling GATE down with a 110mA current, the capacitors at SS and TMR are discharged and the power good signals are reset. At this time, the overcurrent present bit A2 and the overcurrent fault bit B2 are set, and the circuit breaker timer is reset. After the FET is turned off, the overcurrent present bit A2 is cleared. If the overcurrent auto-retry bit D2 has been set, the FET will turn on again automatically after a cooling time of 4tD. Otherwise, the FET will remain off until the overcurrent fault bit B2 is reset. When the overcurrent fault bit is reset (see Resetting Faults), the FET is allowed to turn on again after a delay of 4tD. The 4tD cooling time associated with the overcurrent fault will not be interrupted by any other fault condition. See Figure 5 for operation of LTC4261/LTC4261-2 under overcurrent condition followed by auto-retry. ABSENCE OF UV/OV AND OTHER FAULTS A4 INTVCC UVLO CLR EN STATE-CHANGE DETECTOR S R/W C4 1 tD TIMER DELAY ON S R/W EDGE DETECTOR Q R CLR D3 I2C ALERT RESPONSE READ ANY REGISTER *B4 • C4 IS ONE OF SEVEN CONDITIONS THAT CAN GENERATE AN ALERT OUTPUT. SEE TABLE 5 42612 F04 A7 GATE ON Q B4 ALERT* S CLR Q ALERT I2C INTVCC UVLO Figure 4. Logic Block Diagram of EN and ON Pins 42612fb 16 LTC4261/LTC4261-2 APPLICATIONS INFORMATION OC COOLING DELAY TMR 4x 2x PWRGD1 DELAY 2x PWRGD2 DELAY SS VZ – 1.2V GATE VOUT 1.77V 50mV SENSE 530µs INRUSH PG PGIO 42612 F05 Figure 5. Overcurrent Fault and Auto-Retry In the case of a low impedance short circuit on the load side or an input step during battery replacement, current overshoot is inevitable. A fast SENSE comparator with a threshold of 150mV detects the overshoot and immediately pulls GATE low with a 110mA current. Once the SENSE voltage drops to 50mV, the current limit loop takes over and servos the current as previously described. If the short-circuit condition lasts longer than 530µs, the FET is shut down and the overcurrent fault is registered. In the case of an input step, after an internal clamp pulls the RAMP pin down to 1.1V, the inrush control circuit takes over and the current limit loop is disengaged before the circuit breaker timer expires. From this point on, the device works as in the initial start-up: VOUT is ramped down at the rate set by IRAMP and CR followed by GATE pull-up. The power good signals on the PG and PGIO pins, the TMR pin, and the SS pin are not interrupted through the input step sequence. The waveform in Figure 6 shows how the LTC4261/LTC4261-2 responds to an input step. Note that the current limit threshold should be set sufficiently high to accommodate the sum of the load current and the inrush current to avoid engagement of the current limit loop in the event of an input step. The maximum value of the inrush current is given by: IINRUSH ≤ 0.8 • 45mV – ILOAD RS where the 0.8 factor is used as a worst case margin combined with the minumum threshold (45mV). The active current limit circuit is compensated using the capacitor CG with a series resistor RG (10Ω) connected between GATE and VEE, as shown in Figure 1. The suggested value for CG is 50nF. This value should work for most pass transistors (Q1). Overvoltage Fault An overvoltage fault occurs when the OV pin rises above its 1.77V threshold. This shuts off the pass transistor immediately, sets the overvoltage present bit A0 and the overvoltage fault bit B0, and pulls the SS pin down. Note that the power good signals are not affected by the overvoltage fault. If the OV pin subsequently falls back below the threshold, the pass transistor will be allowed 42612fb 17 LTC4261/LTC4261-2 APPLICATIONS INFORMATION 72V RTN – VEE 36V 0V 2.56V VGATEH GATE FET VTH TMR SS VOUT 50mV SENSE LOAD PG PGIO 0V 0V LOAD + INRUSH LOAD 42612 F06 Figure 6. –36V to –72V Step Response to turn on again immediately (without delay) unless the overvoltage auto-retry has been disabled by clearing register bit D0. Undervoltage Comparator and Undervoltage Fault The LTC4261/LTC4261-2 provide two undervoltage pins, UVH and UVL, for adjustable UV threshold and hysteresis. The UVH and UVL pins have the following accurate thresholds: For UVH rising, VUVH(TH) = 2.56V, turn on For UVL falling, VUVL(TH) = 2.291V, turn off Both UVH and UVL pins have a minimum hysteresis of δVUV (15mV typical). In either a rising or a falling input supply, the undervoltage comparator works in such a way that both the UVH and the UVL pins have to cross their thresholds for the comparator output to change state. The UVH, UVL, and OV threshold ratio is designed to match the standard telecom operating range of 43V to 71V and UV hysteresis of 4.5V when UVH and UVL are tied together as in Figure 1, where the built-in UV hysteresis referred to the UVL pin is: ΔVUV(HYST) = VUVH(TH) – VUVL(TH) = 0.269V Using R1 = 11.8k, R2 = 16.9k and R3 = 453k as in Figure 1 gives a typical operating range of 43.0V to 70.7V, with an undervoltage shutdown threshold of 38.5V and an overvoltage shutdown threshold of 72.3V. The UV hysteresis can be adjusted by separating the UVH and the UVL pins with a resistor RH (Figure 7). To increase the UV hysteresis, the UVL tap should be placed above the UVH tap as in Figure 7a. To reduce the UV hysteresis, place the UVL tap under the UVH tap as in Figure 7b. UV hysteresis referred to the UVL pin is given by: for VUVL ≥ VUVH, ∆VUVL(HYST ) = ∆VUV(HYST ) + 2.56 V • or for VUVL < VUVH, ∆VUVL(HYST) = ∆VUV(HYST ) – 2.56 V • RH R1+ R2 RH R1+ R2 + RH For VUVL < VUVH, the minimum UV hysteresis allowed is the minimum hysteresis at UVH and UVL: δVUV = 15mV when RH(MAX) = 0.11 • (R1 + R2) The design of the LTC4261/LTC4261-2 protects the UV comparator from chattering even when RH is larger than RH(MAX). An undervoltage fault occurs when the UVL pin falls below 2.291V and the UVH pin falls below 2.56V – δVUV. This activates the FET turn-off and sets the undervoltage 42612fb 18 LTC4261/LTC4261-2 APPLICATIONS INFORMATION –48V RTN R3 453k 1% UVL RH 1.91k 1% UVH R2 15k 1% 0V R1 11.8k 1% – 48V INPUT R1 11.8k 1% –48V INPUT 42612 F07 –48V RTN R3 453k 1% UVH TURN-ON = 46V TURN-OFF = 38.5V HYSTERESIS = 7.5V RH 1.91k 1% UVL R2 15k 1% 0V TURN-ON = 43V TURN-OFF = 41.2V HYSTERESIS = 1.8V Power Bad Fault After the FET is turned on and the power good outputs pull PG and PGIO low, a delay timer with duration of 4tD is started and the level of the PGI pin is checked (Figure 3). If the PGI pin is pulled below its 1.4V threshold before the PGI check timer expires, the FET will remain on. Otherwise, the FET is immediately turned off, the power good signals are reset and the power bad present bit A3 and the power bad fault bit B3 are set. After the FET is turned off, the power bad present bit A3 will be cleared. If the PGI pin is subsequently pulled low, the FET will remain off unless the power bad auto-retry has been enabled by setting bit D4 or the power bad fault bit B3 is cleared. In either of those two conditions, the FET will turn on again following a delay of tD and the PGI pin is checked again as described above. External Fault Monitors The FLTIN pin (SSOP only) and the PGIO pin, when configured as general purpose input, allow monitoring of external fault conditions such as broken fuses. If FLTIN is pulled below its 1.4V threshold, bit B7 in the FAULT register is set. An associated alert bit, C7, is also available in the ALERT register. When the PGIO pin is configured as general purpose input, if the voltage at PGIO is above 1.25V, both bit A6 in the STATUS register and bit B6 in the FAULT register are set, though there is no alert bit associated with this fault. The external fault conditions do not directly affect the GATE control functions. Fault Alerts When any of the fault bits in FAULT register B is set, an optional bus alert can be generated by setting the appropriate bit in the ALERT register C. This allows only selected faults to generate alerts. At power-up the default state is not to alert on faults. If an alert is enabled, the corresponding fault will cause the ALERT pin to pull low. After the bus master controller broadcasts the alert response address, the LTC4261/LTC4261-2 will respond with its address on the SDA line and release ALERT as shown in Figure 14. If there is a collision between two LTC4261’s responding with their addresses simultaneously, then the device with 42612fb (7a) (7b) Figure 7. Adjustment of Undervoltage Thresholds for Larger (7a) or Smaller (7b) Hysteresis present bit A1 and the undervoltage fault bit B1. The power good signals at PG and PGIO are also reset. The undervoltage present bit A1 is cleared when the UVH pin rises above 2.56V and the UVL pin rises above 2.291V + δVUV. After a delay of tD, the FET will turn on again unless the undervoltage auto-retry has been disabled by clearing bit D1. When power is applied to the device, if UVL is below the 2.291V threshold and UVH is below 2.56V – δVUV after INTVCC crosses its undervoltage lock out threshold (4.25V), an undervoltage fault will be logged in the fault register. Because of the compromises of selecting from a table of discrete resistor values (1% resistors in 2% increments, 0.1% resistors in 1% increments), best possible OV and UV accuracy is achieved using separate dividers for each pin. This increases the total number of resistors from three or four to as many as six, but maximizes accuracy, greatly simplifies calculations and facilitates running changes to accommodate multiple standards or customization without any board changes. FET Short Fault A FET short fault will be reported if the data converter measures a current sense voltage greater than or equal to 2mV while the FET is turned off. This condition sets the FET short present bit A5 and the FET short fault bit B5. 19 LTC4261/LTC4261-2 APPLICATIONS INFORMATION the lower address wins arbitration and responds first. The ALERT line will also be released if the device is addressed by the bus master. Once the ALERT signal has been released for one fault, it will not be pulled low again until the FAULT register indicates a different fault has occurred, or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared. Resetting Faults Faults are reset with any of the following conditions. First, writing zeros to the FAULT register B will clear the associated fault bits. Second, the entire FAULT register is cleared when either the ON pin or bit D3 goes from high to low, or if INTVCC falls below its 4.25V undervoltage lockout. Pulling the UVL pin below its 1.21V reset threshold also clears the entire FAULT register. When the UVL pin is brought back above 1.21V but below 2.291V, the undervoltage fault bit B1 is set if the UVH pin is below 2.56V. This can be avoided by holding the UVH pin above 2.56V while toggling the UVL pin to reset faults. Finally, when EN is brought from high to low, all fault bits except bit B4 are cleared. The bit B4 that indicates an EN change of state will be set. Fault bits with associated conditions that are still present (as indicated in the STATUS Register A) cannot be cleared. The FAULT register will not be cleared when auto-retrying. When auto-retry is disabled, the existence of B0 (overvoltage), B1 (undervoltage), B2 (overcurrent) or B3 (power bad) fault keeps the FET off. After the fault bit is cleared and a delay of tD (for B0, B1 and B3) or 4tD (for B4) expires, the FET will turn on again. Note that if the overvoltage fault bit B0 is cleared by writing a zero through I2C, the FET is allowed to turn on without a delay. If auto-retry is enabled, then a high value in A0, A1, A2 or A3 will hold the FET off and the FAULT register is ignored. Subsequently, when the A0, A1, A2 and A3 bits are cleared, the FET is allowed to turn on again. Turning the LTC4261/LTC4261-2 On and Off Many methods of on/off control are possible using the ON, EN, UV/OV, FLTIN or PGIO pins along with the I2C port. The EN pin works well with logic inputs or floating switch contacts; I2C control is intended for systems where the board operates only under command of a central control processor and the ON pin is useful with signals referenced to RTN, as are the UV (UVH, UVL) and OV pins. PGIO and FLTIN control nothing directly, but are useful for I2C monitoring of connection sense or other important signals. On/off control is possible with or without I2C intervention. Further, the LTC4261/LTC4261-2 may reside on either the removable board or on the backplane. Even when operating autonomously, the I2C port can still exercise control over the GATE output, although depending on how they are connected, EN and ON could subsequently override conditions set by I2C. UV, OV and other fault conditions seize control as needed to turn off the GATE output, regardless of the state of EN, ON or the I2C port. Figure 8 shows five configurations of on/off control of the LTC4261/LTC4261-2. Determining factors in selecting a pin configuration for autonomous operation are the polarity and voltage of the controlling signal. Optical Isolation. Figure 8a shows an optoisolator driving the ON pin. Rising and falling edges at the ON pin turn the GATE output on and off. If ON is already high when power is applied, GATE is delayed one tD period. The status of ON can be examined or overridden through the I2C port at register bit D3. This circuit works in both backplane and board resident applications. Logic Control. Figure 8b shows an application using logic signal control. Again, the ON pin is used as an input; all remarks made concerning optoisolator control apply here as well. 42612fb 20 LTC4261/LTC4261-2 APPLICATIONS INFORMATION Ejector Switch or Loop-Through Connection Sense. Floating switch contacts or a connection sense loop also work well with the ON pin, replacing the phototransistor in Figure 8a. If an insertion debounce delay is desired, use the EN pin as shown in Figure 8c. Like Figures 8a and 8b, this circuit works on either side of the backplane connector. Short Pin to RTN. Figure 8d uses the UV divider string to detect board insertion. This method works equally well in both backplane and board resident applications. AdvancedTCA Style Control. Figure 2 shows an ATCA application using EN as the interface to the LTC4261. Register bit A4 allows the I2C port to monitor the status of EN and by setting C4 high, bit B4 can generate an alert to instantly report any changes in the state of EN. I2C Only Control. To lock out EN and ON, use the configuration shown in Figure 8e and control the GATE pin with register bit D3. The circuit defaults off at power up. To default on, connect the ON pin to INTVCC. Either FLTIN or PGIO can be used as an input to monitor a connection sense or other control signal. PGIO is configured as an input by setting register bits D6 and D7 high; its input state is stored at location B6. FLTIN is always an input whose state is available from register bit B7. FLTIN generates an alert if C7 is set high. 5V 1k INTVCC LTC4261 ON 47k –48V VEE –48V EN ON VEE –48V INTVCC LTC4261 EN 10nF 100k EN VEE Data Converter The LTC4261/LTC4261-2 incorporates a 10-bit analogto-digital converter (ADC) that continuously monitors three different voltages at (in the sequence of) SENSE, ADIN2/OV (SSOP/QFN) and ADIN. The voltage between the SENSE pin and VEE is monitored with a 64mV full scale and 62.5µV resolution, and the data is stored in registers E and F. The ADIN and the ADIN2/OV pins are monitored with a 2.56V full scale and 2.5mV resolution. The data for the ADIN2/OV pin is stored in registers G and H. The data for the ADIN pin is stored in registers I and J. The results in registers E, F, G, H, I and J are updated at a frequency of 7.3Hz. Setting CONTROL register bit D5 invokes a test mode that halts updating of these registers so that they can be written to and read from for software testing. By invoking the test mode right before reading the ADC data registers, the 10-bit data separated in two registers are synchronized. The ADIN and ADIN2 pins can be used to monitor input and output voltages of the Hot Swap controller as shown in Figures 1 and 2. LOOP OR SWITCH 1M INTVCC LTC4261 ON (8a) Optoisolator Control (8b) Logic Control –48V RTN 453k INTVCC UVL LTC4261 ON 28.7k –48V INPUT UVH VEE EN DEFAULT ON DEFAULT OFF –48V (8c) Contact Debounce Delay Upon Insertion for Use with an Ejector Switch or Loop-Through Style Connection Sense INTVCC ON EN SDAO LTC4261 SDAI SCL VEE 42612 F08 I2 C (8d) Short Pin Connection Sense to RTN (8e) I2C-Only Control 42612fb Figure 8. On/Off Control of the LTC4261 21 LTC4261/LTC4261-2 APPLICATIONS INFORMATION Configuring the PGIO Pin Table 6 describes the possible states of the PGIO pin using the CONTROL register bits D6 and D7. At power-up the default state is for the PGIO pin to pull low when the second power good signal is ready. Other uses for the PGIO pin are to go high impedence when the second power good is ready, a general purpose output and a general purpose input. When the PGIO pin is configured as a general purpose output, the status of bit C6 is sent out to the pin. When it is configured as a general purpose input, if the input voltage at PGIO is higher than 1.25V, both bit A6 in the STATUS register and bit B6 in the FAULT register are set. If the input voltage at PGIO subsequently drops below 1.25V, bit A6 is cleared. Bit B6 can be cleared by resetting the FAULT register as described previously. Design Example As a design example, consider the 200W application with CL = 330µF as shown in Figure 1. The operating voltage range is from 43V to 71V with a UV turn-off threshold of 38.5V. The design flow starts with calculating the maximum input current: IMAX = 200 W = 5.6 A 36 V The FET is selected to handle the maximum power dissipation during start-up or an input step. The latter usually results in a larger power due to summation of the inrush current charging CL and the load current. For a 36V input step, the total P2t in the FET is approximated by: P2 t = ( 36 V • IMAX ) • 2 t 3 where t is the time it takes to charge up CL: t= CL • 36 V 330µF • 36 V = = 18ms IINRUSH 0.66 A which gives a P2t value of 244W2s. Now the P2t given by the SOA (safe operating area) curves of candidate FETs must be lower than 244W2s. The SOA curves of the IRF1310NS provide for 5A at 50V (250W) for 10ms, which gives a P2t value of 625W2s and satisfies the requirement. Sizing R1, R2 and R3 for the required UV and OV threshold voltages: VUV(RISING) = 43V, VUV(FALLING) = 38.5V, (using VUVH(TH) = 2.56V and VUVH(TH) = 2.291V) VOV(RISING) = 72.3V, VOV(FALLING) = 70.7V (using VOV(TH) = 1.77V rising and 1.7325V falling) Layout Considerations To achieve accurate current sensing, a Kelvin connection is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/square. Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive divider to the UV and OV pins close to the chip and keep traces to VIN and VEE short. A 0.1µF capacitor from the UVH or UVL pin (and OV pin through resistor R2) to VEE helps reject supply noise. where 36V is the minimum input voltage. The selection of the sense resistor, RS, is determined by the minimum current limit threshold and maximum input current: RS = ∆VSENSE(MIN) IMAX IRAMP IINRUSH = 45mV = 8mΩ 5.6 A The inrush current is set to 0.66A using CR: CR = CL • = 330µF • 20µA = 10nF 0.66 A The value of RF and CF are chosen to 1k and 33nF as discussed previously. 42612fb 22 LTC4261/LTC4261-2 APPLICATIONS INFORMATION I2C Interface The LTC4261/LTC4261-2 feature an I2C interface to provide access to the ADC data registers and four other registers for monitoring and control of the pass FET. Figure 9 shows a general data transfer format using the I2C. The LTC4261/LTC4261-2 are read-write slave devices and support SMBus bus Read Byte, Write Byte, Read Word and Write Word commands. The second word in a Read Word command will be identical to the first word. The second word in a Write Word command is ignored. The data formats for these commands are shown in Figures 10 to 13. Using Optoisolators with SDA The LTC4261/LTC4261-2 split the SDA line into SDAI (input) and SDAO (output) for convenience of opto-coupling with the host. If optoisolators are not used then tie SDAI and SDAO together to form a normal SDA line. When using optoisolators, connect the SDAI to the output of the incoming optoisolator and connect the SDAO to the input of the outgoing optoisolator (see Figure 2). If the ALERT Stuck-Bus Reset The LTC4261/LTC4261-2 I2C interface features a stuckbus reset timer. The low conditions of the SCL and the SDAI pins are ORed to start the timer. The timer is reset when both SCL and SDAI are pulled high. If the SCL pin or the SDAI pin is held low for over 66ms, the stuck-bus timer will expire and the internal I2C state machine will be line is used as an interrupt for the host to respond to a fault in real time, connect the ALERT to an optoisolator in a way similar to that for the SDAO as shown in Figure 2. START and STOP Conditions When the bus is idle, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transiting SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transiting SDA from low to high while SCL is high. The bus is then free for another transmission. SDA a6 - a0 b7 - b0 b7 - b0 SCL S 1-7 8 9 1-7 8 9 1-7 8 9 P START CONDITION ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION 42612 F09 Figure 9. Data Transfer over I2C or SMBus S ADDRESS W A 0 0 1 a3:a0 0 0 COMMAND X X X X b3:b0 A DATA A P 0 b7:b0 0 S ADDRESS W A 0 0 1 a3:a0 0 0 COMMAND X X X X b3:b0 A DATA A 0 b7:b0 0 DATA XXXXXXXX AP 0 42612 F11 FROM MASTER TO SLAVE FROM SLAVE TO MASTER A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION 42612 F10 Figure 11. LTC4261 Serial Bus SDA Write Word Protocol S ADDRESS W A 0 0 1 a3:a0 0 0 COMMAND X X X X b3:b0 AS 0 ADDRESS R A DATA A P 42612 F12 0 0 1 a3:a0 1 0 b7:b0 1 Figure 10. LTC4261 Serial Bus SDA Write Byte Protocol S ADDRESS W A 0 0 1 a3:a0 0 0 COMMAND X X X X b3:b0 AS 0 Figure 12. LTC4261 Serial Bus SDA Read Byte Protocol ADDRESS R A DATA A DATA A P 42612 F13 0 0 1 a3:a0 1 0 b7:b0 0 b7:b0 1 Figure 13. LTC4261 Serial Bus SDA Read Word Protocol 42612fb 23 LTC4261/LTC4261-2 APPLICATIONS INFORMATION reset to allow normal communication after the stuck-low condition is cleared. When the SCL pin and the SDAI pin are held low alternatively, if the ORed low period of SCL and SDAI exceeds 66ms before the timer reset condition (both SCL and SDAI are high) occurs, the stuck-bus timer will expire and the I2C state machine is reset. I2C Device Addressing Any of eight distinct I2C bus addresses are selectable using the three-state pins ADR0 and ADR1, as shown in Table 1. Note that the configuration of ADR0 = L and ADR1 = H is used to enable the single-wire broadcasting mode. For the eight I2C bus addresses, address bits B6, B5 and B4 are configured to (001) and the least significant bit B0 is the R/W bit. In addition, the LTC4261/LTC4261-2 will respond to two special addresses. Address (0011 111) is a mass write used to write to all LTC4261/LTC4261-2s, regardless of their individual address settings. Address (0001 100) is the SMBus Alert Response Address. If the LTC4261/LTC4261-2 are pulling low on the ALERT pin, it will acknowledge this address using the SMBus Alert Response Protocol. Acknowledge The acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it must pull down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA HIGH, then the master can abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master must pull down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received the master will leave the SDA line HIGH (not acknowledge) and issue a STOP condition to terminate the transmission. Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero. The addressed LTC4261/LTC4261-2 acknowledge this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4261/LTC4261-2 acknowledge this and then latch the lower four bits of the command byte into its internal Register Address pointer. The master then delivers the data byte and the LTC4261/LTC4261-2 acknowledge once more and latch the data into its internal register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte will be acknowledged by the LTC4261/ LTC4261-2 but ignored. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address and the R/W bit set to zero. The addressed LTC4261/LTC4261-2 acknowledge this and then the master sends a command byte that indicates which internal register the master wishes to read. The LTC4261/LTC4261-2 acknowledge this and then latch the lower four bits of the command byte into its internal Register Address pointer. The master then sends a repeated START condition followed by the same seven bit address with the R/W bit now set to one. The LTC4261/LTC4261-2 acknowledge and send the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command, the LTC4261/LTC4261-2 will repeat the requested register as the second data byte. Note that the Register Address pointer is not cleared at the end of the transaction. Thus the Receive Byte protocol can be used to repeatedly read a specific register. Alert Response Protocol The LTC4261/LTC4261-2 implement the SMBus Alert Response Protocol as shown in Figure 14. If enabled to do so through the ALERT register C, the LTC4261/ LTC4261-2 will respond to faults by pulling the ALERT pin low. Multiple LTC4261/LTC4261-2s can share a common ALERT line and the protocol allows a master to determine which LTC4261/LTC4261-2s are pulling the line low. The master begins by sending a START bit followed by the special Alert Response Address (0001 100)b with 42612fb 24 LTC4261/LTC4261-2 APPLICATIONS INFORMATION ALERT DEVICE S RESPONSE R A AP ADDRESS ADDRESS 0 0 0 1 1 0 0 1 0 0 0 1 a3:a0 0 1 42612 F14 this means repeated or continuing faults will not generate alerts until the associated FAULT register bit has been cleared. Single-Wire Broadcast Mode The LTC4261/LTC4261-2 provides a single-wire broadcast mode in which selected register data are sent out to the SDAO pin without clocking the SCL line (Figure 15). The single-wire broadcast mode is enabled by setting the ADR1 pin high and the ADR0 pin low (the I2C interface is disabled). At the end of each conversion of the three ADC channels, a stream of eighteen bits are broadcasted to SDAO with a serial data rate of 15.3kHz ±20% in a format as illustrated in Figure 16. The data bits are encoded with an internal clock in a way similar to Manchester encoding that can be easily decoded by a microcontroller or FPGA. Each data bit consists of a noninverting phase and an inverting phase. During the conversion of each ADC channel, SDAO is idle at high. At the end of the conversion, the SDAO pulls low. The START bit indicates the beginning of data broadcasting and is used along with the dummy bit Figure 14. LTC4261 Serial Bus SDA Alert Response Protocol the R/W bit set to one. Any LTC4261/LTC4261-2 that is pulling its ALERT pin low will acknowledge and begin sending back its individual slave address. An arbitration scheme ensures that the LTC4261/ LTC4261-2 with the lowest address will have priority; all others will abort their response. The successful responder will then release its ALERT pin while any others will continue to hold their ALERT pins low. Polling may also be used to search for any LTC4261/LTC4261-2 that have detected faults. Any LTC4261/LTC4261-2 pulling its ALERT pin low will also release it if it is individually addressed during a read or write transaction. The ALERT signal will not be pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that –48V RTN 6 × 0.51k IN SERIES 1/4W EACH 5V INTVCC VIN SDAI ADR1 SCL ADR0 LTC4261 0.1µF VEE SDAO 7.5k VCC ANODE RL CATHODE VOUT GND HCPL-0300 42612 F15 1µF V DIN DD MICROCONTROLLER –48V INPUT Figure 15. Single-Wire Broadcast Mode INTERNAL CLK DATA START DMY CH1 CH0 ADC9 .. .. .. ADC0 OC UV OV PRTY ADC9 ADC9 ADC0 ADC0 PRTY SDAO PRTY 4261 F16 CH1 CH1 CH0 CH0 UV UV START Figure 16. Single-Wire Broadcast Data Format 42612fb OV OV 0C 0C 25 LTC4261/LTC4261-2 APPLICATIONS INFORMATION (DMY) to measure the internal clock cycle (i.e., the serial data rate). Following the DMY bit are two channel code bits CH1 and CH0 labeling the ADC channel (see Table 10). Ten data bits of the ADC channel (ADC9-0) and three FAULT register bits (B2, B1 and B0) are then sent out. A parity bit (PRTY) ends each data stream. After that the SDAO line enters the idle mode with SDAO pulled high. The following data reception procedure is recommended: 0. Wait for INTVCC rising edge. 1. Wait for SDAO falling edge. 2. The first falling edge could be a glitch, so check again after a delay of 10µs. If back to high, wait again. If still low, it is the START bit. 3. Use the following low-to-high and high-to-low transistions to measure 1/2 of the internal clock cycle. 4. Wait for the second low-to-high transistion (middle of DMY bit). 5. Wait 3/4 of a clock cycle. 6. Sample bit CH1, wait for transistion. 7. Wait 3/4 of a clock cycle. 8. Sample bit CH0, wait for transistion. 9. Wait 3/4 of a clock cycle. 10. Sample ADC9, wait for transistion. 11. Continue until all bits are read. The above procedure can be ported to a microcontroller or used to design a state machine in FPGA. Code should have timeouts in case an edge is missed. Abort the read if it takes more than double the typical time (1.2ms) for all 18 bits to be clocked out. A typical application circuit with the LTC4261/LTC4261-2 in the broadcast mode is illustrated in Figure 17, where input voltage, VDS of the FET and VSENSE are monitored. Register Addresses and Contents The register addresses and contents are summerized in Table 1 and Table 2. The function of each register bit is detailed in Tables 3 to 9. 42612fb 26 LTC4261/LTC4261-2 APPLICATIONS INFORMATION Table 1. LTC4261 Device Addressing DESCRIPTION HEX DEVICE ADDRESS BINARY DEVICE ADDRESS 1 1 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 R/W 0 1 X X X X X X X X LTC4261 ADDRESS PINS ADR1 X X L L H L NC NC H NC H ADR0 X X L NC NC H L NC H H L h 6 5 4 3 2 Mass Write 3E 0 0 1 1 1 Alert Response 19 0 0 0 1 1 0 20 0 0 1 0 0 1 22 0 0 1 0 0 2 24 0 0 1 0 0 3 26 0 0 1 0 0 4 28 0 0 1 0 1 5 2A 0 0 1 0 1 6 2C 0 0 1 0 1 7 2E 0 0 1 0 1 8 Single-Wire Broadcast Mode H = Tie to INVCC; L = Tie to VEE; NC = No connect, open; X = Don’t care Table 2. LTC4261 Register Address and Contents REGISTER ADDRESS* 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h REGISTER NAME STATUS (A) FAULT (B) ALERT (C) CONTROL (D) SENSE (E) SENSE (F) ADIN2/OV (G) ADIN2/OV (H) ADIN (I) ADIN (J) READ/WRITE R R/W R/W R/W R/W** R/W** R/W** R/W** R/W** R/W** DESCRIPTION System Status Information Fault Log and PGIO Input Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register Controls Whether the Part Retries After Faults, Set the On/Off Switch State ADC Current Sense Voltage Data (8 MSBs) ADC Current Sense Voltage Data (2 LSBs) ADC ADIN2/OV (SSOP/QFN) Voltage Data (8 MSBs) ADC ADIN2/OV (SSOP/QFN) Voltage Data (2 LSBs) ADC ADIN Voltage Data (8 MSBs) ADC ADIN Voltage Data (2 LSBs) *Register address MSBs b7-b4 are ignored. **Writable if bit D5 set. 42612fb 27 LTC4261/LTC4261-2 APPLICATIONS INFORMATION Table 3. STATUS Register A (00h)—Read Only BIT A7 A6 A5 A4 A3 A2 A1 A0 NAME FET On PGIO Input FET Short EN Power Bad Overcurrent Undervoltage Overvoltage OPERATION Indicates State of FET; 1 = FET On, 0 = FET Off Indicates State of the PGIO Pin when Configured to General Purpose Input: 1 = PGIO High, 0 = PGIO Low Indicates Potential FET Short if Current Sense Voltage Exceeds 2mV While FET is Off; 1 = FET is Shorted, 0 = FET is Not Shorted Indicates State of the EN Pin; 1 = EN Pin High, 0 = EN Pin Low Indicates Power is Bad when PGI is High at the End of the PGI Check Timer; 1 = PGI High, 0 = PGI Low Indicates Overcurrent Condition; 1 = Overcurrent, 0 = Not Overcurrent Indicates Input Undervoltage when Both UVH and UVL are Low; 1 = UVH and UVL Low, 0 = UVH or UVL High Indicates Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low Table 4. FAULT Register B (01h)—Read/Write BIT B7 B6 B5 B4 B3 B2 B1 B0 NAME External Fault Occurred PGIO Input High Occurred FET Short Fault Occurred EN Changed State Power Bad Fault Occurred Overcurrent Fault Occurred Undervoltage Fault Occurred Overvoltage Fault Occurred OPERATION Latched to 1 if FLTIN Goes Low; 1 = FLTIN Low State Detected, 0 = FLTIN has Not Been Low Latched to 1 if the PGIO Pin Goes High when Configured to General Purpose Input; 1 = PGIO High Detected, 0 = PGIO has Been Low Indicates Potential FET Short was Detected When Measured Current Sense Voltage Exceeded 2mV While FET was Off; 1 = FET Short Fault Occurred, 0 = No FET Short Fault Indicates That a Board was Inserted or Extracted when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged Indicates Power was Bad when PGI was High at the End of the PGI Check Timer; 1 = Power Bad Fault Occurred, 0 = No Power Bad Fault Indicates Overcurrent Fault Occurred; 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Fault Indicates Input Undervoltage Fault Occurred when Both UVH and UVL went Low; 1 = Undervoltage Fault Occurred, 0 = No Undervoltage Fault Indicates Input Overvoltage Fault Occurred when OV was High; 1 = Overvoltage Fault Occurred, 0 = No Overvoltage Fault Table 5. ALERT Register C (02h)—Read/Write BIT C7 C6 C5 C4 C3 C2 C1 C0 NAME External Fault Alert PGIO Output FET Short Alert EN State Change Alert Power Bad Alert Overcurrent Alert Undervoltage Alert Overvoltage Alert OPERATION Enables Alert for External Fault When FLTIN was Low; 1 = Enable Alert, 0 = Disable Alert (Default) Output Data Bit to PGIO Pin when Configured as Output. Defaults to 0 Enables Alert for FET Short Fault; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert when EN Changed State; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Power Bad Fault; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Overcurrent Fault; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Undervoltage Fault; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Overvoltage Fault; 1 = Enable Alert, 0 Disable Alert (Default) 42612fb 28 LTC4261/LTC4261-2 APPLICATIONS INFORMATION Table 6. CONTROL Register D (03h)—Read/Write BIT D7:6 NAME PGIO Configure OPERATION Configures Behavior of PGIO Pin FUNCTION Power Good (Default) Power Good General Purpose Output General Purpose Input D5 D4 D3 D2 D1 D0 Test Mode Enable Power Bad Auto-Retry FET On Control Overcurrent Auto-Retry Undervoltage Auto-Retry Overvoltage Auto-Retry D6 0 0 1 1 D7 0 1 0 1 PGIO PIN Open Drain Open Drain PGIO = C6 PGIO = Hi-Z Test Mode Halts ADC Operation and Enables Writes to ADC Registers; 1 = Enable Test Mode, 0 = Disable Test Mode (Default) Enables Auto-Retry After a Power Bad Fault; 1 = Retry Enabled, 0 = Retry Disabled (Default) Turns FET On and Off; 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Start-Up Debounce Delay Enables Auto-Retry After an Overcurrent Fault; 1 = Retry Enabled (Default, LTC4261-2), 0 = Retry Disabled (Default, LTC4261) Enables Auto-Retry After an Undervoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled Enables Auto-Retry After an Overvoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled Table 7. SENSE Registers E (04h) and F (O5h)—Read/Write BIT E7:0, F7:6 F5:0 NAME SENSE Voltage Data Reserved OPERATION 10-Bit Data of Current Sense Voltage with 62.5µV LSB and 64mV Full Scale Always Returns 0, Not Writable Table 8. ADIN2/OV Registers G (06h) and H (O7h)—Read/Write BIT G7:0, H7:6 H5:0 NAME Reserved OPERATION Always Returns 0, Not Writable ADIN2/OV Voltage Data 10-Bit Data of ADIN2/OV (SSOP/QFN) Voltage with 2.5mV LSB and 2.56V Full Scale Table 9. ADIN Registers I (08h) and J (O9h)—Read/Write BIT I7:0, J7:6 J5:0 NAME ADIN Voltage Data Reserved OPERATION 10-Bit Data of ADIN Voltage with 2.5mV LSB and 2.56V Full Scale Always Returns 0, Not Writable Table 10. ADC Channel Labeling for Single-Wire Broadcast Mode CH1 0 0 1 CH0 0 1 0 ADC CHANNEL SENSE Voltage ADIN2/OV (SSOP/QFN) Voltage ADIN Voltage 42612fb 29 LTC4261/LTC4261-2 PACKAGE DESCRIPTION GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .386 – .393* (9.804 – 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615 .045 ± .005 .033 (0.838) REF .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT .0250 BSC 1 .0532 – .0688 (1.35 – 1.75) 23 4 56 7 8 9 10 11 12 13 14 .004 – .0098 (0.102 – 0.249) .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN28 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 42612fb 30 LTC4261/LTC4261-2 PACKAGE DESCRIPTION UFD Package 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696 Rev A) 0.70 ± 0.05 4.50 ± 0.05 3.10 ± 0.05 2.00 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.00 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 R = 0.05 TYP 2.00 REF R = 0.115 TYP 23 PIN 1 NOTCH R = 0.20 OR C = 0.35 24 0.40 ± 0.10 1 2 5.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 3.00 REF 3.65 ± 0.10 2.65 ± 0.10 (UFD24) QFN 0506 REV A 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 42612fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4261/LTC4261-2 TYPICAL APPLICATIONS –48V RTN R3 432k 1% UVL UVH ADIN2 OV ADR1 ADR0 CIN 1mF VEE CVCC 0.1mF R6 10k 1% INTVCC RIN 6 ´ 0.51k IN SERIES 1/4W EACH R4 7.5k 5V VIN R2 15.8k 1% R1 11.5k 1% SDAI SCL LTC4261CGN SDAO ADIN SENSE GATE RS 0.02W 5% Q1 IRF1310NS VCC ANODE RL CATHODE VOUT GND HCPL-0300 V DIN DD MICROCONTROLLER CL 330mF 100V –48V INPUT VEE VOUT R7 402k 1% 4261 F17 Figure 17. Application Circuit of the LTC4261 in Single-Wire Broadcast Mode –48V RTN 6 × 0.51k IN SERIES 1/4W EACH VISHAY 2381 615 4.104 • 100k AT 25°C 1% 30.1k 1% VIN LTC4261CGN ADIN SDAO SDAI SCL VEE I2C 10k 1% –48V INPUT 1µF 42612 F18 T (°C) = 38.05 × (VADIN (V) – 0.1458), 20°C < T < 60°C Figure 18. Using the LTC4261 and a Thermistor to Monitor Temperature RELATED PARTS PART NUMBER LT1640AH/LT1640AL LTC1921 LT4250L/LT4250H LTC4251/LTC4251-1 DESCRIPTION Negative High Voltage Hot Swap Controllers in SO-8 Dual –48V Supply and Fuse Monitor –48V Hot Swap Controllers in SO-8 –48V Hot Swap Controllers in SOT-23 COMMENTS Negative High Voltage Supplies from –10V to –80V UV/OV Monitor, –10V to –80V Operation, MSOP Package Active Current Limiting, Supplies from –20V to –80V Fast Active Current Limiting, Supplies from –15V Fast Active Current Limiting, Supplies from –15V, ±1% UV/OV (LTC4252A) Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies from –15V With I2C and ADC, Supplies from 8.5V to 80V Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation LTC4252-1/LTC4252-2 –48V Hot Swap Controllers in MS8 LTC4252A-1/LTC4252A-2 LTC4253 LTC4260 LTC4354 –48V Hot Swap Controller with Sequencer Positive High Voltage Hot Swap Controller Negative Voltage Diode-OR Controller and Monitor 42612fb 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0706 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005