LTC4265IDE-TRPBF

LTC4265 IEEE 802.3at High Power PD Interface Controller with 2-Event Classification Recognition FEATURES n n n n n n n n n n DESCRIPTION The LTC®4265 is a 3rd generation Powered Device (PD) Interface controller intended for IEEE 802.3at high power Power-over-Ethernet (PoE) applications up to 25.5W. By supporting 1-event and 2-event classification signaling as defined by IEEE 802.3, the LTC4265 can be used in a wide range of product configurations. A 100V MOSFET isolates the DC/DC converter during detection and classification, and provides 100mA inrush current for a smooth powerup transition. The LTC4265 also includes complementary power good outputs, an on-board signature resistor, undervoltage/overvoltage lockout and comprehensive thermal protection. All Linear Technology PD solutions include a shutdown pin with signature corrupt to provide flexible auxiliary power options. The LTC4265 PD interface controller can be used along with a variety of DC/DC converter products to provide a complete, cost effective power solution for high power PD applications. The LTC4265 is available in the space-saving low profile (4mm × 3mm) DFN package and is drop-in compatible with the LTC4264. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. IEEE 802.3af/at Powered Device (PD) Controller IEEE 802.3at 2-event Classification Signaling Programmable Classification Current Flexible Auxiliary Power Support Using SHDN Pin Rugged 100V Onboard MOSFET with 100mA Inrush Current Limit. Complementary Power Good Outputs Onboard Signature Resistor Comprehensive Thermal Protection Undervoltage and Overvoltage Lockout 12-Lead, 4mm × 3mm DFN Package APPLICATIONS n n n n 802.11n Access Points High Power VoIP Video Phones RFID Reader Systems PTZ Security Cameras and Surveillance Equipment TYPICAL APPLICATION Turn-On vs Time ~ ~ ~ 54V FROM SPARE PAIR 54V FROM DATA PAIR + 0.1μF GND – VIN 50V/DIV LTC4265 GND RCLASS PWRGD RCLASS SHDN VIN PWRGD 5μF MIN CLOAD = 100μF + – + – V+ SWITCHING POWER SUPPLY RUN RTN + 3.3V TO LOGIC GND – VOUT 50V/DIV PWRGD – VOUT 50V/DIV IPD 100mA/DIV TIME 25ms/DIV ~ T2PSE VOUT – TO LOGIC 4265 TA01a TO AUX 4265 TA01b 4265f 1 LTC4265 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3) PIN CONFIGURATION TOP VIEW SHDN T2PSE RCLASS NC VIN VIN 1 2 3 4 5 6 13 12 GND 11 NC 10 PWRGD 9 8 7 PWRGD VOUT VOUT GND Voltage ............................................ –0.3V to 100V VOUT Voltage ........................–0.3V to 100V (and ≤ GND) VOUT Pull-Up Current ..................................................1A SHDN ....................................................... –0.3V to 100V RCLASS, Voltage ............................................ –0.3V to 7V RCLASS Current.......................................................50mA PWRGD Voltage (Note 4) Low Impedance Source .....VOUT – 0.3V to VOUT +11V Pull-Up Current ....................................................5mA PWRGD, T2PSE Voltage........................... –0.3V to 100V PWRGD, T2PSE Pull-Up Current ............................10mA Junction Temperature ........................................... 125°C Operating Ambient Temperature Range LTC4265C ................................................ 0°C to 70°C LTC4265I.............................................. –40°C to 85°C DE PACKAGE 12-LEAD (4mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) TO BE SOLDERED TO PCB HEAT SINK ORDER INFORMATION LEAD FREE FINISH LTC4265CDE#PBF LTC4265IDE#PBF TAPE AND REEL LTC4265CDE#TRPBF LTC4265IDE#TRPBF PART MARKING* 4265 4265 PACKAGE DESCRIPTION 12-Lead (4mm × 3mm) Plastic DFN 12-Lead (4mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4265f 2 LTC4265 ELECTRICAL CHARACTERISTICS PARAMETER Operating Input Voltage Signature Range Classification Range Turn-On Voltage Undervoltage Lock Out Overvoltage Lock Out ON/UVLO Hysteresis Window Signature/Class Hysteresis Window Reset Threshold SUPPLY CURRENT Supply Current at 60V Class 0 Current SIGNATURE Signature Resistance Invalid Signature Resistance, SHDN Invoked CLASSIFICATION Class Accuracy Classification Stability Time NORMAL OPERATION Inrush Current Power FET On Resistance Power FET Leakage Current at VOUT DIGITAL INTERFACE SHDN Input High Level Voltage SHDN Input Low Level Voltage SHDN Input Resistance PWRGD, T2PSE Voltage Output Low PWRGD, T2PSE Leakage Current PWRGD Voltage Output Low PWRGD Voltage Clamp PWRGD Leakage Current GND = 9.8V, SHDN = 9.65V Tested at 1mA, GND = 54V. For T2PSE, Must Complete 2-event Classification to See Active Low. Pin Voltage Pulled 57V, GND = VIN = 0 Tested at 0.5mA, GND = 52V, VOUT = 48V, Output Voltage is with Respect to VOUT Tested at 2mA, VOUT = 0V, Voltage with Respect to VOUT VPWRGD = 11V, VOUT = VIN = 0V, GND = 54V l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS At GND Pin (Note 5) l l l l l l l l l MIN 1.5 12.5 30.0 TYP MAX 60 9.8 21 37.2 UNITS V V V V V V V V 71 4.1 1.4 2.57 5.40 1.35 0.40 23.25 26 11 11 ±3.5 1 State Machine Reset for 2-event Classification Measured at GND Pin GND = 17.5V, No RCLASS Resistor 1.5V ≤ GND ≤ 9.8V (Note 6) 1.5V ≤ GND ≤ 9.8V, VSHDN = 3V (Note 6) V mA mA kΩ kΩ kΩ % ms l l l l l Invalid Signature Resistance During Mark Event (Notes 6, 7) 10mA < ICLASS < 40mA, 12.5V < GND < 21V (Note 8, 9) GND Pin Step to 17.5V, RCLASS = 30.9, ICLASS Within 3.5% of Ideal Value (Notes 8, 9) GND = 54, VOUT = 3V Tested at 600mA into VOUT, GND = 54V GND = SHDN = VOUT = 57V l l l 60 100 0.70 180 1.0 1 mA Ω μA V 3 0.45 100 0.15 1 0.4 12 16.5 1 V kΩ V μA V V μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to VIN pin unless otherwise noted. Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V. Note 4: PWRGD voltage clamps at 14V with respect to VOUT. Note 5: Input voltage specifications are defined with respect to LTC4265 pins and meet IEEE 802.3af/at specifications when the input diode bridge is included. Note 6: Signature resistance is measured via the ΔV/ΔI method with a minimum ΔV of 1V. The LTC4265 signature resistance accounts for the additional series resistance in the input diode bridge. Note 7: An invalid signature after the 1st classification event is mandated by IEEE 802.3at standard. See Applications Information. Note 8: Class accuracy is with respect to the ideal current defined as 1.237/RCLASS and does not include variations in RCLASS resistance. Note 9: This parameter is assured by design and wafer level testing. 4265f 3 LTC4265 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range 0.5 TA = 25°C 50 Input Current vs Input Voltage TA = 25°C CLASS 4 INPUT CURRENT (mA) 10.5 11.0 Input Current vs Input Voltage CLASS 1 OPERATION 0.4 INPUT CURRENT (mA) INPUT CURRENT (mA) 40 0.3 30 CLASS 3 CLASS 2 CLASS 1 85°C –40°C 10.0 0.2 20 0.1 10 CLASS 0 0 0 0 2 4 6 GND VOLTAGE (V) 8 10 4265 G01 0 10 20 30 40 GND VOLTAGE (V) (RISING) 50 60 9.5 12 14 18 16 GND VOLTAGE (V) 20 22 4265 G03 4265 G02 Signature Resistance vs Input Voltage 28 RESISTANCE = V = V2 – V1 I I 2 – I1 27 DIODES: HD01 TA = 25°C IEEE UPPER LIMIT LTC4265 + 2 DIODES 25 24 LTC4265 ONLY 23 IEEE LOWER LIMIT CLASS CURRENT 10mA/DIV INPUT VOLTAGE 10V/DIV Class Operation vs Time TA = 25°C 1.0 RESISTANCE (Ω) On Resistance vs Temperature SIGNATURE RESISTANCE (kΩ) 26 0.8 0.6 0.4 22 V1: 1 V2: 2 3 4 7 5 8 6 GND VOLTAGE (V) 9 10 4265 G04 TIME (10μs/DIV) 4265 G05 0.2 –50 75 0 25 50 –25 JUNCTION TEMPERATURE (°C) 100 4265 G06 PWRGD, T2PSE Output Low Voltage vs Current 0.8 TA = 25°C 1.0 Active High PWRGD Output Low Voltage vs Current TA = 25°C GND – VOUT = 4V 115 110 105 100 95 90 85 Inrush Current vs Input Voltage 0.6 VPWRGD (V) VT2PSE (V) PWRGD (V) 0.8 CURRENT (mA) 0 0.5 1 1.5 CURRENT (mA) 2 4265 G08 0.6 0.4 0.4 0.2 0.2 0 0 2 6 4 CURRENT (mA) 8 10 4265 G07 0 40 45 50 55 GND VOLTAGE (V) 60 4265 G09 4265f 4 LTC4265 PIN FUNCTIONS SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary power application. Drive SHDN high to disable LTC4265 operation and corrupt the signature resistance. If unused, tie SHDN to VIN. T2PSE (Pin 2): Type-2 PSE Indicator, Open-Drain. Low impedance indicates the presence of a Type-2 PSE. RCLASS (Pin 3): Class Select Input. Connect a resistor between RCLASS and VIN to set the classification load current. (See Table 2.) NC (Pin 4, 11): No Connect. VIN (Pins 5, 6): Input Voltage, Negative Rail. Pins 5 and 6 must be electrically tied together at the package. VOUT (Pins 7, 8): Output Voltage Negative Rail. Connects VOUT to VIN through an internal power MOSFET. Pins 7 and 8 must be electrically tied together at the package. PWRGD (Pin 9): Power Good Output, Open Collector. High impedance signals power-up completion. PWRGD is referenced to VOUT and features a 14V clamp. PWRGD (Pin 10): Complementary Power Good Output, Open-Drain. Low impedance signals power up completion. PWRGD is referenced to VIN. GND (Pin 12): Input Voltage, Positive Rail. This pin is connected to the PD positive rail. Exposed Pad (Pin 13): Tie to VIN and PCB heat sink. BLOCK DIAGRAM SHDN 1 CLASSIFICATION CURRENT LOAD 12 GND REF T2PSE 2 + – EN 25k 14k 11 NC RCLASS 3 NC 4 CONTROL CIRCUITS 10 PWRGD 9 PWRGD VIN 5 VIN 6 EXPOSED PAD 13 BOLD LINE INDICATES HIGH CURRENT PATH 8 VOUT 7 VOUT 4265 BD 4265f 5 LTC4265 APPLICATIONS INFORMATION OVERVIEW Power over Ethernet (PoE) continues to gain popularity as more products are taking advantage of having DC power and high speed data available from a single RJ45 connector. As PoE continues to grow in the marketplace, Powered Device (PD) equipment vendors are running into the 12.95W power limit established by the IEEE 802.3af standard. The IEE802.3at standard establishes a higher power allocation for Power-over-Ethernet while maintaining backwards compatibility with the existing IEEE802.3af systems. Power Sourcing Equipments (PSE) and Powered Devices are distinguished as Type-1 complying with the IEEE 802.3af power levels, or Type-2 complying with the IEEE 802.3at power levels. The maximum available power of a Type-2 PD is 25.5W. The IEEE802.3at standard also establishes a new method of acquiring power classification from a PD and communicating the presence of a Type-2 PSE. A Type-2 PSE has the option of acquiring PD power classification by performing 2-event classification (Layer 1) or by communicating with the PD over the data line (Layer 2). In turn, a Type-2 PD must be able to recognize both layers of communications and identify a Type-2 PSE. The LTC4265 is specifically designed to support the front end of a PD that must operate under the IEEE802.3at standard. In particular, the LTC4265 provides the T2PSE indicator bit which recognizes 2-event classification. This indicator bit may be used to alert the LTC4265 output load that a Type-2 PSE is present. With an internal signature resistor, classification circuitry, inrush control, and thermal shutdown, the LTC4265 is a complete PD Interface solution capable of supporting in the next generation PD applications. MODES OF OPERATION The LTC4265 has several modes of operation depending on the input voltage applied between the GND and VIN pins. Figure 1 presents an illustration of voltage and current waveforms the LTC4265 may encounter with the various modes of operation summarized in Table 1. IIN PSE RCLASS VIN GND (V) 50 40 30 20 10 CLASSIFICATION DETECTION V2 DETECTION V1 dV = INRUSH dt C1 UVLO ON UVLO = RLOAD C1 TIME TIME GND – PWRGD (V) –10 –20 –30 –40 –50 POWER BAD PWRGD TRACKS GND POWER BAD PWRGD TRACKS GND PWRGD TRACKS VIN ON UVLO TIME 50 GND – VOUT (V) 40 30 20 10 POWER GOOD PWRGD – VOUT (V) 20 10 POWER BAD POWER GOOD POWER BAD IN DETECTION RANGE TIME INRUSH LOAD, ILOAD PD CURRENT CLASSIFICATION DETECTION I2 DETECTION I1 I1 = V1 – 2 DIODE DROPS V2 – 2 DIODE DROPS I2 = 25kΩ 25kΩ TIME ICLASS DEPENDENT ON RCLASS SELECTION INRUSH = 100mA ILOAD = VIN RLOAD GND LTC4265 RCLASS GND PWRGD PWRGD VOUT 4265 F01 RLOAD C1 VOUT Figure 1. Output Voltage, PWRGD, PWRGD and PD Current as a Function of Input Voltage 4265f 6 LTC4265 APPLICATIONS INFORMATION These modes satisfy the requirements defined in the IEEE 802.3af/at specification. Table 1. LTC4265 Modes of Operation as a Function of Input Voltage GND (V) 0V to 1.4V 1.5V to 9.8V (5.4V to 9.8V) LTC4265 MODES OF OPERATION Inactive (Reset After 1st Classification Event) 25k Signature Resistor Detection Before 1st Classification Event (Mark, 11k Signature Corrupt After 1st Classification Event) Inrush and Power Applied To PD Load Overvoltage Lockout, 4265 Operations are Disabled The input diode bridge introduces a voltage drop that affects the range for each mode of operation. The LTC4265 compensates for these voltage drops so that a PD built with the LTC4265 meets the IEEE 802.3af/at-established voltage ranges. Note that the Electrical Specifications reference with respect to the LTC4265 package pins. DETECTION During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply two voltages in the range of 2.8V to 10V and measures the corresponding currents. Figure 1 shows the detection voltages V1 and V2 and the corresponding PD current. The PSE calculates the signature resistance using the ΔV/ΔI measurement technique. The LTC4265 presents its precision, temperature-compensated 25k resistor between the GND and VIN pins, alerting the PSE that a PD is present and requests power to be applied. The LTC4265 signature resistor also compensates for the additional series resistance introduced by the input diode bridge. Thus a PD built with the LTC4265 conforms to the IEEE 802.3af/at detection specifications. 12.5V to ON/UVLO* Classification Load Current Active ON/UVLO* to 60V >71V *ON/UVLO includes hysteresis. Rising input threshold, 37.2V Max. Falling input threshold, 30V Min. INPUT DIODE BRIDGE In the IEEE 802.3af/at standard, the modes of operation reference the input voltage at the PD’s RJ45 connector. Since the PD must handle power received in either polarity from either the data or the spare pair, input diode bridges BR1 and BR2 are connected between the RJ45 connector and the LTC4265 (Figure 2). RJ45 1 TX+ TX– RX+ RX– T1 BR1 TO PHY 2 3 POWERED DEVICE (PD) INPUT 6 GND 4 5 SPARE+ BR2 0.1μF 100V LTC4265 D3 VIN SPARE– 7 8 4265 F02 Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs 4265f 7 LTC4265 APPLICATIONS INFORMATION SIGNATURE CORRUPT OPTION In some designs that include an auxiliary power option, it is necessary to prevent a PD from being detected by a PSE. The LTC4265 signature resistance can be corrupted with the SHDN pin (Figure 3). Taking the SHDN pin high will reduce the signature resistor below 11k which is an invalid signature per the IEEE 802.3af/at specification, and alerts the PSE not to apply power. Invoking the SHDN pin also ceases operation for classification and disconnects the LTC4265 load from the PD input. If this feature is not used, connect SHDN to VIN. LTC4265 TO PSE 14k SHDN During classification probing, the PSE presents a fixed voltage between 15.5V and 20.5V to the PD (Figure 2). The LTC4265 asserts a load current representing the PD power classification. The classification load current is programmed with a resistor RCLASS that is chosen from Table 2. Table 2. Summary of Power Classifications and LTC4265 RCLASS Resistor Selection CLASS USAGE MAXIMUM POWER LEVELS AT INPUT OF PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 12.95 to 25.5 NOMINAL CLASSIFICATION LOAD CURRENT (mA) < 0.4 10.5 18.5 28 40 LTC4265 RCLASS RESISTOR (Ω, 1%) Open 124 69.8 45.3 30.9 0 1 GND 25k SIGNATURE RESISTOR Default Optional Optional Optional Optional 2 3 4 VIN 4265 F03 2-EVENT CLASSIFICATION AND THE T2PSE PIN A Type-2 PSE may declare the availability of high power by performing 2-event classification (Layer 1) or by communicating over the high speed data line (Layer 2). A Type-2 PD must recognize both layers of communication. Since Layer 2 communications takes place directly between the PSE and the LTC4265 load, the LTC4265 concerns itself only with recognizing 2-event classification. TO AUX Figure 3. 25k Signature Resistor with Disable CLASSIFICATION Classification provides a method for more efficient power allocation by allowing the PSE to identify a PD power classification. Class 0 is included in the IEEE specification for PDs that don’t support classification. Class 1-3 partitions PDs into 3 distinct power ranges. Class 4 includes the new power range under IEEE802.3at (See Table 2). 4265f 8 LTC4265 APPLICATIONS INFORMATION In 2-event classification, a Type-2 PSE probes for power classification twice. Figure 4 presents an example of a 2-event classification. The 1st classification event occurs when the PSE presents an input voltage between 14.5V to 20.5V and the LTC4265 presents a class 4 load current. The PSE then drops the input voltage into the mark voltage range of 6.9V to 10V, signaling the 1st mark event. The PD in the mark voltage range presents a load current between 0.25mA to 4mA. The PSE repeats this sequence, signaling the 2nd Classification and 2nd mark event occurrence. This alerts the LTC4265 that a Type-2 PSE is present. The Type-2 PSE then applies power to the PD and the LTC4265 charges up the reservoir capacitor C1 with a controlled inrush current. When C1 is fully charged, and the LTC4265 declares power good, the T2PSE pin presents an active low signal, or low impedance output with respect to VIN. The T2PSE output becomes inactive when the LTC4265 input voltage falls outside the normal operating range. SIGNATURE CORRUPT DURING MARK As a member of the IEEE802.3at working group, Linear notes that it is possible for a Type-2 PD to receive a false indication of a 2-event classification if a PSE port is pre-charged to a voltage above the detection voltage range before the first detection cycle. The IEEE working group modified the standard to prevent this possibility by requiring a Type-2 PD to corrupt the signature resistance during the mark event, alerting the PSE not to apply power. The LTC4265 conforms to this standard by internally corrupting the signature resistance. This also discharges the port before the PSE begins the next detection cycle. GND – T2PSE (V) –10 –20 –30 –40 –50 TRACKS VIN 50 40 GND (V) 30 20 10 1st CLASS 2nd CLASS ON UVLO DETECTION V1 DETECTION V2 1st MARK 2nd MARK INRUSH PD CURRENT 1st CLASS 2nd CLASS 40mA LOAD, ILOAD TIME DETECTION V1 DETECTION V2 50 GND – VOUT (V) 40 30 20 10 = RLOAD C1 1st MARK 2nd MARK dV = INRUSH dt C1 UVLO ON UVLO TIME TIME INRUSH = 100mA ILOAD = VIN RLOAD RCLASS = 30.9Ω GND LTC4265 IIN PSE RCLASS T2PSE VIN VOUT 4265 F04 RCLASS GND RLOAD C1 VOUT Figure 4. VOUT, T2PSE, and PD Current as a Result of 2-event Classification 4265f 9 LTC4265 APPLICATIONS INFORMATION PD STABILITY DURING CLASSIFICATION Classification presents a challenging stability problem due to the wide range of possible classification load current. The onset of the classification load current introduces a voltage drop across the cable and increases the forward voltage of the input diode bridge. This may cause the PD to oscillate between detection and classification with the onset and removal of the classification load current. The LTC4265 prevents this oscillation by introducing a voltage hysteresis window between the detection and classification ranges. The hysteresis window accommodates the voltage changes a PD encounters at the onset of the classification load current, thus providing a trouble-free transition between detection and classification modes. The LTC4265 also maintains a positive I-V slope throughout the classification ranges up to the ON voltage. In the event a PSE overshoots beyond the classification voltage range, the available load current aids in returning the PD back into the classification voltage range. (The PD input may otherwise be “trapped” by a reverse-biased diode bridge and the voltage held by the 0.1μF capacitor.) INRUSH CURRENT Once the PSE detects and optionally classifies the PD, the PSE then applies powers on the PD. When the LTC4265 input voltage rises above the ON voltage threshold, LTC4265 connects VOUT to VIN through the internal power MOSFET. To control the power-on surge currents in the system, the LTC4265 provides a fixed inrush current, allowing C1 to ramp up to the line voltage in a controlled manner. The LTC4265 keeps the PD inrush current below the PSE current limit to provide a well-controlled power-up VIN characteristic that is independent of the PSE behavior. This ensures a PD using the LTC4265 interoperability with any PSE. UNDERVOLTAGE LOCKOUT The IEEE 802.3af/at specification for the PD dictates a maximum turn-on voltage of 42V and a minimum turn-off voltage of 30V. This specification provides an adequate voltage to begin PD operation, and to discontinue PD operation when the input voltage is too low. In addition, this specification allows PD designs to incorporate an on-off hysteresis window to prevent start-up oscillations. The LTC4265 features an ON-undervoltage lockout (UVLO) hysteresis window (See Figure 5) that conforms with the IEEE 802.3af/at specifications and accommodates the voltage drop in the cable and input diode bridge at the onset of the inrush current. LTC4265 TO PSE GND C1 5μF MIN + PD LOAD UNDERVOLTAGE OVERVOLTAGE LOCKOUT CIRCUIT VOUT 4265 F05 INPUT LTC4265 VOLTAGE POWER MOSFET 0V TO ON* OFF >ON* ON OVLO OFF *INCLUDES ON-UVLO HYSTERESIS ON THRESHOLD ≅ 36.1V UVLO THRESHOLD ≅ 30.7V OVLO THRESHOLD ≅ 71.0V CURRENT-LIMITED TURN ON Figure 5. LTC4265 Undervoltage and Overvoltage Lockout 4265f 10 LTC4265 APPLICATIONS INFORMATION Once C1 is fully charged, the LTC4265 turns on is internal MOSFET and passes power to the PD load. The LTC4265 continues to power the PD load as long as the input voltage does not fall below the UVLO threshold. When the LTC4265 input voltage falls below the UVLO threshold, the PD load is disconnected, and classification mode resumes. C1 discharges through the LTC4265 circuitry. COMPLEMENTARY POWERGOOD When LTC4265 fully charges the load capacitor (C1), power good is declared and the LTC4265 load can safely begin operation. The LTC4265 provides complementary power good signals that remain active during normal operation and are de-asserted when the input voltage falls below the UVLO threshold, when the input voltage exceeds the over-voltage lockout (OVLO) threshold, or in the event of a thermal shutdown. See Figure 6. The PWRGD pin features an open collector output referenced to VOUT which can interface directly with the “Run” pin of a DC/DC converter product. When power good is declared and active, the PWRGD pin is high impedance with respect to VOUT. An internal 14V clamp protects the DC/DC converter from an excessive voltage. The active low PWRGD pin connects to an internal, open drain MOSFET referenced to VIN and can interface directly to the shutdown pin of a DC/DC converter product. When power good is declared and active, the PWRGD pin is low impedance with respect to VIN. PWRGD PIN WHEN SHDN IS INVOKED In PD applications where an auxiliary power supply invokes the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to the “Run” pin of the DC/DC converter from interfering with the DC/DC converter operations when powered by an auxiliary power supply. LTC4265 OVLO ON UVLO TSD 10 PWRGD CONTROL CIRCUIT 9 PWRGD VIN 5 8 VOUT VIN 6 BOLD LINE INDICATES HIGH CURRENT PATH 7 VOUT INRUSH COMPLETE ON < GND < OVLO AND NOT IN THERMAL SHUTDOWN POWER NOT GOOD POWER GOOD GND < UVLO GND > OVLO OR THERMAL SHUTDOWN 4265 F06 Figure 6. LTC4265 Power Good Functional and State Diagram 4265f 11 LTC4265 APPLICATIONS INFORMATION OVERVOLTAGE LOCKOUT The LTC4265 includes an overvoltage lockout (OVLO) feature (Figure 5) which protects the LTC4265 and its load from an overvoltage event. If the input voltage exceeds the OVLO threshold, the LTC4265 discontinues PD operation. Normal operations resume when the input voltage falls below the OVLO threshold and when C1 is charged up. THERMAL PROTECTION The IEEE 802.3af/at specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. However, there are several possible scenarios where a PD may encounter excessive heating. During classification, excessive heating may occur if the PSE exceeds the 75ms probing time limit. At turn-on, when the load capacitor begins to charge, the instantaneous power dissipated by the PD Interface can be large before it reaches the line voltage. And if the PD experiences a fast input positive voltage step in its operational mode (for example, from 37V to 57V), the instantaneous power dissipated by the PD Interface can be large. RJ45 1 TX+ TX– RX+ RX– The LTC4265 includes a Thermal Protection feature which protects the LTC4265 from excessive heating. If the LTC4265 junction temperature exceeds the over-temperature threshold, the LTC4265 discontinues PD operations and power-good becomes inactive. Normal operation resumes when the junction temperature falls below the over-temperature threshold and when C1 is charged up. EXTERNAL INTERFACE AND COMPONENT SELECTION Transformer Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer. For PDs, the isolation transformer must also include a center tap on the RJ45 connector side (See Figure 7). The increased current levels in a Type-2 PD over a Type-1 increase the current imbalance in the magnetics which can interfere with data transmission. In addition, proper termination is also required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. Transformer vendors such as 14 T1 1 12 3 2 5 4 6 GND BR2 HD01 TO PHY BR1 HD01 2 3 13 10 11 6 9 COILCRAFT ETHI - 230LD SPARE+ 4 5 7 8 SPARE– C14 0.1μF 100V D3 SMAJ58A TVS LTC4265 C1 VIN VOUT 4265 F07 VOUT Figure 7. PD Front-End with Isolation Transformer, Diode Bridges, Capacitors, and a Transient Voltage Suppressor (TVS). 4265f 12 LTC4265 APPLICATIONS INFORMATION Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can assist in selecting an appropriate isolation transformer and proper termination methods. Table 4. Power-over-Ethernet Transformer Vendors VENDOR Bel Fuse Inc. CONTACT INFORMATION 206 Van Vorst Street Jersey City, NJ 07302 Tel: 201-432-0463 www.belfuse.com 1102 Silver Lake Road Gary, IL 60013 Tel: 847-639-6400 www.coilcraft.com 1861 Landings Drive Mountain View, CA 94043 Tel: 650-903-3800 www.haloelectronics.com 12220 World Trade Drive San Diego, CA 92128 Tel: 858-674-8100 www.pulseeng.com Tyco Electronics 308 Constitution Drive Menlo Park, CA 94025-1164 Tel: 800-227-7040 www.circuitprotection.com An input diode bridge must exceed the maximum current the PD application will encounter at the temperature the PD will operate. Diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. Consult the diode bridge vendors for the operating current derating curve. A silicon diode bridge can consume over 4% of the available power in some PD applications. Using Schottky diodes can help reduce the power loss with a lower forward voltage. A Schottky bridge may not be suitable for some high temperature PD application. The leakage current has a voltage dependency that can reduce the perceived signature resistance. In addition, the IEEE 802.3af/at specification mandates the leakage back-feeding through the unused bridge cannot generate more than 2.8V across a 100k resistor when a PD is powered with 57V. Sharing Input Diode Bridges At higher temperatures, a PD design may be forced to consider larger bridges in a bigger package because the maximum operating current for the input diode bridge is drastically de-rated. The larger package may not be acceptable in some space-limited environments. One solution to consider is to reconnect the diode bridges so that only one of the four diodes conducts current in each package. This configuration extends the maximum operating current while maintaining a smaller package profiles. Figure 7 shows how to reconnect the two diode bridges. Consult the diode bridge vendors for the de-rating curve when only one of four diodes is in operation. Coilcraft Inc. Halo Electronics Pulse Engineering Input Diode Bridge Figure 2 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the data pair while the other bridge is dedicated to the spare pair. The LTC4265 supports the use of either silicon or Schottky input diode bridges. However, there are tradeoffs in the choice of diode bridges. 4265f 13 LTC4265 APPLICATIONS INFORMATION Input Capacitor The IEEE 802.3af/at standard includes an impedance requirement in order to implement the AC disconnect function. A 0.1μF capacitor (C14 in Figure 7) is used to meet this AC impedance requirement. Transient Voltage Suppressor The LTC4265 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events. However, the pins that interface to the outside world can routinely see excessive peak voltages. To protect the LTC4265, install a transient voltage suppressor (D3) between the input diode bridge and the LTC4265 as shown in Figure 7. Classification Resistor (RCLASS) The RCLASS resistor sets the classification load current, corresponding to the PD power classification. Select the value of RCLASS from Table 2 and connect the resistor between the RCLASS and VIN pins as shown in Figure 4, or float the RCLASS pin if the classification load current is not required. The resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classification circuit. Load Capacitor The IEEE 802.3af/at specification requires that the PD maintains a minimum load capacitance of 5μF and does not specify a maximum load capacitor. However, if the load capacitor is too large, there may be a problem with inadvertent power shutdown by the PSE. This occurs when the PSE voltage drops quickly. The input diode bridge reverses bias, and the PD load momentarily powers off the load capacitor. If the PD does not draw power within the PSE’s 300ms disconnection delay, the PSE may remove power from the PD. Thus, it is necessary to evaluate the load current and capacitance to ensure that an inadvertent shutdown cannot occur. The load capacitor can store significant energy when fully charged. The PD design must ensure that this energy is not inadvertently dissipated in the LTC4265. For example, if the GND pin shorts to VIN while the capacitor is charged, current will flow through the parasitic body diode of the internal MOSFET and may cause permanent damage to the LTC4265. Power Good Interface The LTC4265 provides complementary power good signals to simplify the DC/DC converter interface. Using the power good signal to delay converter operation until the load capacitor is fully charged is highly recommended to ensure trouble free start up. Figure 8 presents examples of power good interface circuits. The active high PWRGD pin has an open collector transistor referenced to VOUT while the active low PWRGD pin has a high voltage, open-drain MOSFET referenced to VIN. The designer can choose either signal to enable the DC/DC converter. When using PWRGD, diode D9 and resistor RS protects the converter shutdown pin from excessive reverse voltage. 4265f 14 LTC4265 APPLICATIONS INFORMATION ACTIVE-HIGH ENABLE GND TO PSE LTC4265 PWRGD PD LOAD RUN –54V VIN VOUT ACTIVE-LOW ENABLE R9 100k RS 10k D9 5.1V MMBZ5231B VIN VOUT PD LOAD SHDN GND TO PSE LTC4265 PWRGD Figure 9 shows two interface options using the T2PSE pin and the opto-isolator. The T2PSE pin is active low and connects to an opt-isolater to communicate across the DC/DC converter isolation barrier. The pull up resistor RP is sized according to the requirements of the opto-isolator operating current, the pull-down capability of the T2PSE pin, and the choice of V+. V+ for example can come from the PoE supply rail (which the LTC4265 GND is tied to), or from the voltage source that supplies power to the DC/DC converter. Option 1 has the advantage of not drawing power unless T2PSE is declared active. GND TO PSE LTC4265 V+ RP –54V ACTIVE-LOW ENABLE TO PD LOAD –54V GND TO PSE LTC4265 PWRGD D9 MMBD4148 –54V VIN VOUT R10 100k RS 10k Q1 FMMT2222 V+ PD LOAD GND 4265 F08 VIN T2PSE OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT V+ RP TO PSE LTC4265 T2PSE Figure 8. Power Good Interface Examples –54V VIN VOUT TO PD LOAD 4265 F09 T2PSE Interface When a 2-event Classification sequence successfully completes, the LTC4265 recognizes this sequence, and provides an indicator bit, declaring the presence of a Type-2 PSE. The open drain output provides the option to use this signal to communicate to the LTC4265 load, or to leave the pin unconnected. OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT Figure 9. T2PSE Interface Examples 4265f 15 LTC4265 APPLICATIONS INFORMATION Shutdown Interface To corrupt the signature resistance, the SHDN pin can be driven high with respect to VIN or connected to GND. If unused, connect SHDN directly to VIN. Exposed Pad The LTC4265 uses a thermally enhanced DFN12 package that includes an Exposed Pad. The exposed may be electrically connected to VIN and must connect to a printed circuit board heat sink. Auxiliary Power Source In some applications, it is desirable to power the PD from an auxiliary power source such as a wall adapter. Auxiliary power can be injected into an LTC4265-based PD at the input of the LTC4265, the output of the LTC4265, or even the output of the DC/DC converter. In addition, some PD application may desire auxiliary supply dominance or may be configured for PoE dominance. Furthermore, PD applications may also opt for a seamless transition — that is, without power disruption — between PoE and auxiliary power. The most common auxiliary power option injects power between the LTC4265 and the DC/DC converter. Figure 10 presents an example of this application. In this example, the auxiliary port injects 48V onto the line via diode D1. The components surrounding the SHDN pin are selected so that the LTC4265 disconnects power to the output when the auxiliary supply reaches 36V. This configuration is an auxiliary-dominant configuration. That is, the auxiliary power source supplies the power even if PoE power is already present. This configuration also provides a seamless transition from PoE to auxiliary power when auxiliary power is applied, however, the removal of auxiliary power to PoE power is not seamless. Contact Linear Technology applications support for detail information on implementing a custom auxiliary power supply. RJ45 1 TX+ TX– RX+ RX– T1 TVS + TO PHY BR1 2 3 0.1μF 100V C1 – 36V 100k GND LTC4265 10k BR2 SHDN 10k 6 PD LOAD 4 5 7 8 SPARE+ + SPARE– ISOLATED WALL TRANSFORMER – + VIN VOUT D1 – 4265 F10 Figure 10. Auxiliary Power Dominant PD Interface 4265f 16 LTC4265 APPLICATIONS INFORMATION IEEE 802.3at SYSTEM POWER-UP REQUIREMENT Under the IEEE 802.3at standard, a PD must operate under 12.95 Watts in accordance with IEEE 802.3af standards until it recognizes a Type-2 PSE. Initializing PD operation in 12.95-Watt mode eliminates interoperability issue in case a Type-2 PD is connects to a Type-1 PSE. Once the PD recognizes a Type-2 PSE, the IEEE 802.3at standard requires the PD to wait 80ms in 12.95W operation before 25.5W operation can commence. MAINTAIN POWER SIGNATURE In an IEEE 802.3af/at system, the PSE uses the maintain power signature (MPS) to determine if a PD continues to require power. The MPS requires the PD to periodically draw at least 10mA and also have an AC impedance less than 26.25k in parallel with 0.05μF If one of these conditions . is not met, the PSE may disconnect power to the PD. LAYOUT CONSIDERATION FOR THE LTC4265 The LTC4265 is relatively immune to layout problems. Here are some recommendations. Avoid excessive parasitic capacitance on the RCLASS pin and place resistor RCLASS close to the LTC4265. Connect the LTC4265 exposed pad to a PC board heat sink. Make the heat sink as large as possible. Place the input capacitor and transient voltage suppressor (C14 and D3 in Figure 7) as close to the LTC4265 as possible. If using the SHDN pin for auxiliary power application, separate the SHDN pin from other high voltage connections, like GND and VOUT, to avoid leakage and capacitive coupling shutting down the LTC4265. 4265f 17 High Efficiency 12V Isolated Power Supply (Contact LTC for 3.3V and 5V Power Supply Applications) PA2467NL LTC4265 APPLICATIONS INFORMATION OUTPUT (V) EFFICIENCY (%) 18 • 0.33μH GND 4.7μH 10μF 16V + 47μF 16V 12V 2A + SMAJ58A 30k 150Ω 47pF 470pF 2kV 2.2nF 2kV 15Ω FDS3572 BAS21 20Ω SG LTC4265 GND 29.4k SG MMBT3906 MMBT3904 100Ω 1μF 2.2nF 4.7nF 1nF 12k 1.8k 0.1μF 33pF 1 GND 51k 10k 4 PE-68386 T2P (TO MICROCONTROLLER) 38.3k 100k 8 15Ω 1μF 16V 25mΩ LT3825 SENSE– VC GND 383k UVLO VOUT T2PSE 14k 3.01k PGDLY tON SYNC RCMP ENDLY OSC SFST CCMP FB VCC SG PG SENSE+ FDS2582 15μF 16V 10μF 100V 1μF 100V • • B1100 8 PLCS 0.1μF 100V –54V FROM DATA PAIR –54V FROM SPARE PAIR RCLASS 30.9Ω SHDN VIN • • 5 BAT54 10k 20k 4265 TA02 LTV357TA Efficiency vs Load Current 93 91 89 87 85 83 81 79 77 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) 4265 TA02a Output Regulation vs Load Current 12.4 12.3 12.2 42V 48V 57V EXCLUDING BRIDGES 12.1 12.0 11.9 42V 48V 57V 11.8 11.7 11.6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) 4265 TA02b 4265f LTC4265 PACKAGE DESCRIPTION DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695 Rev C) 0.70 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE 3.60 0.05 2.20 0.05 0.25 0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) R = 0.05 TYP 3.30 0.10 PIN 1 TOP MARK (NOTE 6) 3.00 0.10 (2 SIDES) 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER 0.75 0.05 6 0.25 1 0.05 0.50 BSC 2.50 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD (UE12/DE12) DFN 0806 REV D 7 R = 0.115 TYP 0.40 12 0.10 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4265f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC4265 TYPICAL APPLICATION PoE-Based Self-Driven Synchronous Forward Power Supply 1mH DO1608C-105 BAS516 PA2431NL • GND 18V PDZ18B 10μH BAS516 6.8μH PG0702.682 • 4.7nF 250V + B1100 –54V FROM DATA PAIR 8 PLCS 10μF 100V 2.2μF 100V VCC 10μF 16V • 5.1Ω + 33k 0.1μF IRF6217 5V 5A 220μF 6.3V PSLVOJ227M(12) FDS2582 FDS8880 10k 50mΩ 2.2nF 2kV 1nF 5.1Ω FDS8880 1nF 5.1Ω BAS516 BAS516 237k VIN SOUT OUT 133Ω OC COMP 2k 1.5k 33k 22k BC857BF VCC PS2801-1-L 4.7nF –54V FROM SPARE PAIR 0.1μF 100V LTC4265 SMAJ58A 30.9Ω GND RCLASS SHDN VIN T2PSE 10.0k VOUT PGND GND BLANK 82k DELAY SD_VSEC LT1952 ISENSE FB VREF SS_MAXDC ROSC 158k 10nF 22.1k 1.2k 0.1μF TLV431A 11.3k Efficiency vs Load Current 95 90 85 80 75 70 65 42V 50V 57V 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 332k 100pF 158k 0.22μF GND 51k 5V 20k T2P (TO MICROCONTROLLER) 3.65k EFFICIENCY (%) PS22801-1-L 4265 TA03a LOAD (A) 4265 TA03b RELATED PARTS PART NUMBER LT1952 LT1952-1 LTC3805 LTC3825 LTC4257-1 LTC4258 LTC4259A-1 DESCRIPTION Single Switch Synchronous Forward Controller Adjustable Frequency Current Mode Flyback Controller Isolate No-Opto Synchronous Flyback Controller with Wide Input Supply Range IEEE 802.3af PD Interface Controller Quad IEEE 802.3af Power over Ethernet Controller Quad IEEE 802.3af Power over Ethernet PSE Controller with AC Disconnect High Power PD Interface Controller with 750mA Current Limit IEEE 802.3af PD Interface with Integrated Switching Regulator High Power PD with Synchronous No Opto Flyback Controller COMMENTS Adjustable Switching Frequency, Programmable Undervoltage Lockout, Optional Burst Mode® Operation at Light Load Slope Comp Overcurrent Protect, Internal/External Clock Adjustable Switching Frequency, Programmable Undervoltage Lockout, Accurate Regulation without Trim, Synchronous for High Efficiency. 100V 400mA Internal Switch, Programmable Classification Current Limit DC Disconnect Only, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control AC or DC Disconnect IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control Internal Switch, Autonomous Operation or I2C Control. 15.4W or 30W. 750mA Internal Switch, Programmable Classification Current Limit with disable, Complementary Power Good 100V 400mA Internal Switch, Programmable Classification, 200KHz or 300KHz Constant Frequency PWM, Interface and Switcher Optimized for IEEE-Compliant PD System. 750mA Internal Switch, Programmable Class, Current Limit, Synchronous Programmable Switching Frequency and UVLO, High Efficiency 4265f LTC4263/LTC4263-1 Single IEEE 802.3af Power over Ethernet Controller LTC4264 LTC4267 LTC4267-1 LTC4267-3 LTC4268-1 ThinSOT is a trademark of Linear Technology Corporation. 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 1208 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008