LTC4272

LTC4270/LTC4271 12-Port PoE/PoE+/LTPoE++ PSE Controller FEATURES n n n DESCRIPTION The LTC®4270/LTC4271 chipset is a 12-Port Power Sourcing Equipment (PSE) controller designed for use in IEEE 802.3at Type 1 and Type 2 (high power) compliant Power over Ethernet (PoE) systems. Transformer-isolated communication protocol replaces expensive opto-couplers and complex isolated 3.3V supply resulting in significant BOM cost savings. The LTC4270/LTC4271 chipset delivers lowest-in-industry heat dissipation by utilizing low-RDS(ON) external MOSFETs and 0.25Ω sense resistors. Advanced power management features include per-port 12bit current monitoring ADCs, DAC-programmable current limit, and versatile fast shut-down of preselected ports. Advanced power management host software is available under a no-cost license. PD Discovery uses a proprietary dual-mode 4-point detection mechanism ensuring excellent immunity from false PD detection. Midspan PSEs are supported with 2-event classification and a 2 second backoff timer. The LTC4270/LTC4271 includes an I2C serial interface operable up to 1MHz. The LTC4270/LTC4271 is available in multiple power grades allowing delivered PD power up to 90W. L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks and LTPoE++ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. n n n n n n n n n 12 Independent PSE Channels Compliant with IEEE 802.3at Type 1 and 2 Chipset Provides Electrical Isolation Reduced BOM Cost Eliminates up to 6 High Speed Opto-Couplers Eliminates Isolated 3.3V Power Supply Low Power Dissipation 0.25Ω Sense Resistance Per Channel Very High Reliability 4-Point PD Detection 2-Point Forced Voltage 2-Point Forced Current Temperature Monitoring VEE and VPORT Monitoring 1 Second Rolling IPORT Averaging Supports 2-Pair and 4-Pair Output Power 1MHz I2C Compatible Serial Control Interface Available In Three Power Grades A-Grade – LTPoE++™ 35W to 90W B-Grade – PoE+ 25.5W C-Grade – PoE 13W Available In 52-Lead 7mm × 8mm (LTC4270) and 24-Lead 4mm × 4mm (LTC4271) QFN Packages APPLICATIONS n n PoE PSE Switches/Routers PoE PSE Midspans TYPICAL APPLICATION 3.3V 0.1μF NO ISOLATION REQUIRED ON I2C INTERFACE GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 DGND VDD33 CPD 100Ω 3.3V 100Ω CND DPD 100Ω 3.3V 100Ω DND CAP1 1μF 2nF 2kV 0.1μF 1μF –54V >47μF SYSTEM BULK CAP 100Ω –54V 100Ω DNA OUT1 GATE1 0.25Ω –54V SENSE1 CAP2 VEE VSSK AGND 100Ω –54V 100Ω CNA DPA LTC4270 0.22μF 100V S1B PORT1 S1B GATEn 0.25Ω SENSEn –54V S1B CPA XIO0 XIO1 OUTn 0.22μF 100V S1B PORTn LTC4270/LTC4271 FAMILY MAX LTC4270 DELIVERED GRADE ISOLATION LTPoE++ PoE+ PoE POWER A B C Transformer Transformer Transformer l l l l l l 90W 25.5W 13W + –54V 42701 TA01a 42701f 1 LTC4270/LTC4271 ABSOLUTE MAXIMUM RATINGS LTC4270 (Note 1, Note 4) Supply Voltages AGND – VEE ........................................... –0.3V to 80V VSSK (Note 7) ..................... VEE – 0.3V to VEE + 0.3V Digital Pins XIOn ................................. VEE – 0.3V to CAP2 + 0.3V Analog Pins SENSEn, GATEn, OUTn ........ VEE – 0.3V to VEE + 80V CAP2 (Note 13) ....................... VEE – 0.3V to VEE + 5V CPA, CNA, DPA, DNA ..................VEE – 0.3V to VEE + 0.3 Operating Ambient Temperature Range LTC4270I .............................................–40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ......................–65 to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C ABSOLUTE MAXIMUM RATINGS LTC4271 (Note 1) Supply Voltages VDD – DGND ......................................... –0.3V to 3.6V Digital Pins SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO, MID, GPn ........................DGND – 0.3V to VDD + 0.3V Operating Ambient Temperature Range LTC4271I..............................................–40°C to 85°C Analog Pins CAP1 (Note 13) ...........................–0.3V to DGND + 2V Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ......................–65 to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C CPD, CND, DPD, DND........... DGND – 0.3 to DGND + 0.3 42701f 2 LTC4270/LTC4271 PIN CONFIGURATION LTC4270 TOP VIEW DNA CNA DPA CPA LTC4271 VEE VEE VEE NC NC NC NC 52 51 50 49 48 47 46 45 44 43 42 41 SENSE1 1 GATE1 2 OUT1 3 SENSE2 4 GATE2 5 OUT2 6 CAP2 7 SENSE3 8 GATE3 9 OUT3 10 SENSE4 11 GATE4 12 OUT4 13 XIO0 14 15 16 17 18 19 20 21 22 23 24 25 26 SENSE5 GATE5 OUT5 SENSE6 GATE6 OUT6 SENSE7 GATE7 OUT7 SENSE8 GATE8 OUT8 53 VSSK 40 SENSE12 39 GATE12 38 OUT12 37 SENSE11 36 GATE11 35 OUT11 34 AGND 33 SENSE10 32 GATE10 31 OUT10 30 SENSE9 29 GATE9 28 OUT9 27 XIO1 AD0 1 AD1 2 AD2 3 AD3 4 AD6 5 MID 6 7 NC 8 NC TOP VIEW VDD33 DND AUTO CAP1 18 SCL 17 SDAIN 25 DGND 16 SDAOUT 15 INT 14 RESET 13 DNC 9 10 11 12 VDD33 CND DPD MSD GP0 CPD GP1 24 23 22 21 20 19 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 53) IS VSSK, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC4271IUF#PBF LTC4270AIUKG#PBF LTC4270BIUKG#PBF LTC4270CIUKG#PBF TAPE AND REEL LTC4271IUF#TRPBF LTC4270AIUKG#TRPBF LTC4270BIUKG#TRPBF LTC4270CIUKG#TRPBF PART MARKING 4271 LTC4270A LTC4270B LTC4270C PACKAGE DESCRIPTION 24-Lead (4mm × 4mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 52-Lead (7mm × 8mm) Plastic QFN 90W 25.5W 13W MAX PWR TEMPERATURE RANGE –40°C to 85°C –40°C to 85°C –40°C to 85°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 42701f 3 LTC4270/LTC4271 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3 & 4) SYMBOL PARAMETER VEE Main PoE Supply Voltage CONDITIONS AGND – VEE For IEEE Type 1 Compliant Output For IEEE Type 2 Compliant Output For LTPoE++ Compliant Output AGND – VEE VDD – DGND VDD – DGND VCAP1 – DGND VCAP2 – VEE (AGND – VEE) = 55V VEE < 15V (VDD – DGND) = 3.3V First Point, AGND – VOUTn = 10V Second Point, AGND – VOUTn = 3.5V AGND – VOUTn, 5μA ≤ IOUTn ≤ 500μA First Point Second Point AGND – VOUTn = 0V AGND – VOUTn, Open Port AGND – VOUTn, CPORT = 0.15μF l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS MIN 32 45 51 54.75 20 3.0 TYP 54 MAX 66 57 57 57 30 3.6 UNITS V V V V V V V V V Undervoltage Lock-Out VDD VCAP1 VCAP2 IEE REE IDD Detection Detection Current – Forced Current Detection Voltage – Forced Voltage VDD Supply Voltage Undervoltage Lock-Out Internal Regulator Supply Voltage Internal Regulator Supply Voltage VEE Supply Current VEE Supply Resistance VDD Supply Current 25 3.3 2.7 1.84 4.3 9 10 15 12 15 260 180 9 5 0.9 12 0.01 18.5 32 20.5 mA kΩ mA μA μA V V mA V V/μs kΩ kΩ V mA mA mA mA mA mA V mA mA mA mA 220 143 7 3 240 160 8 4 0.8 10.4 Detection Current Compliance VOC Detection Voltage Compliance Detection Voltage Slew Rate Min. Valid Signature Resistance Max. Valid Signature Resistance Classification VCLASS Classification Voltage Classification Current Compliance Classification Threshold Current 15.5 27.5 16.0 53 5.5 13.5 21.5 31.5 45.2 7.5 53 0.4 0.08 8 2 300 17 29.7 AGND – VOUTn, 0mA ≤ IOUTn ≤ 50mA VOUTn = AGND Class 0-1 Class 1-2 Class 2-3 Class 3-4 Class 4-Overcurrent AGND – VOUTn, 0.1mA ≤ ICLASS ≤ 5mA VOUTn = AGND Port Off, VGATEn = VEE + 5V Port Off, VGATEn = VEE + 1V VGATEn = VEE + 5V VGATEn – VEE, IGATEn = 1μA VOUTn – VEE 0V ≤ (AGND – VOUT) ≤ 5V 61 6.5 14.5 23 33 48 9 61 67 7.5 15.5 24.5 34.9 50.8 10 67 VMARK Classification Mark State Voltage Mark State Current Compliance Gate Driver GATE Pin Pull-Down Current GATE Pin Fast Pull-Down Current GATE Pin On Voltage Output Voltage Sense VPG Power Good Threshold Voltage OUT Pin Pull-Up Resistance to AGND 2.4 500 2.8 700 V kΩ 0.12 30 14 V 42701f 4 LTC4270/LTC4271 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3 & 4) SYMBOL PARAMETER VCUT Overcurrent Sense Voltage CONDITIONS VSENSEn – VEE, hpen = 0Fh, cutn = D4h hpen = 0Fh, cutn = E2h (Note 12) Class 0, Class 3 Class 1 Class 2 Class 4 VSENSEn – VEE, hpen = 0Fh, limn = 80h VEE < VOUT < AGND – 29V AGND – VOUT = 0V (Note 12) hpen = 0Fh, limn = C0h VOUT – VEE = 0 – 10V VEE + 23V < VOUT < AGND – 29V AGND – VOUT = 0V (Note 12) VEE < VOUT < AGND – 10V Class 0 to Class 3 Class 4 VSENSE – VEE, rdis Bit = 0 VSENSE – VEE, rdis Bit = 1 (Note 12) VSENSEn – VEE – VLIM, rdis Bit = 0 rdis bit = 1 (Note 12) No Missing Codes VSENSEn – VEE l l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS MIN 89 152 89 26 49 152 102 25 204 102 25 102 204 2.6 1.3 125 70 TYP 94 159 94 28 52 159 106 MAX 99 168 99 30 55 168 112 50 225 115 50 112 225 4.9 2.45 255 135 UNITS mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV Bits μV/LSB ms/ Convert Bits mV/LSB °C °C/LSB Overcurrent Sense in AUTO Pin Mode VLIM Active Current Limit in 802.3af Compliant Mode Active Current Limit in High Power Mode 212 106 Active Current Limit in AUTO Pin Mode 106 212 3.8 1.9 200 100 12 30.518 25.1 VMIN VSC DC Disconnect Sense Voltage Short-Circuit Sense Port Current Readback Resolution LSB Weight Conversion Period Port Voltage Readback Resolution LSB Weight LTC4270 Die Temperature Die Temperature Offset Die Temperature LSB Weight Digital Interface VILD VIHD Digital Input Low Voltage Digital Input High Voltage Digital Output Voltage Low Internal Pull Up to VDD Internal Pull Down To DGND (Note 6) (Note 6) ISDAOUT = 3mA, IINT = 3mA ISDAOUT = 5mA, IINT = 5mA ADn, RESET, MSD, INT, GPn AUTO, MID l l l l l l No Missing Codes VSENSEn – VEE Temperature Register = 00h (Note 7) (Note 7) 12 5.8250 –40 0.7 0.8 2.2 0.4 0.7 50 50 V V V V kΩ kΩ 42701f 5 LTC4270/LTC4271 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3 & 4) SYMBOL PARAMETER XIO VOLX VOHX XIO Digital Output Low XIO Digital Output High XIO Digital Input Low Voltage XIO Digital Input High Voltage Internal Pull Up to VEE + 4.3V PSE Timing Characteristics tDET tCLE tCLEON tME tMEL tPON Detection Time Class Event Duration Class Event Turn On Duration Mark Event Duration Last Mark Event Duration Power On Delay in AUTO Pin Mode Turn-On Rise Time Turn-On Ramp Rate tTOCL tED Turn-On Class Transition Fault Delay Midspan Mode Detection Backoff Power Removal Detection Delay tSTART tCUT Maximum Current Limit Duration During Port Start-Up Maximum Overcurrent Duration After Port StartUp Maximum Current Limit Duty Cycle tLIM Beginning To End of Detection (Note 7) (Note 7) CPORT = 0.6μF (Note 7) (Note 7, Note 11) Event 2 of 2 or 3 of 3 (Note 7, Note 11) From End of Valid Detect to Application of Power to Port (Note 7) (AGND – VOUT): 10% to 90% of (AGND VEE) CPORT = 0.15μF (Note 7) CPORT = 0.15μF (Note 7) CPORT = 0.15μF (Note 7) From ICUT or ILIM Fault to Next Detect (Note 7) RPORT = 15.5kΩ (Note 7) From Power Removal After tDIS to Next Detect (Note 7) (Note 7) (Note 7) (Note 7) l l l l l l l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS CONDITIONS VXIOn – VEE, IXIOn = 5mA VXIOn – VEE, IXIOn = 100μA VXIOn – VEE VXIOn – VEE XIO0, XIO1 l l l l l MIN TYP MAX 0.7 UNITS V V V V kΩ ms ms 3.5 0.8 3.4 50 220 12 0.1 8.6 16 22 60 15 24 10 0.1 1.0 2.3 1.0 52 52 5.8 10 52 1.6 320 1.5 3 4.5 350 2 1.1 2.5 1.3 59 59 6.3 12 59 2.7 2.5 66 66 6.7 14 66 3.6 380 6.5 3 ms ms ms ms μs V/μs ms s s s ms ms % ms ms ms ms μs s μs μs Maximum Current Limit Duration After Port Start- tLIM = 1 (Note 7, Note 12) Up – tLIM Enabled Maximum Current Limit Duration After Port Start- tLIM = 0 (Note 7, Note 12) Up – tLIM as tCUT tMPS tDIS tMSD Maintain Power Signature (MPS) Pulse Width Sensitivity Maintain Power Signature (MPS) Dropout Time Masked Shut Down Delay I2C Watchdog Timer Duration Minimum Pulse Width for Masked Shut Down Minimum Pulse Width for RESET Current Pulse Width to Reset Disconnect Timer (Note 7, Note 8) (Note 7, Note 5) (Note 7) (Note 7) (Note 7) (Note 7) 42701f 6 LTC4270/LTC4271 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3 & 4) SYMBOL PARAMETER I2C Timing fSCLK t1 t2 t3 t4 t5 t5 t6 t7 t8 tr tf Clock Frequency Bus Free Time Start Hold Time SCL Low Time SCL High Time SDAIN Data Hold Time Data Clock to SDAOUT Valid Data Set-Up Time Start Set-Up Time Stop Set-Up Time SCL, SDAIN Rise Time SCL, SDAIN Fall Time Fault Present to INT Pin Low Stop Condition to INT Pin Low ARA to INT Pin High Time SCL Fall to ACK Low (Note 7) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) (Notes 7, 9, 10) (Notes 7, 9, 10) (Notes 7, 9) (Notes 7, 9) l l l l l l l l l l l l l l l l ELECTRICAL CHARACTERISTICS CONDITIONS MIN TYP MAX 1 UNITS MHz ns ns ns ns ns 480 240 480 240 60 130 80 240 240 120 60 150 1.5 1.5 130 ns ns ns ns ns ns ns μs μs ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. With the exception of (VDD – DGND), exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 140ºC when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: All currents into device pins are positive; all currents out of device pins are negative. Note 4: The LTC4270 operates with a negative supply voltage (with respect to AGND). To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Note 5: tDIS is the same as tMPDO defined by IEEE 802.3at Note 6: The LTC4271 digital interface operates with respect to DGND. All logic levels are measured with respect to DGND. Note 7: Guaranteed by design, not subject to test. Note 8: The IEEE 802.3af specification allows a PD to present its Maintain Power Signature (MPS) on an intermittent basis without being disconnected. In order to stay powered, the PD must present the MPS for tMPS within any tMPDO time window. Note 9: Values Measured at VILD and VIHD Note 10: If a fault condition occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. Note 11: Load characteristics of the LTC4270 during Mark: 7V < (AGND – VOUTn) < 10V or IOUT < 50μA. Note 12: See the LTC4271 Software Programming documentation for information on serial bus usage and device configuration and status registers. Note 13: Do not source or sink current from CAP1 and CAP2. 42701f 7 LTC4270/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af Power On Sequence in AUTO Pin Mode 0 –10 PORT VOLTAGE (V) PORT VOLTAGE (V) –20 –30 –40 –50 –60 50ms/DIV 42701 G01 802.3at Power On Sequence in AUTO Pin Mode 0 –10 –20 –30 –40 –50 –60 50ms/DIV 42701 G02 Power On Sequence with 10VPP 60Hz Noise 5 0 PORT VOLTAGE (V) PORT OFF AGND FORCED VOLTAGE DETECTION AGND AGND FORCED CURRENT DETECTION FORCED VOLTAGE DETECTION VEE = –55V CLASS 3 PD VEE 802.3af CLASSIFICATION POWER ON FORCED CURRENT DETECTION FORCED VOLTAGE DETECTION VEE = –55V CLASS 4 PD 802.3at CLASSIFICATION POWER ON –5 –10 –15 –20 –25 FORCED CURRENT DETECTION 802.3af CLASSIFICATION DETECT WITH 60Hz NOISE NORMAL DETECT POWER ON 50ms/DIV 42701 G03 VEE Powering Up into a 180μF Load AGND PORT VOLTAGE 20V/DIV VEE LOAD FULLY CHARGED PORT CURRENT 200mA/DIV 0mA GATE VOLTAGE 10V/DIV VEE FOLDBACK 425mA CURRENT LIMIT VEE = –54V 40mA PORT CURRENT 20mA/DIV 0mA Classification Transient Response to 40mA Load Step 0 VDD = 3.3V VEE = –54V CLASSIFICATION VOLTAGE (V) –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 Classification Current Compliance FET ON PORT VOLTAGE 1V/DIV –20V 5ms/DIV 42701 G04 50μs/DIV 42701 G05 0 10 20 30 40 50 60 CLASSIFICATION CURRENT (mA) 70 42701 G06 VDD Supply Current vs Voltage 15.0 9.0 8.5 IEE SUPPLY CURRENT (mA) 85°C 25°C –40 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD SUPPLY VOLTAGE (V) 42701 G07 VEE Supply Current vs Voltage IDD SUPPLY CURRENT (mA) 12.0 8.0 7.5 7.0 6.5 6.0 –60 85°C 25°C –40 –50 –40 –30 VEE SUPPLY VOLTAGE (V) –20 42701 G08 9.0 6.0 3.0 0.0 42701f 8 LTC4270/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3at ILIM Threshold vs Temperature 220 PORT 1 REG 48h = C0h RSENSE = 0.25Ω 880 166 802.3at ICUT Threshold vs Temperature PORT 1 REG 47h = E2h 164 R SENSE = 0.25Ω 162 VCUT (mV) ILIM (mA) 160 158 156 154 664 656 648 ICUT (mA) 640 632 624 616 608 100 120 42701 G10 216 VLIM (mV) 864 212 848 208 832 204 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 816 100 120 42701 G09 152 –40 –20 0 20 40 60 80 TEMPERATURE (°C) DC Disconnect Threshold vs Temperature 2.50 PORT 1 REG 47h = E2h RSENSE = 0.25Ω 10 900 800 9 700 600 VMIN (mV) ILIM (mA) 2.00 8 IMIN (mA) 500 400 300 1.50 6 200 100 1.25 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 5 100 120 42701 G11 802.3at Current Limit Foldback PORT 1 REG 48h = C0h RSENSE = 0.25Ω 225 200 175 150 VLIM (mV) 125 100 75 50 25 0 –45 –36 –27 –18 VOUTn (V) –9 0 42701 G12 2.25 1.75 7 0 –54 INT and SDAOUT Pull Down Voltage vs Load Current 3.0 2.5 PULLDOWN VOLTAGE (V) 2.0 1.5 1.0 0.5 0.0 0 10 20 30 40 LOAD CURRENT (mA) 50 60 42701 G13 MOSFET Gate Drive With Fast Pull Down GND PORT VOLTAGE 20V/DIV VEE GATE VOLTAGE 10V/DIV VEE 50Ω FAULT APPLIED FAST PULL DOWN VDD = 3.3V VEE = –54V CURRENT LIMIT 50Ω FAULT REMOVED PORT CURRENT 500mA/DIV 0mA 100μs/DIV 42701 G14 42701f 9 LTC4270/LTC4271 TEST TIMING DIAGRAMS tDET FORCED-CURRENT 0V VPORTn VOC VMARK VCLASS tCLE tCLE PD CONNECTED tCLEON tMEL 15.5V 20.5V FORCEDVOLTAGE CLASSIFICATION tME tPON VEE INT 42701 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes VLIM VSENSEn TO VEE 0V INT 42701 F02 VCUT tSTART, tCUT Figure 2. Current Limit Timing VSENSEn TO VEE VMIN INT tMPS tDIS 42701 F03 Figure 3. DC Disconnect Timing 42701f 10 LTC4270/LTC4271 TEST TIMING DIAGRAMS VGATEn tMSD MSD 42701 F04 VEE Figure 4. Shut Down Delay Timing t3 t4 SCL t2 SDA t1 t5 tr tf t6 t7 t8 42701 F05 Figure 5. I2C Interface Timing 42701f 11 LTC4270/LTC4271 I2C TIMING DIAGRAMS SCL SDA AD6 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE ACK BY SLAVE FRAME 3 DATA BYTE ACK BY SLAVE STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 42701 F06 Figure 6. Writing to a Register SCL SDA AD6 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK AD6 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE ACK BY SLAVE REPEATED START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 42701 F07 Figure 7. Reading from a Register 42701f 12 LTC4270/LTC4271 I2C TIMING DIAGRAMS SCL SDA AD6 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER 42701 F08 Figure 8. Reading the Interrupt Register (Short Form) SCL SDA 0 0 0 1 1 0 0 R/W ACK AD6 1 0 AD3 AD2 AD1 AD0 1 ACK START BY MASTER FRAME 1 ALERT RESPONSE ADDRESS BYTE ACK BY SLAVE NO ACK BY MASTER FRAME 2 SERIAL BUS ADDRESS BYTE STOP BY MASTER 42701 F09 Figure 9. Reading from Alert Response Address 42701f 13 LTC4270/LTC4271 PIN FUNCTIONS LTC4270 SENSEn (Pins 1, 4, 8, 11, 15, 18, 21, 24, 30, 33, 37, 40): Port n Current Sense Input. SENSEn monitors the external MOSFET current via a 0.5Ω or 0.25Ω sense resistor between SENSEn and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up. If the voltage across the sense resistor reaches the current limit threshold VLIM, the GATEn pin voltage is lowered to maintain constant current in the external MOSFET. See Applications Information for further details. If the port is unused, the SENSEn pin must be tied to VEE. GATEn (Pins 2, 5, 9, 12, 16, 19, 22, 25, 29, 32, 36, 39): Port n Gate Drive. GATEn should be connected to the gate of the external MOSFET for port n. When the MOSFET is turned on, the gate voltage is driven to 13V (typ) above VEE. During a current limit condition, the voltage at GATEn will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATEn is pulled down, turning the MOSFET off and recording a port fault event. If the port is unused, float the GATEn pin. OUTn (Pins 3, 6, 10, 13, 17, 20, 23, 26, 28, 31, 35, 38): Port n Output Voltage Monitor. OUTn should be connected to the output port. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source voltage exceeds 10V. The port n Power Good bit is set when the voltage from OUTn to VEE drops below 2.4V (typ). A 500k resistor is connected internally from OUTn to AGND when the port is idle. If the port is unused, the OUTn pin must be floated. CAP2 (Pin 7): Analog Internal 4.3V Power Supply Bypass Capacitor. Connect 0.1μF ceramic cap to VEE. XIO0 (Pin 14): General Purpose Digital Input Output. Logic signal between VEE and VEE + 4.3V. Internal pull up. XIO1 (Pin 27): General Purpose Digital Input Output. Logic signal between VEE and VEE + 4.3V. Internal pull up. AGND (Pin 34): Analog Ground. Connect AGND to the return for the VEE supply. VEE (Pins 41, 51, 52): Main PoE Supply Input. Connect to a –45V to –57V supply, relative to AGND. Voltage depends on PSE type (Type 1, Type 2 or LTPoE++.) DNA (Pin 47): Data Transceiver Negative Input Output (Analog). Connect to DND through a data transformer. DPA (Pin 48): Data Transceiver Positive Input Output (Analog). Connect to DPD through a data transformer. CNA (Pin 49): Clock Transceiver Negative Input Output (Analog). Connect to CND through a data transformer. CPA (Pin 50): Clock Transceiver Positive Input Output (Analog). Connect to CPD through a data transformer. VSSK (Exposed Pad Pin 53): Kelvin Sense to VEE. Connect to sense resistor common node. Do not connect directly to VEE plane. See Layout Guide. Common Pins NC, DNC (LTC4271 Pins 7,13; LTC4270 Pins 42, 43, 44, 45, 46): All pins identified with “NC” or “DNC” must be left unconnected. LTC4271 AD0 (Pin 1): Address Bit 0. Tie the address pins high or low to set the starting I2C serial address to which the LTC4271 responds. The chip will respond to this address plus the next two incremental addresses. The base address of the first four ports will be (A610A3A2A1A0)b. The second and third groups of four ports will respond at the next two logical addresses. Internally pulled up to VDD. AD1 (Pin 2): Address Bit 1. See AD0. AD2 (Pin 3): Address Bit 2. See AD0. AD3 (Pin 4): Address Bit 3. See AD0. AD6 (Pin 5): Address Bit 6. See AD0. MID (Pin 6): Midspan Mode Input. When high, the LTC4271 acts as a midspan device. Internally pulled down to DGND. 42701f 14 LTC4270/LTC4271 PIN FUNCTIONS CPD (Pin 8): Clock Transceiver Positive Input Output (Digital). Connect to CPA through a data transformer. CND (Pin 9): Clock Transceiver Negative Input Output (Digital). Connect to CNA through a data transformer. DPD (Pin 10): Data Transceiver Positive Input Output (Digital). Connect to DPA through a data transformer. DND (Pin 11): Data Transceiver Negative Input Output (Digital). Connect to DNA through a data transformer. VDD33 (Pins 12, 20): VDD IO Power Supply. Connect to a 3.3V power supply relative to DGND. VDD33 must be bypassed to DGND near the LTC4271 with at least a 0.1μF capacitor. RESET (Pin 14): Reset Input, Active Low. When the RESET pin is low, the LTC4270/LTC4271 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4271 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1μs wide from resetting the LTC4270/LTC4271. Internally pulled up to VDD. INT (Pin 15): Interrupt Output, Open Drain. INT will pull low when any one of several events occur in the LTC4271. It will return to a high impedance state when bits 6 or 7 are set in the Reset PB register (1Ah). The INT signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. Individual INT events can be disabled using the INT Mask register (01h). See LTC4271 Software Programming documentation for more information. The INT pin is only updated between I2C transactions. SDAOUT (Pin 16): Serial Data Output, Open Drain Data Output for the I2C Serial Interface Bus. The LTC4271 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See Applications Information for more information. SDAIN (Pin 17): Serial Data Input. High impedance data input for the I2C serial interface bus. The LTC4271 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See Applications Information for more information. SCL (Pin 18): Serial Clock Input. High impedance clock input for the I2C serial interface bus. The SCL pin should be connected directly to the I2C SCL bus line. SCL must be tied high if the I2C serial interface bus is not used. CAP1 (Pin 19): Core Power Supply Bypass Capacitor. Connect a 1μF Bypass capacitance to DGND for the internal 1.8V regulator. Do not use other capacitor values. AUTO (Pin 21): AUTO Pin Mode Input. AUTO pin mode allows the LTC4271 to detect and power up a PD even if there is no host controller present on the I2C bus. The AUTO pin determines the state of the internal registers when the LTC4271 is reset or comes out of VDD UVLO (see LTC4271 Software Programming documentation). The states of these register bits can subsequently be changed via the I2C interface. Internally pulled down to DGND. Must be tied locally to either VDD or DGND. GP1 (Pin 22): General Purpose Digital Input Output for customer applications. Referenced to DGND. GP0 (Pin 23): General Purpose Digital Input Output for customer applications. Referenced to DGND. MSD (Pin 24): Maskable Shutdown Input. Active low. When pulled low, all ports that have their corresponding mask bit set in the mconfig register (17h) will be reset. Internal filtering of the MSD pin prevents glitches less than 1μs wide from resetting ports. The MSD Pin Mode register can configure the MSD pin polarity. Internally pulled up to VDD. DGND (Exposed Pad Pin 25): Digital Ground. DGND should be connected to the return from the VDD supply. 42701f 15 LTC4270/LTC4271 APPLICATIONS INFORMATION OVERVIEW Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial specification was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.3at or PoE+, increasing the voltage and current requirements to provide 25W of power. The IEEE standard also defines PoE terminology. A device that provides power to the network is known as a PSE, or power sourcing equipment, while a device that draws power from the network is known as a PD, or powered device. PSEs come in two types: Endpoints (typically network switches or routers), which provide data and power; and Midspans, which provide power but pass through data. Midspans are typically used to add PoE capability to existing non-PoE networks. PDs are typically IP phones, wireless access points, security cameras, and similar devices. PoE++ Evolution Even during the process of creating the IEEE PoE+ 25.5W specification it became clear that there was a significant and increasing need for more than 25.5W of delivered power. The A-grade LTC4270/LTC4271 chipset responds to this market by allowing a reliable means of providing up PSE RJ45 4 5 GND 0.22μF 100V X7R Tx 2 3 Rx 6 S1B 7 S1B 8 SPARE PAIR 42701 F10 to 90W of delivered power to a LTPoE++ PD. The LTPoE++ specification provides reliable detection and classification extensions to the existing IEEE PoE protocols that are backward compatible and interoperable with existing Type 1 and Type 2 PDs. Unlike other proprietary PoE++ solutions Linear’s LTPoE++ provides mutual identification between the PSE and PD. This ensures the LTPoE++ PD knows it may use the requested power at start-up because it has detected a LTPoE++ PSE. LTPoE++ PSEs can differentiate between a LTPoE++ PD and all other types of IEEE compliant PDs allowing LTPoE++ PSEs to remain compliant and interoperable with existing equipment. LTC4270/LTC4271 Product Family The LTC4270/LTC4271 family is a fourth generation 12-port PSE controller that implements 12 PSE ports in either an endpoint or midspan design. Virtually all necessary circuitry is included to implement an IEEE 802.3at compliant PSE design, requiring only an external power MOSFET and sense resistor per channel; these minimize power loss compared to alternative designs with onboard MOSFETs and increase system reliability in the event a single channel fails. All grades of the LTC4270/LTC4271 family offer advanced fourth generation PSE features, including per-port current monitoring, global temperature and VEE monitoring, port current policing, one second current averaging and four general purpose input/output pins. CAT 5 20Ω MAX ROUNDTRIP 0.05μF MAX RJ45 4 5 PD SPARE PAIR 1 1 Rx DATA PAIR 2 3 Tx DATA PAIR 6 1N4002 4 DGND 3.3V INTERRUPT I2C VDD33 1/12 INT LTC4270/ SCL SDAIN LTC4271 SDAOUT VEE AGND SMAJ58A 58V 5μF ≤ CIN ≤ 300μF SMAJ58A 0.1μF 1N4002 4 GND RCLASS PWRGD DC/DC CONVERTER 1μF 100V X7R –48V SENSE GATE OUT + VOUT 0.25Ω LTC4265 7 8 –48VIN –48VOUT – Figure 10. Power over Ethernet System Diagram 42701f 16 LTC4270/LTC4271 APPLICATIONS INFORMATION The LTC4270/LTC4271 chipset implements a proprietary isolation scheme for inter-chip communication. This architecture dramatically reduces BOM cost by replacing expensive opto-isolators and isolated power supplies with a single low-cost transformer. The LTC4270/LTC4271 comes in three grades which support different PD power levels. The A-grade LTC4270/LTC4271 chipset extends PoE power delivery capabilities to LTPoE++ levels. LTPoE++ is a Linear Technology proprietary specification allowing for the delivery of up to 90W to LTPoE++ compliant PDs. The LTPoE++ architecture extends the IEEE physical power negotiation to include 35W, 45W, 70W and 90W power levels. The A-grade LTC4270/LTC4271 also incorporates all B- and C-grade features. The B-grade LTC4270/LTC4271 is a fully IEEE-compliant Type 2 PSE supporting autonomous detection, classification and powering of Type 1 and Type 2 PDs. The B-grade LTC4270/LTC4271 also incorporates all C-grade features. The C-grade LTC4270/LTC4271 is a fully autonomous 802.3af Type 1 PSE solution. Intended for use only with the AUTO pin tied high, the C-grade chipset autonomously supports detection, classification and powering of Type 1 PDs. As a Type 1 PSE, two event classification is prohibited and Class 4 PDs are automatically treated as Class 0 PDs. PoE BASICS Common Ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as CAT-5 cable), transformer-coupled at each end to avoid ground loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps of the data transformers to transmit power from the PSE to the PD without affecting data transmission. Figure 10 shows a high level PoE system schematic. To avoid damaging legacy data equipment that does not expect to see DC voltage, the PoE spec defines a protocol that determines when the PSE may apply and remove power. Valid PDs are required to have a specific 25k common mode resistance at their input. When such a PD is connected to the cable, the PSE detects this signature resistance and turns on the power. When the PD is later disconnected, the PSE senses the open circuit and turns power off. The PSE also turns off power in the event of a current fault or short circuit. When a PD is detected, the PSE optionally looks for a classification signature that tells the PSE the maximum power the PD will draw. The PSE can use this information to allocate power among several ports, to police the current consumption of the PD, or to reject a PD that will draw more power than the PSE has available. The classification step is optional; if a PSE chooses not to classify a PD, it must assume that the PD is a 13W (full 802.3af power) device. New in 802.3at The newer 802.3at standard supersedes 802.3af and brings several new features: • A PD may draw as much as 25.5W. Such PDs (and the PSEs that support them) are known as Type 2. Older 13W 802.3af equipment is classified as Type 1. Type 1 PDs will work with all PSEs; Type 2 PDs may require Type 2 PSEs to work properly. The LTC4270/LTC4271 is designed to work in both Type 1 and Type 2 PSE designs, and also supports non-standard configurations at higher power levels. • The Classification protocol is expanded to allow Type 2 PSEs to detect Type 2 PDs, and to allow Type 2 PDs to determine if they are connected to a Type 2 PSE. Two versions of the new Classification protocol are available: an expanded version of the 802.3af Class Pulse protocol, and an alternate method integrated with the existing LLDP protocol (using the Ethernet data path). The LTC4270/LTC4271 fully supports the new Class Pulse protocol and is also compatible with the LLDP protocol (which is implemented in the data communications layer, not in the PoE circuitry). • Fault protection current levels and timing are adjusted to reduce peak power in the MOSFET during a fault; this allows the new 25.5W power levels to be reached using the same MOSFETs as older 13W designs. 42701f 17 LTC4270/LTC4271 APPLICATIONS INFORMATION Extended Power LTPoE++ A-grade LTC4270/LTC4271 parts add the capability to autonomously deliver up to 90W of power to the PD. LTPoE++ PDs may forgoe 802.3 LLDP support and rely solely on the LTPoE++ Physical Classification to negotiate power with LTPoE++ PSEs; this greatly simplifies highpower PD implementations. LTPoE++ may be optionally enabled for A-grade LTC4270/ LTC4271s by setting both the High Power Enable and LTPoE++ Enable bits. The higher levels of LTPoE++ delivery impose additional layout and component selection constraints. LTC4270 pin selects allow the AUTO pin mode LTC4271 to autonomously power up to supported power levels. If the AUTO pin is high, the XIO1 and XIO0 pins are sampled at reset to determine the maximum deliverable power. PDs requesting more than the available power limits are not powered. Table 1. LTPoE++ AUTO Pin Mode Maximum Delivered Power Capabilities POWER 35W 45W 70W 90W XIO1 0 0 1 1 XIO0 0 1 0 1 OPERATING MODES The LTC4270/LTC4271 includes 12 independent ports, each of which can operate in one of four modes: manual, semi-auto, AUTO pin, or shutdown. Table 2. Operating Modes MODE AUTO OPMD DETECT/ PIN CLASS 1 0 0 0 11b 11b 10b 01b Enabled at Reset N/A Host Enabled Once Upon Request Disabled POWER-UP AUTOMATIC ICUT/ILIM ASSIGNMENT Yes N/A No No AUTO Pin Reserved Semi-auto Manual Automatically N/A Upon Request Upon Request Disabled Shutdown 0 00b No In manual mode, the port waits for instructions from the host system before taking any action. It runs a single detection or classification cycle when commanded to by the host, and reports the result in its Port Status register. The host system can command the port to turn on or off the power at any time. In semi-auto mode, the port repeatedly attempts to detect and classify any PD attached to it. It reports the status of these attempts back to the host, and waits for a command from the host before turning on power to the port. The host must enable detection (and optionally classification) for the port before detection will start. AUTO pin mode operates the same as semi-auto mode except it will automatically turn on the power to the port if detection is successful. AUTO pin mode will autonomously set the ICUT and ILIM values based on the class result. This operational mode is only valid if the AUTO pin is high. In shutdown mode, the port is disabled and will not detect or power a PD. Regardless of which mode it is in, the LTC4270/LTC4271 will remove power automatically from any port that generates a current limit fault. It will also automatically remove power from any port that generates a disconnect event if disconnect detection is enabled. The host controller may also command the port to remove power at any time. 42701f BACKWARDS COMPATIBILITY The LTC4270/LTC4271 chipset is designed to be backward compatible with the LTC4266, operating in Type 2 mode, without software changes; only minor layout changes are required to implement a fully compliant IEEE 802.3at design. Some LTC4266 registers have been obsoleted in the LTC4270/LTC4271 chipset. The obsoleted registers are not required for 802.3at compliant PSE operation. For more details about software differences between the LTC4266 and LTC4270/LTC4271, refer to the LTC4271 Software Programming document. Operation with high power mode disabled is obsoleted in the LTC4270/LTC4271 chipset. All operations previously available in low power mode are fully implemented as a subset of the high power mode capabilities. 18 LTC4270/LTC4271 APPLICATIONS INFORMATION Reset and the AUTO/MID Pins The initial LTC4270/LTC4271 configuration depends on the state of the AUTO and MID pins during reset. Reset occurs at power-up, or whenever the RESET pin is pulled low or the global Reset All bit is set. Note that the AUTO pin is only sampled when a reset occurs. Changing the state of AUTO or MID after power-up will not properly change the port behavior of the LTC4270/LTC4271 until a reset occurs. Although typically used with a host controller, the LTC4270/ LTC4271 can also be used in a standalone mode with no connection to the serial interface. If there is no host present, the AUTO pin should be tied high so that, at reset, all ports will be configured to operate automatically. Each port will detect and classify repeatedly until a PD is discovered, set ICUT and ILIM according to the classification results, apply power to valid PDs, and remove power when a PD is disconnected. Table 3 shows the ICUT and ILIM values that will be automatically set in standalone (AUTO pin) mode, based on the discovered class. Table 3. ICUT and ILIM Values in Standalone Mode CLASS Class 1 Class 2 Class 3 or 0 Class 4 mode resistance of 25k ±5% at any port voltage below 10V. The PSE must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in Figure 11). The PSE may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. In particular, the PSE must reject standard computer network ports, many of which have 150Ω common-mode termination resistors that will be damaged if power is applied to them (the black region at the left of Figure 11). RESISTANCE 0Ω PD PSE 150Ω (NIC) 15k 10k 20k 23.75k 19k 30k 26.25k 26.5k 33k 42701 F11 Figure 11. IEEE 802.3af Signature Resistance Ranges 4-Point Detection The LTC4270/LTC4271 uses a 4-point detection method to discover PDs. False-positive detections are minimized by checking for signature resistance with both forced-current and forced-voltage measurements. Initially, two test currents are forced onto the port (via the OUTn pin) and the resulting voltages are measured. The detection circuitry subtracts the two V-I points to determine the resistive slope while removing offset caused by series diodes or leakage at the port (see Figure 12). If the forcedcurrent detection yields a valid signature resistance, two test voltages are then forced onto the port and the resulting currents are measured and subtracted. Both methods must report valid resistances for the port to report a valid detection. PD signature resistances between 17k and 29k (typically) are detected as valid and reported as Detect Good in the corresponding Port Status register. Values outside this range, including open and short circuits, are also reported. If the port measures less than 1V at the first forced-current test, the detection cycle will abort and Short Circuit will be reported. Table 4 shows the possible detection results. ICUT 112mA 206mA 375mA 638mA ILIM 425mA 425mA 425mA 850mA The automatic setting of ICUT and ILIM values only occurs if the LTC4270/LTC4271 is reset with the AUTO pin high. If the standalone application is a midspan, the MID pin should be tied high to enable correct midspan detection timing. DETECTION Detection Overview To avoid damaging network devices that were not designed to tolerate DC voltage, a PSE must determine whether the connected device is a real PD before applying power. The IEEE specification requires that a valid PD have a common- 42701f 19 LTC4270/LTC4271 APPLICATIONS INFORMATION 275 CURRENT (μA) 25kΩ SLOPE 165 FIRST DETECTION POINT a power-on command unless the current detect result is detect good. Any other detect result will generate a tSTART fault if a power-on command is received. In high power mode the port must be placed in manual mode to force a port on regardless of detect outcome. Behavior in AUTO pin mode is similar to semi-auto; however, after detect good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. In standalone (AUTO pin) mode, the ICUT and ILIM thresholds are automatically set; see the Reset and the AUTO/MID Pins section for more information. The signature detection circuitry is disabled when the port is initially powered up with the AUTO pin low, in shutdown mode, or when the corresponding Detect Enable bit is cleared. Detection of Legacy PDs Proprietary PDs that predate the original IEEE 802.3af standard are commonly referred to today as legacy devices. One type of legacy PD uses a large common mode capacitance (>10μF) as the detection signature. Note that PDs in this range of capacitance are defined as invalid, so a PSE that detects legacy PDs is technically noncompliant with the IEEE spec. The LTC4270/LTC4271 can be configured to detect this type of legacy PD. Legacy detection is disabled by default, but can be manually enabled on a per-port basis. When enabled, the port will report Detect Good when it sees either a valid IEEE PD or a high-capacitance legacy PD. With legacy mode disabled, only valid IEEE PDs will be recognized. CLASSIFICATION 802.3af Classification A PD may optionally present a classification signature to the PSE to indicate the maximum power it will draw while operating. The IEEE specification defines this signature as a constant current draw when the PSE port voltage is in the VCLASS range (between 15.5V and 20.5V), with the current level indicating one of 5 possible PD classes. Figure 13 shows a typical PD load line, starting with the slope of the 25k signature resistor below 10V, then transitioning to 42701f VALID PD SECOND DETECTION POINT 0V-2V OFFSET VOLTAGE 42701 F12 Figure 12. PD Detection Table 4. Detection Status MEASURED PD SIGNATURE Incomplete or Not Yet Tested < 2.4k Capacitance > 2.7μF 2.4k < RPD < 17k 17k < RPD < 29k > 29k > 50k Voltage > 10V DETECTION RESULT Detect Status Unknown Short Circuit CPD too High RSIG too Low Detect Good RSIG too High Open Circuit Port Voltage Outside Detect Range More on Operating Modes The port’s operating mode determines when the LTC4270/ LTC4271 runs a detection cycle. In manual mode, the port will idle until the host orders a detect cycle. It will then run detection, report the results, and return to idle to wait for another command. In semi-auto mode, the LTC4270/LTC4271 autonomously polls a port for PDs, but it will not apply power until commanded to do so by the host. The Port Status register is updated at the end of each detection cycle. If a valid signature resistance is detected and classification is enabled, the port will classify the PD and report that result as well. The port will then wait for at least 100ms (or 2 seconds if midspan mode is enabled), and will repeat the detection cycle to ensure that the data in the Port Status register is up-to-date. If the port is in semi-auto mode and high power operation is enabled, the port will not turn on in response to 20 LTC4270/LTC4271 APPLICATIONS INFORMATION the classification signature current (in this case, Class 3) in the VCLASS range. Table 4 shows the possible classification values. Table 4. 802.3af and 802.3at Classification Values CLASS Class 0 Class 1 Class 2 Class 3 Class 4 RESULT No Class Signature Present; Treat Like Class 3 3W 7W 13W 25.5W (Type 2) 802.3at 2-Event Classification The 802.3at specification defines two methods of classifying a Type 2 PD. A-grade and B-grade LTC4270/LTC4271 parts support 802.3at 2-event classification. One method adds extra fields to the Ethernet LLDP data protocol; although the LTC4270/LTC4271 is compatible with this classification method, it cannot perform classification directly since it doesn’t have access to the data path. LLDP classification requires the PSE to power the PD as a standard 802.3af (Type 1) device. It then waits for the host to perform LLDP communication with the PD and update the PSE port data. The LTC4270/LTC4271 supports changing the ILIM and ICUT levels on the fly, allowing the host to complete LLDP classification. The second 802.3at classification method, known as 2-event classification or ping-pong, is supported by the LTC4270/LTC4271. A Type 2 PD that is requesting more than 13W will indicate Class 4 during normal 802.3af classification. If the LTC4270/LTC4271 sees Class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9V), pauses briefly, and then re-runs classification to verify the Class 4 reading (Figure 1). It also sets a bit in the High Power Status register to indicate that it ran the second classification cycle. The second cycle alerts the PD that it is connected to a Type 2 PSE which can supply Type 2 power levels. 2-event ping-pong classification is enabled by setting a bit in the port’s High Power Mode register. Note that a pingpong enabled port only runs the second classification cycle when it detects a Class 4 device; if the first cycle returns Class 0 to 3, the port determines it is connected to a Type 1 PD and does not run the second classification cycle. Invalid Type 2 Class Combinations If classification is enabled, the port will classify the PD immediately after a successful detection cycle in semi-auto or AUTO pin modes, or when commanded to in manual mode. It measures the PD classification signature by applying 18V for 12ms (both values typical) to the port via the OUTn pin and measuring the resulting current; it then reports the discovered class in the Port Status register. If the LTC4270/LTC4271 is in AUTO pin mode, it will additionally use the classification result to set the ICUT and ILIM thresholds. See the Reset and the AUTO/MID Pin section for more information. The classification circuitry is disabled when the port is initially powered up with the AUTO pin low, in shutdown mode, or when the corresponding Class Enable bit is cleared. 60 50 40 30 20 10 0 PSE LOAD LINE OVER CURRENT 48mA CURRENT (mA) CLASS 4 CLASS 3 33mA 23mA TYPICAL CLASS 3 PD LOAD LINE 0 5 CLASS 2 14.5mA CLASS 1 CLASS 0 6.5mA 20 25 42701 F13 10 15 VOLTAGE (VCLASS) Figure 13. PD Classification The 802.3at specification defines a Type 2 PD class signature as two consecutive Class 4 results; a Class 4 followed by a Class 0-3 is not a valid signature. In AUTO pin mode, the LTC4270/LTC4271 will power a detected PD regardless of the classification results, with one exception: if the PD presents an invalid Type 2 signature (Class 4 followed by Class 0 to 3), the LTC4270/LTC4271 will not provide power and will restart the detection process. To aid in diagnosis, 42701f 21 LTC4270/LTC4271 APPLICATIONS INFORMATION the Port Status register will always report the results of the last class pulse, so an invalid Class 4–Class 2 combination would report a second class pulse was run in the High Power Status register (which implies that the first cycle found class 4), and Class 2 in the Port Status register. POWER CONTROL The primary function of the LTC4270/LTC4271 is to control the delivery of power to the PSE port. It does this by controlling the gate drive voltage of an external power MOSFET while monitoring the current via an external sense resistor and the output voltage at the OUT pin. This circuitry serves to couple the raw VEE input supply to the port in a controlled manner that satisfies the PDs power needs while minimizing both power dissipation in the MOSFET and disturbances on the VEE backplane. Inrush Control Once the command has been given to turn on a port, the LTC4270/LTC4271 ramps up the GATE pin of that port’s external MOSFET in a controlled manner. Under normal power-up circumstances, the MOSFET gate will rise until the port current reaches the inrush current limit level (typically 425mA), at which point the GATE pin will be servoed to maintain the specified IINRUSH current. During this inrush period, a timer (tSTART) runs. When output charging is complete, the port current will fall and the GATE pin will be allowed to continue rising to fully enhance the MOSFET and minimize its on-resistance. The final VGS is nominally 13V. The inrush period is maintained until the tSTART timer expires. At this time if the inrush current limit level is still exceeded, the port will be turned back off and a tSTART fault reported. Current Limit Each LTC4270/LTC4271 port includes two current limiting thresholds (ICUT and ILIM), each with a corresponding timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds depends on several factors: the class of the PD, the voltage of the main supply (VEE), the type of PSE (Type 1 or Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and whether or not the system is required to enforce class current levels. Per the IEEE specification, the LTC4270/LTC4271 will allow the port current to exceed ICUT for a limited period of time before removing power from the port, whereas it will actively control the MOSFET gate drive to keep the port current below ILIM. The port does not take any action to limit the current when only the ICUT threshold is exceeded, but does start the tCUT timer. If the current drops below the ICUT current threshold before its timer expires, the tCUT timer counts back down, but at 1/16 the rate that it counts up. If the tCUT timer reaches 60ms (typical) the port is turned off and the port tCUT fault is set. This allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. The ILIM current limiting circuit is always enabled and actively limiting port current. The tLIM timer is enabled only when the tLIM Enable bit is set. This allows tLIM to be set to a shorter value than tCUT to provide more aggressive MOSFET protection and turn off a port before MOSFET damage can occur. The tLIM timer starts when the ILIM threshold is exceeded. When the tLIM timer reaches 12ms (typical) the port is turned off and the port tLIM fault is set. When the tLIM Enable bit is disabled tLIM behaviors are tracked by the tCUT timer, which counts up during both ILIM and ICUT events. ICUT is typically set to a lower value than ILIM to allow the port to tolerate minor faults without current limiting. Per the IEEE specification, the LTC4270/LTC4271 will automatically set ILIM to 425mA (shown in bold in Table 5) during inrush at port turn-on, and then switch to the programmed ILIM setting once inrush has completed. To maintain IEEE compliance, ILIM should be kept at 425mA for all Type 1 PDs, and 850mA if a Type 2 PD is detected. ILIM is automatically reset to 425mA when a port turns off. 42701f 22 LTC4270/LTC4271 APPLICATIONS INFORMATION Table 5. Example Current Limit Settings INTERNAL REGISTER SETTING (hex) ILIM (mA) 53 106 159 213 266 319 372 425 478 531 584 638 744 850 956 1063 1169 1275 1488 1700 1913 2125 2338 2550 2975 RSENSE = 0.5Ω 88 08 89 80 8A 09 8B 00 8E 92 CB 10 D2 40 4A 50 5A 60 52 90 9A C0 CA D0 DA E0 49 40 4A 50 5A 60 52 8A 80 89 08 88 RSENSE = 0.25Ω The shaded areas in Table 5 indicate settings that may require a larger external MOSFET, additional heat sinking, or setting tLIM Enable. MOSFET Fault Detection LTC4270/LTC4271 PSE ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged. A failed MOSFET may short source to drain, which will make the port appear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the LTC4270 SENSE pin to rise to an abnormally high voltage. A failed MOSFET may also short from gate to drain, causing the LTC4270 GATE pin to rise to an abnormally high voltage. The LTC4270 OUT, SENSE and GATE pins are designed to tolerate up to 80V faults without damage. If the LTC4270/LTC4271 sees any of these conditions for more than 180μs, it disables all port functionality, reduces the gate drive pull-down current for the port and reports a FET Bad fault. This is typically a permanent fault, but the host can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault. If the MOSFET is in fact bad, the fault will quickly return, and the port will disable itself again. The remaining ports of the LTC4270/LTC4271 are unaffected. An open or missing MOSFET will not trigger a FET Bad fault, but will cause a tSTART fault if the LTC4270/LTC4271 attempts to turn on the port. Port Current Readback The LTC4270/LTC4271 measures the current at each port with an internal A/D converter. Port data is only valid when the port power is on and reads zero at all other times. The converter has two modes: • 100ms mode: Samples are taken continuously and the measured value is updated every 100ms • 1s mode: Samples are taken continuously; a moving 1 second average is updated every 100ms ILIM Foldback The LTC4270/LTC4271 features a two-stage foldback circuit that reduces the port current if the port voltage falls below the normal operating voltage. This keeps MOSFET power dissipation at safe levels for typical 802.3af MOSFETs, even at extended 802.3at power levels. Current limit and foldback behavior are programmable on a per-port basis. Table 5 gives examples of recommended ILIM register settings. The LTC4270/LTC4271 will support current levels well beyond the maximum values in the 802.3at specification. 42701f 23 LTC4270/LTC4271 APPLICATIONS INFORMATION Port Current Policing The LTC4270/LTC4271 can augment tCUT current monitoring with a policing function to track the one second current averages. A port violating the user-specified Port Police Threshold will be shut off with both a tCUT and Police event recorded. A port current Police event can be differentiated from a port tCUT violation by reading both events bits; both bits are set for a Police violation while only the tCUT bit is set for tCUT timer violations. Port Voltage Readback The LTC4270/LTC4271 measures the output voltage at each port with an internal A/D converter. Port data is only valid when the port power is on and reads zero at all other times. Disconnect The LTC4270/LTC4271 monitors powered ports to ensure the PD continues to draw the minimum specified current. A disconnect timer counts up whenever port current is below 7.5mA (typ), indicating that the PD has been disconnected. If the tDIS timer expires, the port will be turned off and the disconnect bit in the fault event register will be set. If the current returns before the tDIS timer runs out, the timer resets. As long as the PD exceeds the minimum current level more often than tDIS, it will remain powered. Although not recommended, the DC disconnect feature can be disabled by clearing the corresponding enable bits. Note that this defeats the protection mechanisms built into the IEEE specification, since a powered port will stay powered after the PD is removed. If the still-powered port is subsequently connected to a non-PoE data device, the device may be damaged. The LTC4270/LTC4271 does not include AC disconnect circuitry, but includes AC Disconnect Enable bits to maintain compatibility with the LTC4259A. If the AC Disconnect Enable bits are set, DC disconnect will be used. Masked Shutdown The LTC4270/LTC4271 provides a low latency port shedding feature to quickly reduce the system load when required. By allowing a pre-determined set of ports to be turned off, the current on an overloaded main power supply can be reduced rapidly while keeping high priority devices powered. Each port can be configured to high or low priority; all low-priority ports will shut down within 6.5μs after the MSD pin is pulled low, high priority ports will remain powered. If a port is turned off via MSD, the corresponding Detection and Classification Enable bits are cleared, so the port will remain off until the host explicitly re-enables detection. In the LTC4270/LTC4271 chipset the active level of MSD is register configurable as active high or low. The default is LTC4266-compatible active low behavior. Temperature and VEE Readback The LTC4270/LTC4271 measures the analog die temperature and VEE voltage with an internal 12-bit A/D converter. General Purpose IO Two sets of general purpose IO pins are available in the LTC4270/LTC4271 chipset. The first set of general purpose IO are GP1 and GP0. These fully bidirectional IO are 3.3V CMOS IO on the LTC4271 chip. The second set of general purpose IO pins are XIO1 and XIO0. These fully bidirectional IO are 4.3V CMOS IO on the LTC4270 chip. Code Download LTC4271 firmware is field-upgradable by downloading and executing RAM images. RAM images are volatile and must be re-downloaded after each VDD power cycle, but will remain valid during reset and VEE power events. Contact Linear Technology for code download procedures and RAM images. 42701f 24 LTC4270/LTC4271 APPLICATIONS INFORMATION SERIAL DIGITAL INTERFACE QUAD 0 I2C ADDRESS LTC4271 LTC4271 QUAD 0 QUAD 1 QUAD 2 42701 F15 I2C ADDRESS Overview The LTC4270/LTC4271 communicates with the host using a standard SMBus/I2C 2-wire interface. The LTC4270/ LTC4271 is a slave-only device, and communicates with the host master using the standard SMBus protocols. Interrupts are signaled to the host via the INT pin. The Timing Diagrams (Figures 5 through 9) show typical communication waveforms and their timing relationships. More information about the SMBus data protocols can be found at www.smbus.org. The LTC4270/LTC4271 requires both the VDD and VEE supply rails to be present for the serial interface to function. Bus Addressing The LTC4270/LTC4271’s primary 7-bit serial bus address is A610A3A2A1A0b, with bit 6 controlled by AD6 and the lower four bits set by the AD3-AD0 pins; this allows up to 10 LTC4270/LTC4271s, on a single bus. Ten LTC4270/ LTC4271 are equivalent to 30 quad PSEs or 120 ports. All LTC4270/LTC4271s also respond to the broadcast address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple LTC4270/ LTC4271s in a single transaction. If the LTC4270/LTC4271 is asserting the INT pin, it will also respond to the alert response address (0001100b) per the SMBus specification. Each LTC4270/LTC4271 is logically composed of three quads of four ports each. Each quad occupies separate, contiguous I2C addresses. The AD6, AD3-0 pins set the address of the base quad while the remaining quads are consecutively numbered. I2C addresses outside of the x10xxxxb range are considered illegal and will not respond. Each internal quad is independent of the other quads, with the exception of writes to the Chip Reset, MSD Inversion and General Purpose Input Output registers. These registers are global in nature and will affect all quads. SCL SDA AD0 AD1 AD2 AD3 AD6 0100000 3.3V AD0 AD1 AD2 AD3 AD6 0100001 0100111 QUAD 1 0101000 QUAD 2 SCL SDAIN SDAOUT 0100010 SCL SDAIN SDAOUT 0101001 Figure 14. Example I2C Bus Addressing Interrupts and SMBAlert Most LTC4270/LTC4271 port events can be configured to trigger an interrupt, asserting the INT pin and alerting the host to the event. This removes the need for the host to poll the LTC4270/LTC4271, minimizing serial bus traffic and conserving host CPU cycles. Multiple LTC4270/ LTC4271s can share a common INT line, with the host using the SMBAlert protocol (ARA) to determine which LTC4270/LTC4271 caused an interrupt. Register Description For information on serial bus usage and device configuration and status, refer to the LTC4271 Software Programming documentation. ISOLATION REQUIREMENTS IEEE 802.3 Ethernet specifications require that network segments (including PoE circuitry) be electrically isolated from the chassis ground of each network interface device. However, network segments are not required to be isolated from each other, provided that the segments are connected to devices residing within a single building on a single power distribution system. 42701f 25 LTC4270/LTC4271 APPLICATIONS INFORMATION For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main power supply for the entire device. This strategy can be used if the device has no electrically conducting ports other than twisted-pair Ethernet. In this case, the SDAIN and SDAOUT pins can be tied together and will act as a standard I2C/SMBus SDA pin. If the device is part of a larger system, contains additional external non-Ethernet ports, or must be referenced to protective ground for some other reason, the Power over Ethernet subsystem must be electrically isolated from the rest of the system. The LTC4270/LTC4271 chipset simplifies PSE isolation by allowing the LTC4271 chip to reside on the non-isolated side. There it can receive power from the main logic supply and connect directly to the I2C/SMBus bus. Isolation between the LTC4271 and LTC4270 is implemented using a proprietary transformer-based communication protocol. Additional details are provided in the Serial Bus Isolation section of this data sheet. EXTERNAL COMPONENT SELECTION Power Supplies and Bypassing The LTC4270/LTC4271 requires two supply voltages to operate. VDD requires 3.3V (nominally) relative to DGND. VEE requires a negative voltage of between –44V and –57V for Type 1 PSEs, –50V to –57V for Type 2 PSEs, or –54.75V to –57V for LTPoE++ PSEs, relative to AGND. Digital Power Supply VDD provides digital power for the LTC4271 processor, and draws a maximum of 15mA. A ceramic decoupling cap of at least 0.1μF should be placed from VDD to DGND, as close as practical to each LTC4271 chip. A 1.8V core voltage supply is generated internally and requires a 1μF ceramic decoupling cap between the CAP1 pin and DGND. In the LTC4270/LTC4271, VDD should be delivered by the host controller’s non-isolated 3.3V supply. To maintain required isolation AGND and DGND must not be connected in any way. Main PoE Power Supply VEE is the main isolated PoE supply that provides power to the PDs. Because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. For minimum IR loss and best system efficiency, set VEE near maximum amplitude (57V), leaving enough margin to account for transient over or undershoot, temperature drift, and the line regulation specifications of the particular power supply used. Bypass capacitance between AGND and VEE is very important for reliable operation. If a short circuit occurs at one of the output ports it can take as long as 1μs for the LTC4270 to begin regulating the current. During this time the current is limited only by the small impedances in the circuit and a high current spike typically occurs, causing a voltage transient on the VEE supply and possibly causing the LTC4270/LTC4271 to reset due to a UVLO fault. A 1μF , 100V X7R capacitor placed near the VEE pin along with an electrolytic bulk capacitor of at least 47μF is recommended to minimize spurious resets. Serial Bus Isolation The LTC4270/LTC4271 chipset uses transformers to isolate the LTC4271 from the LTC4270. In this case, the SDAIN and SDAOUT pins can be shorted to each other and tied directly to the I2C/SMBus bus. The transformers should be 10BASE-T or 10/100BASE-T with a 1:1 turns ratio. It is important that the selected transformers do not have common-mode chokes. These transformers typically provide 1500V of isolation between the LTC4271 and the LTC4270. For proper operation strict layout guidelines must be met. 42701f 26 LTC4270/LTC4271 APPLICATIONS INFORMATION 3.3V 0.1μF NO ISOLATION REQUIRED ON I2C INTERFACE GP0 GP1 MID RESET MSD AUTO INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 VDD33 CPD 100Ω 3.3V 100Ω LTC4271 CND DPD 100Ω 3.3V 100Ω DND DGND CAP1 1μF 2nF 2kV , XIO0 CPA 100Ω –54V 100Ω T1 100Ω –54V 100Ω T2 DNA CAP2 VEE 0.1μF VSSK CNA DPA XIO1 OUTn GATEn 0.22μF 100V S1B PORTn S1B 0.25Ω SENSEn LTC4270 0.22μF 100V OUT1 GATE1 0.25Ω AGND SENSE1 –54V S1B S1B PORT1 –54V 1μF –54V >47μF SYSTEM BULK CAP + –54V 42701 F16 Figure 15. LTC4270/LTC4271 Proprietary Isolation External MOSFET Careful selection of the power MOSFET is critical to system reliability. LTC recommends either Fairchild IRFM120A, FDT3612, FDMC3612 or Philips PHT6NQ10T for their proven reliability in Type 1 and Type 2 PSE applications. SOA curves are not a reliable specification for MOSFET selection. Contact LTC Applications before using a MOSFET other than one of these recommended parts. Sense Resistor The LTC4270/LTC4271 is designed to use 0.25Ω current sense resistors to reduce power dissipation. Four commonly available 1Ω resistors (sized according to power dissipation) can be used in parallel in place of a single 0.25Ω resistor. In order to meet the ICUT and ILIM accuracy required by the IEEE specification, the sense resistors should have ±1% tolerance or better, and no more than ±200ppm/°C temperature coefficient. In addition, the sense resistors must meet strict layout guidelines. Port Output Cap Each port requires a 0.22μF cap across its outputs to keep the LTC4270 stable while in current limit during startup or overload. Common ceramic capacitors often have significant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this problem, X7R ceramic capacitors rated for at least 100V are recommended and must be located close to the PSE. 42701f 27 LTC4270/LTC4271 APPLICATIONS INFORMATION ESD/Cable Discharge Protection Ethernet ports can be subject to significant ESD events when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the RJ45 jack. To protect against damage, each port requires a pair of clamp diodes; one to AGND and one to VEE (Figure 16). An additional surge suppressor is required for each LTC4270 chip from VEE to AGND. The diodes at the ports steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the VEE bypass capacitance. The surge suppressor has the additional benefit of protecting the LTC4270 from transients on the VEE supply. S1B diodes work well as port clamp diodes, and an SMAJ58A or equivalent is recommended for the VEE surge suppressor. LAYOUT GUIDELINES Strict adherence to board layout, parts placement and routing guidelines is critical for optimal current reading accuracy, IEEE compliance, system robustness, and thermal dissipation. Refer to the DC1682A Demo Board as a layout reference. Contact LTC Applications to obtain a full set of layout guidelines, example layouts and BOMs. AGND OUTn LTC4270 SMAJ58A 0.1μF GATEn SENSEn VEE –54V 0.25Ω 42701 F17 0.22μF S1B PORTn S1B Figure 16. LTC4270 Discharge Protection 42701f 28 3.3V 0.1μF 1μF 12 11 XIO1 1 TYPICAL APPLICATION 2 CPD 100Ω 3.3V 100Ω LTC4270 T2 CNA DPA OUT1 GATE1 SENSE1 RS 0.25Ω, 1% FDMC3612 T3 1μF 1μF DTSS 1μF 100V X7R –54V ISOLATED PHY ISOLATED GND >47μF SYSTEM BULK CAP –54V T1 0.01μF 200V 75Ω DNA AGND CAP2 VEE VSSK S1B –54V 100Ω 3.3V 100Ω DND S1B CND DPD 0.22μF 100V X7R –54V OUT12 GATE12 SENSE12 XIO0 CPA VDD33 GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 RJ45 CONNECTOR DGND CAP1 2nF 2000V RJ45 0.01μF CONNECTOR 200V 1 2 0.01μF 3 200V 75Ω 4 5 6 0.01μF 200V 7 8 (NETWORK PHYSICAL LAYER CHIP) 0.01μF 200V 75Ω 0.01μF 200V 75Ω 1 2 3 4 5 6 7 8 + 42701 F16 LTC4270/LTC4271 29 42701f LTC4270/LTC4271 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 ¥ 45 CHAMFER 23 24 0.40 0.10 1 2 2.45 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 0.25 0.05 0.50 BSC 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 42701f 30 LTC4270/LTC4271 PACKAGE DESCRIPTION UKG Package 52-Lead Plastic QFN (7mm × 8mm) (Reference LTC DWG # 05-08-1729 Rev Ø) 7.50 0.05 6.10 0.05 5.50 REF (2 SIDES) 0.70 0.05 6.45 0.05 6.50 REF (2 SIDES) 7.10 0.05 8.50 0.05 5.41 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (2 SIDES) 0.75 0.05 0.00 – 0.05 R = 0.115 TYP 5.50 REF (2 SIDES) 51 52 0.40 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 ¥ 45C CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 6.45 0.10 8.00 0.10 (2 SIDES) 6.50 REF (2 SIDES) 5.41 0.10 TOP VIEW 0.200 REF 0.00 – 0.05 R = 0.10 TYP (UKG52) QFN REV Ø 0306 0.25 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 0.75 0.05 SIDE VIEW NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 42701f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4270/LTC4271 TYPICAL APPLICATION 3.3V 0.1μF 1μF 12 11 VDD33 GP0 GP1 MID RESET MSD AUTO INT LTC4271 SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 AD6 DGND CAP1 1μF CPD 100Ω 3.3V 100Ω CND DPD 100Ω 3.3V 100Ω DND T3 1μF DTSS DNA AGND CAP2 VEE VSSK 1μF 100V X7R –54V ISOLATED ISOLATED GND >47μF SYSTEM BULK CAP PHY (NETWORK PHYSICAL LAYER CHIP) –54V T2 CNA DPA –54V XIO0 CPA XIO1 OUT12 GATE12 SENSE12 S1B 1 0.22μF 100V X7R 2 LTC4270 OUT1 GATE1 SENSE1 RS 0.25Ω, 1% FDMC3612 S1B T1 0.01μF 200V 75Ω RJ45 CONNECTOR RJ45 0.01μF CONNECTOR 200V 1 2 0.01μF 3 200V 75Ω 4 5 6 0.01μF 200V 7 8 0.01μF 200V 75Ω 1 2 3 4 5 6 7 8 2nF 2000V + –54V 0.01μF 200V 75Ω 42701 F16 RELATED PARTS PART NUMBER LTC4257-1 LTC4263 LTC4263-1 LTC4265 LTC4266 LTC4267 LTC4267-1 LTC4267-3 LTC4269-1 LTC4269-2 LTC4272 LTC4278 LTC4274 LTC4311 DESCRIPTION IEEE 802.3af PD Interface Controller Single IEEE 802.3af PSE Controller High Power Single PoE PSE Controller IEEE 802.3at PD Interface Controller Quad IEEE 802.3at PoE PSE Controller IEEE 802.3af PD Interface With Integrated Switching Regulator IEEE 802.3af PD Interface With Integrated Switching Regulator IEEE 802.3af PD Interface With Integrated Switching Regulator IEEE 802.3af PD Interface With Integrated Flyback Switching Regulator IEEE 802.3af PD Interface With Integrated Forward Switching Regulator Single-chip 12-port IEEE 802.3at PoE PSE Controller IEEE 802.3af PD Interface With Integrated Flyback Switching Regulator Single IEEE 802.3at PoE PSE Controller SMBus/ I2C Accelerator COMMENTS Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class Internal FET Switch With Internal FET Switch Internal 100V, 1A Switch, 2-Event Classification Recognition With Programmable CUT/LIM, 2-Event Classification, and Port Current and Voltage Monitoring Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class Internal 100V, 400mA Switch, Programmable Class, 200kHz Constant Frequency PWM Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, Aux Support 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to 500kHz, Aux Support With Programmable CUT/LIM, 2-Event Class, and Port Current and Voltage Monitoring 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, 12V Aux Support With Programmable CUT/LIM, 2-Event Classification, and Port Current and Voltage Monitoring Improved I2C Rise Time, Ensures Data Integrity 42701f 32 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0411 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011