LTC4274_1

LTC4274 Single PoE+ PSE Controller FEATURES n n n DESCRIPTION The LTC®4274 is a single power sourcing equipment controller designed for use in IEEE 802.3 Type 1 and Type 2 (high power) compliant Power over Ethernet systems. External power MOSFETs enhance system reliability and minimize channel resistance, cutting power dissipation and eliminating the need for heatsinks even at Type 2 power levels. External power components also allow use at very high power levels while remaining otherwise compatible with the IEEE standard. 80V-rated port pins provide robust protection against external faults. The LTC4274 includes advanced power management features, including current and voltage readback and programmable ICUT and ILIM thresholds. Available C libraries simplify software development; an optional AUTO pin mode provides fully IEEE-compliant standalone operation with no software required. Proprietary 4-point PD detection circuitry minimizes false PD detection while supporting legacy phone operation. Midspan operation is supported with built-in 2-event classification and backoff timing. Host communication is via a 1MHz I2C serial interface. The LTC4274 is available in a 5mm × 7mm QFN package that significantly reduces board space compared with competing solutions. n n n n n n n Compliant with IEEE 802.3at Type 1 and 2 0.34Ω Total Channel Resistance 130mW/Port at 600mA Advanced Power Management 8-Bit Programmable Current Limit (ILIM) 7-Bit Programmable Overload Currents (ICUT) Fast Shutdown 14.5-Bit Port Current/Voltage Monitoring 2-Event Classification Very High Reliability 4-Point PD Detection: 2-Point Forced Voltage 2-Point Forced Current High Capacitance Legacy Device Detection LTC4259A-1 and LTC4266 SW Compatible 1MHz I2C Compatible Serial Control Interface Midspan Backoff Timer Supports Proprietary Power Levels Above 25W Available in 38-Pin 5mm × 7mm QFN Package APPLICATIONS n n PSE Switches/Routers PSE Midspans L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Complete Ethernet High Power Source 3.3V 0.1μF INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 1μF 100V SHDN VDD AUTO MSD RESET MID GATE OUT S1B 0.22μF 100V PORT 4274 TA01 LTC4274 VEE SENSE SMAJ58A –54V S1B –54V 4274fa 1 LTC4274 ABSOLUTE MAXIMUM RATINGS Supply Voltages (Note 1) AGND – VEE ........................................... –0.3V to 80V DGND – VEE ............................................... –0.3V to 80V VDD – DGND.............................................. –0.3V to 5.5V Digital Pins SCL, SDAIN, SDAOUT, INT, SHDN, MSD, ADn, RESET, AUTO, MID........... DGND –0.3V to VDD + 0.3V Analog Pins GATE, SENSE, OUT ................ VEE – 0.3V to VEE + 80V Operating Temperature Range LTC4274C ................................................ 0°C to 70°C LTC4274I..............................................–40°C to 85°C Junction Temperature (Note 2) ............................. 125°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C PIN CONFIGURATION TOP VIEW RESET AUTO MSD OUT 31 GATE 30 SENSE 29 NC 28 NC 27 VEE VEE 39 26 VEE 25 VEE 24 NC 23 NC 22 VEE 21 NC 20 NC 13 14 15 16 17 18 19 SHDN DGND DGND DGND AGND VDD VEE MID SCL SDAOUT 1 NC 2 SDAIN 3 AD3 4 AD2 5 AD1 6 AD0 7 DNC 8 NC 9 DGND 10 NC 11 NC 12 INT 38 37 36 35 34 33 32 UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN EXPOSED PAD IS VEE (PIN 39) MUST BE SOLDERED TO PCB TJMAX = 125°C, JA = 34°C/W ORDER INFORMATION LEAD FREE FINISH LTC4274CUHF#PBF LTC4274IUHF#PBF PACKAGE DESCRIPTION TEMPERATURE RANGE 0°C to 70°C 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C 38-Lead (5mm × 7mm) Plastic QFN Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. TAPE AND REEL LTC4274CUHF#TRPBF LTC4274IUHF#TRPBF PART MARKING* 4274 4274 For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4274fa 2 LTC4274 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER –48V Supply Voltage The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) CONDITIONS AGND – VEE For IEEE Type 1 Complaint Output For IEEE Type 2 Complaint Output VDD – DGND DGND – VEE (AGND – VEE) = 55V (VDD – DGND) = 3.3V First Point, AGND – VOUT = 9V Second Point, AGND – VOUT = 3.5V AGND – VOUT, 5μA ≤ IOUT ≤ 500μA First Point Second Point AGND – VOUT = 0V AGND – VOUT, Open Port AGND – VOUT, CPORT = 0.15μF l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l MIN 45 51 20 3.0 25 TYP MAX 57 57 UNITS V V V V V V mA mA μA μA V V mA V V/μs kΩ kΩ V mA mA mA mA mA mA V mA mA mA mA Undervoltage Lock-out Level VDD VDD Supply Voltage Undervoltage Lock-out Allowable Digital Ground Offset IEE IDD Detection Detection Current – Force Current Detection Voltage – Force Voltage VEE Supply Current VDD Supply Current 25 3.3 2.2 30 4.3 57 –2.4 1.1 220 140 7 3 240 160 8 4 0.8 10.4 15.5 27.5 16.0 53 5.5 13.5 21.5 31.5 45.2 7.5 53 0.4 0.08 8 2 300 2.4 500 61 6.5 14.5 23 33 48 9 61 17 29.7 –5 3 260 180 9 5 0.9 12 0.01 18.5 32 20.5 67 7.5 15.5 24.5 34.9 50.8 10 67 Detection Current Compliance VOC Detection Voltage Compliance Detection Voltage Slew Rate Min. Valid Signature Resistance Max. Valid Signature Resistance Classification VCLASS Classification Voltage Classification Current Compliance Classification Threshold Current AGND – VOUT, 0mA ≤ ICLASS ≤ 50mA VOUT = AGND Class 0 – 1 Class 1 – 2 Class 2 – 3 Class 3 – 4 Class 4 – Overcurrent AGND – VOUT, 0.1mA ≤ ICLASS ≤ 10mA VOUT = AGND Port Off, VGATE = VEE + 5V Port Off, VGATE = VEE + 1V VGATE = VEE + 5V VGATE – VEE, IGATE = 1μA VOUT – VEE 0V ≤ (AGND – VOUT) ≤ 5V VMARK Gate Driver Classification Mark State Voltage Mark State Current Compliance GATE Pin Pull-Down Current GATE Pin Fast Pull-Down Current GATE Pin On Voltage 0.12 30 14 2.8 700 V V kΩ Output Voltage Sense VPG Power Good Threshold Voltage OUT Pin Pull-Up Resistance to AGND 4274fa 3 LTC4274 ELECTRICAL CHARACTERISTICS SYMBOL VCUT PARAMETER Overcurrent Sense Voltage Current Sense VSENSE – VEE, icut1 = hpen = 00h hpen = 01h, cut[5:0] ≥ 4 (Note 12) cutrng = 0 cutrng = 1 Class 0, Class 3 Class 1 Class 2 Class 4 VSENSE – VEE, dblpwr = hpen = 00h VEE = 55V (Note 12) VEE < VOUT < AGND – 29V AGND – VOUT = 0V hpen = 01h, lim1 = C0h, VEE = 55V VOUT – VEE = 0V to 10V VEE + 23V < VOUT < AGND – 29V AGND – VOUT = 0V VOUT – VEE = 0V to 10V, VEE = 55V Class 0 to Class 3 Class 4 VSENSE – VEE, rdis = 0 VSENSE – VEE, rdis = 1 VSENSE – VEE – VLIM, rdis = 0 VSENSE – VEE – VLIM, rdis = 1 No missing codes, fast_iv = 0 VSENSE – VEE (Note 7) No missing codes, fast_iv = 0 AGND – VOUT (Note 7) (Note 6) (Note 6) ISDAOUT = 3mA, IINT = 3mA ISDAOUT = 5mA, IINT = 5mA ADn, SHDN, RESET, MSD AUTO, MID l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) CONDITIONS MIN 180 9 4.5 90 26 49 152 TYP 188 9.38 4.69 94 28 52 159 MAX 196 9.75 4.88 98 30 55 166 UNITS mV mV/LSB mV/LSB mV mV mV mV Overcurrent Sense in AUTO Pin Mode VLIM Active Current Limit in 802.3af Compliant Mode l l l l l l l l l l l 204 40 204 100 20 102 204 2.6 1.3 160 75 212 220 100 221 113 50 110 221 4.8 2.41 255 135 mV mV mV mV mV mV mV mV mV mV mV bits μV/LSB dB bits mV/LSB dB VLIM Active Current Limit in High Power Mode 212 106 VLIM Active Current Limit in AUTO Pin Mode 106 212 3.8 1.9 200 100 14 30.5 30 14 5.835 30 VMIN VSC DC Disconnect Sense Voltage Short-Circuit Sense Port Current ReadBack Resolution LSB Weight 50-60Hz Noise Rejection Port Voltage ReadBack Resolution LSB Weight 50-60Hz noise rejection Digital Interface VILD VIHD Digital Input Low Voltage Digital Input High Voltage Digital Output Low Voltage Internal Pull-Up to VDD Internal Pull-Down to DGND 0.8 2.2 0.4 0.7 50 50 V V V V kΩ kΩ 4274fa 4 LTC4274 ELECTRICAL CHARACTERISTICS SYMBOL tDET tDETDLY tCLE1 tME1 tCLE2 tME2 tCLE3 tPON PARAMETER Detection Time Detection Delay First Class Event Duration First Mark Event Duration Second Class Event Duration Second Mark Event Duration Third Class Event Duration Power On Delay in AUTO Pin Mode Turn On Rise Time Turn On Ramp Rate Fault Delay Midspan Mode Detection Backoff Power Removal Detection Delay tSTART tLIM, tICUT Timing Characteristics Beginning to End of Detection (Note 7) From PD Connected to Port to Detection Complete (Note 7) (Note 7) (Notes 7, 11) (Note 7) (Note 7) CPORT = 0.6μF (Note 7) From End of Valid Detect to Application of Power to Port (Note 7) (AGND – VOUT): 10% to 90% of (AGND – VEE), CPORT = 0.15μF (Note 7) CPORT = 0.15μF (Note 7) From ICUT Fault to Next Detect Rport = 15.5kΩ (Note 7) From Power Removal After tDIS to Next Detect (Note 7) l l l l l l l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) CONDITIONS MIN 270 300 11 6.8 11 19 12 8.6 12 22 0.1 60 15 24 10 1.0 2.3 1.0 52 52 5.8 1.6 320 350 1.1 2.5 1.3 62.5 62.5 6.3 2.7 2.5 66 66 6.7 3.6 380 6.5 6.5 1.5 3 3 4.5 2 3 TYP 290 MAX 310 470 13 10.3 13 UNITS ms ms ms ms ms ms ms ms μs V/μs s s s ms ms % ms ms μs μs s μs μs μs Maximum Current Limit Duration During Port tSTART1 = 0, tSTART0 = 0 (Notes 7, 12) Start-Up Maximum Current Limit Duration After Port Start-Up Maximum Current Limit Duty Cycle tICUT1 = 0, tICUT0 = 0 (Notes 7, 12) (Note 7) tMPS tDIS tMSD tSHDN Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect Sensitivity Timer (Notes 7, 8) Maintain Power Signature (MPS) Dropout Time Masked Shut Down Delay Port Shut Down Delay I2C Watchdog Timer Duration Minimum Pulse Width for Masked Shut Down Minimum Pulse Width for SHDN Minimum Pulse Width for RESET (Note 7) (Note 7) (Note 7) tconf [1:0] = 00b (Notes 5, 12) (Note 7) (Note 7) l l l 4274fa 5 LTC4274 ELECTRICAL CHARACTERISTICS SYMBOL I2C Timing Clock Frequency t1 t2 t3 t4 t5 t6 t7 t8 tr tf Bus Free Time Start Hold Time SCL Low Time SCL High Time Data Hold Time Data Set-Up Time Start Set-Up Time Stop Set-Up Time SCL, SDAIN Rise Time SCL, SDAIN Fall Time Fault Present to INT Pin Low Stop Condition to INT Pin Low ARA to INT Pin High Time SCL Fall to ACK Low (Note 7) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Data into chip Data out of chip Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) Figure 5 (Notes 7, 9) (Notes 7, 9, 10) (Notes 7, 9, 10) (Notes 7, 9) (Notes 7, 9) l l l l l l l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless otherwise noted. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX 1 480 240 480 240 60 120 80 240 240 120 60 150 1.5 1.5 120 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns μs μs ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 140°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: All currents into device pins are positive; all currents out of device pins are negative. Note 4: The LTC4274 operates with a negative supply voltage (with respect to ground). To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Note 5: tDIS is the same as tMPDO defined by IEEE 802.3at. Note 6: The LTC4274 digital interface operates with respect to DGND. All logic levels are measured with respect to DGND. Note 7: Guaranteed by design, not subject to test. Note 8: The IEEE 802.3af specification allows a PD to present its Maintain Power Signature (MPS) on an intermittent basis without being disconnected. In order to stay powered, the PD must present the MPS for tMPS within any tMPDO time window. Note 9: Values measured at VILD(MAX) and VIHD(MIN). Note 10: If fault condition occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. Note 11: Load Characteristic of the LTC4274 during Mark: 7V < (AGND – VOUT) < 10V or IOUT < 50μA Note 12: See the LTC4274 Software Programming documentation for information on serial bus usage and device configuration and status registers. 4274fa 6 LTC4274 TYPICAL PERFORMANCE CHARACTERISTICS Power On Sequence in AUTO Pin Mode 10 FORCED CURRENT DETECTION 0 –10 PORT VOLTAGE (V) –20 –30 –40 –50 –60 –70 100ms/DIV 4274 G01 Powering Up into a 180μF Load GND GND PORT VOLTAGE 20V/DIV VDD = 3.3V VEE = –54V VEE PORT CURRENT 200 mA/DIV 0mA GATE VOLTAGE 10V/DIV VEE FOLDBACK PORT VOLTAGE 10V/DIV LOAD FULLY CHARGED 802.3af Classification in AUTO Pin Mode GND –18.4 FORCED VOLTAGE DETECTION PORT 1 VDD = 3.3V VEE = –54V VEE 802.3af CLASSIFICATION POWER ON 425mA CURRENT LIMIT VDD = 3.3V VEE = –55V PD IS CLASS 1 FET ON VEE 5ms/DIV 4274 G02 5ms/DIV 4274 G03 2-Event Classification in AUTO Pin Mode GND PORT CURRENT 20mA/DIV –17.6 1ST CLASS EVENT 2ND CLASS EVENT PORT VOLTAGE 10V/DIV VDD = 3.3V VEE = –55V PD IS CLASS 4 40mA Classification Transient Response to 40mA Load Step VDD = 3.3V VEE = –54V CLASSIFICATION VOLTAGE (V) 0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 50μs/DIV 4274 G04 4274 G05 Classification Current Compliance VDD = 3.3V VEE = –54V TA = 25°C 0mA PORT VOLTAGE 1V/DIV –20V VEE 10ms/DIV 0 10 20 30 40 50 60 CLASSIFICATION CURRENT 70 4274 G06 VDD Supply Current vs Voltage 1.8 1.7 IDD SUPPLY CURRENT (mA) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.7 2.9 3.1 3.3 3.5 3.7 3.9 VDD SUPPLY VOLTAGE (V) 4.1 4.3 –40°C 25°C 85°C 2.4 VEE Supply Current vs Voltage 215 802.3at ILIM Threshold vs Temperature VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 48h = C0h 860 IEE SUPPLY CURRENT (mA) 2.3 VLIM (mV) 214 856 213 852 ILIM (mA) 2.2 212 848 2.1 –40°C 25°C 85°C 2.0 –60 –55 –50 –45 –40 –35 –30 –25 –20 VEE SUPPLY VOLTAGE (V) 4274 G08 211 844 210 –40 0 40 –80 TEMPERATURE (°C) 840 120 4274 G09 4274 G07 4274fa 7 LTC4274 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af ILIM Threshold vs Temperature 108.00 VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 48h = 80h 432 163 802.3at ICUT Threshold vs Temperature VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 47h = E2h 652 107.25 VLIM (mV) 429 VCUT (mV) ILIM (mA) 162 648 161 644 ICUT (mA) 106.50 426 160 640 105.75 423 159 636 105.00 –40 0 40 80 TEMPERATURE (°C) 420 120 4274 G10 158 –40 0 40 80 TEMPERATURE (°C) 630 120 4274 G11 802.3af ICUT Threshold vs Temperature 96.00 VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 47h = D4h 384 2.0000 DC Disconnect Threshold vs Temperature 8.00 VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 47h = E2h 95.25 VCUT (mV) 381 VMIN (mV) ICUT (mA) 1.9375 7.75 IMIN (mV) 94.50 378 1.8750 7.50 93.75 375 1.8125 7.25 93.00 –40 0 80 40 TEMPERATURE (°C) 372 120 4274 G12 1.7500 –40 0 80 40 TEMPERATURE (°C) 7.00 120 4266 G13 Current Limit Foldback 900 800 700 600 ILIM (mA) 500 400 300 200 100 0 –54 –45 –36 –18 –27 VOUTn (V) –9 0 4274 G14 ADC Noise Histogram Current Readback in Fast Mode 225 200 175 150 125 100 75 50 25 0 BIN COUNT VLIM (mV) 400 350 300 250 200 150 100 50 0 191 192 193 194 ADC OUTPUT 195 196 4274 G15 ADC Integral Nonlinearity Current Readback in Fast Mode 1.0 ADC INTEGRAL NONLINEARITY (LSBs) VDD = 3.3V VEE = –54V RSENSE = 0.25Ω REG 48h = C0h VSENSE – VEE = 110.4mV 0.5 0 –0.5 –1.0 0 50 100 150 200 250 300 350 400 450 500 CURRENT SENSE RESISTOR INPUT VOLTAGE (mV) 4274 G16 4274fa 8 LTC4274 TYPICAL PERFORMANCE CHARACTERISTICS ADC Noise Histogram Current Readback in Slow Mode 300 250 200 BIN COUNT 150 100 50 0 6139 6141 6143 ADC OUTPUT 6145 6147 4274 G17 ADC Integral Nonlinearity Current Readback in Slow Mode 1.0 ADC INTEGRAL NONLINEARITY (LSBs) 600 500 0.5 400 0 BIN COUNT 300 200 –0.5 100 –1.0 0 ADC Noise Histogram Port Voltage Readback in Fast Mode AGND – VOUTn = 48.3V VSENSEn – VEE = 110.4mV 0 50 100 150 200 250 300 350 400 450 500 CURRENT SENSE RESISTOR INPUT VOLTAGE (mV) 4274 G18 260 261 262 263 ADC OUTPUT 264 265 4274 G19 ADC Integral Nonlinearity Voltage Readback in Fast Mode 1.0 ADC INTEGRAL NONLINEARITY (LSBs) 600 500 0.5 400 BIN COUNT 0 300 200 –0.5 100 –1.0 0 ADC Noise Histogram Port Voltage Readback in Slow Mode ADC INTEGRAL NONLINEARITY (LSBs) AGND – VOUTn = 48.3V 1.0 ADC Integral Nonlinearity Voltage Readback in Slow Mode 0.5 0 –0.5 0 10 20 40 30 PORT VOLTAGE (V) 50 60 4274 G20 –1.0 8532 8533 8534 8535 ADC OUTPUT 8536 4274 G21 0 10 20 40 30 PORT VOLTAGE (V) 50 60 4274 G22 INT and SDAOUT Pull Down Voltage vs Load Current 3 2.5 PULL DOWN VOLTAGE (V) 2 1.5 1 0.5 0 0 5 10 15 20 25 30 LOAD CURRENT (mA) 35 40 PORT VOLTAGE 20V/DIV VEE GATE VOLTAGE 10V/DIV VEE GND MOSFET Gate Drive With Fast Pull Down VDD = 3.3V VEE = –54V FAST PULL DOWN PORT CURRENT 500mA/DIV 0mA 50Ω FAULT APPLIED CURRENT LIMIT 50Ω FAULT REMOVED 100μs/DIV 4274 G24 4274 G23 4274fa 9 LTC4274 TEST TIMING DIAGRAMS tDET FORCED-CURRENT 0V VPORT VOC VMARK VCLASS tCLE1 tCLE2 PD CONNECTED tCLE3 tME2 15.5V 20.5V FORCEDVOLTAGE CLASSIFICATION tME1 tDETDLY INT tPON VEE 4274 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes VLIM VSENSE TO VEE 0V INT VCUT tSTART, tICUT VSENSE TO VEE VMIN INT tMPS 4274 F02 tDIS 4274 F03 Figure 2. Current Limit Timing Figure 3. DC Disconnect Timing t3 VGATE tMSD tSHDN MSD or SHDN 4274 F04 tr t4 tf VEE SCL t2 SDA t1 4274 F05 t5 t6 t7 t8 Figure 4. Shut Down Delay Timing Figure 5. I2C Interface Timing 4274fa 10 LTC4274 I2C TIMING DIAGRAMS SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE ACK BY SLAVE FRAME 3 DATA BYTE ACK BY SLAVE STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 4274 F06 Figure 6. Writing to a Register SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE ACK BY SLAVE REPEATED START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER FRAME 2 REGISTER ADDRESS BYTE 4274 F07 Figure 7. Reading from a Register SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER 4274 F08 Figure 8. Reading the Interrupt Register (Short Form) SCL SDA 0 0 0 1 1 0 0 R/W ACK 0 1 0 AD3 AD2 AD1 AD0 1 ACK START BY MASTER FRAME 1 ALERT RESPONSE ADDRESS BYTE ACK BY SLAVE NO ACK BY MASTER STOP BY MASTER 4274 F09 FRAME 2 SERIAL BUS ADDRESS BYTE Figure 9. Reading from Alert Response Address 4274fa 11 LTC4274 PIN FUNCTIONS RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4274 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4274 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1μs wide from resetting the LTC4274. Internally pulled up to VDD. MID: Midspan Mode Input. When high, the LTC4274 acts as a midspan device. Internally pulled down to DGND. INT: Interrupt Output, Open Drain. INT will pull low when any one of several events occur in the LTC4274. It will return to a high impedance state when bits 6 or 7 are set in the Reset PB register (1Ah). The INT signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. Individual INT events can be disabled using the Int Mask register (01h). See the LTC4274 Software Programming documentation for more information. The INT pin is only updated between I2C transactions. SCL: Serial Clock Input. High impedance clock input for the I2C serial interface bus. SCL must be tied high if not used. SDAOUT: Serial Data Output, Open Drain Data Output for the I2C Serial Interface Bus. The LTC4274 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. SDAOUT should be grounded or left floating if not used. See Applications Information for more information. SDAIN: Serial Data Input. High impedance data input for the I2C serial interface bus. The LTC4274 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. SDAIN must be tied high if not used. See Applications Information for more information. AD3: Address Bit 3. Tie the address pins high or low to set the I2C serial address to which the LTC4274 responds. This address will be 010A3A2A1A0b. Internally pulled up to VDD. AD2: Address Bit 2. See AD3. AD1: Address Bit 1. See AD3. AD0: Address Bit 0. See AD3. NC, DNC: All pins identified with “NC” or “DNC” must be left unconnected. DGND: Digital Ground. DGND is the return for the VDD supply. VDD: Logic Power Supply. Connect to a 3.3V power supply relative to DGND. VDD must be bypassed to DGND near the LTC4274 with at least a 0.1μF capacitor. SHDN: Shutdown, Active Low. When pulled low, SHDN shuts down the port, regardless of the state of the internal registers. Pulling SHDN low is equivalent to setting the Reset Port bit in the Reset Pushbutton register (1Ah). Internal filtering of the SHDN pin prevents glitches less than 1μs wide from reseting the port. Internally pulled up to VDD. AGND: Analog Ground. AGND is the return for the VEE supply. SENSE: Current Sense Input. SENSE monitors the external MOSFET current via a 0.5Ω or 0.25Ω sense resistor between SENSE and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up. If the voltage across the sense resistor reaches the current limit threshold VLIM, the GATE pin voltage is lowered to maintain constant current in the external MOSFET. See Applications Information for further details. GATE: Gate Drive. GATE should be connected to the gate of the external MOSFET for the port. When the MOSFET is turned on, the gate voltage is driven to 13V (typ) above VEE. During a current limit condition, the voltage at GATE will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE is pulled down, turning the MOSFET off and recording a tCUT or tSTART event. 4274fa 12 LTC4274 PIN FUNCTIONS OUT: Output Voltage Monitor. OUT should be connected to the output port. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source voltage exceeds 10V. The Power Good bit is set when the voltage from OUT to VEE drops below 2.4V (typ). A 500k resistor is connected internally from OUT to AGND when the port is idle. VEE: Main Supply Input. Connect to a –45V to –57V supply, relative to AGND. AUTO: AUTO Pin Mode Input. AUTO pin mode allows the LTC4274 to detect and power up a PD even if there is no host controller present on the I2C bus. The voltage of the AUTO pin determines the state of the internal registers when the LTC4274 is reset or comes out of VDD UVLO (see the Register map). The states of these register bits can subsequently be changed via the I2C interface. The real-time state of the AUTO pin is read at bit 0 in the Pin Status register (11h). Internally pulled down to DGND. Must be tied locally to either VDD or DGND. MSD: Maskable Shutdown Input. Active low. When pulled low, all ports that have their corresponding mask bit set in the Misc Config register (17h) will be reset, equivalent to pulling the SHDN pin low. Internal filtering of the MSD pin prevents glitches less than 1μs wide from resetting ports. Internally pulled up to VDD. 4274fa 13 LTC4274 OPERATION Overview Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial spec was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.3at or PoE+, increasing the voltage and current requirements to provide 25W of power. The IEEE standard also defines PoE terminology. A device that provides power to the network is known as a PSE, or power sourcing equipment, while a device that draws power from the network is known as a PD, or powered device. PSEs come in two types: Endpoints (typically network switches or routers), which provide data and power; and Midspans, which provide power but pass through data. Midspans are typically used to add PoE capability to existing non-PoE networks. PDs are typically IP phones, wireless access points, security cameras, and similar devices, but could be nearly anything that runs from 25W or less and includes an RJ45-style network connector. The LTC4274 is a third-generation single PSE controller in either an endpoint or midspan design. Virtually all necessary circuitry is included to implement a IEEE 802.3at compliant PSE design, requiring only an external power MOSFET and sense resistor; these minimize power loss PSE RJ45 4 5 GND 0.22μF 100V X7R Tx 2 3 Rx 6 S1B IRFM120A S1B 7 8 SPARE PAIR 4274 F10 compared to alternative designs with on-board MOSFETs and increase system reliability in the event a single channel is damaged. PoE Basics Common Ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as CAT-5 cable), transformer-coupled at each end to avoid ground loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps of the data transformers to transmit power from the PSE to the PD without affecting data transmission. Figure 10 shows a high-level PoE system schematic. To avoid damaging legacy data equipment that does not expect to see DC voltage, the PoE spec defines a protocol that determines when the PSE may apply and remove power. Valid PDs are required to have a specific 25kΩ common-mode resistance at their input. When such a PD is connected to the cable, the PSE detects this signature resistance and turns on the power. When the PD is later disconnected, the PSE senses the open circuit and turns power off. The PSE also turns off power in the event of a current fault or short circuit. When a PD is detected, the PSE optionally looks for a classification signature that tells the PSE the maximum power the PD will draw. The PSE can use this information to allocate power among several ports, police the current consumption of the PD, or to reject a PD that will draw CAT 5 RJ45 4 5 PD SPARE PAIR 1 1 Rx DATA PAIR 2 3 Tx DATA PAIR 6 1N4002 4 DGND 3.3V INTERRUPT SMAJ58A 58V I 2C VDD INT SCL LTC4274 SDAIN SDAOUT VEE AGND SMAJ58A 58V 5μF ≤ CIN ≤ 300μF 0.1μF 1N4002 4 100V GND RCLASS PWRGD DC/DC CONVERTER 1μF 100V X7R –54V SENSE GATE OUT + VOUT 0.25Ω LTC4265 7 8 VIN VOUT – Figure 10. Power Over Ethernet System Diagram 4274fa 14 LTC4274 OPERATION more power that the PSE has available. The classification step is optional; if a PSE chooses not to classify a PD, it must assume that the PD is a 13W (full 802.3af power) device. New in 802.3at The newer 802.3at standard supersedes 802.3af and brings several new features: • A PD may draw as much as 25.5W. Such PDs (and the PSEs that support them) are known as Type 2. Older 13W 802.3af equipment is classified as Type 1. Type 1 PDs will work with all PSEs; Type 2 PDs may require Type 2 PSEs to work properly. The LTC4274 is designed to work in both Type 1 and Type 2 PSE designs, and also supports non-standard configurations at higher power levels. • The Classification protocol is expanded to allow Type 2 PSEs to detect Type 2 PDs, and to allow Type 2 PDs to determine if they are connected to a Type 2 PSE. Two versions of the new Classification protocol are available: an expanded version of the 802.3af Class Pulse protocol, and an alternate method integrated with the existing LLDP protocol (using the Ethernet data path). The LTC4274 fully supports the new Class Pulse protocol and is also compatible with the LLDP protocol (which is implemented in the data communications layer, not in the PoE circuitry). • Fault protection current levels and timing are adjusted to reduce peak power in the MOSFET during a fault; this allows the new 25.5W power levels to be reached using the same MOSFETs as older 13W designs. BACKWARDS COMPATIBILITY The LTC4274 is fully software and pin compatible with the LTC4266 if only port 1 was used. The LTC4274 is designed to be backward compatible with earlier PSE chips in both software and pin functions. Existing systems using either the LTC4258 or LTC4259A (or compatible) devices can be substituted with the LTC4274 without software or PCB layout changes if only port 1 was used; only minor BOM changes are required to implement a fully compliant 802.3at design. Because of the backwards compatibility features, some of the internal registers are redundant or unused when the LTC4274 is operated as recommended. For more details on usage in compatibility mode, refer to the LTC4258/ LTC4259A device datasheets. Special Compatibility Mode Notes • The LTC4274 can use either 0.5Ω or 0.25Ω sense resistors, while the LTC425x chips always used 0.5Ω. To maintain compatibility, if the AUTO pin is low when the LTC4274 powers up it assumes the sense resistor is 0.5Ω; if it is high at power up, the LTC4274 assumes 0.25Ω. The resistor value setting can be reconfigured at any time after power up. In particular, systems that use 0.25Ω sense resistors and have AUTO tied low must reconfigure the resistor settings after power up. • The LTC4259A included both AC and DC disconnect sensing circuitry, but the LTC4274 has only DC disconnect sensing. For the sake of compatibility, register bits used to enable AC disconnect in the LTC4259A are implemented in the LTC4274, but they simply mirror the bits used for DC disconnect. • The LTC4258 and LTC4259A required 10k resistors between the OUTn pins and the drains of the external MOSFETs. These resistors must be shorted or replaced with zero ohm jumpers when using the LTC4274. • The LTC4258 and LTC4259A included a BYP pin, decoupled to AGND with 0.1μF This pin changes to the MID . pin on the LTC4274. The capacitor should be removed for Endspan applications, or replaced with a zero ohm jumper for Midspan applications. 4274fa 15 LTC4274 APPLICATIONS INFORMATION Operating Modes The LTC4274 can operate in one of four modes: manual, semi-auto, AUTO pin, or shutdown. Table 1. Operating Modes AUTO PIN OPMD 1 0 0 0 0 11b 11b 10b 01b 00b DETECT/ CLASS AUTOMATIC ICUT/ILIM ASSIGNMENT Yes N/A No No No Regardless of which mode it is in, the LTC4274 will remove power automatically from a port that generates a current limit fault. It will also automatically remove power from a port that generates a disconnect event if disconnect detection is enabled. The host controller may also command the port to remove power at any time. Reset and the AUTO/MID pins The initial LTC4274 configuration depends on the state of the AUTO and MID pins during reset. Reset occurs at power-up, or whenever the RESET pin is pulled low or the global Reset All bit is set. Note that the AUTO pin is only sampled when a reset occurs. Changing the state of AUTO or MID after power-up will not change the port behavior of the LTC4274 until a reset occurs. Although typically used with a host controller, the LTC4274 can also be used in a standalone mode with no connection to the serial interface. If there is no host present, the AUTO pin should be tied high so that, at reset, the port will be configured to operate automatically. The port will detect and classify repeatedly until a PD is discovered, set ICUT and ILIM according to the classification results, apply power after successful detection, and remove power when a PD is disconnected. Similarly, if the standalone application is a midspan, the MID pin should be tied high to enable correct midspan detection timing. Table 2 shows the ICUT and ILIM values that will be automatically set in AUTO pin mode, based on the discovered class. Table 2. ICUT and ILIM Values in AUTO Pin Mode CLASS Class 1 Class 2 Class 3 or Class 0 Class 4 ICUT 112mA 206mA 375mA 638mA ILIM 425mA 425mA 425mA 850mA MODE AUTO Pin Reserved Semi-auto Manual Shutdown POWER-UP Enabled at Automatically Reset N/A Host Enabled Once Upon Request Disabled N/A Upon Request Upon Request Disabled • In manual mode, the port waits for instructions from the host system before taking any action. It runs a single detection or classification cycle when commanded to by the host, and reports the result in its Port Status register. The host system can command the port to turn on or off the power at any time. This mode should only be used for diagnostic and test purposes. • In semi-auto mode, the port repeatedly attempts to detect and classify any PD attached to it. It reports the status of these attempts back to the host, and waits for a command from the host before turning on power to the port. The host must enable detection (and optionally classification) for the port before detection will start. • AUTO pin mode operates the same as semi-auto mode except that it will automatically turn on the power to the port if detection is successful. In AUTO pin mode, ICUT and ILIM values are set automatically by the LTC4274. The AUTO pin must be high at reset to ensure proper AUTO pin mode operation. • In shutdown mode, the port is disabled and will not detect or power a PD. The automatic setting of the ICUT and ILIM values only occurs if the LTC4274 is reset with the AUTO pin high. 4274fa 16 LTC4274 APPLICATIONS INFORMATION DETECTION Detection Overview To avoid damaging network devices that were not designed to tolerate DC voltage, a PSE must determine whether the connected device is a real PD before applying power. The IEEE specification requires that a valid PD have a commonmode resistance of 25k ±5% at any port voltage below 10V. The PSE must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in Figure 11). The PSE may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. In particular, the PSE must reject standard computer network ports, many of which have 150Ω common-mode termination resistors that will be damaged if power is applied to them (the black region at the left of Figure 11). RESISTANCE 0Ω PD PSE 150Ω (NIC) 15k 10k 20k 23.75k 19k 30k 26.25k 26.5k 33k 4274 F11 and short circuits, are also reported. If the port measures less than 1V at the first forced-current test, the detection cycle will abort and Short Circuit will be reported. Table 3 shows the possible detection results. Table 3. Detection Status MEASURED PD SIGNATURE Incomplete or Not Yet Tested 2.7μF 2.4k < RPD < 17k 17k < RPD < 29k >29k >50k Voltage > 10V DETECTION RESULT Detect Status Unknown Short Circuit CPD too High RSIG too Low Detect Good RSIG too High Open Circuit Port Voltage Outside Detect Range Operating Modes The port’s operating mode determines when the LTC4274 runs a detection cycle. In manual mode, the port will idle until the host orders a detect cycle. It will then run detection, report the results, and return to idle to wait for another command. In semi-auto mode, the LTC4274 autonomously polls the port for PDs, but it will not apply power until commanded to do so by the host. The Port Status register is updated at the end of each detection cycle. If a valid signature resistance is detected and classification is enabled, the port will classify the PD and report that result as well. Figure 11. IEEE 802.3af Signature Resistance Ranges 4-Point Detection The LTC4274 uses a 4-point detection method to discover PDs. False-positive detections are minimized by checking for signature resistance with both forced-current and forced-voltage measurements. Initially, two test currents are forced onto the port (via the OUT pin) and the resulting voltages are measured. The detection circuitry subtracts the two V-I points to determine the resistive slope while removing offset caused by series diodes or leakage at the port (see Figure 12). If the forced-current detection yields a valid signature resistance, two test voltages are then forced onto the port and the resulting currents are measured and subtracted. Both methods must report valid resistances for the port to report a valid detection. PD signature resistances between 17k and 29k (typically) are detected as valid and reported as Detect Good in the Port Status register. Values outside this range, including open 275 CURRENT (μA) 25kΩ SLOPE 165 FIRST DETECTION POINT VALID PD SECOND DETECTION POINT 0V-2V OFFSET VOLTAGE 4274 F12 Figure 12. PD Detection 4274fa 17 LTC4274 APPLICATIONS INFORMATION The port will then wait for at least 100ms (or 2 seconds if midspan mode is enabled), and will repeat the detection cycle to ensure that the data in the Port Status register is up-to-date. If the port is in semi-auto mode and high power operation is enabled, the port will not turn on in response to a power-on command unless the current detect result is detect good. Any other detect result will generate a tSTART fault if a power-on command is received. If the port is not in high power mode, it will ignore the detection result and apply power when commanded, maintaining backwards compatibility with the LTC4259A. Behavior in AUTO pin mode is similar to semi-auto; however, after Detect Good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. In standalone (AUTO pin) mode, the ICUT and ILIM thresholds are automatically set; see the Reset and the AUTO Pin section for more information. The signature detection circuitry is disabled when the port is initially powered up with the AUTO pin low, in shutdown mode, or when the corresponding Detect Enable bit is cleared. Detection of Legacy PDs Proprietary PDs that predate the original IEEE 802.3af standard are commonly referred to today as legacy devices. One type of legacy PD uses a large common mode capacitance (>10μF) as the detection signature. Note that PDs in this range of capacitance are defined as invalid, so a PSE that detects legacy PDs is technically noncompliant with the IEEE spec. The LTC4274 can be configured to detect this type of legacy PD. Legacy detection is disabled by default, but can be manually enabled. When enabled, the port will report Detect Good when it sees either a valid IEEE PD or a high-capacitance legacy PD. With legacy mode disabled, only valid IEEE PDs will be recognized. CLASSIFICATION 802.3af Classification A PD can optionally present a classification signature to the PSE to indicate the maximum power it will draw while operating. The IEEE specification defines this signature as a constant current draw when the PSE port voltage is in the VCLASS range (between 15.5V and 20.5V), with the current level indicating one of 5 possible PD classes. Figure 14 shows a typical PD load line, starting with the slope of the 25kΩ signature resistor below 10V, then transitioning to the classification signature current (in this case, Class 3) in the VCLASS range. Table 4 shows the possible classification values. Table 4. Classification Values CLASS Class 0 Class 1 Class 2 Class 3 Class 4 RESULT No Class Signature Present; Treat Like Class 3 3W 7W 13W 25.5W (Type 2) If classification is enabled, the port will classify the PD immediately after a successful detection cycle in semi-auto or AUTO pin modes, or when commanded to in manual mode. It measures the PD classification signature by applying 18V for 12ms (both values typical) to the port via 60 50 40 30 20 10 0 PSE LOAD LINE OVER CURRENT 48mA CURRENT (mA) CLASS 4 CLASS 3 33mA 23mA TYPICAL CLASS 3 PD LOAD LINE 0 5 CLASS 2 14.5mA CLASS 1 CLASS 0 6.5mA 20 25 4274 F13 10 15 VOLTAGE (VCLASS) Figure 13. PD Classification 4274fa 18 LTC4274 APPLICATIONS INFORMATION the OUT pin and measuring the resulting current; it then reports the discovered class in the Port Status register. If the LTC4274 is in AUTO pin mode, it will additionally use the classification result to set the ICUT and ILIM thresholds. See the Reset and the AUTO/MID Pin section for more information. The classification circuitry is disabled when the port is initially powered up with the AUTO pin low, in shutdown mode, or when the corresponding Class Enable bit is cleared. 802.3at 2-Event Classification The 802.3at spec defines two methods of classifying a Type 2 PD. One method adds extra fields to the Ethernet LLDP data protocol; although the LTC4274 is compatible with this classification method, it cannot perform classification directly since it doesn’t have access to the data path. LLDP classification requires the PSE to power the PD as a standard 802.3af (Type 1) device. It then waits for the host to perform LLDP communication with the PD and update the PSE port data. The LTC4274 supports changing the ILIM and ICUT levels on the fly, allowing the host to complete LLDP classification. The second 802.3at classification method, known as 2-event classification or ping-pong, is fully supported by the LTC4274. A Type 2 PD that is requesting more than 13W will indicate Class 4 during normal 802.3af classification. If the LTC4274 sees Class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9V), pauses briefly, and then re-runs classification to verify the Class 4 reading (Figure 1). It also sets a bit in the High Power Status register to indicate that it ran the second classification cycle. The second cycle alerts the PD that it is connected to a Type 2 PSE which can supply Type 2 power levels. 2-event ping-pong classification is enabled by setting a bit in the port’s High Power Mode register. Note that a pingpong enabled port only runs the second classification cycle when it detects a Class 4 device; if the first cycle returns Class 0 to 3, the port assumes it is connected to a Type 1 PD and does not run the second classification cycle. Invalid Type 2 Class Combinations The 802.3at spec defines a Type 2 PD class signature as two consecutive Class 4 results; a Class 4 followed by a Class 0-3 is not a valid signature. In AUTO pin mode, the LTC4274 will power a detected PD regardless of the classification results, with one exception: if the PD presents an invalid Type 2 signature (Class 4 followed by Class 0 to 3), the LTC4274 will not provide power and will restart the detection process. To aid in diagnosis, the Port Status register will always report the results of the last class pulse, so an invalid Class 4–Class 2 combination would report a second class pulse was run in the High Power Status register (which implies that the first cycle found Class 4), and Class 2 in the Port Status register. POWER CONTROL External MOSFET, Sense R Summary The primary function of the LTC4274 is to control the delivery of power to the PSE port. It does this by controlling the gate drive voltage of an external power MOSFET while monitoring the current via an external sense resistor and the output voltage at the OUT pin. This circuitry serves to couple the raw VEE input supply to the port in a controlled manner that satisfies the PD’s power needs while minimizing power dissipation in the MOSFET and disturbances on the VEE backplane. The LTC4274 is designed to use 0.25Ω sense resistors to minimize power dissipation. It also supports 0.5Ω sense resistors, which are the default when LTC4258/LTC4259A compatibility is desired. Inrush Control Once the command has been given to turn on the port, the LTC4274 ramps up the GATE pin of the port’s external MOSFET in a controlled manner. Under normal power-up circumstances, the MOSFET gate will rise until the port 4274fa 19 LTC4274 APPLICATIONS INFORMATION current reaches the inrush current limit level (typically 450mA), at which point the GATE pin will be servoed to maintain the specified IINRUSH current. During this inrush period, a timer (tSTART) runs. When output charging is complete, the port current will fall and the GATE pin will be allowed to continue rising to fully enhance the MOSFET and minimize its on-resistance. The final VGS is nominally 13V. If the tSTART timer expires before the inrush period completes, the port will be turned back off and a tSTART fault reported. Current Limit Each LTC4274 port includes two current limiting thresholds (ICUT and ILIM), each with a corresponding timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds depends on several factors: the class of the PD, the voltage of the main supply (VEE), the type of PSE (1 or 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and whether or not the system is required to implement class enforcement. Per the IEEE spec, the LTC4274 will allow the port current to exceed ICUT for a limited period of time before removing power from the port, whereas it will actively control the MOSFET gate drive to keep the port current below ILIM. The port does not take any action to limit the current when only the ICUT threshold is exceeded, but does start the tCUT timer. The tLIM timer starts when the ILIM threshold is exceeded and current limit is active. If the current drops below the ICUT current threshold before its timer expires, the tCUT timer counts back down, but at 1/16 the rate that it counts up. This allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. ICUT is typically set to a lower value than ILIM to allow the port to tolerate minor faults without current limiting. Per the IEEE specification, the LTC4274 will automatically set ILIM to 425mA (shown in bold in Table 5) during inrush at port turn-on, and then switch to the programmed ILIM setting once inrush has completed. To maintain IEEE compliance, ILIM should kept at 425mA for all Type 1 PDs, and 850mA if a Type 2 PD is detected. ILIM is automatically reset to 425mA when a port turns off. Table 5. Example Current Limit Settings INTERNAL REGISTER SETTING (hex) ILIM (mA) 53 106 159 213 266 319 372 425 478 531 584 638 744 850 956 1063 1169 1275 1488 1700 1913 2125 2338 2550 2975 RSENSE = 0.5Ω 88 08 89 80 8A 09 8B 00 8E 92 CB 10 D2 40 4A 50 5A 60 52 90 9A C0 CA D0 DA E0 49 40 4A 50 5A 60 52 8A 80 89 08 88 RSENSE = 0.25Ω ILIM Foldback The LTC4274 features a two-stage foldback circuit that reduces the port current if the port voltage falls below the normal operating voltage. This keeps MOSFET power dissipation at safe levels for typical 802.3af MOSFETs, 4274fa 20 LTC4274 APPLICATIONS INFORMATION even at extended 802.3at power levels. Current limit and foldback behavior are programmable. Figure 14 shows MOSFET power dissipation with 802.3af-style foldback compared with a typical MOSFET SOA curve; Figure 15 demonstrates how two-stage foldback keeps the FET within its SOA under the same conditions. Table 4 gives examples of recommended ILIM register settings. The LTC4274 will support current levels well beyond the maximum values in the 802.3at specification. The shaded areas in Table 5 indicate settings that may require a larger external MOSFET, additional heat sinking, or a reduced tLIM setting. 1.0 MOSFET Fault Detection LTC4274 PSE ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged. A failed MOSFET may short source to drain, which will make the port appear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the LTC4274 SENSE pin to rise to an abnormally high voltage. A failed MOSFET may also short from gate to drain, causing the LTC4274 GATE pin to rise to an abnormally high voltage. The LTC4274 SENSE and GATE pins are designed to tolerate up to 80V faults without damage. If the LTC4274 sees any of these conditions for more than 180μs, it disables all port functionality, reduces the gate drive pull-down current for the port and reports a FET Bad fault. This is typically a permanent fault, but the host can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault. If the MOSFET is in fact bad, the fault will quickly return, and the port will disable itself again. An open or missing MOSFET will not trigger a FET Bad fault, but will cause a tSTART fault if the LTC4274 attempts to turn on the port. Voltage and Current Readback The LTC4274 measures the output voltage and current at each port with an internal A/D converter. Port data is only valid when the port power is on. The converter has two modes: • Slow mode: 14 samples per second, 14.5 bits resolution • Fast mode: 440 samples per second, 9.5 bits resolution In fast mode, the least significant 5 bits of the lower byte are zeroes so that bit scaling is the same in both modes. Disconnect 25 sA m 75 SO A 2x 80 2.3 af FO LD 802.3af FOLDBACK SOA DC AT 90°C 0 10 30 40 50 20 PD Voltage (V) at VPSE = 58V 60 4274 F14 0.9 0.8 PSE Current (A) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Figure 14. Turn On Currents vs FET Safe Operating Area at 90°C Ambient 1.0 25 m sA 0.8 SO A PSE Current (A) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 SO A 802.3af FOLDBACK LTC4 m 75 sA T 274 F 0.7 9 C 0° OLDB ACK 0.9 75 T °C BA CK T °C SOA DC AT 90°C 10 30 40 50 20 PD Voltage (V) at VPSE = 58V 60 4274 F15 Figure 15. LTC4274 Foldback vs FET Safe Operating Area at 90°C Ambient The LTC4274 monitors the port to make sure that the PD continues to draw the minimum specified current. A disconnect timer counts up whenever port current is below 7.5mA (typ), indicating that the PD has been disconnected. If the tDIS timer expires, the port will be turned off and the disconnect bit in the fault event register will be set. If the current returns before the tDIS timer runs out, the 4274fa 21 LTC4274 APPLICATIONS INFORMATION timer resets and will start counting from the beginning if the undercurrent condition returns. As long as the PD exceeds the minimum current level more often than tDIS, it will stay powered. Although not recommended, the DC disconnect feature can be disabled by clearing the DC Disconnect Enable bit. Note that this defeats the protection mechanisms built into the IEEE spec, since a powered port will stay powered after the PD is removed. If the still-powered port is subsequently connected to a non-PoE data device, the device may be damaged. The LTC4274 does not include AC disconnect circuitry, but includes an AC disconnect enable bit to maintain compatibility with the LTC4259A. If the AC Disconnect Enable bit is set, DC disconnect will be used. Shutdown Pin The LTC4274 includes a hardware SHDN pin. When the SHDN pin is pulled to DGND, the port will be shut off immediately. The port remains shut down until re-enabled via I2C or a device reset in AUTO pin mode. Masked Shutdown The LTC4274 provides a low latency port shedding feature to quickly reduce the system load when required. By allowing a pre-determined set of ports to be turned off, the current on an overloaded main power supply can be reduced rapidly while keeping high priority devices powered. Each port can be configured to high or low priority; all low-priority ports will shut down within 6.5μs after the MSD pin is pulled low. If a port is turned off via MSD, the corresponding Detection and Classification Enable bits are cleared, so the port will remain off until the host explicitly re-enables detection. SERIAL DIGITAL INTERFACE Overview The LTC4274 communicates with the host using a standard SMBus/I2C 2-wire interface. The LTC4274 is a slave-only device, and communicates with the host master using the standard SMBus protocols. Interrupts are signaled to the host via the INT pin. The Timing Diagrams (Figures 5 through 9) show typical communication waveforms and their timing relationships. More information about the SMBus data protocols can be found at www.smbus.org. The LTC4274 requires both the VDD and VEE supply rails to be present for the serial interface to function. Bus Addressing The LTC4274’s primary serial bus address is 010xxxxb, with the lower four bits set by the AD3-AD0 pins; this allows up to 16 LTC4274s on a single bus. All LTC4274s also respond to the address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple LTC4274s in a single transaction. If the LTC4274 is asserting the INT pin, it will also respond to the alert response address (0001100b) per the SMBus spec. Interrupts and SMBAlert Most LTC4274 port events can be configured to trigger an interrupt, asserting the INT pin and alerting the host to the event. This removes the need for the host to poll the LTC4274, minimizing serial bus traffic and conserving host CPU cycles. Multiple LTC4274s can share a common INT line, with the host using the SMBAlert protocol (ARA) to determine which LTC4274 caused an interrupt. Register Description For information on serial bus usage and device configuration and status, refer to the LTC4274 Software Programming documentation. EXTERNAL COMPONENT SELECTION Power Supplies and Bypassing The LTC4274 requires two supply voltages to operate. VDD requires 3.3V (nominally) relative to DGND. VEE requires a negative voltage of between –44V and –57V for Type 1 PSEs, or –50V to –57V for Type 2 PSEs, relative to AGND. The relationship between the two grounds is not fixed; AGND can be referenced to any level from VDD to DGND, although it should typically be tied to either VDD or DGND. 4274fa 22 LTC4274 APPLICATIONS INFORMATION VDD provides power for most of the internal LTC4274 circuitry, and draws a maximum of 3mA. A ceramic decoupling cap of at least 0.1μF should be placed from VDD to DGND, as close as practical to each LTC4274 chip. Figure 16 shows a three component low dropout regulator for a negative supply to DGND generated from the negative VEE supply. VDD is tied to AGND and DGND is negative referenced to AGND. This regulator drives a single LTC4274 device. In Figure 17, DGND is tied to AGND in this boost converter circuit for a positive VDD supply of 3.3V above AGND. This circuit can drive multiple LTC4274 devices and opto couplers. 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10 30 40 20 PD VOLTAGE (V) 50 60 4274 F16 VEE is the main supply that provides power to the PD. Because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. For minimum IR loss and best system efficiency, set VEE near maximum amplitude (57V), leaving enough margin to account for transient over- or undershoot, temperature drift, and the line regulation specs of the particular power supply used. Bypass capacitance between AGND and VEE is very important for reliable operation. If a short circuit occurs at the output port it can take as long as 1μs for the LTC4274 to begin regulating the current. During this time the current is limited only by the small impedances in the circuit and a high current spike typically occurs, causing a voltage transient on the VEE supply and possibly causing the LTC4274 to reset due to a UVLO fault. A 1μF 100V X7R , capacitor placed near the VEE pin is recommended to minimize spurious resets. Isolating the Serial Bus The LTC4274 includes a split SDA pin (SDAIN and SDAOUT) to ease opto-isolation of the bidirectional SDA line. IEEE 802.3 Ethernet specifications require that network segments (including PoE circuitry) be electrically isolated from the chassis ground of each network interface device. However, network segments are not required to be isolated PSE CURRENT (A) SO A 75 m 802.3af FOLDBACK Figure 16. Negative LDO to DGND LTC427 s AT 90 °C 4 FOLD AT 1.17 BACK A L3 100μH SUMIDA CDRH5D28-101NC R51 4.7k 1% R53 4.7k 1% 5 VCC 1 R58 10Ω R54 56k C79 2200pF ITH/RUN NGATE 6 C75 10μF 16V D28 B1100 C74 100μF 6.3V L4 10μH SUMIDA CDRH4D28-100NC 3.3V AT 400mA R52 3.32k 1% C73 10μF 6.3V C76 10μF 63V C77 0.22μF 100V + C78 0.22μF 100V Q13 FMMT723 Q15 FDC2512 R55 806Ω 1% R56 47.5k 1% Q14 FMMT723 LTC3803 3 VFB GND 2 SENSE 4 R57 1k R59 0.100Ω 1%, 1W 4274 F17 R60 10Ω VEE Figure 17. Positive VDD Boost Converter 4274fa 23 LTC4274 APPLICATIONS INFORMATION 0.1 F 200 VDD CPU U1 SCL 200 U2 2k ISOLATED 3.3V 0.1 F 2k VDD LTC4274 INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND SDA HCPL-063L TO CONTROLLER 10 F U3 200 ISOLATED GND + 200 SMBALERT 0.1 F GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L HCPL-063L 4274 F18 Figure 18. Opto-Isolating the I2C Bus from each other, provided that the segments are connected to devices residing within a single building on a single power distribution system. For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main power supply for the entire device. This strategy can be used if the device has no electrically conducting ports other than twisted-pair Ethernet. In this case, the SDAIN and SDAOUT pins can be tied together and will act as a standard I2C/SMBus SDA pin. If the device is part of a larger system, contains additional external non-Ethernet ports, or must be referenced to protective ground for some other reason, the Power over Ethernet subsystem (including all LTC4274s) must be electrically isolated from the rest of the system. Figure 18 shows a typical isolated serial interface. The SDAOUT pin of the LTC4274 is designed to drive the inputs of an optocoupler directly. Standard I2C/SMBus devices typically cannot drive opto-couplers, so U1 is used to buffer the signals from the host controller side. External MOSFET Careful selection of the power MOSFET is critical to system reliability. LTC recommends either Fairchild IRFM120A, FDT3612, FDMC3612 or Philips PHT6NQ10T for their proven reliability in Type 1 and Type 2 PSE applications. Non-standard applications that provide more current than the 850mA IEEE maximum may require heat sinking and other MOSFET design considerations. Contact LTC Applications before using a MOSFET other than one of these recommended parts. 4274fa 24 LTC4274 APPLICATIONS INFORMATION Sense Resistor The LTC4274 is designed to use either 0.5Ω or 0.25Ω current sense resistors. For new designs 0.25Ω is recommended to reduce power dissipation; the 0.5Ω option is intended for existing systems where the LTC4274 is used as a drop-in replacement for the LTC4258 or LTC4259A. The lower sense resistor values reduce heat dissipation. Four commonly available 1Ω resistors (0402 or larger package size) can be used in parallel in place of a single 0.25Ω resistor. In order to meet the ICUT and ILIM accuracy required by the IEEE specification, the sense resistors should have ±1% tolerance or better, and no more than ±200ppm/°C temperature coefficient. Output Cap The port requires a 0.22μF cap across its output to keep the LTC4274 stable while in current limit during startup or overload. Common ceramic capacitors often have significant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this problem, X7R ceramic capacitors rated for at least 100V are recommended. ESD/Cable Discharge Protection Ethernet ports can be subject to significant ESD events when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the RJ45 jack. To protect against damage, the port requires a pair of clamp diodes; one to AGND and one to VEE (Figure 10). An additional surge suppressor is required for each LTC4274 chip from VEE to AGND. The diodes at the port steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the VEE bypass capacitance. The surge suppressor has the additional benefit of protecting the LTC4274 from transients on the VEE supply. S1B diodes work well as port clamp diodes, and an SMAJ58A or equivalent is recommended for the VEE surge suppressor. LAYOUT GUIDELINES Standard power layout guidelines apply to the LTC4274: place the decoupling caps for the VDD and VEE supplies near their respective supply pins, use ground planes, and use wide traces wherever there are significant currents. 4274fa 25 LTC4274 PACKAGE DESCRIPTION UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 0.05 5.50 0.05 4.10 0.05 3.00 REF 5.15 ± 0.05 3.15 ± 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.5 REF 6.10 7.50 0.05 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.35 45 CHAMFER 37 38 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.00 0.10 0.75 0.05 0.00 – 0.05 3.00 REF 5.15 ± 0.10 7.00 0.10 5.50 REF 3.15 ± 0.10 (UH) QFN REF C 1107 0.200 REF 0.25 0.05 0.50 BSC R = 0.125 TYP R = 0.10 TYP BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4274fa 26 LTC4274 REVISION HISTORY REV A DATE 4/11 DESCRIPTION Revised entire data sheet PAGE NUMBER 1 to 28 4274fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC4274 TYPICAL APPLICATION Autonomous Midspan PSE 0.1μF 3.3V 10k SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND 1μF 100V RSENSE IRFM120A VDD AUTO MID RESET SHDN MSD INT 10k LTC4274 VEE SENSE GATE OUT SMAJ58A –54V S1B 0.22μF 100V PORT 4274 TA02 –54V RELATED PARTS PART NUMBER LT1619 LTC4257 LTC4257-1 LTC4258 LTC4259A-1 LTC4263 LTC4263-1 LTC4264 LTC4265 LTC4266 LTC4267 LTC4267-1 LTC4267-3 LTC4268-1 LTC4269-1 LTC4269-2 LTC4278 LTC4311 DESCRIPTION Low Voltage Current Mode PWM Controller IEEE 802.3af PD Interface Controller IEEE 802.3af PD Interface Controller Quad IEEE 802.3af PoE PSE Controller Quad IEEE 802.3af PoE PSE Controller Single IEEE 802.3af PSE Controller High Power Single PoE PSE Controller High Power PD Controller IEEE 802.3at PD Interface Controller IEEE 802.3at Quad PSE Controller IEEE 802.3af PD Interface Console with Integrated Switching Regulator IEEE 802.3af PD Interface with Integrated Switching Regulator IEEE 802.3af PD Interface with Integrated Switching Regulator High Power PD with Synchronous Flyback Controller IEEE 802.3at PD Interface Console with Integrated Switching Regulator IEEE 802.3at PD Interface Console with Integrated Switching Regulator IEEE 802.3at PD Interface with Integrated Switching Regulator SMBus/I2C Accelerator COMMENTS –48V to 3.3V at 300mA, MSOP Package 100V, 400mA Internal Switch, Programmable Class 100V, 400mA Internal Switch, Dual Current Limit, Programmable Class DC Disconnect Sensing Only With Both AC and DC Disconnect Sensing Internal FET Switch, Autonomous Operation Internal FET Switch, Autonomous Operation Internal FET Switch With 750mA Current Limit 100V, 1A Internal Switch, 2-Event Classification Recognition Supports IEEE 802.3at Type 1 and 2 PDs, 0.34Ω Channel Resistance, Advanced Power Management, High-Reliability 4-Point PD Detection, Legacy Capacitance Detect Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class 100V, 400mA Internal Switch, Programmable Class, 200kHz Constant Frequency PWM 100V, 400mA Internal Switch, Programmable Class, 300kHz Constant Frequency PWM No Optocoupler Required 2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, Auxiliary Support 2-Event Classification, Programmable Classification, Synchronous Forward Controller, 100kHz to 500kHz, Auxiliary Support 2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, 12V Auxiliary Support Improved I2C Rise Time, Ensures Data Integrity 4274fa 28 Linear Technology Corporation (408) 432-1900 ● LT 0411 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORA TION 2009