LTC4278CDKD

FEATURES n n n n LTC4278 IEEE 802.3at PD with Synchronous No-Opto Flyback Controller and 12V Aux Support DESCRIPTION The LTC®4278 is an integrated Powered Device (PD) controller and switching regulator intended for high power IEEE 802.3at and 802.3af applications. With a wide input voltage range, the LTC4278 is specifically designed to support PD applications that include a low-voltage auxiliary power input such as a 12V wall adaptor. The inclusion of a shutdown pin provides simple implementation of both PoE and auxiliary dominate applications. In addition, the LTC4278 supports both 1-event and 2-event classifications as defined by the IEEE, thereby allowing the use in a wide range of product configurations. The LTC4278 synchronous, current mode, flyback controller generates multiple supply rails in a single conversion step providing for the highest system efficiency while maintaining tight regulation across all outputs. The LTC4278 includes Linear Technology’s patented No-Opto feedback topology to provide full IEEE 802.3 isolation without the need of an opto-isolator circuit. A true soft-start function allows graceful ramp-up of all output voltages. The LTC4278 is available in a space saving 32-pin DFN package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5841643. n n n n n n n n n 25.5W IEEE 802.3at Compliant (Type 2) PD 10V to 57V Auxiliary Power Input Shutdown Pin for Flexible Auxiliary Power Support Integrated State-of-the-Art No-Opto Synchronous Flyback Controller – Isolated Power Supply Efficiency >92% – 88% Efficiency Including Diode Bridge and Hot Swap™ FET Superior EMI Performance Robust 100V 0.7Ω (Typ) Integrated Hot Swap MOSFET IEEE 802.3at High Power Available Indicator Integrated Signature Resistor and Programmable Class Current Undervoltage, Overvoltage and Thermal Protection Short-Circuit Protection with Auto-Restart Programmable Soft-Start and Switching Frequency Complementary Power Good Indicators Thermally Enhanced 7mm × 4mm DFN Package APPLICATIONS n n n n n VoIP Phones with Advanced Display Options Dual-Radio Wireless Access Points PTZ Security Cameras RFID Readers Industrial Controls TYPICAL APPLICATION + AUXILIARY SUPPLY (10V TO 57V) 100k BSS63LT1 680k EPC3472G-LF 25W PD Solution with 12V Auxiliary 2.2μH 10μF 294k TO MICRO CONTROLLER T2P • 0.18μH 47μF 5V 5A 100μF + • 10μF 21.5k 1μF 3.01k FDMS2572 + • – 41.2k 54V FROM DATA PAIR HAT2169 ~+ ~– PDS5100H UVLO PWRGD VPORTP SHDN RCLASS FB VCC PG SENSE+ 12mΩ LTC4278 SENSE– SG VCMP 2.2nF 54V FROM SPARE PAIR ~+ ~– 0.1μF 24k 30.9Ω VPORTN VNEG SYNC GND OSC 1μF PGDLY 10k 33pF tON ENDLY RCMP CCMP 38.3k 1.8k 0.1μF • • 100k 4278 TA01a 4278f 1 LTC4278 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW SHDN T2P RCLASS NC VPORTN VPORTN NC NC SG 1 2 3 4 5 6 7 8 9 33 32 VPORTP 31 NC 30 PWRGD 29 PWRGD 28 NC 27 VNEG 26 VNEG 25 NC 24 PG 23 PGDLY 22 RCMP 21 CCMP 20 SENSE+ 19 SENSE – 18 UVLO 17 VCMP Pins with Respect to VPORTN VPORTP Voltage......................................... –0.3V to 100V VNEG Voltage ......................................... –0.3V to VPORTP VNEG Pull-Up Current ..................................................1A SHDN ....................................................... –0.3V to 100V RCLASS, Voltage ............................................ –0.3V to 7V RCLASS Source Current...........................................50mA PWRGD Voltage (Note 3) Low Impedance Source ......VNEG – 0.3V to VNEG +11V Sink Current.........................................................5mA PWRGD, T2P Voltage ............................... –0.3V to 100V PWRGD, T2P Sink Current .....................................10mA Pins with Respect to GND VCC Voltage ................................................ –0.3V to 22V SENSE–, SENSE+ Voltage ........................ –0.5V to +0.5V UVLO, SYNC Voltage...................................–0.3V to VCC FB Current ..............................................................±2mA VCMP Current .........................................................±1mA Operating Ambient Temperature Range LTC4278C-1 ................................................. 0°C to 70°C LTC4278I-1 ..............................................–40°C to 85°C VCC 10 tON 11 ENDLY 12 SYNC 13 SFST 14 OSC 15 FB 16 DKD32 PACKAGE 32-LEAD (7mm × 4mm) PLASTIC DFN TJMAX = 125°C, θJA = 34°C/W, θJC = 2°C/W GND, EXPOSED PAD (PIN 33) MUST BE SOLDERED TO A HEAT SINKING PLANE THAT IS CONNECTED TO VNEG ORDER INFORMATION LEAD FREE FINISH LTC4278CDKD#PBF LTC4278IDKD#PBF TAPE AND REEL LTC4278CDKD#TRPBF LTC4278IDKD#TRPBF PART MARKING* 4278 4278 PACKAGE DESCRIPTION 32-Lead (7mm × 4mm) Plastic DFN 32-Lead (7mm × 4mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4278f 2 LTC4278 ELECTRICAL CHARACTERISTICS PARAMETER Interface Controller (Note 4) Operating Input Voltage Signature Range Classification Range ON Voltage OFF Voltage Overvoltage Lockout ON/OFF Hysteresis Window Signature/Class Hysteresis Window Reset Threshold Supply Current Supply Current at 57V Class 0 Current Signature Signature Resistance Invalid Signature Resistance, SHDN Invoked Classification Class Accuracy Classification Stability Time Normal Operation Inrush Current Power FET On-Resistance Power FET Leakage Current at VNEG Digital Interface SHDN Input High Level Voltage SHDN Input Low Level Voltage SHDN Input Resistance PWRGD, T2P Output Low Voltage PWRGD, T2P Leakage Current PWRGD Output Low Voltage PWRGD Clamp Voltage PWRGD Leakage Current VPORTP = 9.8V, SHDN = 9.65V Tested at 1mA, VPORTP = 54V. For T2P, Must Complete 2-Event Classification to See Active Low Pin Voltage Pulled 57V, VPORTP = VPORTN = 0V Tested at 0.5mA, VPORTP = 52V, VNEG = 48V, Output Voltage Is With Respect to VNEG Tested at 2mA, VNEG = 0V, Voltage With Respect to VNEG VPWRGD = 11V, VNEG = 0V, Voltage With Respect to VNEG l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS At VPORTP (Note 5) MIN TYP MAX 60 9.8 21 37.2 71 l l l l l l l l l l UNITS V V V V V V V V l l l l 1.5 12.5 30.0 4.1 1.4 2.57 State Machine Reset for 2-Event Classification Measured at VPORTP Pin VPORTP = 17.5V, No RCLASS Resistor 1.5V ≤ VPORTP ≤ 9.8V (Note 6) 1.5V ≤ VPORTP ≤ 9.8V, VSHDN = 3V (Note 6) 5.40 1.35 0.40 V mA mA kΩ kΩ kΩ % ms 23.25 26 11 11 ±3.5 1 Invalid Signature Resistance During Mark Event (Notes 6, 7) 10mA < ICLASS < 40mA, 12.5V < VPORTP < 21V (Notes 8, 9) VPORTP Pin Step to 17.5V, RCLASS = 30.9, ICLASS Within 3.5% of Ideal Value (Notes 8, 9) VPORTP = 54V, VNEG = 3V Tested at 600mA into VNEG, VPORTP = 54V VPORTP = SHDN = VNEG = 57V l l l 60 100 0.7 180 1.0 1 mA Ω μA V 3 0.45 100 0.15 1 0.4 12 16.5 1 V kΩ V μA V V μA 4278f 3 LTC4278 ELECTRICAL CHARACTERISTICS PARAMETER PWM Controller (Note 10) Power Supply VCC Operating Range VCC Supply Current (ICC) VCC Shutdown Current Feedback Amplifier Feedback Regulation Voltage (VFB) Feedback Pin Input Bias Current Feedback Amplifier Transconductance Feedback Amplifier Source or Sink Current Feedback Amplifier Clamp Voltage Reference Voltage Line Regulation Feedback Amplifier Voltage Gain Soft-Start Charging Current Soft-Start Discharge Current Control Pin Threshold (VCMP) Gate Outputs PG, SG Output High Level PG, SG Output Low Level PG, SG Output Shutdown Strength PG Rise Time SG Rise Time PG, SG Fall Time Current Amplifier Switch Current Limit at Maximum VCMP ΔVSENSE /ΔVCMP Sense Voltage Overcurrent Fault Voltage Timing Switching Frequency (fOSC) Oscillator Capacitor Value (COSC) Minimum Switch On Time (tON(MIN)) Flyback Enable Delay Time (tENDLY) PG Turn-On Delay Time (tPGDLY) Maximum Switch Duty Cycle SYNC Pin Threshold SYNC Pin Input Resistance ● ● ● ● ● ● The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS MIN TYP MAX UNITS 4.5 4 6.4 50 1.220 700 25 1.237 200 1000 55 2.56 0.84 20 10 150 1.251 1400 90 V mA μA V nA μmho μA V V VCMP = Open (Note 11) VCMP = Open, VUVLO = 0V ● ● RCMP Open ΔIC = ±10μA VFB = 0.9V VFB = 1.4V 12V ≤ VCC ≤ 18V VCMP = 1.2V to 1.7V VSFST = 1.5V VSFST = 1.5V, VUVLO = 0V Duty Cycle = Min 6.6 16 0.7 ● ● ● 0.005 1400 20 1.3 1 7.4 0.01 1.6 11 15 10 0.05 25 %/ V V/ V μA mA V 8 0.05 2.3 V V V ns ns ns VUVLO = 0V; IPG, ISG = 20mA CPG = 1nF CSG = 1nF CPG, CSG = 1nF VSENSE+ VSENSE+, VSFST < 1V COSC = 100pF (Note 12) ● ● 88 98 0.07 206 110 230 110 200 mV V/ V mV kHz pF ns ns ns % ● ● 84 33 100 200 265 200 85 88 1.53 40 2.1 V kΩ 4278f 4 LTC4278 ELECTRICAL CHARACTERISTICS PARAMETER Load Compensation Load Compensation to VSENSE Offset Voltage Feedback Pin Load Compensation Current UVLO Function UVLO Pin Threshold (VUVLO) UVLO Pin Bias Current VUVLO = 1.2V VUVLO = 1.3V ● The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. CONDITIONS VRCMP with VSENSE+ = 0V VSENSE+ = 20mV, VFB = 1.230V 1.215 –0.25 –4.50 MIN TYP 0.8 20 1.240 0.1 –3.4 1.265 0.25 –2.50 MAX UNITS mV μA V μA μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C, otherwise 90V. Note 3: Active high PWRGD internal clamp self-regulates to 14V with respect to VNEG. Note 4: All voltages are with respect to VPORTN pin unless otherwise noted. Note 5: Input voltage specifications are defined with respect to LTC4278 pins and meet IEEE 802.3af/at specifications when the input diode bridge is included. Note 6: Signature resistance is measured via the ΔV/ΔI method with the minimum ΔV of 1V. The LTC4278 signature resistance accounts for the additional series resistance in the input diode bridge. Note 7: An invalid signature after the 1st classification event is mandated by the IEEE802.3at standard. See the Applications Information section. Note 8: Class accuracy is with respect to the ideal current defined as 1.237/RCLASS and does not include variations in RCLASS resistance. Note 9: This parameter is assured by design and wafer level testing. Note 10: VCC = 14V; PG, SG Open; VCMP = 1.4V, VSENSE– = 0V, RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. All voltages are with respect to GND. Note 11: Supply current does not include gate charge current to the MOSFETs. See the Applications Information section. Note 12: Component value range guaranteed by design. 4278f 5 LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range 0.5 TA = 25°C 50 Input Current vs Input Voltage TA = 25°C CLASS 4 VPORTP CURRENT (mA) 10.5 11.0 Input Current vs Input Voltage CLASS 1 OPERATION 0.4 VPORTP CURRENT (mA) VPORTP CURRENT (mA) 40 0.3 30 CLASS 3 CLASS 2 CLASS 1 85°C –40°C 10.0 0.2 20 0.1 10 CLASS 0 0 0 0 2 6 VPORTP VOLTAGE (V) 4 8 10 4278 G01 0 10 30 40 VPORTP VOLTAGE (V) (RISING) 20 50 60 9.5 12 14 20 18 16 VPORTP VOLTAGE (V) 22 4278 G03 4278 G02 Signature Resistance vs Input Voltage 28 RESISTANCE = ΔV = V2 – V1 ΔI I2 – I1 27 DIODES: HD01 TA = 25°C IEEE UPPER LIMIT LTC4278 + 2 DIODES 25 24 LTC4278 ONLY 23 IEEE LOWER LIMIT CLASS CURRENT 10mA/DIV VPORTP VOLTAGE 10V/DIV Class Operation vs Time TA = 25°C 1.0 RESISTANCE (Ω) TIME (10μs/DIV) On-Resistance vs Temperature SIGNATURE RESISTANCE (kΩ) 26 0.8 0.6 0.4 22 V1: 1 V2: 2 3 4 7 5 8 6 VPORTP VOLTAGE (V) 9 10 4278 G04 4278 G05 0.2 –50 0 25 50 75 –25 JUNCTION TEMPERATURE (°C) 100 4278 G06 PWRGD, T2P Output Low Voltage vs Current 0.8 TA = 25°C 1.0 Active High PWRGD Output Low Voltage vs Current TA = 25°C VPORTP – VNEG = 4V 115 110 105 100 95 90 85 Inrush Current vs Input Voltage VPWRGD – VPORTN (V) VT2P – VPORTN (V) 0.6 PWRGD (V) 0.8 CURRENT (mA) 0 0.5 1 1.5 CURRENT (mA) 2 4278 G08 0.6 0.4 0.4 0.2 0.2 0 0 2 6 4 CURRENT (mA) 8 10 4278 G07 0 40 45 50 55 VPORTP VOLTAGE (V) 60 4278 G09 4278f 6 LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS VCC Shutdown Current vs Temperature 90 80 70 VCC CURRENT (μA) 60 50 40 30 20 10 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 4 VCC = 14V 3 50 –50 –25 25 75 0 TEMPERATURE (°C) VCC = 14V IVCC (mA) 8 7 6 STATIC PART CURRENT 5 VUVLO = 0 9 DYNAMIC CURRENT CPG = 1nF , , CSG = 1nF fOSC = 100kHz SENSE VOLTAGE (mV) 10 VCC Current vs Temperature 110 108 106 104 102 100 98 96 94 92 100 125 SENSE Voltage vs Temperature FB = 1.1V SENSE = VSENSE+ WITH VSENSE– = 0V 90 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 4278 G02 4278 G12 4278 G13 SENSE Fault Voltage vs Temperature 220 SENSE = VSENSE – 215 WITH VSENSE = 0V SENSE VOLTAGE (mV) 210 fOSC (kHz) 205 200 195 190 185 180 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 + Oscillator Frequency vs Temperature 110 108 106 104 102 100 98 96 94 92 90 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 COSC = 100pF 1.240 1.239 1.238 1.237 VFB (V) 1.236 1.235 1.234 1.233 1.232 1.231 VFB vs Temperature 1.230 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 4278 G14 4278 G15 4278 G16 Feedback Pin Input Bias vs Temperature 300 RCMP OPEN FEEDBACK PIN INPUT BIAS (nA) 250 200 150 100 50 0 –50 –25 1.03 1.02 VFB RESET (V) 1.04 VFB Reset vs Temperature 70 50 30 IVCMP (μA) 10 –10 –30 –50 –70 Feedback Amplifier Output Current vs VFB 125°C 25°C –40°C 1.01 1.00 0.99 0.98 0.97 50 25 75 0 TEMPERATURE (°C) 100 125 0.96 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 0.9 1 1.1 1.2 VFB (V) 1.3 1.4 1.5 4278 G19 4278 G17 4278 G18 4278f 7 LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS Feedback Amplifier Source and Sink Current vs Temperature 70 65 60 IVCMP (μA) 55 50 950 45 40 –50 900 –50 SOURCE CURRENT VFB = 1.1V SINK CURRENT VFB = 1.4V 1100 Feedback Amplifier gm vs Temperature 1700 1650 1600 1050 gm (μmho) 1550 1500 1000 AV (V/V) 1450 1400 1350 1300 1250 1200 1150 Feedback Amplifier Voltage Gain vs Temperature –25 50 25 75 0 TEMPERATURE (°C) 100 125 –25 75 0 25 50 TEMPERATURE (°C) 100 125 1100 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 4278 G20 4278 G21 4278 G22 UVLO vs Temperature 1.250 1.245 1.240 IUVLO (μA) UVLO (V) 1.235 3.7 3.6 3.5 3.4 3.3 3.2 3.1 IUVLO Hysteresis vs Temperature 1.230 1.225 1.220 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3.0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 4278 G23 4278 G24 Soft-Start Charge Current vs Temperature 23 22 SFST CHARGE CURRENT (μA) 21 TIME (ns) 20 19 18 17 16 15 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 80 70 60 50 PG, SG Rise and Fall Times vs Load Capacitance TA = 25°C FALL TIME 40 30 RISE TIME 20 10 0 0 1 2 34567 CAPACITANCE (nF) 8 9 10 4278 G25 4278 G26 4278f 8 LTC4278 TYPICAL PERFORMANCE CHARACTERISTICS Minimum PG On-Time vs Temperature 340 330 320 tON(MIN) (ns) tPGDLY (ns) 310 300 290 280 270 260 –50 –25 0 75 50 25 TEMPERATURE (°C) 100 125 50 0 –50 225 205 –50 –25 200 tENDLY (ns) 150 100 RPGDLY = 16.9k RtON(MIN) = 158k 300 250 RPGDLY = 27.4k 285 265 245 PG Delay Time vs Temperature 325 305 Enable Delay Time vs Temperature RENDLY = 90k –25 25 0 75 50 TEMPERATURE (°C) 100 125 50 25 75 0 TEMPERATURE (°C) 100 125 4278 G28 4278 G29 4278 G30 4278f 9 LTC4278 PIN FUNCTIONS SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary power application. Drive SHDN high to disable LTC4278 operation and corrupt the signature resistance. If unused, tie SHDN to VPORTN. T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low impedance indicates the presence of a Type 2 PSE. RCLASS (Pin 3): Class Select Input. Connect a resistor between RCLASS and VPORTN to set the classification load current (see Table 2). NC (Pins 4, 7, 8, 25, 28, 31): No Connect. VPORTN (Pins 5, 6): Input Voltage, Negative Rail. Pin 5 and Pin 6 must be electrically tied together at the package. SG (Pin 9): Synchronous Gate Drive Output. This pin provides an output signal for a secondary-side synchronous rectifier. Large dynamic currents may flow during voltage transitions. See the Applications Information section for details. VCC (Pin 10): Supply Voltage Pin. Bypass this pin to GND with a low ESR ceramic capacitor. See the Applications Information section for details. tON (Pin 11): Pin for external programming resistor to set the minimum time that the primary switch is on for each cycle. Minimum turn-on facilitates the isolated feedback method. See the Applications Information section for details. ENDLY (Pin 12): Pin for external programming resistor to set enable delay time. The enable delay time disables the feedback amplifier for a fixed time after the turn-off of the primary-side MOSFET. This allows the leakage inductance voltage spike to be ignored for flyback voltage sensing. See the Applications Information section for details. SYNC (Pin 13): External Sync Input. This pin is used to synchronize the internal oscillator with an external clock. The positive edge of the clock causes the oscillator to discharge causing PG to go low (off) and SG high (on). The sync threshold is typically 1.5V. Tie to ground if unused. See the Applications Information section for details. SFST (Pin 14): Soft-Start. This pin, in conjunction with a capacitor (CSFST) to GND, controls the ramp-up of peak primary current through the sense resistor. It is also used to control converter inrush at start-up. The SFST clamps the VCMP voltage and thus limits peak current until softstart is complete. The ramp time is approximately 70ms per μF of capacitance. Leave SFST open if not using the soft-start function. OSC (Pin 15): Oscillator. This pin, in conjunction with an external capacitor (COSC) to GND, defines the controller oscillator frequency. The frequency is approximately 100kHz • 100/COSC (pF). FB (Pin 16): Feedback Amplifier Input. Feedback is usually sensed via a third winding and enabled during the flyback period. This pin also sinks additional current to compensate for load current variation as set by the RCMP pin. Keep the Thevenin equivalent resistance of the feedback divider at roughly 3k. VCMP (Pin 17): Frequency Compensation Control. VCMP is used for frequency compensation of the switcher control loop. It is the output of the feedback amplifier and the input to the current comparator. Switcher frequency compensation components are placed on this pin to GND. The voltage on this pin is proportional to the peak primary switch current. The feedback amplifier output is enabled during the synchronous switch on time. UVLO (Pin 18): Undervoltage Lockout. A resistive divider from VPORTP to this pin sets an undervoltage lockout based upon VPORTP level (not VCC). When the UVLO pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from VCC. The bias current on this pin has hysteresis such that the bias current is sourced when UVLO threshold is exceeded. This introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor. The user can control the amount of hysteresis by adjusting the impedance of the divider. Tie the UVLO pin to VCC if not using this function. See the Applications 4278f 10 LTC4278 PIN FUNCTIONS Information section for details. This pin is used for the UVLO function of the switching regulator. The PD interface section has an internal UVLO. SENSE –, SENSE+ (Pins 19, 20): Current Sense Inputs. These pins are used to measure primary-side switch current through an external sense resistor. Peak primary-side current is used in the converter control loop. Make Kelvin connections to the sense resistor RSENSE to reduce noise problems. SENSE – connects to the GND side. At maximum current (VCMP at its maximum voltage) SENSE pins have 100mV threshold. The signal is blanked (ignored) during the minimum turn-on time. CCMP (Pin 21): Load Compensation Capacitive Control. Connect a capacitor from CCMP to GND in order to reduce the effects of parasitic resistances in the feedback sensing path. A 0.1μF ceramic capacitor suffices for most applications. Short this pin to GND when load compensation is not needed. RCMP (Pin 22): Load Compensation Resistive Control. Connect a resistor from RCMP to GND in order to compensate for parasitic resistances in the feedback sensing path. In less demanding applications, this resistor is not needed and this pin can be left open. See the Applications Information section for details. PGDLY (Pin 23): Primary Gate Delay Control. Connect an external programming resistor (RPGDLY) to set delay from synchronous gate turn-off to primary gate turn-on. See the Applications Information section for details. PG (Pin 24): Primary Gate Drive. PG is the gate drive pin for the primary-side MOSFET switch. Large dynamic currents flow during voltage transitions. See the Applications Information section for details. VNEG (Pins 26, 27): System Negative Rail. Connects VNEG to VPORTN through an internal power MOSFET. Pin 26 and Pin 27 must be electrically tied together at the package. PWRGD (Pin 29): Power Good Output, Open-Collector. High impedence signals power-up completion. PWRGD is referenced to VNEG and features a 14V clamp. PWRGD (Pin 30): Complementary Power Good Output, Open-Drain. Low impedance signals power-up completion. PWRGD is referenced to VPORTN. VPORTP (Pin 32): Positive Power Input. Tie to the input port power through the input diode bridge. Exposed Pad (Pin 33): Ground. This is the negative rail connection for both signal ground and gate driver grounds of the flyback controller. This pin should be connected to VNEG. 4278f 11 LTC4278 BLOCK DIAGRAM CLASSIFICATION CURRENT LOAD 1 2 SHDN 1.237V T2P + 16k 25k VPORTP 32 – RCLASS NC 31 3 PWRGD 30 CONTROL CIRCUITS 4 NC VPORTN VPORTN BOLD LINE INDICATES HIGH CURRENT PATH CLAMPS 0.7 14V PWRGD 29 5 6 VNEG VNEG 27 26 7 NC 8 NC 10 VCC + – FB 1.3 16 – + S R Q Q ERROR AMP VCMP 17 1.237V REFERENCE (VFB) DISABLE 0.8V 3V INTERNAL REGULATOR + + UVLO IUVLO TSD OSCILLATOR COLLAPSE DETECT 18 CURRENT TRIP SENSE+ RCMPF 50k SET ENABLE CCMP SLOPE COMPENSATION 15 OSC 13 11 23 12 SYNC tON LOGIC BLOCK TO FB + – LOAD COMPENSATION PGDLY ENDLY PGATE SGATE GATE DRIVE + 25 NC 28 NC GATE DRIVE SG GND (EXPOSED PAD) 9 33 – 3V 12 – + – CURRENT COMPARATOR + + – UVLO 1V OVERCURRENT FAULT SENSE– CURRENT SENSE AMP 19 + SFST 14 20 21 RCMP 22 PG 24 4278 BD – – – 4278f LTC4278 APPLICATIONS INFORMATION OVERVIEW Power over Ethernet (PoE) continues to gain popularity as more products are taking advantage of having DC power and high speed data available from a single RJ45 connector. As PoE continues to grow in the marketplace, powered device (PD) equipment vendors are running into the 12.95W power limit established by the IEEE 802.3af standard. The IEE802.3at standard establishes a higher power allocation for Power over Ethernet while maintaining backwards compatibility with the existing IEEE 802.3af systems. Power sourcing equipment (PSE) and powered devices are distinguished as Type 1 complying with the IEEE 802.3af/IEEE 802.3at power levels, or Type 2 complying with the IEEE 802.3at power levels. The maximum available power of a Type 2 PD is 25.5W. The IEEE 802.3at standard also establishes a new method of acquiring power classification from a PD and communicating the presence of a Type 2 PSE. A Type 2 PSE has the option of acquiring PD power classification by performing 2-event classification (layer 1) or by communicating with the PD over the data line (layer 2). In turn, a Type 2 PD must be able to recognize both layers of communications and identify a Type 2 PSE. The LTC4278 is specifically designed to support the front end of a PD that must operate under the IEEE 802.3at standard. In particular, the LTC4278 provides the T2P indicator bit which recognizes 2-event classification. This indicator bit may be used to alert the LTC4278 output load that a Type 2 PSE is present. With an internal signature resistor, classification circuitry, inrush control, and thermal shutdown, the LTC4278 is a complete PD Interface solution capable of supporting in the next generation PD applications. MODES OF OPERATION The LTC4278 has several modes of operation depending on the input voltage applied between the VPORTP and VPORTN pins. Figure 1 presents an illustration of voltage and current waveforms the LTC4278 may encounter with the various modes of operation summarized in Table 1. IIN PSE RCLASS VPORTN VPORTP (V) 50 40 30 20 10 CLASSIFICATION DETECTION V2 DETECTION V1 dV = INRUSH dt C1 OFF ON OFF τ = RLOAD C1 TIME TIME VPORTP – PWRGD (V) –10 –20 –30 –40 –50 POWER BAD PWRGD TRACKS VPORTP POWER BAD PWRGD TRACKS VPORTP PWRGD TRACKS VPORTN ON OFF TIME 50 VPORTP – VNEG (V) 40 30 20 10 POWER GOOD PWRGD – VNEG (V) 20 10 POWER BAD POWER GOOD POWER BAD IN DETECTION RANGE TIME INRUSH PD CURRENT LOAD, ILOAD CLASSIFICATION DETECTION I2 DETECTION I1 I1 = V1 – 2 DIODE DROPS V2 – 2 DIODE DROPS I2 = 25kΩ 25kΩ TIME ICLASS DEPENDENT ON RCLASS SELECTION INRUSH = 100mA V ILOAD = PORTP RLOAD LTC4278 RCLASS VPORTP PWRGD PWRGD VNEG 4278 F01 RLOAD C1 Figure 1. VNEG, PWRGD, PWRGD and PD Current as a Function of Input Voltage 4278f 13 LTC4278 APPLICATIONS INFORMATION Table 1. LTC4278 Modes of Operation as a Function of Input Voltage VPORTP–VPORTN (V) 0V to 1.4V 1.5V to 9.8V (5.4V to 9.8V) 12.5V to ON/OFF* ON/OFF* to 60V >71V LTC4278 MODES OF OPERATION Inactive (Reset After 1st Classification Event) 25k Signature Resistor Detection Before 1st Classification Event (Mark, 11k Signature Corrupt After 1st Classification Event) Classification Load Current Active Inrush and Power Applied To PD Load Overvoltage Lockout, Classification and Hot Swap Are Disabled The input diode bridge introduces a voltage drop that affects the range for each mode of operation. The LTC4278 compensates for these voltage drops so that a PD built with the LTC4278 meets the IEEE 802.3af/IEEE 802.3at-established voltage ranges. Note the Electrical Characteristics are referenced with respect to the LTC4278 package pins. DETECTION During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply two voltages in the range of 2.8V to 10V and measures the corresponding currents. Figure 1 shows the detection voltages V1 and V2 and the corresponding PD current. The PSE calculates the signature resistance using the ΔV/ΔI measurement technique. The LTC4278 presents its precision, temperature-compensated 25k resistor between the VPORTP and VPORTN pins, alerting the PSE that a PD is present and requests power to be applied. The LTC4278 signature resistor also compensates for the additional series resistance introduced by the input diode bridge. Thus a PD built with the LTC4278 conforms to the IEEE 802.3af/IEEE 802.3at specifications. *ON/OFF includes hysteresis. Rising input threshold, 37.2V Max. Falling input threshold, 30V Min. These modes satisfy the requirements defined in the IEEE 802.3af/IEEE 802.3at specification. INPUT DIODE BRIDGE In the IEEE 802.3af/IEEE 802.3at standard, the modes of operation reference the input voltage at the PD’s RJ45 connector. Since the PD must handle power received in either polarity from either the data or the spare pair, input diode bridges BR1 and BR2 are connected between the RJ45 connector and the LTC4278 (Figure 2). RJ45 1 TX+ TX– RX+ T1 BR1 TO PHY 2 3 – POWERED 6 RX DEVICE (PD) SPARE+ INPUT 4 VPORTP BR2 0.1μF 100V D3 LTC4278 5 7 8 SPARE– VPORTN 4278 F02 Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs 4278f 14 LTC4278 APPLICATIONS INFORMATION SIGNATURE CORRUPT OPTION In some designs that include an auxiliary power option, it is necessary to prevent a PD from being detected by a PSE. The LTC4278 signature resistance can be corrupted with the SHDN pin (Figure 3). Taking the SHDN pin high will reduce the signature resistor below 11k which is an invalid signature per the IEEE 802.3af/IEEE 802.3at specification, and alerts the PSE not to apply power. Invoking the SHDN pin also ceases operation for classification and disconnects the LTC4278 load from the PD input. If this feature is not used, connect SHDN to VPORTN. Table 2. Summary of Power Classifications and LTC4278 RCLASS Resistor Selection CLASS USAGE MAXIMUM POWER LEVELS AT INPUT OF PD (W) 0.44 to 12.95 0.44 to 3.84 3.84 to 6.49 6.49 to 12.95 12.95 to 25.5 NOMINAL CLASSIFICATION LOAD CURRENT (mA) < 0.4 10.5 18.5 28 40 LTC4278 RCLASS RESISTOR (Ω, 1%) Open 124 69.8 45.3 30.9 0 1 2 3 4 Type 1 Type 1 Type 1 Type 1 Type 2 2-EVENT CLASSIFICATION AND THE T2P PIN A Type 2 PSE may declare the availability of high power by performing a 2-event classification (layer 1) or by communicating over the high speed data line (layer 2). A Type 2 PD must recognize both layers of communication. Since layer 2 communication takes place directly between the PSE and the LTC4278 load, the LTC4278 concerns itself only with recognizing 2-event classification. In 2-event classification, a Type 2 PSE probes for power classification twice. Figure 4 presents an example of a 2-event classification. The 1st classification event occurs when the PSE presents an input voltage between 15.5V to 20.5V and the LTC4278 presents a class 4 load current. The PSE then drops the input voltage into the mark voltage range of 7V to 10V, signaling the 1st mark event. The PD in the mark voltage range presents a load current between 0.25mA to 4mA. The PSE repeats this sequence, signaling the 2nd Classification and 2nd mark event occurrence. This alerts the LTC4278 that a Type 2 PSE is present. The Type 2 PSE then applies power to the PD and the LTC4278 charges up the reservoir capacitor C1 with a controlled inrush current. When C1 is fully charged, and the LTC4278 declares power good, the T2P pin presents an active low signal, or low impedance output with respect to VPORTN . The T2P output becomes inactive when the LTC4278 input voltage falls below undervoltage lockout threshold. LTC4278 TO PSE 16k SHDN VPORTP 25k SIGNATURE RESISTOR VPORTN 4278 F03 SIGNATURE DISABLE Figure 3. 25k Signature Resistor with Disable CLASSIFICATION Classification provides a method for more efficient power allocation by allowing the PSE to identify a PD power classification. Class 0 is included in the IEEE specification for PDs that do not support classification. Class 1-3 partitions PDs into three distinct power ranges. Class 4 includes the new power range under IEEE802.3at (see Table 2). During classification probing, the PSE presents a fixed voltage between 15.5V and 20.5V to the PD (Figure 1). The LTC4278 asserts a load current representing the PD power classification. The classification load current is programmed with a resistor RCLASS that is chosen from Table 2. 4278f 15 LTC4278 APPLICATIONS INFORMATION 50 40 VPORTP (V) 30 20 10 1st CLASS 2nd CLASS ON OFF SIGNATURE CORRUPT DURING MARK As a member of the IEEE 802.3at working group, Linear Technology noted that it is possible for a Type 2 PD to receive a false indication of a 2-event classification if a PSE port is pre-charged to a voltage above the detection voltage range before the first detection cycle. The IEEE working group modified the standard to prevent this possibility by requiring a Type 2 PD to corrupt the signature resistance during the mark event, alerting the PSE not to apply power. The LTC4278 conforms to this standard by corrupting the signature resistance. This also discharges the port before the PSE begins the next detection cycle. PD STABILITY DURING CLASSIFICATION Classification presents a challenging stability problem due to the wide range of possible classification load current. The onset of the classification load current introduces a voltage drop across the cable and increases the forward voltage of the input diode bridge. This may cause the PD to oscillate between detection and classification with the onset and removal of the classification load current. The LTC4278 prevents this oscillation by introducing a voltage hysteresis window between the detection and classification ranges. The hysteresis window accommodates the voltage changes a PD encounters at the onset of the classification load current, thus providing a trouble-free transition between detection and classification modes. The LTC4278 also maintains a positive I-V slope throughout the classification range up to the on-voltage. In the event a PSE overshoots beyond the classification voltage range, the available load current aids in returning the PD back into the classification voltage range. (The PD input may otherwise be “trapped” by a reverse-biased diode bridge and the voltage held by the 0.1μF capacitor). INRUSH CURRENT Once the PSE detects and optionally classifies the PD, the PSE then applies powers on the PD. When the LTC4278 input voltage rises above the on-voltage threshold, LTC4278 connects VNEG to VPORTN through the internal power MOSFET. 4278f DETECTION V1 DETECTION V2 1st MARK 2nd MARK INRUSH PD CURRENT 1st CLASS 2nd CLASS 40mA LOAD, ILOAD TIME DETECTION V1 DETECTION V2 50 VPORTP – VNEG (V) 40 30 20 10 τ = RLOAD C1 1st MARK 2nd MARK dV = INRUSH dt C1 OFF ON OFF TIME TIME VPORTP – T2P (V) –10 –20 –30 –40 –50 TRACKS VPORTN INRUSH = 100mA V ILOAD = PORTN RLOAD LTC4278 IIN PSE RCLASS VPORTN RCLASS = 30.9Ω RCLASS VPORTP T2P VNEG C1 RLOAD 4278 F04 Figure 4. VNEG, T2P and PD Current as a Result of 2-Event Classification 16 LTC4278 APPLICATIONS INFORMATION To control the power-on surge currents in the system, the LTC4278 provides a fixed inrush current, allowing C1 to ramp up to the line voltage in a controlled manner. The LTC4278 keeps the PD inrush current below the PSE current limit to provide a well controlled power-up characteristic that is independent of the PSE behavior. This ensures a PD using the LTC4278 interoperability with any PSE. TURN-ON/ TURN-OFF THRESHOLD The IEEE 802.3af/at specification for the PD dictates a maximum turn-on voltage of 42V and a minimum turn-off voltage of 30V. This specification provides an adequate voltage to begin PD operation, and to discontinue PD operation when the input voltage is too low. In addition, this specification allows PD designs to incorporate an ON/OFF hysteresis window to prevent start-up oscillations. The LTC4278 features an ON/OFF hysteresis window (see Figure 5) that conforms with the IEEE 802.3af/at specification and accommodates the voltage drop in the cable and input diode bridge at the onset of the inrush current. Once C1 is fully charged, the LTC4278 turns on is internal MOSFET and passes power to the PD load. The LTC4278 continues to power the PD load as long as the input voltage does not fall below the OFF threshold. When the LTC4278 input voltage falls below the OFF threshold, the PD load is disconnected, and classification mode resumes. C1 discharges through the LTC4278 circuitry. COMPLEMENTARY POWER GOOD When LTC4278 fully charges the load capacitor (C1), power good is declared and the LTC4278 load can safely begin operation. The LTC4278 provides complementary power good signals that remain active during normal operation and are de-asserted when the input voltage falls below the OFF threshold, when the input voltage exceeds the overvoltage lockout (OVLO) threshold, or in the event of a thermal shutdown (see Figure 6). The PWRGD pin features an open collector output referenced to VNEG which can interface directly with the UVLO pin. When power good is declared and active, the PWRGD pin is high impedance with respect to VNEG. An internal 14V clamp protects the UVLO pin from an excessive voltage. LTC4278 OVLO ON/OFF TSD 30 PWRGD CONTROL CIRCUIT 29 PWRGD LTC4278 TO PSE VPORTP + C1 5μF MIN PD LOAD VPORTN 5 27 VNEG ON/OFF AND OVERVOLTAGE LOCKOUT CIRCUIT VPORTN VNEG 4278 F05 VPORTN 6 BOLD LINE INDICATES HIGH CURRENT PATH INRUSH COMPLETE ON < VPORTP < OVLO AND NOT IN THERMAL SHUTDOWN 26 VNEG VPORTP – VPORTN LTC4278 VOLTAGE POWER MOSFET 0V TO ON* OFF >ON* ON OVLO OFF *INCLUDES ON/OFF HYSTERESIS ON THRESHOLD ≅ 36.1V OFF THRESHOLD ≅ 30.7V OVLO THRESHOLD ≅ 71.0V CURRENT-LIMITED TURN ON POWER NOT GOOD POWER GOOD VPORTP < OFF VPORTP > OVLO OR THERMAL SHUTDOWN 4278 F06 Figure 5. LTC4278 ON/OFF and Overvoltage Lockout Figure 6. LTC4278 Power Good Functional and State Diagram 4278f 17 LTC4278 APPLICATIONS INFORMATION The active low PWRGD pin connects to an internal, opendrain MOSFET referenced to VPORTN and may be used as an indicator bit when power good is declared and active. The PWRGD pin is low impedance with respect to VPORTN. PWRGD PIN WHEN SHDN IS INVOKED In PD applications where an auxiliary power supply invokes the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to the UVLO pin from interfering with the DC/DC converter operations when powered by an auxiliary power supply. OVERVOLTAGE LOCKOUT The LTC4278 includes an overvoltage lockout (OVLO) feature (Figure 6) which protects the LTC4278 and its load from an overvoltage event. If the input voltage exceeds the OVLO threshold, the LTC4278 discontinues PD operation. Normal operations resume when the input voltage falls below the OVLO threshold and when C1 is charged up. THERMAL PROTECTION The IEEE 802.3af/at specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. However, there are several possible scenarios where a PD may encounter excessive heating. During classification, excessive heating may occur if the PSE exceeds the 75ms probing time limit. At turn-on, when the load capacitor begins to charge, the instantaneous power dissipated by the PD interface can be large before it reaches the line voltage. And if the PD experiences a fast input positive voltage step in its operational mode (for example, from 37V to 57V), the instantaneous power dissipated by the PD Interface can be large. The LTC4278 includes a thermal protection feature which protects the LTC4278 from excessive heating. If the LTC4278 junction temperature exceeds the over-temperature threshold, the LTC4278 discontinues PD operations and power good becomes inactive. Normal operation resumes when the junction temperature falls below the overtemperature threshold and when C1 is charged up. Coilcraft Inc. EXTERNAL INTERFACE AND COMPONENT SELECTION Transformer Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer. For PDs, the isolation transformer must also include a center tap on the RJ45 connector side (see Figure 7). The increased current levels in a Type 2 PD over a Type 1 increase the current imbalance in the magnetics which can interfere with data transmission. In addition, proper termination is also required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. Transformer vendors such as Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can assist in selecting an appropriate isolation transformer and proper termination methods. Table 4. Power over Ethernet Transformer Vendors VENDOR Bel Fuse Inc. CONTACT INFORMATION 206 Van Vorst Street Jersey City, NJ 07302 Tel: 201-432-0463 www.belfuse.com 1102 Silver Lake Road Gary, IL 60013 Tel: 847-639-6400 www.coilcraft.com 1861 Landings Drive Mountain View, CA 94043 Tel: 650-903-3800 www.haloelectronics.com 12220 World Trade Drive San Diego, CA 92128 Tel: 858-674-8100 www.pulseeng.com 308 Constitution Drive Menlo Park, CA 94025-1164 Tel: 800-227-7040 www.circuitprotection.com Halo Electronics Pulse Engineering Tyco Electronics Input Diode Bridge Figure 2 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the data pair while the other bridge is dedicated to the spare pair. The LTC4278 supports the use of either silicon or Schottky input diode bridges. However, there are tradeoffs in the choice of diode bridges. 4278f 18 LTC4278 APPLICATIONS INFORMATION An input diode bridge must be rated above the maximum current the PD application will encounter at the temperature the PD will operate. Diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. Consult the diode bridge vendors for the operating current derating curve. A silicon diode bridge can consume over 4% of the available power in some PD applications. Using Schottky diodes can help reduce the power loss with a lower forward voltage. A Schottky bridge may not be suitable for some high temperature PD application. The leakage current has a voltage dependency that can reduce the perceived signature resistance. In addition, the IEEE 802.3af/at specification mandates the leakage back-feeding through the unused bridge cannot generate more than 2.8V across a 100k resistor when a PD is powered with 57V. Sharing Input Diode Bridges At higher temperatures, a PD design may be forced to consider larger bridges in a bigger package because the maximum operating current for the input diode bridge is drastically derated. The larger package may not be acceptable in some space-limited environments. One solution to consider is to reconnect the diode bridges so that only one of the four diodes conducts current in each package. This configuration extends the maximum operating current while maintaining a smaller package profile. Figure 7 shows how to reconnect the two diode bridges. Consult the diode bridge vendors for the derating curve when only one of four diodes is in operation. Input Capacitor The IEEE 802.3af/at standard includes an impedance requirement in order to implement the AC disconnect function. A 0.1μF capacitor (C14 in Figure 7) is used to meet this AC impedance requirement. Transient Voltage Suppressor The LTC4278 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events. However, the pins that interface to the outside world can routinely see excessive peak voltages. To protect the LTC4278, install a transient voltage suppressor (D3) between the input diode bridge and the LTC4278 as shown in Figure 7. RJ45 1 TX+ TX– RX+ RX– 14 T1 1 12 3 2 5 4 6 VPORTP BR2 HD01 TO PHY BR1 HD01 2 3 13 10 11 6 9 COILCRAFT ETHI - 230LD SPARE + 4 5 7 8 SPARE – C14 0.1μF 100V D3 SMAJ58A TVS LTC4278 C1 VPORTN VNEG 4278 F07 Figure 7. PD Front-End with Isolation Transformer, Diode Bridges, Capacitors, and a Transient Voltage Suppressor (TVS). 4278f 19 LTC4278 APPLICATIONS INFORMATION Classification Resistor (RCLASS) The RCLASS resistor sets the classification load current, corresponding to the PD power classification. Select the value of RCLASS from Table 2 and connect the resistor between the RCLASS and VPORTN pins as shown in Figure 4, or float the RCLASS pin if the classification load current is not required. The resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classification circuit. Load Capacitor The IEEE 802.3af/at specification requires that the PD maintains a minimum load capacitance of 5μF and does not specify a maximum load capacitor. However, if the load capacitor is too large, there may be a problem with inadvertent power shutdown by the PSE. This occurs when the PSE voltage drops quickly. The input diode bridge reverses bias, and the PD load momentarily powers off the load capacitor. If the PD does not draw power within the PSE’s 300ms disconnection delay, the PSE may remove power from the PD. Thus, it is necessary to evaluate the load current and capacitance to ensure that an inadvertent shutdown cannot occur. The load capacitor can store significant energy when fully charged. The PD design must ensure that this energy is not inadvertently dissipated in the LTC4278. For example, if the VPORTP pin shorts to VPORTN while the capacitor is charged, current will flow through the parasitic body diode of the internal MOSFET and may cause permanent damage to the LTC4278. T2P Interface When a 2-event classification sequence successfully completes, the LTC4278 recognizes this sequence, and provides an indicator bit, declaring the presence of a Type 2 PSE. The open-drain output provides the option to use this signal to communicate to the LTC4278 load, or to leave the pin unconnected. Figure 8 shows two interface options using the T2P pin and the opto-isolator. The T2P pin is active low and connects to an opto-isolator to communicate across the TO PSE VPORTP TO PSE LTC4278 V+ RP TO PD LOAD –54V VPORTN T2P OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT V+ VPORTP LTC4278 T2P TO PD LOAD –54V VPORTN VNEG 4278 F08 RP OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT Figure 8. T2P Interface Examples DC/DC converter isolation barrier. The pull-up resistor RP is sized according to the requirements of the opto-isolator operating current, the pull-down capability of the T2P pin, and the choice of V+. V+ for example can come from the PoE supply rail (which the LTC4278 VPORTP is tied to), or from the voltage source that supplies power to the DC/DC converter. Option 1 has the advantage of not drawing power unless T2P is declared active. Shutdown Interface To corrupt the signature resistance, the SHDN pin can be driven high with respect to VPORTN. If unused, connect SHDN directly to VPORTN. Auxiliary Power Source In some applications, it is desirable to power the PD from an auxiliary power source such as a wall adapter. Auxiliary power can be injected into an LTC4278-based PD at the input of the LTC4278 VPORTN , at VNEG, or even the power supply output. In addition, some PD applications may desire auxiliary supply dominance or may be configured 4278f 20 LTC4278 APPLICATIONS INFORMATION for PoE dominance. Furthermore, PD applications may also opt for a seamless transition — that is, without power disruption — between PoE and auxiliary power. The most common auxiliary power option injects power at VNEG. Figure 9 presents an example of this application.In this example, the auxiliary port injects 48V onto the line via diode D1. The components surrounding the SHDN pin are selected so that the LTC4278 does not disconnect power to the output until the auxiliary supply exceeds 36V. This configuration is an auxiliary-dominant configuration. That is, the auxiliary power source supplies the power even if PoE power is already present. This configuration also provides a seamless transition from PoE to auxiliary power when auxiliary power is applied, however, the removal of auxiliary power to PoE power is not seamless. Contact Linear Technology applications support for detail information on implementing a custom auxiliary power supply. IEEE 802.3at SYSTEM POWER-UP REQUIREMENT Under the IEEE 802.3at standard, a PD must operate under 12.95W in accordance with IEEE 802.3at standard until it recognizes a Type 2 PSE. Initializing PD operation in 12.95W mode eliminates interoperability issue in case a Type 2 PD connects to a Type 1 PSE. Once the PD recognizes a Type 2 PSE, the IEEE 802.3at standard requires the PD to wait 80ms in 12.95W operation before 25.5W operation can commence. MAINTAIN POWER SIGNATURE In an IEEE 802.3af/at system, the PSE uses the maintain power signature (MPS) to determine if a PD continues to require power. The MPS requires the PD to periodically draw at least 10mA and also have an AC impedance less than 26.25k in parallel with 0.05μF If one of these conditions . is not met, the PSE may disconnect power to the PD. SWITCHING REGULATOR OVERVIEW The LTC4278 includes a current mode converter designed specifically for use in an isolated flyback topology employing synchronous rectification. The LTC4278 operation is similar to traditional current mode switchers. The major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. This precludes the need of an opto-isolator in isolated designs, thus greatly improving dynamic response and reliability. The LTC4278 has a unique feedback amplifier that samples a transformer winding voltage during the flyback period and uses that voltage to control output voltage. The internal blocks are similar to many current mode controllers. The differences lie in the feedback amplifier and load RJ45 1 TX+ TX– RX+ RX– T1 TVS + TO PHY BR1 2 3 0.1μF 100V C1 – 36V 100k VPORTP LTC4278 10k BR2 SHDN 10k GND 6 4 5 7 8 SPARE+ + SPARE– ISOLATED WALL TRANSFORMER – + VPORTN VNEG D1 – 4278 F09 Figure 9. Auxiliary Power Dominant PD Interface Example 4278f 21 LTC4278 APPLICATIONS INFORMATION compensation circuitry. The logic block also contains circuitry to control the special dynamic requirements of flyback control. For more information on the basics of current mode switcher/controllers and isolated flyback converters see Application Note 19. Feedback Amplifier—Pseudo DC Theory For the following discussion, refer to the simplified Switching Regulator Feedback Amplifier diagram (Figure 10A). When the primary-side MOSFET switch MP turns off, its drain voltage rises above the VPORTP rail. Flyback occurs when the primary MOSFET is off and the synchronous secondary MOSFET is on. During flyback the voltage on nondriven transformer pins is determined by the secondary voltage. The amplitude of this flyback pulse, as seen on the third winding, is given as: VFLBK = VOUT + ISEC • ESR + RDS(ON) NSF Combining this with the previous VFLBK expression yields an expression for VOUT in terms of the internal reference, programming resistors and secondary resistances: VOUT = R1+ R2 • VFB • NSF R2 ISEC • ESR + RDS(ON) ( ) The effect of nonzero secondary output impedance is discussed in further detail (see Load Compensation Theory). The practical aspects of applying this equation for VOUT are found in subsequent sections of the Applications Information. Feedback Amplifier Dynamic Theory So far, this has been a pseudo-DC treatment of flyback feedback amplifier operation. But the flyback signal is a pulse, not a DC level. Provision is made to turn on the flyback amplifier only when the flyback pulse is present, using the enable signal as shown in the timing diagram (Figure 10b). Minimum Output Switch On Time (tON(MIN)) The LTC4278 affects output voltage regulation via flyback pulse action. If the output switch is not turned on, there is no flyback pulse and output voltage information is not available. This causes irregular loop response and start-up/latchup problems. The solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. To accomplish this the current limit feedback is blanked each cycle for tON(MIN). If the output load is less than that developed under these conditions, forced continuous operation normally occurs. See subsequent discussions in the Applications Information section for further details. Enable Delay Time (ENDLY) The flyback pulse appears when the primary-side switch shuts off. However, it takes a finite time until the transformer primary-side voltage waveform represents the output voltage. This is partly due to rise time on the primaryside MOSFET drain node, but, more importantly, is due ( ) RDS(ON) = on-resistance of the synchronous MOSFET MS ISEC = transformer secondary current ESR = impedance of secondary circuit capacitor, winding and traces NSF = transformer effective secondary-to-flyback winding turns ratio (i.e., NS/NFLBK) The flyback voltage is scaled by an external resistive divider R1/R2 and presented at the FB pin. The feedback amplifier compares the voltage to the internal bandgap reference. The feedback amp is actually a transconductance amplifier whose output is connected to VCMP only during a period in the flyback time. An external capacitor on the VCMP pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. The regulation voltage at the FB pin is nearly equal to the bandgap reference VFB because of the high gain in the overall loop. The relationship between VFLBK and VFB is expressed as: VFLBK = R1+ R2 • VFB R2 4278f 22 LTC4278 APPLICATIONS INFORMATION VFLBK FLYBACK R1 16 R2 FB 1V VFB 1.237V LTC4278 FEEDBACK AMP T1 • VCMP 17 CVCMP VIN PRIMARY – + + – • SECONDARY + COUT • COLLAPSE DETECT MP MS ISOLATED OUTPUT R ENABLE S Q 4278 F10a Figure 10a. LTC4278 Switching Regulator Feedback Amplifier PRIMARY-SIDE MOSFET DRAIN VOLTAGE VFLBK 0.8 • VFLBK VIN PG VOLTAGE SG VOLTAGE 4278 F10b tON(MIN) ENABLE DELAY MIN ENABLE FEEDBACK AMPLIFIER ENABLED PG DELAY Figure 10b. LTC4278 Switching Regulator Timing Diagram 4278f 23 LTC4278 APPLICATIONS INFORMATION to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to output voltage. Some time is also required for internal settling of the feedback amplifier circuitry. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.” In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See the subsequent sections for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, which compares the flyback voltage (FB) to a fixed reference, nominally 80% of VFB. When the flyback waveform drops below this level, the feedback amplifier is disabled. Minimum Enable Time The feedback amplifier, once enabled, stays on for a fixed minimum time period, termed “minimum enable time.” This prevents lockup, especially when the output voltage is abnormally low, e.g., during start-up. The minimum enable time period ensures that the VCMP node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. This time is set internally. Effects of Variable Enable Period The feedback amplifier is enabled during only a portion of the cycle time. This can vary from the fixed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. Certain parameters of feedback amp behavior are directly affected by the variable enable period. These include effective transconductance and VCMP node slew rate. Load Compensation Theory The LTC4278 uses the flyback pulse to obtain information about the isolated output voltage. An error source is caused by transformer secondary current flow through the synchronous MOSFET RDS(ON) and real life nonzero impedances of the transformer secondary and output capacitor. This was represented previously by the expression, ISEC • (ESR + RDS(ON)). However, it is generally more useful to convert this expression to effective output impedance. Because the secondary current only flows during the off portion of the duty cycle (DC), the effective output impedance equals the lumped secondary impedance divided by off time DC. Since the off-time duty cycle is equal to 1 – DC, then: RS(OUT) = where: RS(OUT) = effective supply output impedance DC = duty cycle RDS(ON) and ESR are as defined previously This impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. In these cases, the external FB resistive divider is adjusted to compensate for nominal expected error. In more demanding applications, output impedance error is minimized by the use of the load compensation function. Figure 11 shows the block diagram of the load compensation function. Switch current is converted to a voltage by the external sense resistor, averaged and lowpass filtered by the internal 50k resistor RCMPF and the external capacitor on CCMP. This voltage is impressed across the external RCMP resistor by op amp A1 and transistor Q3 producing a current at the collector of Q3 that is subtracted from the FB node. This effectively increases the voltage required at the top of the R1/R2 feedback divider to achieve equilibrium. The average primary-side switch current increases to maintain output voltage regulation as output loading increases. The increase in average current increases RCMP resistor current which affects a corresponding increase in sensed output voltage, compensating for the IR drops. ESR + RDS(ON) 1− DC 4278f 24 LTC4278 APPLICATIONS INFORMATION Assuming relatively fixed power supply efficiency, Eff, power balance gives: POUT = Eff • PIN VOUT • IOUT = Eff • VIN • IIN Average primary-side current is expressed in terms of output current as follows: IIN = K1• IOUT where: K1= VOUT VIN • Eff Nominal output impedance cancellation is obtained by equating this expression with RS(OUT): K1• ESR + RDS(ON) RSENSE • R1• NSF = RCMP 1− DC Solving for RCMP gives: RCMP = K1• RSENSE • (1− DC) • R1• NSF ESR + RDS(ON) The practical aspects of applying this equation to determine an appropriate value for the RCMP resistor are discussed subsequently in the Applications Information section. Transformer Design Transformer design/specification is the most critical part of a successful application of the LTC4278. The following sections provide basic information about designing the transformer and potential tradeoffs. If you need help, the LTC Applications group is available to assist in the choice and/or design of the transformer. Turns Ratios The design of the transformer starts with determining duty cycle (DC). DC impacts the current and voltage stress on the power switches, input and output capacitor RMS currents and transformer utilization (size vs power). The ideal turns ratio is: N IDEAL= VOUT 1− DC • VIN DC So, the effective change in VOUT target is: R ΔVOUT = K1• SENSE • R1• NSF • ΔIOUT RCMP thus: ΔVOUT R = K1• SENSE • R1• NSF ΔIOUT RCMP where: K1 = dimensionless variable related to VIN, VOUT and efficiency, as previously explained RSENSE = external sense resistor VFLBK R1 FB 16 Q1 Q2 VFB VIN • • • R2 LOAD COMP I + Q3 A1 MP RCMPF + 50k SENSE 20 Avoid extreme duty cycles, as they generally increase current stresses. A reasonable target for duty cycle is 50% at nominal input voltage. For instance, if we wanted a 48V to 5V converter at 50% DC then: – 22 RCMP 21 CCMP RSENSE N IDEAL= 5 1− 0.5 1 • = 48 0.5 9.6 4278 F11 Figure 11. Load Compensation Diagram In general, better performance is obtained with a lower turns ratio. A DC of 45.5% yields a 1:8 ratio. 4278f 25 LTC4278 APPLICATIONS INFORMATION Note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. Turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. When building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous rectifier on longer, and thus, keep secondary windings coupled longer. For a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. The ratio between two output voltages is set with the formula VOUT2 = VOUT1 • N21 where N21 is the turns ratio between the two windings. Also keep the secondary MOSFET RDS(ON) small to improve cross regulation. The feedback winding usually provides both the feedback voltage and power for the LTC4278. Set the turns ratio between the output and feedback winding to provide a rectified voltage that under worst-case conditions is greater than the the preregulator maximum supply voltage. For example if the preregulator maximum output were 7V: NSF > VOUT 7 + VF the voltage extends the flyback pulse width. If the flyback pulse extends beyond the enable delay time, output voltage regulation is affected. The feedback system has a deliberately limited input range, roughly ±50mV referred to the FB node. This rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. Therefore, it is advisable to arrange the clamp circuit to clamp at as high a voltage as possible, observing MOSFET breakdown, such that leakage spike duration is as short as possible. Application Note 19 provides a good reference on clamp design. As a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a clamp, but exhibit little to no regulation error due to leakage spike behavior. Inductances from several percent up to, perhaps, ten percent, cause increasing regulation error. Avoid double digit percentage leakage inductances. There is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leakage spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. Once load current is reduced sufficiently, the system snaps back to normal operation. When using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. 2. Temporarily short-circuit the output. 3. Observe that normal operation is restored. If the output voltage is found to hang up at an abnormally low value, the system has a problem. This is usually evident by simultaneously viewing the primary-side MOSFET drain voltage to observe firsthand the leakage spike behavior. 4278f where : VF = Diode Forward Voltage 5 1 = For our example: NSF > 7 + 0.7 1.56 1 We will choose 3 Leakage Inductance Transformer leakage inductance (on either the primary or secondary) causes a spike after the primary-side switch turn-off. This is increasingly prominent at higher load currents, where more stored energy is dissipated. Higher flyback voltage may break down the MOSFET switch if it has too low a BVDSS rating. One solution to reducing this spike is to use a clamp circuit to suppress the voltage excursion. However, suppressing 26 LTC4278 APPLICATIONS INFORMATION A final note—the susceptibility of the system to bistable behavior is somewhat a function of the load current/ voltage characteristics. A load with resistive—i.e., I = V/R behavior—is the most apt to be bistable. Capacitive loads that exhibit I = V2/R behavior are less susceptible. Secondary Leakage Inductance Leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the flyback pulse. This increases the output voltage target by a similar percentage. Note that unlike leakage spike behavior, this phenomenon is independent of load. Since the secondary leakage inductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. Winding Resistance Effects Primary or secondary winding resistance acts to reduce overall efficiency (POUT/PIN). Secondary winding resistance increases effective output impedance, degrading load regulation. Load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. Bifilar Winding A bifilar, or similar winding, is a good way to minimize troublesome leakage inductances. Bifilar windings also improve coupling coefficients, and thus improve cross regulation in multiple winding transformers. However, tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary breakdown voltage, so is not always practical. Primary Inductance The transformer primary inductance, LP, is selected based on the peak-to-peak ripple current ratio (X) in the transformer relative to its maximum value. As a general rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to 0.4). Higher values of ripple will increase conduction losses, while lower values will require larger cores. where: fOSC is the oscillator frequency DCMIN is the DC at maximum input voltage XMAX is ripple current ratio at maximum input voltage Using common high power PoE values, a 48V (41V < VIN < 57V) to 5V/5.3A converter with 90% efficiency, POUT= 26.5W and PIN = 29.5W. Using X = 0.4 N = 1/8 and fOSC = 200kHz: DCMIN = 1+ LP = 1 = N • VIN(MAX) VOUT 2 Ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. LP is calculated from the following equation. LP ( VIN(MAX) • DCMIN )2 = ( VIN(MAX) • DCMIN )2 • Eff = fOSC • XMAX • PIN fOSC • XMAX • POUT 1 = 41.2% 1 57 1+ • 85 = 260μH (57V • 0.412) 200kHz • 0.4 • 26.5W Optimization might show that a more efficient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. A simple spreadsheet program is useful for looking at tradeoffs. Transformer Core Selection Once LP is known, the type of transformer is selected. High efficiency converters use ferrite cores to minimize core loss. Actual core loss is independent of core size for a fixed inductance, but decreases as inductance increases. Since increased inductance is accomplished through more turns of wire, copper losses increase. Thus, transformer design balances core and copper losses. Remember that increased winding resistance will degrade cross regulation and increase the amount of load compensation required. The main design goals for core selection are reducing copper losses and preventing saturation. Ferrite core material saturates hard, rapidly reducing inductance 4278f 27 LTC4278 APPLICATIONS INFORMATION when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. Do not allow the core to saturate! The maximum peak primary current occurs at minimum VIN: IPK = now : DCMAX = 1+ 1 = N • VIN(MIN) VOUT 1 = 49.4% 1 41 1+ • 85 2 Continuing the example, if ESR + RDS(ON) = 8mΩ, R2 = 3.32k, then: R1= 3.32k choose 37.4k. It is recommended that the Thevenin impedance of the resistive divider (R1||R2) is roughly 3k for bias current cancellation and other reasons. Current Sense Resistor Considerations 5 + 5.3 • 0.008 1 = 37.28k 1.237 • 1/ 3 PIN X • 1+ MIN VIN(MIN) • DCMAX 2 XMIN ( VIN(MIN) • DCMAX ) = fOSC • LP • PIN = 0.267 = (41• 49.4%) 2 200kHz • 260μH • 29.5W Using the example numbers leads to: IPK = 0.267 29.5W • 1+ = 1.65A 2 41• 0.494 The external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. Use a noninductive current sense resistor (no wire-wound resistors). Mounting the resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance and inductance low. The dual sense pins allow for a full Kelvin connection. Make sure that SENSE+ and SENSE– are isolated and connect close to the sense resistor. Peak current occurs at 100mV of sense voltage VSENSE. So the nominal sense resistor is VSENSE/IPK. For example, a peak switch current of 10A requires a nominal sense resistor of 0.010Ω Note that the instantaneous peak power in the sense resistor is 1W, and that it is rated accordingly. The use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. Size RSENSE using worst-case conditions, minimum LP, VSENSE and maximum VIN. Continuing the example, let us assume that our worst-case conditions yield an IPK of 40% above nominal, so IPK = 2.3A. If there is a 10% tolerance on RSENSE and minimum VSENSE = 88mV, then RSENSE • 110% = 88mV/2.3A and nominal RSENSE = 35mΩ. Round to the nearest available lower value, 33mΩ. Multiple Outputs One advantage that the flyback topology offers is that additional output voltages can be obtained simply by adding windings. Designing a transformer for such a situation is beyond the scope of this document. For multiple windings, realize that the flyback winding signal is a combination of activity on all the secondary windings. Thus load regulation is affected by each winding’s load. Take care to minimize cross regulation effects. Setting Feedback Resistive Divider The expression for VOUT developed in the Operation section is rearranged to yield the following expression for the feedback resistors: R1= R2 VOUT + ISEC • ESR + RDS(ON) VFB • NSF ( ) 1 4278f 28 LTC4278 APPLICATIONS INFORMATION Selecting the Load Compensation Resistor The expression for RCMP was derived in the Operation section as: RCMP = K1• RSENSE • (1− DC) • R1• NSF ESR + RDS(ON) 4. Compute: RCMP = K1• RSENSE • R1• NSF RS(OUT) 5. Verify this result by connecting a resistor of this value from the RCMP pin to ground. 6. Disconnect the ground short to CCMP and connect a 0.1μF filter capacitor to ground. Measure the output impedance RS(OUT) = ΔVOUT/ΔIOUT with the new compensation in place. RS(OUT) should have decreased significantly. Fine tuning is accomplished experimentally by slightly altering RCMP. A revised estimate for RCMP is: RCMP = RCMP • 1+ RS(OUT)CMP RS(OUT ) Continuing the example: K1= DC= 1+ VOUT 5 = 0.116 = VIN • Eff 48 • 90% 1 = N•VIN(NOM) VOUT 1 = 45.5% 1 48 1+ • 85 If ESR + RDS(ON) = 8m RCMP = 0.116 • = 3.25k This value for RCMP is a good starting point, but empirical methods are required for producing the best results. This is because several of the required input variables are difficult to estimate precisely. For instance, the ESR term above includes that of the transformer secondary, but its effective ESR value depends on high frequency behavior, not simply DC winding resistance. Similarly, K1 appears as a simple ratio of VIN to VOUT times efficiency, but theoretically estimating efficiency is not a simple calculation. The suggested empirical method is as follows: 1. Build a prototype of the desired supply including the actual secondary components. 2. Temporarily ground the CCMP pin to disable the load compensation function. Measure output voltage while sweeping output current over the expected range. Approximate the voltage variation as a straight line. ΔVOUT/ΔIOUT = RS(OUT) . 3. Calculate a value for the K1 constant based on VIN, VOUT and the measured efficiency. 33m • (1 0.455) 8m • 37.4k • 1 3 where RCMP is the new value for the load compensation ʹ resistor. RS(OUT)CMP is the output impedance with RCMP in place and RS(OUT) is the output impedance with no load compensation (from step 2). Setting Frequency The switching frequency of the LTC4278 is set by an external capacitor connected between the OSC pin and ground. Recommended values are between 200pF and 33pF yielding switching frequencies between 50kHz and , 250kHz. Figure 12 shows the nominal relationship between external capacitance and switching frequency. Place the capacitor as close as possible to the IC and minimize OSC 300 200 fOSC (kHz) 100 50 30 100 COSC (pF) 200 4278 F12 Figure 12. fOSC vs OSC Capacitor Values 4278f 29 LTC4278 APPLICATIONS INFORMATION trace length and area to minimize stray capacitance and potential noise pick-up. You can synchronize the oscillator frequency to an external frequency. This is done with a signal on the SYNC pin. Set the LTC4278 frequency 10% slower than the desired external frequency using the OSC pin capacitor, then use a pulse on the SYNC pin of amplitude greater than 2V and with the desired frequency. The rising edge of the SYNC signal initiates an OSC capacitor discharge forcing primary MOSFET off (PG voltage goes low). If the oscillator frequency is much different from the sync frequency, problems may occur with slope compensation and system stability. Also, keep the sync pulse width greater than 500ns. Selecting Timing Resistors There are three internal “one-shot” times that are programmed by external application resistors: minimum on-time, enable delay time and primary MOSFET turn-on delay. These are all part of the isolated flyback control technique, and their functions are previously outlined in the Theory of Operation section. The following information should help in selecting and/or optimizing these timing values. Minimum Output Switch On-Time (tON(MIN)) Minimum on-time is the programmable period during which current limit is blanked (ignored) after the turn-on of the primary-side switch. This improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. This spike is due to both the gate/source charging current and the discharge of drain capacitance. The isolated flyback sensing requires a pulse to sense the output. Minimum on-time ensures that the output switch is always on a minimum time and that there is always a signal to close the loop. The LTC4278 does not employ cycle skipping at light loads. Therefore, minimum on-time along with synchronous rectification sets the switch over to forced continuous mode operation. The tON(MIN) resistor is set with the following equation R tON(MIN) (kΩ) = tON(MIN) (ns) − 104 1.063 Keep RtON(MIN) greater than 70k. A good starting value is 160k. Enable Delay Time (ENDLY) Enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback amplifier. As discussed earlier, this delay allows the feedback amplifier to ignore the leakage inductance voltage spike on the primary side. The worst-case leakage spike pulse width is at maximum load conditions. So, set the enable delay time at these conditions. While the typical applications for this part use forced continuous operation, it is conceivable that a secondaryside controller might cause discontinuous operation at light loads. Under such conditions, the amount of energy stored in the transformer is small. The flyback waveform becomes “lazy” and some time elapses before it indicates the actual secondary output voltage. The enable delay time should be made long enough to ignore the “irrelevant” portion of the flyback waveform at light loads. Even though the LTC4278 has a robust gate drive, the gate transition time slows with very large MOSFETs. Increase delay time as required when using such MOSFETs. The enable delay resistor is set with the following equation: RENDLY (kΩ) = tENDLY (ns) − 30 2.616 Keep RENDLY greater than 40k. A good starting point is 56k. 4278f 30 LTC4278 APPLICATIONS INFORMATION Primary Gate Delay Time (PGDLY) Primary gate delay is the programmable time from the turn-off of the synchronous MOSFET to the turn-on of the primary-side MOSFET. Correct setting eliminates overlap between the primary-side switch and secondary-side synchronous switch(es) and the subsequent current spike in the transformer. This spike will cause additional component stress and a loss in regulator efficiency. The primary gate delay resistor is set with the following equation: RPGDLY (kΩ) = tPGDLY (ns) + 47 9.01 Switcher’s UVLO Pin Function The UVLO pin provides a user programming undervoltage lockout. This is typically used to provide undervoltage lockout based on VIN. The gate drivers are disabled when UVLO is below the 1.24V UVLO threshold. An external resistive divider between the input supply and ground is used to set the turn-on voltage. The bias current on this pin depends on the pin voltage and UVLO state. The change provides the user with adjustable UVLO hysteresis. When the pin rises above the UVLO threshold a small current is sourced out of the pin, increasing the voltage on the pin. As the pin voltage drops below this threshold, the current is stopped, further dropping the voltage on UVLO. In this manner, hysteresis is produced. Referring to Figure 13, the voltage hysteresis at VIN is equal to the change in bias current times RA. The design procedure is to select the desired VIN referred voltage hysteresis, VUVHYS. Then: RA = where: IUVLO = IUVLOL – IUVLOH is approximately 3.4μA RB is then selected with the desired turn-on voltage: RB = RA VIN(ON) VUVLO –1 VIN IUVLO VIN RA RB UVLO LTC4278 VIN RA2 RA RB UVLO LTC4278 CUVLO RB 4278 F13 A good starting point is 15k. Soft-Start Function The LTC4278 contains an optional soft-start function that is enabled by connecting an external capacitor between the SFST pin and ground. Internal circuitry prevents the control voltage at the VCMP pin from exceeding that on the SFST pin. There is an initial pull-up circuit to quickly bring the SFST voltage to approximately 0.8V. From there it charges to approximately 2.8V with a 20μA current source. The SFST node is discharged to 0.8V when a fault occurs. A fault occurs when the current sense voltage is greater than 200mV or the IC’s thermal (overtemperature) shutdown is tripped. When SFST discharges, the VCMP node voltage is also pulled low to below the minimum current voltage. Once discharged and the fault removed, the SFST charges up again. In this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. The time it takes to fully charge soft-start is: • 1.4V C t ss = SFST = 70kΩ • CSFST (μF ) 20μA VUVHYS IUVLO IUVLO RA1 UVLO (13a) UV Turning On (13b) UV Turning Off (13c) UV Filtering Figure 13. UVLO Pin Function and Recommended Filtering 4278f 31 LTC4278 APPLICATIONS INFORMATION If we wanted a VIN-referred trip point of 36V, with 1.8V (5%) of hysteresis (on at 36V, off at 34.2V): RA = 1.8V = 529k, use 523k 3.4μA RB = 523k = 18.5k, use 18.7k ⎛ 36V ⎞ – 1⎟ ⎜ ⎝ 1.23V ⎠ to turn off QPR. If the two voltage ranges overlap, the only disadvantage is that a small degradation in efficiency may occur. It is also necessary to verify that the worst-case maximum winding voltage is not high enough to damage the B-E junction of QPR. VIN • • LTC4278 GND FB 4278 F14 Converter Start-Up The standard topology for the LTC4278 uses a third transformer winding on the primary side that provides both the feedback information and local VCC power for the LTC4278 (Figure 14). This power bootstrapping improves converter efficiency but is not inherently self-starting. Start-Up is affected with an external preregulator circuit that conditions the input line voltage for the LTC4278 during start-up. Upon application of power, CVCC is charged via the preregulator, thereby providing an appropriate supply voltage at the VCC pin for the LTC4278. This supply voltage is typically in the range 7V and is used during start-up. After converter startup, the third transformer winding becomes energized and is designed to generate a higher voltage than the preregulator. The higher voltage of the third winding turns off QPR and provides an efficient method to power the LTC4278. Design of the VCC power circuitry involves selecting appropriate voltage ranges for both the preregulator and the third transformer winding. The preregulator voltage is set as low as possible while ensuring it’s worst-case minimum voltage is high enough to drive the switching FETs gates during the startup period. The third winding output voltage is selected to ensure that it’s worst-case minimum voltage exceeds the preregulator voltage in order Figure 14. Typical Power Bootstrapping Control Loop Compensation Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback amplifier (VCMP pin) to ground as shown in Figure 15. Because of the sampling behavior of the feedback amplifier, compensation is different from traditional current mode controllers. Normally only CVCMP is required. RVCMP can be used to add a zero, but the phase margin improvement traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. CVCMP2 can be used to add an additional high frequency pole and is usually sized at 0.1 times CVCMP. VCMP 17 CVCMP2 RVCMP CVCMP 4278 F15 Figure 15. VCMP Compensation Network 4278f 32 • Even with good board layout, board noise may cause problems with UVLO. You can filter the divider but keep large capacitance off the UVLO node because it will slow the hysteresis produced from the change in bias current. Figure 13c shows an alternate method of filtering by splitting the RA resistor with the capacitor. The split should put more of the resistance on the UVLO side. QPR CVCC VCC PG LTC4278 APPLICATIONS INFORMATION In further contrast to traditional current mode switchers, VCMP pin ripple is generally not an issue with the LTC4269-1. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VCMP voltage changes during the flyback pulse, but is then held during the subsequent switch-on portion of the next cycle. This action naturally holds the VCMP voltage stable during the current comparator sense action (current mode switching). Application Note 19 provides a method for empirically tweaking frequency compensation. Basically, it involves introducing a load current step and monitoring the response. Slope Compensation The LTC4278 incorporates current slope compensation. Slope compensation is required to ensure current loop stability when the DC is greater than 50%. In some switching regulators, slope compensation reduces the maximum peak current at higher duty cycles. The LTC4278 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. Minimum Load Considerations At light loads, the LTC4278 derived regulator goes into forced continuous conduction mode. The primary-side switch always turns on for a short time as set by the tON(MIN) resistor. If this produces more power than the load requires, power will flow back into the primary during the off period when the synchronization switch is on. This does not produce any inherently adverse problems, although light load efficiency is reduced. Maximum Load Considerations The current mode control uses the VCMP node voltage and amplified sense resistor voltage as inputs to the current comparator. When the amplified sense voltage exceeds the VCMP node voltage, the primary-side switch is turned off. In normal use, the peak switch current increases while FB is below the internal reference. This continues until VCMP reaches its 2.56V clamp. At clamp, the primary-side MOSFET will turn off at the rated 100mV VSENSE level. This repeats on the next cycle. It is possible for the peak primary switch currents as referred across RSENSE to exceed the max 100mV rating because of the minimum switch on time blanking. If the voltage on VSENSE exceeds 205mV after the minimum turn-on time, the SFST capacitor is discharged, causing the discharge of the VCMP capacitor. This then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. Short-Circuit Conditions Loss of current limit is possible under certain conditions such as an output short-circuit. If the duty cycle exhibited by the minimum on-time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. It ratchets up cycle-by-cycle to some higher level. Expressed mathematically, the requirement to maintain short-circuit control is: DCMIN = tON(MIN) • fOSC < ISC • RSEC + RDS(ON) VIN • NSP ( ) where: tON(MIN) is the primary-side switch minimum on-time ISC is the short-circuit output current NSP is the secondary-to-primary turns ratio (NSEC/NPRI) (other variables as previously defined) Trouble is typically encountered only in applications with a relatively high product of input voltage times secondary to primary turns ratio and/or a relatively long minimum switch on time. Additionally, several real world effects such as transformer leakage inductance, AC winding losses and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. Prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. 4278f 33 LTC4278 APPLICATIONS INFORMATION Output Voltage Error Sources The LTC4278’s feedback sensing introduces additional minor sources of errors. The following is a summary list: • The internal bandgap voltage reference sets the reference voltage for the feedback amplifier. The specifications detail its variation. • The external feedback resistive divider ratio directly affects regulated voltage. Use 1% components. • Leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio (NS/NF) from its ideal value. This increases the output voltage target by a similar percentage. Since secondary leakage inductance is constant from part to part (within a tolerance) adjust the feedback resistor ratio to compensate. • The transformer secondary current flows through the impedances of the winding resistance, synchronous MOSFET RDS(ON) and output capacitor ESR. The DC equivalent current for these errors is higher than the load current because conduction occurs only during the converter’s off-time. So, divide the load current by (1 – DC). If the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. Otherwise, use the LTC4278 load compensation circuitry (see Load Compensation). If multiple output windings are used, the flyback winding will have a signal that represents an amalgamation of all these windings impedances. Take care that you examine worst-case loading conditions when tweaking the voltages. Power MOSFET Selection The power MOSFETs are selected primarily on the criteria of on-resistance RDS(ON), input capacitance, drain-to-source breakdown voltage (BVDSS), maximum gate voltage (VGS) and maximum drain current (ID(MAX)). For the primary-side power MOSFET, the peak current is: IPK(PRI) = PIN X • 1+ MIN VIN(MIN) • DCMAX 2 For each secondary-side power MOSFET, the peak current is: I X IPK(SEC) = OUT • 1+ MIN 1 DCMAX 2 Select a primary-side power MOSFET with a BVDSS greater than: VOUT(MAX ) L BVDSS ≥ IPK LKG + VIN(MAX ) + CP NSP where NSP reflects the turns ratio of that secondary-to primary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from the drain capacitance (COSS) of the primary-side power MOSFET). A clamp may be added to reduce the leakage inductance as discussed. For each secondary-side power MOSFET, the BVDSS should be greater than: BVDSS ≥ VOUT + VIN(MAX) • NSP Choose the primary-side MOSFET RDS(ON) at the nominal gate drive voltage (7.5V). The secondary-side MOSFET gate drive voltage depends on the gate drive method. Primary-side power MOSFET RMS current is given by: IRMS(PRI) = PIN VIN(MIN) DCMAX For each secondary-side power MOSFET RMS current is given by: IRMS(SEC) = IOUT 1− DCMAX Calculate MOSFET power dissipation next. Because the primary-side power MOSFET operates at high VDS, a transition power loss term is included for accuracy. CMILLER is the most critical parameter in determining the transition loss, but is not directly specified on the data sheets. where XMIN is peak-to-peak current ratio as defined earlier. 4278f 34 LTC4278 APPLICATIONS INFORMATION CMILLER is calculated from the gate charge curve included on most MOSFET data sheets (Figure 16). The secondary-side power MOSFETs typically operate at substantially lower VDS, so you can neglect transition losses. The dissipation is calculated using: PDIS(SEC) = IRMS(SEC)2 • RDS(ON)(1 + δ) b 4278 F16 VGS a MILLER EFFECT With power dissipation known, the MOSFETs’ junction temperatures are obtained from the equation: TJ = TA + PDIS • θJA where TA is the ambient temperature and θJA is the MOSFET junction to ambient thermal resistance. Once you have TJ iterate your calculations recomputing δ and power dissipations until convergence. Gate Drive Node Consideration The PG and SG gate drivers are strong drives to minimize gate drive rise and fall times. This improves efficiency, but the high frequency components of these signals can cause problems. Keep the traces short and wide to reduce parasitic inductance. The parasitic inductance creates an LC tank with the MOSFET gate capacitance. In less than ideal layouts, a series resistance of 5Ω or more may help to dampen the ringing at the expense of slightly slower rise and fall times and poorer efficiency. The LTC4278 gate drives will clamp the max gate voltage to roughly 7.5V, so you can safely use MOSFETs with maximum VGS of 10V and larger. Synchronous Gate Drive There are several different ways to drive the synchronous gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished by way of a pulse transformer. Usually the pulse driver is used to drive a buffer on the secondary, as shown in the application on the front page of this data sheet. However, other schemes are possible. There are gate drivers and secondary-side synchronous controllers available that provide the buffer function as well as additional features. QA QB GATE CHARGE (QG) Figure 16. Gate Charge Curve The flat portion of the curve is the result of the Miller (gate to-drain) capacitance as the drain voltage drops. The Miller capacitance is computed as: Q − QA CMILLER = B VDS The curve is done for a given VDS. The Miller capacitance for different VDS voltages are estimated by multiplying the computed CMILLER by the ratio of the application VDS to the curve specified VDS. With CMILLER determined, calculate the primary-side power MOSFET power dissipation: PD(PRI) = IRMS(PRI)2 • RDS(ON) (1+ δ ) + VIN(MAX ) • where: RDR is the gate driver resistance (≈10Ω) VTH is the MOSFET gate threshold voltage fOSC is the operating frequency VGATE(MAX) = 7.5V for this part (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve. If you don’t have a curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs. PIN(MAX ) DCMIN • RDR • CMILLER •f VGATE(MAX ) − VTH OSC 4278f 35 LTC4278 APPLICATIONS INFORMATION Capacitor Selection In a flyback converter, the input and output current flows in pulses, placing severe demands on the input and output filter capacitors. The input and output filter capacitors are selected based on RMS current ratings and ripple voltage. Select an input capacitor with a ripple current rating greater than: IRMS(PRI) = PIN VIN(MIN) 1− DCMAX DCMAX PRIMARY CURRENT IPRI SECONDARY CURRENT IPRI N ΔVCOUT OUTPUT VOLTAGE RIPPLE WAVEFORM RINGING DUE TO ESL ΔVESR 4278 F17 Figure 17. Typical Flyback Converter Waveforms Continuing the example: IRMS(PRI) = 29.5W 41V 1− 49.4% = 0.728 A 49.4% Keep input capacitor series resistance (ESR) and inductance (ESL) small, as they affect electromagnetic interference suppression. In some instances, high ESR can also produce stability problems because flyback converters exhibit a negative input resistance characteristic. Refer to Application Note 19 for more information. The output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. The output capacitor should have an RMS current rating greater than: IRMS(SEC) = IOUT DCMAX 1− DCMAX 49.4% = 5.24A 1− 49.4% simplicity, we will choose 2% for the maximum output ripple, divided equally between the ESR step and the charging/discharging ΔV. This percentage ripple changes, depending on the requirements of the application. You can modify the following equations. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor is determined by: ESRCOUT ≤ 1% • VOUT • (1− DCMAX ) IOUT The other 1% is due to the bulk C component, so use: COUT ≥ IOUT 1% • VOUT • fOSC Continuing the example: IRMS(SEC) = 5.3A In many applications, the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reliability and cost goals. For example, a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor satisfies the required bulk C. Continuing our example, the output capacitor needs: ESRCOUT ≤ 1% • COUT ≥ 5V • (1− 49.4%) 5.3A = 4mΩ This is calculated for each output in a multiple winding application. ESR and ESL along with bulk capacitance directly affect the output voltage ripple. The waveforms for a typical flyback converter are illustrated in Figure 17. The maximum acceptable ripple voltage (expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. For the purpose of 5.3A = 600μF 1% • 5 • 200kHz These electrical characteristics require paralleling several low ESR capacitors possibly of mixed type. 4278f 36 LTC4278 APPLICATIONS INFORMATION One way to reduce cost and improve output ripple is to use a simple LC filter. Figure 18 shows an example of the filter. L1, 0.1μH FROM SECONDARY WINDING VOUT COUT 470μF COUT2 1μF 4278 F18 ISOLATION The 802.3 standard requires Ethernet ports to be electrically isolated from all other conductors that are user accessible. This includes the metal chassis, other connectors and any auxiliary power connection. For PDs, there are two common methods to meet the isolation requirement. If there will be any user accessible connection to the PD, then an isolated DC/DC converter is necessary to meet the isolation requirements. If user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the PD in an insulated housing. In all PD applications, there should be no user accessible electrical connections to the LTC4278 or support circuitry other than the RJ-45 port. LAYOUT CONSIDERATIONS FOR THE LTC4278 The LTC4278’s PD front end is relatively immune to layout problems. Excessive parasitic capacitance on the RCLASS pin should be avoided. Include a PCB heat sink to which the exposed pad on the bottom of the package can be soldered. This heat sink should be electrically connected to GND. For optimum thermal performance, make the heat sink as large as possible. Voltages in a PD can be as large as 57V for PoE applications, so high voltage layout techniques should be employed. The SHDN pin should be separated from other high voltage pins, like VPORTP, VNEG, to avoid the possibility of leakage currents shutting down the LTC4278. If not used, tie SHDN to VPORTN. The load capacitor connected between VPORTP and VNEG of the LTC4278 can store significant energy when fully charged. The design of a PD must ensure that this energy is not inadvertently dissipated in the LTC4278. The polarityprotection diodes prevent an accidental short on the cable from causing damage. However if, VPORTN is shorted to VPORTP inside the PD while capacitor C1 is charged, current will flow through the parasitic body diode of the internal MOSFET and may cause permanent damage to the LTC4278. In order to minimize switching noise and improve output load regulation, connect the GND pin of the LTC4278 directly SwitcherCAD is a registered trademark of Linear Technology Corporation. + C1 47μF ×3 + RLOAD Figure 18. The design of the filter is beyond the scope of this data sheet. However, as a starting point, use these general guidelines. Start with a COUT 1/4 the size of the nonfilter solution. Make C1 1/4 of COUT to make the second filter pole independent of COUT. C1 may be best implemented with multiple ceramic capacitors. Make L1 smaller than the output inductance of the transformer. In general, a 0.1μH filter inductor is sufficient. Add a small ceramic capacitor (COUT2) for high frequency noise on VOUT. For those interested in more details refer to “Second-Stage LC Filter Design,” Ridley, Switching Power Magazine, July 2000 p8-10. Circuit simulation is a way to optimize output capacitance and filters, just make sure to include the component parasitic. LTC SwitcherCAD® is a terrific free circuit simulation tool that is available at www.linear.com. Final optimization of output ripple must be done on a dedicated PC board. Parasitic inductance due to poor layout can significantly impact ripple. Refer to the PC Board Layout section for more details. ELECTRO STATIC DISCHARGE AND SURGE PROTECTION The LTC4278 is specified to operate with an absolute maximum voltage of –100V and is designed to tolerate brief overvoltage events. However, the pins that interface to the outside world (primarily VPORTN and VPORTP) can routinely see peak voltages in excess of 10kV. To protect the LTC4278, it is highly recommended that the SMAJ58A unidirectional 58V transient voltage suppressor be installed between the diode bridge and the LTC4278 (D3 in Figure 2). 4278f 37 LTC4278 APPLICATIONS INFORMATION to the ground terminal of the VCC decoupling capacitor, the bottom terminal of the current sense resistor and the ground terminal of the input capacitor, using a ground plane with multiple vias. Place the VCC capacitor immediately adjacent to the VCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. Use a low ESR ceramic capacitor. Take care in PCB layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. These are typically the traces associated with the switches. This reduces the parasitic inductance and also minimizes magnetic field radiation. Figure 19 outlines the critical paths. Keep electric field radiation low by minimizing the length and area of traces (keep stray capacitances low). The drain of the primary-side MOSFET is the worst offender in this category. Always use a ground plane under the switcher circuitry to prevent coupling between PCB planes. Check that the maximum BVDSS ratings of the MOSFETs are not exceeded due to inductive ringing. This is done by viewing the MOSFET node voltages with an oscilloscope. If it is breaking down, either choose a higher voltage device, add a snubber or specify an avalanche-rated MOSFET. Place the small-signal components away from high frequency switching nodes. This allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the VCC decoupling capacitor) and small-signal currents flow in the other direction. Keep the trace from the feedback divider tap to the FB pin short to preclude inadvertent pick-up. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC4278 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple which could interfere with the LTC4278 operation. A few inches of PC trace or wire (L ≅ 100nH) between the CIN of the LTC4278 and the actual source VIN, is sufficient to prevent current sharing problems. T1 VCC CVCC VCC PG GATE TURN-OFF RSENSE VCC VCC SG Q3 T2 MP GATE TURN-ON VIN • • • CVIN OUT + + CR Q4 + GATE TURN-ON MS GATE TURN-OFF COUT • • 4278 F19 Figure 19. Layout Critical High Current Paths 4278f 38 LTC4278 PACKAGE DESCRIPTION DKD Package 32-Lead Plastic DFN (7mm × 4mm) (Reference LTC DWG # 05-08-1734 Rev A) 0.70 ± 0.05 4.50 ± 0.05 3.10 ± 0.05 2.65 ±0.05 6.43 ±0.05 PACKAGE OUTLINE 0.40 BSC 6.00 REF RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.20 ± 0.05 7.00 ±0.10 R = 0.05 TYP 17 R = 0.115 TYP 32 0.40 ± 0.10 6.43 ±0.10 4.00 ±0.10 2.65 ±0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 16 0.75 ±0.05 0.40 BSC 0.20 ± 0.05 1 6.00 REF BOTTOM VIEW—EXPOSED PAD (DKD32) QFN 0707 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4278f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 39 LTC4278 RELATED PARTS PART NUMBER LT 1952 LTC3803-3 LTC3805 LTC3825 LTC4257-1 LTC4258 LTC4259A-1 LTC4263 LTC4263-1 LTC4264 LTC4265 LTC4266 ® DESCRIPTION Single Switch Synchronous Forward Counter Current Mode Flyback DC/DC Controller in ThinSOT TM COMMENTS Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current 300kHz Constant-Frequency, Adjustable Slope Compensation, Optimized for High Input Voltage Applications Slope Comp, Overcurrent Protect, Internal/External Clock Adjustable Switching Frequency, Programmable Undervoltage Lockout, Accurate Regulation without Trim, Synchronous for High Efficiency 100V 400mA Internal Switch, Programmable Classification, Dual Current Limit DC Disconnect Only, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control AC or DC Disconnect, IEEE-Compliant PD Detection and Classification, Autonomous Operation AC or DC Disconnect, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control Internal Switch, Autonomous Operation, 30W 750mA Internal Switch, Programmable Classification Current to 75mA, Precision Dual Current Limit with Disable. 2-Event Classification Recognition, 100mA Inrush Current, Single-Class Programming Resistor, Full Compliance to 802.3at Supports IEEE 802.3at Type 1 and Type 2 PDs, 0.34Ω Channel Resistance, Advanced Power Management, High Reliability 4-Point PD Detection, Legacy Capacitance Detect 100V 400mA Internal Switch, Programmable Classification, 200kHz Constant-Frequency PWM, Optimized for IEEE-Compliant PD System 100V 400mA Internal Switch, Programmable Classification, 300kHz Constant-Frequency PWM, Optimized for IEEE-Compliant PD System IEEE 802.3af Compliant, 750mA Hot Swap FET, 92% Power Supply Efficiency, Flexible Aux Support, Superior EMI 2-Event Classification Recognition, 92% Power Supply Efficiency, Flexible Aux Support, Superior EMI 2-Event Classification Recognition, 94% Power Supply Efficiency, Flexible Aux Support, Superior EMI Adjustable Frequency Current Mode Flyback Controller Isolated No-Opto Synchronous Flyback Controller with Wide Input Supply Range IEEE 802.3af PD Interface Controller Quad IEEE 802.3af Power over Ethernet Controller Quad IEEE 802.3af Power over Ethernet Controller Single IEEE 802.3af Power over Ethernet Controller High Power Single PSE Controller High Power PD Interface Controller with 750mA Current Limit IEEE 802.3at High Power PD Interface Controller with 2-Event Classification IEEE 802.3at Quad PSE Controller LTC4267-1 LTC4267-3 LTC4268-1 LTC4269-1 LTC4269-2 IEEE 802.3af PD Interface with an Integrated Switching Regulator IEEE 802.3af PD Interface with an Integrated Switching Regulator High Power PD with Synchronous No-Opto Flyback Controller IEEE 802.3af/IEEE 802.3at PD with Synchronous No-Opto Flyback Controller IEEE 802.3af/IEEE 802.3at PD with Synchronous Forward Controller ThinSOT is a trademark of Linear Technology Corporation. 4278f 40 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0609 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009