LTC4301IMS8

LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Bus Pull-Up Voltages Above or Below VCC Bidirectional Buffer* for SDA and SCL Lines Increases Fanout Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane Isolates Input SDA and SCL Line from Output 10kV Human Body Model ESD Protection 1V Precharge On All SDA and SCL Lines Supports Clock Stretching, Arbitration and Synchronization High Impedance SDA, SCL Pins for VCC = 0V CS Gates Connection from Input to Output Compatible with I2CTM, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation) Small 8-Pin MSOP and DFN (3mm × 3mm) Packages The LTC®4301 supply independent, hot swappable, 2-wire bus buffer allows I/O card insertion into a live backplane without corruption of the data and clock busses. In addition, the LTC4301 allows the VCC, SDAIN and SCLIN pullup voltage and the SDAOUT and SCLOUT pull-up voltage to be independent from each other. Control circuitry prevents the backplane from being connected to the card until a stop bit or a bus idle is present. When the connection is made, the LTC4301 provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. When driven low, the CS input pin allows the part to connect after a stop bit or bus idle occurs. Driving CS high breaks the connection between SCLIN and SCLOUT and between SDAIN and SDAOUT. The READY output pin indicates that the backplane and card sides are connected together. The LTC4301 is offered in 8-pin DFN (3mm × 3mm) and MSOP packages. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7032051. APPLICATIO S ■ ■ ■ ■ ■ Hot Board Insertion Servers Capacitance Buffer/Bus Extender Desktop Computers CompactPCITM and ATCA Systems TYPICAL APPLICATIO 3.3V 5V 0.01µF 10k 10k BACK_SCL 10k VCC LTC4301 10k STAGGERED CONNECTOR SCLIN SCLOUT CARD_SCL OUTPUT SIDE 20pF SDAIN 5V 10k CS GND SDAOUT CARD_SDA BACK_SDA 1V/DIV READY 4301 TA01 BACKPLANE CONNECTOR CARD U Input-Output Connection INPUT SIDE 55pF 1µs/DIV 4301 TA01b U U 4301fb 1 LTC4301 ABSOLUTE MAXIMUM RATINGS VCC to GND ................................................. –0.3V to 7V SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V READY ........................................................ –0.3V to 6V Operating Temperature Range LTC4301C ............................................... 0°C to 70°C LTC4301I ............................................ – 40°C to 85°C PACKAGE/ORDER INFORMATION TOP VIEW CS 1 SCLOUT 2 SCLIN 3 GND 4 9 8 7 6 5 VCC SDAOUT SDAIN READY ORDER PART NUMBER LTC4301CDD LTC4301IDD DD PART MARKING* LBBY TOP VIEW CS SCLOUT SCLIN GND 1 2 3 4 8 7 6 5 VCC SDAOUT SDAIN READY DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 9) PCB CONNECTION OPTIONAL Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL Power Supply VCC ICC Positive Supply Voltage Supply Current PARAMETER The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. CONDITIONS ● VCC = 5.5V, VSDAIN = VSCLIN = 0V VCC = 5.5V, CS = 5.5V SDA, SCL Floating IPULLUP = 3mA CS from 0V to VCC Rising Edge (Note 3) Start-Up Circuitry VPRE tIDLE RDYVOL VTHRCS ICS VTHR VHYS tPLH tPHL IOFF Precharge Voltage Bus Idle Time READY Output Low Voltage Connection Sense Threshold CS Input Current SDA, SCL Logic Input Threshold Voltage SDA, SCL Logic Input Threshold Voltage Hysteresis CS Delay On-Off READY Delay Off-On CS Delay Off-On READY Delay On-Off Ready Off Leakage Current ● ● ● 2 U U W WW U W (Note 1) Storage Temperature Range MSOP ............................................... – 65°C to 150°C DFN .................................................. – 65°C to 125°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC4301CMS8 LTC4301IMS8 MS8 PART MARKING* LTBBW MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/W MIN 2.7 TYP MAX 5.5 UNITS V mA µA V µs V V µA V mV ns ns µs ns µA 4301fb ● 4.5 300 0.85 60 0.8 1.55 1.05 95 1.4 ±0.1 1.8 50 10 10 95 10 ±0.1 6.2 1.25 175 0.4 2 ±1 2.0 LTC4301 ELECTRICAL CHARACTERISTICS SYMBOL VOS CIN ILEAK VOL fI2C,MAX tBUF tHD,STA tSU,STA tSU,STO tHD,DATI tSU,DAT PARAMETER Input-Output Offset Voltage Digital Input Capacitance SDAIN, SDAOUT, SCLIN, SCLOUT Input Leakage Current Output Low Voltage, Input = 0V I2C Maximum Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Set-Up Time Stop Condition Set-Up Time Data Hold Time Input Data Set-Up Time Input-Output Connection The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. CONDITIONS 10k to VCC on SDA, SCL, VCC = 3.3V, SDA or SCL = 0.2V (Note 2) (Note 3) SDA, SCL Pins SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) ● ● MIN 0 TYP 100 MAX 175 10 ±5 UNITS mV pF µA V kHz 0 400 600 0.4 Timing Characteristics 1.3 100 0 0 0 100 µs ns ns ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in the Typical Performance Characteristics section. Note 3: Determined by design, not tested in production. TYPICAL PERFOR A CE CHARACTERISTICS ICC vs Temperature 4.9 4.8 4.7 4.6 ICC (mA) VCC = 5.5V 80 4.4 4.3 4.2 4.1 4.0 VCC = 3.3V VCC = 2.7V TIME (ns) 4.5 60 VOUT – VIN (mV) 3.9 –80 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) UW 4301 G01 Input – Output High to Low Propagation Delay vs Temperature 100 VCC = 2.7V 250 VCC = 3.3V 200 150 300 Connection Circuitry VOUT – VIN TA = 25°C VIN = 0V 40 VCC = 5V 100 VCC = 3.3V 50 0 VCC = 5.5V 20 CIN = COUT = 100pF RPULLUPIN = RPULLUPOUT = 10k –25 0 25 50 TEMPERATURE (°C) 75 100 4301 G02 80 100 0 –50 0 10,000 20,000 30,000 RPULLUP (Ω) 40,000 4301 G03 4301fb 3 LTC4301 PI FU CTIO S CS (Pin 1): The connection sense pin is a 1.4V threshold digital input pin. For normal operation CS is grounded. Driving CS above the 1.4V threshold isolates SDAIN from SDAOUT and SCLIN from SCLOUT and asserts READY low. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the SCL bus on the card. SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL on the bus backplane. GND (Pin 4): Ground. Connect this pin to a ground plane for best results. READY (Pin 5): The READY pin is an open drain N-channel MOSFET output which pulls down when CS is high or when the start-up sequence described in the Operation section has not been completed. READY goes high when CS is low and a start-up is complete. SDAIN (Pin 6): Serial Data Input. Connect this pin to the SDA bus on the backplane. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the SDA bus on the card. VCC (Pin 8): Main Input Supply. Place a bypass capacitor of at least 0.01µF close to VCC for best results. Exposed Pad (Pin 9): Exposed pad may be left open or connected to device ground. BLOCK DIAGRA 6 SDAIN 3 SCLIN 1.8V 1.8V 1 CS 95µs DELAY 1.4V 4 W U U U LTC4301 Supply Independent 2-Wire Bus Buffer PRECHARGE VCC 8 R1 200k PRECHARGE R2 CONNECT 200k CONNECT PRECHARGE CONNECT R3 200k R4 200k SDAOUT 7 CONNECT SCLOUT 2 LOGIC PRECHARGE CONNECT CONNECT READY 5 UVLO CONNECT GND 4 4301 BD 4301fb LTC4301 OPERATIO Start-Up When the LTC4301 first receives power on its VCC pin, either during power-up or live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2.5V (typical). This is to ensure that the part does not try to function until it has enough voltage to do so. During this time, the 1V precharge circuitry is active and forces 1V through 200k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4301 comes out of UVLO, it assumes that SDAIN and SCLIN have been inserted into a live system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. For proper operation, logic low input voltages should be no higher than 0.4V with respect to the ground pin voltage of the LTC4301. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4301. Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane U and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms as described here. Input-to-Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4301’s data or clock pins, the LTC4301 regulates the voltage on the other side of the device (call it VLOW2) at a slightly higher voltage, as directed by the following equation: VLOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical) where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 = 108mV (typical). See the Typical Performance Characteristics section for curves showing the offset voltage as a function of VCC and R. Propagation Delays During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line. If the pull-up resistors are the same, a difference in rise time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 1 for VCC = 5V and a 10k pull-up resistor on each side (55pF on one side and 20pF on the other). SDAIN and SCLIN are pulled-up to 3.3V, and SDAOUT and SCLOUT are pulledup to 5V. Since the output side has less capacitance than the input, it rises faster and the effective low to high propagation delay is negative. OUTPUT SIDE 20pF 1V/DIV INPUT SIDE 55pF 1µs/DIV 4301 F01 Figure 1. Input-Output Connection 4301fb 5 LTC4301 OPERATIO There is a finite high to low propagation delay through the connection circuitry for falling waveforms. Figure 2 shows the falling edge waveforms for the same pull-up resistors and equivalent capacitance conditions as used in Figure 1. An external N-channel MOSFET device pulls down the voltage on the side with 55pF capacitance; LTC4301 pulls down the voltage on the opposite side with a delay of 60ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows high to low propagation delay as a function of temperature and voltage for 10k pull-up resistors pulled-up to VCC and 100pF equivalent capacitance on both sides of the part. Larger output capacitances translate to longer delays (up to 150ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. INPUT SIDE 55pF 1V/DIV Figure 2. Input-Output Connection High to Low Propagation Delay 6 U Ready Digital Output This pin provides a digital flag which is low when either CS is high or the start-up sequence described earlier in this section has not been completed. READY goes high when CS is low and start-up is complete. The pin is driven by an open-drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10k to VCC to provide the pull-up. Connection Sense When the CS pin is driven above 1.4V with respect to the LTC4301’s ground, the backplane side is disconnected from the card side and the READY pin is internally pulled low. When the pin voltage is low, the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before reconnecting the two sides. At this time the internal pulldown on READY releases. OUTPUT SIDE 20pF 20ns/DIV 4301 F02 4301fb LTC4301 APPLICATIO S I FOR ATIO Live Insertion and Capacitance Buffering Application Figures 3 illustrates applications of the LTC4301 with different bus pull-up and VCC voltages, demonstrating its ability to recognize and buffer bus data levels that are above or below its VCC supply. All of these applications take advantage of the LTC4301’s Hot SwapTM controlling, capacitance buffering and precharge features. If the I/O cards were plugged directly into the backplane without the LTC4301 buffer, all of the backplane and card capacitances would add directly together, making rise- and falltime requirements difficult to meet. Placing an LTC4301 5V STAGGERED CONNECTOR 3.3V 10k 10k SDA SCL BACKPLANE CONNECTOR 3.3V STAGGERED CONNECTOR 5V 10k 10k SDA SCL BACKPLANE CONNECTOR 3.3V STAGGERED CONNECTOR 5V 10k 10k SDA SCL BACKPLANE CONNECTOR Figure 3. Typical Supply Independent Applications 4301fb U on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the LTC4301 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the LTC4301, which is less than 10pF. In most applications the LTC4301 will be used with a staggered connector where VCC and GND will be long pins. SDA and SCL are medium length pins to ensure that the VCC and GND pins make contact first. This will allow the precharge circuitry to be activated on SDA and SCL before Hot Swap is a trademark of Linear Technology Corporation. 0.01µF 10k CS SDAIN SCLIN VCC LTC4301 GND SDAOUT SCLOUT READY 10k 10k CARD_SDA CARD_SCL CARD 0.01µF 10k CS SDAIN SCLIN VCC LTC4301 GND SDAOUT SCLOUT READY 10k 10k CARD_SDA CARD_SCL CARD 2.5V 0.01µF 10k CS SDAIN SCLIN VCC LTC4301 GND SDAOUT SCLOUT READY 4301 F03 W UU 10k 10k CARD_SDA CARD_SCL CARD 7 LTC4301 APPLICATIO S I FOR ATIO they make contact. CS is a short pin that is pulled up when not connected. This is to ensure that the connection between the backplane and the cards data and clock busses is not enabled until the transients associated with live insertion have settled. Figure 4 shows the LTC4301 in a CompactPCITM configuration. The LTC4301 receives its VCC voltage from one of the long “early power” pins. Because this power is not switched, add a 5Ω to 10Ω resistor between VCC of the LTC4301 and the connector VCC pin. Establishing early BACKPLANE VCC STAGGERED CONNECTOR BACKPLANE CONNECTOR VCC2 R1 10k BD_SEL SDA SCL R2 10k STAGGERED CONNECTOR STAGGERED CONNECTOR Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a CompactPCI System 4301fb 8 U power VCC ensures that the 1V precharge voltage is present at SDAIN and SCLIN before they make contact. The CS pin is driven by the CompactPCI’s BD_SEL# pin using a short pin. This is to ensure that a connection is not enabled until the transients associated with live insertion have settled. Figure 5 shows the LTC4301 in a PCI application where all of the pins have the same length. In this case, an RC filter circuit on the I/O card with a product of 10ms provides a CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group. 5.1Ω R3 10k CS SDAIN SCLIN VCC LTC4301 GND SDAOUT SCLOUT READY I/O PERIPHERAL CARD 1 0.01µF R4 10k R5 10k R6 10k CARD_SDA CARD_SCL 5.1Ω R7 10k CS SDAIN SCLIN VCC LTC4301 GND SDAOUT SCLOUT READY I/O PERIPHERAL CARD 2 0.01µF R8 10k R9 10k R10 10k CARD2_SDA CARD2_SCL ••• W UU 5.1Ω R11 10k CS SDAIN SCLIN I/O PERIPHERAL CARD N 0.01µF R12 10k R13 10k R14 10k CARDN_SDA CARDN_SCL VCC LTC4301 GND SDAOUT SCLOUT READY 4301 F03 LTC4301 APPLICATIO S I FOR ATIO BACKPLANE VCC 0.1µF VCC2 R1 10k SDA SCL R2 10k R3 100k CS SDAIN SCLIN VCC LTC4301 GND SDAOUT SCLOUT READY BACKPLANE CONNECTOR Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a PCI System filter to prevent the LTC4301 from becoming activated until the transients associated with live insertion have settled. Connect the capacitor between VCC and CS, and the resistor from CS to GND. Repeater/Bus Extender Application Users who wish to connect two 2-wire systems separated by a distance can do so by connecting two LTC4301s back-to-back as shown in Figure 6. The I2C specification allows for 400pF maximum bus capacitance, severely limiting the length of the bus. The SMBus specification places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise- and fall-time specifications are to be met. Using the LTC4301 allows the capacitance to be isolated into smaller sections, enabling the U I/O PERIPHERAL CARD 1 0.01µF R4 10k R5 10k R6 10k CARD_SDA CARD_SCL I/O PERIPHERAL CARD 2 0.1µF R7 100k CS SDAIN SCLIN VCC LTC4301 GND 0.01µF SDAOUT SCLOUT READY R8 10k R9 10k R10 10k CARD2_SDA CARD2_SCL W UU • • • 4301 F05 system to meet rise- and fall-time requirements. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because valid logic low voltage with respect to the ground at one end of the system may violate the allowed VOL specification with respect to the ground at the other end. In addition, the connection circuitry offset voltages of the back-to-back LTC4301s add together, directly contributing to the same problem. Systems with Supply Voltage Droop In large 2-wire systems, the VCC voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. This situation is well modelled by a series resistor in the VCC line as shown in Figure 7. For proper operation, make sure that the VCC(LTC4301) is ≥ 2.7V. 4301fb 9 LTC4301 APPLICATIO S I FOR ATIO VCC1 VCC2 0.01µF R1 10k R4 10k LTC4301 VCC CS SDAOUT SCLOUT READY GND SDA1 SDAIN SCLIN SCL1 TO OTHER SYSTEM 1 DEVICES Figure 6. Repeater/Bus Extender Application RDROP VCC (BUS) R1 10k R2 10k CS SDA SCL SDAIN SCLIN 0.01µF Figure 7. System with VCC Voltage Droop 10 U VCC3 VCC4 VCC5 W UU 0.01µF R5 10k R3 R2 5.1k 5.1k R6 10k LTC4301 VCC R7 10k CS R8 10k SDAOUT SCLOUT READY LONG DISTANCE BUS GND SDAIN SCLIN SDA2 SCL2 TO OTHER SYSTEM 2 DEVICES 4301 F07 VCC R3 10k VCC LTC4301 GND SDAOUT SCLOUT READY 4301 F06 R4 10k R5 10k SDA2 SCL2 4301fb LTC4301 PACKAGE DESCRIPTIO 3.5 ± 0.05 1.65 ± 0.05 2.15 ± 0.05 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.25 ± 0.05 0.50 BSC 2.38 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.889 ± 0.127 (.035 ± .005) GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) DETAIL “A” 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC RECOMMENDED SOLDER PAD LAYOUT Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.675 ± 0.05 0.38 ± 0.10 8 3.00 ± 0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) (DD8) DFN 1203 PACKAGE OUTLINE 0.200 REF 0.75 ± 0.05 4 0.25 ± 0.05 2.38 ± 0.10 (2 SIDES) 1 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.52 (.0205) REF 8 7 65 0.254 (.010) DETAIL “A” 0° – 6° TYP 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.53 ± 0.152 (.021 ± .006) 0.18 (.007) SEATING PLANE 1 23 4 1.10 (.043) MAX 0.86 (.034) REF 0.22 – 0.38 (.009 – .015) TYP NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.65 (.0256) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS8) 0204 4301fb 11 LTC4301 TYPICAL APPLICATIO 3.3V 5V 0.01µF 10k 10k BACK_SCL 10k VCC LTC4301 10k STAGGERED CONNECTOR BACK_SDA FROM MICROPROCESSOR RELATED PARTS PART NUMBER LTC1380/LTC1393 LTC1427-50 LTC1623 LTC1663 LTC1694/LTC1694-1 LT1786F LTC1695 LTC1840 LTC4300A-1/LTC4300A-2 LTC4301L LTC4302-1/LTC4302-2 DESCRIPTION Single-Ended 8-Channel/Differential 4-Channel Analog Mux with SMBus Interface Micropower, 10-Bit Current Output DAC with SMBus Interface SMBus Interface 10-Bit Rail-to-Rail Micropower DAC SMBus Accelerator SMBus Controlled CCFL Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM Dual I2C Fan Speed Controller Hot Swappable 2-Wire Bus Buffer Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation Addressable 2-Wire Bus Buffer COMMENTS Low RON: 35Ω Single-Ended/70Ω Differential, Expandable to 32 Single or 16 Differential Channels Precision 50µA ± 2.5% Tolerance Over Temperature, 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale DNL < 0.75LSB Max, 5-Lead SOT-23 Package Improved SMBus/I2C Rise-Time, Ensures Data Integrity with Multiple SMBus/I2C Devices 1.25A, 200kHz, Floating or Grounded Lamp Configurations 0.75Ω PMOS 180mA Regulator, 6-Bit DAC Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0 Isolates Backplane and Card Capacitances Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN Address Expansion, GPIO, Software Controlled Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability ThinSOT is a trademark of Linear Technology Corporation. 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U SCLIN SCLOUT CARD_SCL SDAIN 5V 10k CS GND READY 4301 TA01 SDAOUT CARD_SDA BACKPLANE CONNECTOR CARD Figure 8. System with Active Connection Control 4301fb LT 0806 REV B • PRINTED IN THE USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004