LTC4310IDD-1-PBF

LTC4310-1/LTC4310-2 Hot-Swappable I2C Isolators FeaTures n n DescripTion The LTC®4310 provides bidirectional I2C communications between two I2C buses whose grounds are isolated from one another. Each LTC4310 encodes I2C bus logic states into signals that are transmitted across an isolation barrier to another LTC4310. The receiving LTC4310 decodes the transmission and drives its l2C bus to the appropriate logic state. The isolation barrier can be bridged by an inexpensive Ethernet, or other transformer, to achieve communications across voltage differences reaching thousands of volts, or it can be bridged by capacitors for lower voltage isolation. The LTC4310-1 is intended for use in 100kHz I2C systems. The LTC4310-2 is intended for 400kHz I2C systems. Rise time accelerators provide strong pull-up currents on SCL and SDA rising edges to meet rise time specifications for heavily loaded systems. Data and clock Hot Swap™ circuitry prevent data corruption when a card is inserted into or removed from a live bus. When a bus is stuck low for 37ms, the LTC4310 turns off its pull-down devices and generates up to sixteen clocks and a STOP bit in an attempt to free the bus. Driving EN low sets the LTC4310 in a very low current shutdown mode to conserve power. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. n n n n n n n n n n Bidirectional I2C Communication Between Two Isolated Buses Full Isolation with Inexpensive Ethernet Transformers or Capacitors Low Voltage Level Shifting I2C Maximum Operating Frequency: 100kHz for LTC4310-1 400kHz for LTC4310-2 2C Specification Compliant V , V I OL IL ±5kV Human Body Model ESD Protection Rise Time Accelerators SDA, SCL Hot-Swapping Very Low Shutdown Current Stuck Bus Disconnect and Recovery Thermal Shutdown 10-Lead MSOP and 3mm × 3mm DFN Packages Isolated I2C, SMBus and PMBus Interfaces Isolated Power Supplies Positive-to-Negative Rail Communications Power-over-Ethernet applicaTions n n n n Typical applicaTion 1500V Isolated I2C System 3.3V 0.01µF 10/100Base-TX ETHERNET TRANSFORMER VCC TXP RXP VCC 0.01µF ISOLATED 5V 0V 3.3k 3.3k LTC4310-1 SDA SCL EN READY GND RXN EPF8119S 0.01µF TXN RXP 0.01µF LTC4310-1 RXN TXP SDA SCL EN READY TXN GND 431012 TA01a LTC4310 Operating Through 20kV/µs Common Mode Transient SCL SDA 2V/DIV 3.3k 3.3k SDA1 SCL1 SDA2 SCL2 20kV/µs 0V 2µs/DIV 431012 TA01b 500V/ DIV 431012f  LTC4310-1/LTC4310-2 absoluTe MaxiMuM raTings (Notes 1, 4) Input Supply Voltage (VCC) .......................... –0.3V to 6V Input and Bidirectional Pin Voltages SCL, SDA, EN, RXP RXN.......................... –0.3V to 6V , Output Voltages READY ..................................................... –0.3V to 6V TXP TXN ...................... –0.3V to VCC + 0.3V (6V Max) , Maximum Sink Current (SDA, SCL, READY) ..........30mA Operating Ambient Temperature Range LTC4310C ................................................ 0°C to 70°C LTC4310I.............................................. –40°C to 85°C Storage Temperature Range DD ..................................................... –65°C to 125°C MS ..................................................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package ...................................................... 300°C pin conFiguraTion TOP VIEW EN SDA SCL READY GND 1 2 3 4 5 11 GND 10 RXN 9 RXP 8 VCC 7 TXP 6 TXN EN SDA SCL READY GND 1 2 3 4 5 TOP VIEW 10 9 8 7 6 RXN RXP VCC TXP TXN DD PACKAGE 10-LEAD (3mm 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 11) PCB CONNECTION TO GROUND IS OPTIONAL MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 120°C/W orDer inForMaTion LEAD FREE FINISH LTC4310CDD-1#PBF LTC4310IDD-1#PBF LTC4310CMS-1#PBF LTC4310IMS-1#PBF LTC4310CDD-2#PBF LTC4310IDD-2#PBF LTC4310CMS-2#PBF LTC4310IMS-2#PBF TAPE AND REEL LTC4310CDD-1#TRPBF LTC4310IDD-1#TRPBF LTC4310CMS-1#TRPBF LTC4310IMS-1#TRPBF LTC4310CDD-2#TRPBF LTC4310IDD-2#TRPBF LTC4310CMS-2#TRPBF LTC4310IMS-2#TRPBF PART MARKING* LFCH LFCH LTFCG LTFCG LFCK LFCK LTFCJ LTFCJ PACKAGE DESCRIPTION 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead (3mm × 3mm) Plastic DFN 10-Lead (3mm × 3mm) Plastic DFN 10-Lead Plastic MSOP 10-Lead Plastic MSOP TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 431012f  LTC4310-1/LTC4310-2 elecTrical characTerisTics SYMBOL Supplies VCC ICC ICC(SD) VCCH(UVL) VCC(UVL, HYST) I2C Interface VSDA,SCL(OL) VSDA,SCL(IL,R) VSDA,SCL(IL,F) ISDA,SCL(OH) dV/dtRISE SDA, SCL Logic Low Output Voltage I(SDA,SCL) = 4mA, 500µA; VCC = 3V, 5.5V l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted. PARAMETER Input Supply Range Input Supply Current, LTC4310-1 Input Supply Current, LTC4310-2 Shutdown Input Supply Current Input Supply Undervoltage Lockout Rising Threshold Voltage Input Supply Undervoltage Lockout Hysteresis EN = VCC = 5.5V, SDA = SCL = VSDA,SCL(OL) EN = VCC = 5.5V, SDA = SCL = VSDA,SCL(OL) EN = 0V, VCC = 5.5V CONDITIONS l l l l l l MIN 3 TYP MAX 5.5 UNITS V mA mA µA V mV 6.5 7 0.1 2.1 90 2.4 190 8 8.5 ±10 2.7 270 310 0.3 • VCC 0.4 • VCC 350 0.35 • VCC 0.45 • VCC 0 380 0.4 • VCC 0.5 • VCC ±5 1.4 2.6 3.9 6.9 270 mV V V µA V/µs V/µs V/µs V/µs ns kHz kHz SDA, SCL Controlled Rising Edge Rate VCC = 3V, 5.5V (Note 5) Turn-Off Threshold Voltage SDA, SCL Logic Low Falling Input Threshold Voltage SDA, SCL Input Current Bus Line Controlled Rising Edge Rate, LTC4310-1 Bus Line Controlled Rising Edge Rate, LTC4310-2 VCC = 3V SCL, SDA = VCC = 0V, 5.5V 0.35V < VBUS < 0.35 • VCC, VCC = 3V 0.35V < VBUS < 0.35 • VCC, VCC = 5.5V 0.35V < VBUS < 0.35 • VCC, VCC = 3V 0.35V < VBUS < 0.35 • VCC, VCC = 5.5V VCC = 5.5V (Note 3) LTC4310-1 LTC4310-2 SCL, SDA = VCC (Note 2) VCC = 3V (Note 5) VCC = 3V I2C Interface Timing l l l l l l l 0.8 1.5 2 3.9 1.16 2.14 3 5.4 170 tPHL(SDA,SCL) fSCL(MAX) CIN VBOOST IBOOST SDA, SCL High-to-Low Propagation Delay Maximum SCL Clock Frequency SCL, SDA Input Capacitance SDA, SCL Rise Time Accelerator Activation Threshold Voltage SDA, SCL Rise Time Accelerator Current READY Output Low Voltage READY Off-Current EN Rising Threshold Voltage EN Falling Threshold Voltage EN Input Current Bus Idle Time Start-Up Filter Time SDA, SCL Bus Stuck Low Disconnect 100 400 10 pF V mA Rise Time Accelerators l l 0.32 • VCC 0.45 • VCC 2 6 0.5 • VCC READY Open-Drain Output VREADY(OL) IREADY(OH) VEN,RISE VEN,FALL IEN(OH) tIDLE tUVLO,EN_FILT tSTUCK IREADY = 4mA READY= VCC = 5.5V, EN = 0V l l 50 0.1 0.6 • VCC 0.1 • VCC 75 700 27 0.3 • VCC 0.1 115 900 37 400 ±10 0.9 • VCC ±10 155 1200 47 mV µA V V µA µs µs ms Connection Control l l EN = VCC = 5.5V l l l l 431012f  LTC4310-1/LTC4310-2 elecTrical characTerisTics SYMBOL tMAX(TX) tMAX(RX) Transmit Outputs VTX(OL) VTX(OH) tR(TX) tF(TX) tPWMIN(TX) Receive Inputs VRX(TH) tPWMIN(RX) RRX(IN) RXP RXN Differential High Level , Threshold RXP RXN Minimum Received Pulse , Width RXP RXN Differential Input Resistance , RXP RXN Pins; VCC = 3V, 5.5V , VCC = 3V, 5.5V l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted. PARAMETER Maximum Time Between TXP TXN , Transmit Events Maximum Time Between RXP RXN , Receive Events TXP TXN Single-Ended Output Low , TXP TXN Single-Ended Output High , TXP TXN Output Rise Time , TXP TXN Output Fall Time , TXP TXN Minimum Transmission , Pulse Width ISINK = 100µA, VCC = 3V 15kΩ to GND on TXP TXN; VCC = 3V, 5.5V , CTXP, CTXN = 20pF CTXP, CTXN = 20pF VCC = 3V, 5.5V CONDITIONS l l MIN 0.85 3.4 TYP 1.15 4.6 MAX 1.45 5.8 UNITS ms ms l l l l l 1.5 0.95 1.25 1 1 31.5 35 5 1.52 3 3 39 mV V ns ns ns 0.3 30 13 0.5 0.875 V ns 16.5 20 kΩ Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. Guaranteed by design, not tested in production. Note 3. SDA, SCL high-to-low propagation delay is measured from the beginning of a new received message telling the LTC4310 to drive its SDA, SCL pins from high to low, to when the SDA, SCL lines have fallen below 0.5 • VCC. It includes approximately 87ns required for an LTC4310 to receive a message on the RXP and RXN pins, plus the time the LTC4310 requires to process the message and pass the low to the data and clock buffers, plus the time required by the buffers to drive their bus pins below 0.5 • VCC. Note 4. All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 5. Internal control circuitry prevents the rise time accelerators from activating until the rising edge rate control circuitry is off. 431012f  LTC4310-1/LTC4310-2 Typical perForMance characTerisTics 5.0 ICC vs Temperature, LTC4310-1 SDA = 0V SCL = VCC VCC = 5V CONTROLLED RISE RATE (V/µs) SDA, SCL Controlled Rising Edge Rate vs Temperature, LTC4310-1 2.0 VCC = 5V 4.8 1.8 ICC (mA) 4.6 VCC = 3.3V 1.6 4.4 4.2 1.4 VCC = 3.3V 1.2 –50 –25 0 25 50 75 100 125 4.0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 431012 G01 TEMPERATURE (°C) 431012 G02 SDA, SCL Controlled Rising Edge Rate vs Temperature, LTC4310-2 5.5 CONTROLLED RISE RATE (V/µs) 5.0 4.5 4.0 3.5 3.0 2.5 –50 VCC = 3.3V VCC = 5V PULL-UP CURRENT (mA) 11 10 9 8 7 6 SDA, SCL Rise Time Accelerator Pull-Up Current vs Temperature VCC = 5V VCC = 3.3V –25 0 25 50 75 100 125 5 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 431012 G03 TEMPERATURE (°C) 431012 G04 SDA, SCL Rise Time Accelerator Pull-Up Current vs Bus Capacitance 12 10 PULL-UP CURRENT (mA) VCC = 5V 8 6 4 2 0 VCC = 3.3V PROPAGATION DELAY (ns) TA = 25°C 220 200 180 160 140 120 SDA,SCL Falling Propagation Delay vs Temperature VCC = 3.3V VCC = 5V 0 100 200 300 400 500 600 700 800 BUS CAPACITANCE (pF) 431012 G05 0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 431012 G06 431012f  LTC4310-1/LTC4310-2 pin FuncTions EN (Pin 1): Device Enable Input. Pulling EN up to VCC sets the device in normal operation mode, allowing bus information to be sent and received across the barrier. Grounding EN disables communication across the barrier and debiases all internal circuitry, setting the device in a very low current shutdown mode. Connect to VCC if unused. SDA (Pin 2): Serial Bus Data Input/Output. This is the bidirectional data line for the two-wire bus. An external pull-up resistor or current source from SDA to a supply voltage greater than or equal to the VCC voltage is required. See the Applications Information section for guidance on selecting the resistor or current source value. Do not leave open. SCL (Pin 3): Serial Bus Clock Input/Output. This is the bidirectional clock line for the two-wire bus. An external pull-up resistor or current source from SCL to a supply voltage greater than or equal to the VCC voltage is required. See the Applications Information section for guidance on selecting the resistor or current source value. Do not leave open. READY (Pin 4): Device Receiving Indicator Output. READY is an open-drain digital output that pulls low when the LTC4310 is driving its SDA and SCL pins with the logic state information it is receiving on its RXP and RXN pins. Connect this pin to VCC with a 10k resistor. This pin can be left open or tied to GND if unused. GND (Pin 5): Device Ground. TXN (Pin 6): Negative Transmit Output. Tie TXN to the negative side of the transformer primary winding or to the RXN pin of another LTC4310 through a ceramic capacitor. See the Applications Information section for guidance in selecting the capacitor value. Do not leave open. TXP (Pin 7): Positive Transmit Output. Tie TXP to the positive side of the transformer primary winding or to the RXP pin of another LTC4310 through a ceramic capacitor. See the Applications Information section for guidance in selecting the capacitor value. Do not leave open. VCC (Pin 8): Device Power Supply Input. Connect a bypass capacitor of at least 0.01µF directly between VCC and GND. RXP (Pin 9): Positive Receive Input. Tie RXP to the positive side of the transformer secondary winding or to the TXP pin of another LTC4310 through a ceramic capacitor. See the Applications Information section for guidance in selecting the capacitor value. Do not leave open. RXN (Pin 10): Negative Receive Input. Tie RXN to the negative side of the transformer secondary winding or to the TXN pin of another LTC4310 through a ceramic capacitor. See the Applications Information section for guidance in selecting the capacitor value. Do not leave open. Exposed Pad (Pin 11) DFN Package Only: The exposed pad may be left open or connected to device ground. 431012f  LTC4310-1/LTC4310-2 FuncTional DiagraM + – 0.45 • VCC 1.25V 8 VCC IBOOST SDA 0.35 • VCC 0.45 • VCC LOGIC + – + – – + FALLING VIL 1.25V RISING VIL RX TXP 7 TXN 2 6 0.35V LOGIC RISE RATE LIMITER dV/dtRISE 150µA 0.5V + – + – – + –+ RXP 9 VCC LOGIC IBOOST + – 0.45 • VCC –+ 0.5V RXN 10 3 SCL 0.45 • VCC + – + – – + FALLING VIL STOP BIT AND BUS IDLE DETECTORS RXP RXN 0.35 • VCC RISING VIL RX STUCK BUS TIMERS SCL SDA 0.35V RISE RATE LIMITER dV/dtRISE 150µA 1 EN + – READY 4 GND tSD VCC 2.4V/2.21V 5 + – UVLO POR CIRCUITRY 431012 FD 431012f  LTC4310-1/LTC4310-2 operaTion (LTC4310 refers to both LTC4310-1 and LTC4310-2) The LTC4310 provides fully bidirectional communications between two I2C or SMBus buses whose grounds are isolated from one another. Clock stretching, clock synchronization, arbitration and data acknowledging all work seamlessly across the barrier, regardless of the locations of the master(s) and slave(s). Referring to the application circuit shown in Figure 1, an LTC4310 is located on each side of the isolation barrier. Each LTC4310 contains logic detection circuitry that can differentiate externally driven SDA and SCL logic signals from its own output signals. Each LTC4310 converts the logic state of the externally driven signals into a sequence of pulses that are then transmitted across the isolation barrier via an Ethernet transformer (or coupling capacitors for low isolation voltage applications) to the other LTC4310. Each LTC4310 also receives and decodes corresponding pulses from the other LTC4310 and drives its SDA and SCL pins accordingly. Transmissions occur on the TXP and TXN pins in a sequence of 1.25V pulses. The LTC4310 receives messages on its RXP and RXN pins. Signals having less than 500mV differential voltages are rejected to provide noise immunity against common-mode transients. When the LTC4310 receives a message to drive SDA low, it regulates SDA to 0.35V. If an external device pulls SDA below 0.35V during this time, the LTC4310 detects this condition and immediately transmits a LOW to the other LTC4310. When an external pull-down device drives SDA below 0.45 • VCC from a logic high, TXP and TXN transmit a message across the isolation barrier instructing the other LTC4310 to drive its SDA line low. When the external pull-down device turns off and SDA is rising between 0V and 0.35 • VCC, the LTC4310 limits the bus rise rate to dV/dtRISE via the rise rate limiter circuitry. It also transmits a high to the other LTC4310. If the SDA rise rate falls below the threshold, it is assumed that another pull-down on the bus has turned on and is pulling SDA low, and a command to pull the far side low is sent across the isolation barrier. When SDA rises above 0.35 • VCC, the rise rate limiter circuitry is deactivated. When SDA rises above 0.45 • VCC, the rise time accelerator current IBOOST is activated, which provides a strong, slew-limited pull-up current to reduce system rise time. The LTC4310 contains power-on reset (POR) circuitry that sets the data and clock pins in a high impedance state and deactivates the transmit and receive circuitry until the EN voltage is high, the device is not in thermal shutdown and the VCC voltage is above the 2.4V UVLO threshold voltage. The LTC4310 enters thermal shutdown when the die temperature exceeds 150°C. Grounding EN sets the LTC4310 in a near-zero current mode. After the LTC4310 exits POR, STOP bit and bus idle detector circuitry monitors the logic state of its own SDA and SCL bus and of the other I2C bus in the system via RXP and RXN. When a STOP bit or bus idle occurs simultaneously on both I2C buses, the LTC4310 activates its SDA and SCL drivers, logic detection circuitry and rise time accelerators and drives READY low. The stuck bus timer and recovery circuitry disable the SDA and SCL driver, logic detection circuitry and rise time accelerators if the bus is low for 37ms. A stuck bus also causes READY to be released high. If the stuck bus releases high, the I2C driver and accelerator circuitry are reactivated when a STOP bit or bus idle occurs simultaneously on both I2C buses, as previously described. 431012f  LTC4310-1/LTC4310-2 operaTion 3.3V C1 0.01µF R1 7.5k R2 7.5k READY TXP LTC4310-1 VCC EN SCL1 SDA SCL TXN RXP R3 10k 1 10/100Base-TX ETHERNET TRANSFORMER R4 10k 16 READY RXP LTC4310-1 C3 0.01µF RXN TXP VCC EN SDA SCL C4 0.01µF R5 7.5k IS0LATED 5V R6 7.5k 15 CBUS = 40pF 3 6 14 11 CBUS = 80pF SCL2 SLAVE#1 . . . SLAVE#4 µP SLAVE 7 C2 0.01µF 8 EPF8119S GND RXN 9 TXN GND 431012 F01 Figure 1. The LTC4310-1 in a Transformer Isolated Application 431012f  LTC4310-1/LTC4310-2 applicaTions inForMaTion SDA, SCL Bus Pull-Up Resistor Value Selection When the SDA (or SCL) bus is rising between 0V and 0.35 • VCC, the LTC4310 controls the bus rise rate to (0.35 • VCC)/900ns for the LTC4310-1 and to (0.35 • VCC)/ 300ns for the LTC4310-2. Users must quantify their parasitic bus capacitance, CBUS, and choose a bus pullup resistor, RBUS, based on their bus pull-up supply voltage and maximum bus switching frequency to ensure that each bus rises faster than the controlled rise rate. For bus frequencies up to 100kHz, choose the LTC4310-1 and refer to Figure 2 for the maximum pull-up resistance to use. For bus frequencies between 100kHz and 400kHz, choose the LTC4310-2 and refer to Figure 3 for the maximum pull-up resistance to use. Be sure to include worst-case resistor tolerance when selecting resistor value. Rise Time Accelerators The LTC4310’s rise time accelerator circuitry on the SDA and SCL lines turns on during rising edges to 18 16 14 RBUS(MAX) (k ) 12 10 8 6 4 2 0 1 10 CBUS(MAX) (pF) 100 1000 431012 F02 reduce the bus rise time. When the bus has risen above 0.45 • VCC, the LTC4310 turns on a strong, slew-limited pull-up current, I BOOST, to help even heavily loaded buses meet the rise time specificat ions. See the Typical Performance Characterist ics section for the rise time accelerator pull-up c urrent as a function of temperature and bus capacitance. When either the bus has risen above (VCC – 1V) or 300ns after the pull-up current has t urned on (whichever comes first), the LTC4310 d eactivates its pull-up current to deter fighting w ith the subsequent falling edge. Users must ensure that the bus pull-up supply voltage VBUS ≥ VCC, so that the accelerators do not overdrive the SDA, SCL bus and source current into VBUS. The rise time accelerators are deactivated during start-up, thermal shutdown, shutdown and after disconnection due to a stuck bus or failure to receive a transmission within 4.6ms. 18 16 VCC = 5V RBUS(MAX) (k ) VCC = 3.3V 14 12 10 8 6 4 2 0 1 10 CBUS(MAX) (pF) 100 1000 431012 F03 VCC = 5V VCC = 3.3V Figure 2. Maximum SDA,SCL Bus Pull-Up Resistor Value as a Function of Parasitic Bus Capacitance for the LTC4310-1 Figure 3. Maximum SDA,SCL Bus Pull-Up Resistor Value as a Function of Parasitic Bus Capacitance for the LTC4310-2 431012f 0 LTC4310-1/LTC4310-2 applicaTions inForMaTion Bus Rising Edge Waveform When all external pull-downs on SCL1 (Figure 1) turn off, the SCL1 rising waveform will resemble that shown in Figure 4. The LTC4310-1 senses that SCL1 is rising and transmits a message to the other LTC4310-1 to release SCL2 high. During the transmission, the first LTC4310-1 also drives SCL1 to 0.35V, so that when the transmission is complete, both buses will rise simultaneously from 0.35V at a rate of (0.35 • VCC)/900ns. This functionality minimizes the effective skew between the two buses. When SCL1 reaches 0.35 • VCC, the LTC4310-1 deactivates its rise rate regulation circuitry. The bus then rises with a time constant of (RBUS • CBUS) until it reaches 0.45 • VCC, at which point the IBOOST rise time accelerator pull-up current is activated. Figure 5 shows SCL1 and SCL2 for an entire 100kHz switching cycle. Because the LTC4310-1 regulates the bus rise rate to (0.35 • VCC)/900ns, the 5V bus signal rises more quickly than the 3.3V bus signal. Both buses reach (0.35 • VCC) in approximately 900ns, so the effective skew between the buses is nearly zero. The LTC4310-2 functions the same as the LTC4310-1, except the controlled rise rate is limited to (0.35 • VCC)/300ns. Start-Up, Data and Clock Hot Swap Circuitry The LTC4310 contains power-on reset (POR) circuitry that sets the data and clock pins in a high impedance state and deactivates the transmit circuitry until the EN voltage is high, the device is not in thermal shutdown and the VCC voltage is above 2.4V. After the LTC4310 exits the POR state, it activates its transmit circuitry and communicates its SDA, SCL logic states across the barrier to the other LTC4310 via its TXP and TXN pins. The receive circuitry remains deactivated for an additional 900µs after the LTC4310 exits POR. The 900µs filter time is required for the LTC4310 to charge its RXP and RXN pins to their DC bias voltage, assuming a 0.01µF common-mode noise filtering capacitor at the center-tap of the secondary side of the external transformer. When the filter time has elapsed, the LTC4310 activates its receive circuitry and decodes the messages it receives on its RXP and RXN pins, registering the logic state of the remote I2C bus. When both the local and remote two-wire buses are “quiet” (i.e., no data transactions are occurring on either bus), the LTC4310 then drives its READY pin low to indicate that it has linked the logic state of the local I2C bus with the logic state of the remote I2C bus. This means that the LTC4310 will now drive its SDA and SCL pins to the logic state of the remote I2C bus, as specified by the messages it receives on RXP and RXN. The LTC4310 considers a two-wire bus SCL2 RISE TIME ACCELERATOR ACTIVE 1V/DIV SCL1 SET TO 0.35V DURING TX BUS RC 0.35 • VCC 900 ns 1V/DIV SCL1 dV/dt = 200ns/DIV 431012 F04 2µs/DIV 431012 F05 Figure 4. SCL1 Rising Waveform of SCL1 for Application Circuit Shown in Figure 1 Figure 5. 100kHz SCL Waveforms for Application Circuit Shown in Figure 1 431012f  LTC4310-1/LTC4310-2 applicaTions inForMaTion quiet if it has been idle high for at least 115µs, or if a STOP bit has occurred and both data and clock have remained high since the STOP bit. This functionality makes the LTC4310 ideal for hot-swapping cards into and out of a live I2C system. The threshold voltages for the STOP bit and bus idle comparators are 0.5 • VCC. Stuck Bus Disconnect and Recovery An internal timer runs whenever SDA, SCL or both are low. The timer is only reset when both SDA and SCL are high. If the timer does not reset within 37ms, the LTC4310 assumes the bus is stuck low. Accordingly, it ceases driving its SDA and SCL pins and transmits a special message across the barrier to inform the other LTC4310. Upon receiving this message, the other LTC4310 also ceases driving its SDA and SCL pins. At least 40µs after determining the bus is stuck low, the LTC4310 generates up to sixteen clock cycles on SCL in an attempt to make the slave release the SDA line. The LTC4310 stops issuing clocks when the SDA line releases high, or after sixteen cycles, whichever comes first. Once the clock pulses have completed, the LTC4310 issues a STOP bit on SDA and SCL to reset all devices on the bus. The LTC4310 reactivates its amplifiers and rise time accelerators when the bus releases high and a STOP bit or bus idle occurs on both the local and isolated buses, as previously described in the Start-Up, Data and Clock Hot Swap Circuitry section. The stuck bus disconnect and recovery circuitry is disabled when the LTC4310 is in UVLO, thermal shutdown and low current shutdown. Transmit and Receive Circuitry Transmissions occur on the TXP and TXN pins whenever the externally driven SDA or SCL logic state changes – in other words, transmissions are event driven. In addition, if SDA and SCL do not change state for 1.15ms, the LTC4310 retransmits the logic state. The TXP and TXN pins are driven in a pseudo differential fashion. Both pins are driven to ground when inactive and are driven to 1.25V (typical) in matched sets of alternating 35ns pulses to send information across the barrier to the other LTC4310. The LTC4310 receives and decodes the pulses sent by the other LTC4310 on its RXP and RXN pins. Assuming the start-up sequence previously described has been completed, the LTC4310 drives its SDA and SCL lines to the logic state dictated by the decoded RXP and RXN signals. The LTC4310 rejects RXP and RXN signals having less than 500mV magnitude to provide noise immunity against common-mode transients.The parasitic capacitances of the LTC4310’s RXP and RXN pins and their associated board traces form a capacitive divider with the transmit/receive coupling capacitors, as shown in Figure 6. To guarantee robust communications, minimize the parasitic capacitance CPAR by minimizing the trace length from the coupling capacitors to the RXP and RXN pins and choose coupling capacitor values, CRXP and CRXN, that are at least ten times larger than CPAR. CRXP ≥47pF CPAR1 4.7pF LTC4310 RXP CRXN ≥47pF RXN CPAR2 4.7pF GND 431012 F06 Figure 6. Parasitic Trace and Pin Capacitances Form a Capacitive Divider with CRXP and CRXN. Ensure CRXP, CRXN ≥ 10 • CPAR If the LTC4310 has not received a message in 4.6ms, it assumes there is a communication problem and ceases driving its SDA and SCL pins. It also transmits a special message to the other LTC4310 to inform it that it is no longer driving its SDA and SCL bus. Upon receiving this message, the other LTC4310 also ceases driving its SDA and SCL pins. Once the communication problem is resolved, both LTC4310’s reactivate their amplifiers and rise time accelerators after a STOP bit or bus idle has occurred on both buses, as previously described in the Start-Up, Data and Clock Hot Swap Circuitry section. Thermal Shutdown If the die temperature of the LTC4310 exceeds 150°C, the LTC4310 enters a thermal shutdown mode. It sets TXP and TXN to a high impedance state, ceases driving SDA and SCL, and ignores the signals on RXP and RXN. When the temperature drops back below 130°C, the LTC4310 goes through the POR sequence previously described. 431012f  LTC4310-1/LTC4310-2 applicaTions inForMaTion Once a STOP bit or bus idle occurs on both the local and isolated buses, the LTC4310 reactivates its buffers and rise time accelerators. READY Digital Output The READY pin provides a digital output flag that pulls low to indicate that the LTC4310 is driving its SDA and SCL pins with the logic state information it is receiving on its RXP and RXN pins from the other LTC4310. READY is driven by an N-channel MOSFET open-drain pull-down that is capable of sinking 4mA while holding 0.4V maximum. The pull-down turns off whenever the LTC4310 is not driving its SDA and SCL pins—during start-up, thermal shutdown, low current shutdown and after disconnection due to a stuck bus or failure to receive a transmission within 4.6ms. Connect a resistor to the bus pull-up supply to provide the pull-up. Design Example: High Voltage Isolation Using an Inexpensive Ethernet Transformer Figure 1 shows the LTC4310-1 providing I2C communications between two buses whose ground voltages can differ up to 1500V. An EPF8119S Ethernet transformer is used to bridge the isolation barrier. The left I2C bus connects to the LTC4310-1 and two other devices, resulting in a bus parasitic capacitance of 40pF in this example set-up. Referring to the VCC = 3.3V curve in Figure 2, 7.5k pull-up resistors are chosen for R1 and R2. The right I2C bus connects to another LTC4310-1 and four slave devices, resulting in a bus parasitic capacitance of 80pF . Referring to the VCC = 5V curve in Figure 2, 7.5k pull-up resistors are also chosen for R5 and R6. Standard 5% resistors are used. Sudden changes in the ground differential across the isolation barrier can be effectively resisted by tying the center tap of the receive side of the transformer to the local ground through a 0.01µF capacitor, as shown by capacitors C2 and C3. Figure 7 shows the same application as Figure 1, but with each LTC4310-1 replaced by an LTC4310-2, so that the bus can switch at frequencies up to 400kHz. To meet the requirements shown in the curves of Figure 3, R1 and R2 are changed from 7.5k to 4.3k, and R5 and R6 are changed from 7.5k to 3.3k. IS0LATED 5V R5 3.3k R6 3.3k 3.3V C1 0.01µF R1 4.3k R2 4.3k READY TXP LTC4310-2 VCC EN SCL1 SDA SCL TXN RXP R3 10k 1 10/100Base-TX ETHERNET TRANSFORMER R4 10k 16 READY RXP LTC4310-2 C3 0.01µF RXN TXP VCC EN SDA SCL C4 0.01µF 15 CBUS = 40pF 3 6 14 11 CBUS = 80pF SCL2 SLAVE#1 . . . SLAVE#4 µP SLAVE 7 C2 0.01µF 8 EPF8119S GND RXN 9 TXN GND 431012 F07 Figure 7. The LTC4310-2 in a 400kHz Application 431012f  LTC4310-1/LTC4310-2 applicaTions inForMaTion TYPICAL APPLICATIONS Figure 8 shows the LTC4310-1 providing I2C communications between an I2C bus referenced to system ground and an I2C bus using –5V for its ground reference. Ceramic coupling capacitors, C1-C5, are used to bridge the isolation barrier. This circuit is recommended for ground isolation voltages less than 100V and is limited by the voltage rating of C1-C5. Higher voltage ceramic capacitors may be used to achieve higher isolation voltages. Because the LTC4310 uses a pseudo-differential transmit scheme, capacitor C5 must be connected between ground and –5V to provide a return path for the transmitted current. Figure 9 shows the LTC4310-1 in an application circuit using its zero current shutdown mode. A microprocessor only activates the left LTC4310-1 when it needs to communicate with the isolated I2C bus. Because the LTC4310-1 contains a STOP bit and bus idle detection circuitry, there is no danger of connecting in the middle of a message when the microprocessor asynchronously reenables the LTC4310-1. Figure 10 shows the LTC4310-1 in a two-wire bus Hot Swap application. Using a staggered connector, make EN the shortest length pin to ensure that the transients associated with hot swapping have settled before the LTC4310-1 can be enabled. After connection is complete, a master on the backplane may drive EN high to bring the LTC4310-1 out of shutdown mode and into normal operation. Due to its STOP bit and bus idle detection circuitry, the LTC4310-1’s driver circuitry is not activated until transactions on both buses are complete. 3.3V C6 0.01µF R1 5.1k R2 5.1k R3 10k C1 C7 0.01µF –5V R4 10k R5 10k R6 10k TXP LTC4310-1 CBUS = 100pF SDA SCL READY EN GND TXN RXP RXN C5 C3 VCC C2 RXP LTC4310-1 RXN TXP TXN GND 431012 F08 VCC SDA SCL READY EN CBUS = 30pF C4 –5V C1 TO C5 = 47pF 100V , Figure 8. Low Voltage I2C Isolation Between a Ground Referenced Bus and a –5V Referenced Bus 431012f  LTC4310-1/LTC4310-2 applicaTions inForMaTion 5V C6 0.01µF R1 3.3k R2 3.3k R3 10k C1 C2 C3 C4 C7 0.01µF –5V TXP LTC4310-1 CBUS = 200pF µP OFF ON GND SDA SCL READY EN TXN RXP RXN C5 VCC EN RXP LTC4310-1 RXN TXP TXN GND 431012 F09 VCC R4 10k R5 5.1k R6 5.1k READY SDA SCL SLAVE#1 . . . SLAVE#N CBUS = 150pF –5V C1 TO C5 = 47pF 100V , Figure 9. The LTC4310-1 in a Zero Current Shutdown Application BACKPLANE CONNECTOR BACKPLANE 5V CARD CONNECTOR I/O PERIPHERAL CARD C6 0.01µF C7 0.01µF R4 6.8k R5 6.8k R6 10k 3.3V R1 2k R2 2k R3 10k TXP LTC4310-1 SDA C = 400pF SCL BUS READY EN R7 100k SDA SCL READY EN TXN RXP RXN GND C5 C3 VCC C1 C2 RXP LTC4310-1 RXN TXP TXN GND SDA SCL READY EN CBUS = 50pF SDA2 SCL2 READY2 EN2 VCC C4 C1 TO C5 = 47pF 100V , 431012 F10 Figure 10. The LTC4310-1 in an I2C Hot-Swapping Application 431012f  LTC4310-1/LTC4310-2 applicaTions inForMaTion LTC4310 Compatibility with Other LTC Bus Buffers The LTC4310 cannot be used on the same I2C bus with the LTC4300A-1, LTC4303 or LTC4307. During rising edges, the rise time accelerators of these buffers turn on before the LTC4310 disables its rise rate regulation circuitry, resulting in nonmonotonic bus edges. The LTC4310-1 is compatible with the LTC4301 and LTC4301L. It is also compatible with the LTC4302, LTC4304, LTC4305 and LTC4306, provided that the rise time accelerators of these buffers are permanently disabled. All of the previously mentioned buffers are incompatible with the LTC4310-2 because the compensation networks of these buffers cause the bus to rise more slowly than (0.35 • VCC)/300ns, therefore the LTC4310-2 would not be able to control the bus rise rate. LTC4310-1 Compatibility with LTC4310-2 In a typical application such as shown in Figure 1, an LTC4310-1 can be used on one bus and an LTC4310-2 can be used on the other, provided that the bus pull-up resistors connected to the LTC4310-1 meet the requirements of Figure 2, and the bus pull-up resistors connected to the LTC4310-2 meet the requirements of Figure 3. However, the bus switching frequency is limited by the rise rate regulation circuitry of the LTC4310-1. In addition, significant skew is introduced on the rising edges due to the large difference in the controlled rise rates of the two buses. For this reason, it is recommended to use two LTC4310-1’s in SMBus and standard mode I2C applications and to use two LTC4310-2’s in fast mode I2C applications. The LTC4310-1 cannot be used on the same physical I2C bus with the LTC4310-2, because the LTC4310-1’s rise rate regulation circuitry controls the bus rise rate to (0.35 • VCC)/900ns, therefore the LTC4310-2 would not be able to control the bus rise rate. Using the LTC4310-1 at Frequencies Above 100kHz Users who implement custom two-wire buses may use the LTC4310-1 at bus frequencies above 100kHz provided that all other devices on the bus can tolerate the approximately 1µs bus rise times resulting from the LTC4310-1’s bus rise rate regulation circuitry. 431012f  LTC4310-1/LTC4310-2 Typical applicaTions Transformer Selection Guide As shown in Figure 1, a transformer passes transmit and receive signals between the two LTC4310’s. The transmit signals have 1.25V magnitude and 35ns pulse width. The receive circuitry has an equivalent input impedance of 16.5kΩ and can receive differential signals ranging from 0.875V to 1.55V. To meet these requirements, choose a transformer having a magnetizing inductance ranging from 50µH to 350µH, a 1:1 turns ratio and a maximum insertion loss of –1.5dB. For optimal common mode noise rejection, choose a center-tapped transformer and connect the center tap on the receiving side to local ground using a 0.01µF capacitor. Ringing at the LTC4310’s RXP and RXN pins can effectively be damped by inserting 50Ω series resistors between each LTC4310’s TXP and TXN pins and the corresponding transformer primary windings. Table 1 shows a recommended list of transformers for use with the LTC4310. 10/100BaseTX Ethernet transformers Table 1. LTC4310 Recommended Transformers MANUFACTURER PCA Electronics Pulse Würth Electronics Midcom PART NUMBER EPF8119S EPF8119SE E5017 000-7090-37R-LF1 749014012 ISOLATION VOLTAGE 1500VRMS 1500VRMS 1500VRMS 1500VRMS 4000VRMS FORM FACTOR (mm) x 10.41 10.2 9.4 9.4 17 y 12.45 12.7 12.7 12.95 24.55 z 5.84 5.96 5.08 5.33 10.85 TURNS RATIO 1:1 1:1 1:1 1:1 1:1 CENTER TAP Yes Yes Yes Yes Yes OPERATING TEMPERATURE 0°C TO 70°C –40°C TO 85°C 0°C TO 70°C –40°C TO 85°C 0°C TO 70°C are inexpensive and work very well in this application for isolation voltages up to 1500V. For applications requiring 4000V isolation, the Würth Electronics Midcom 749014012 transformer is recommended. RF Radiated Emissions The LTC4310 evaluation board passes CISPR22 Class B requirements for radiated emissions. The results of CISPR22 testing are shown in the evaluation board manual. To reduce radiated emission levels further, enclose the LTC4310 application circuit in a shielded enclosure. Common Mode Transient Immunity The LTC4310 has high immunity to common mode transients. This is tested by applying a square voltage pulse having very fast edges between the isolated grounds. The LTC4310 passes 20kV/us edges without corruption of the I2C bus logic states. 431012f  LTC4310-1/LTC4310-2 package DescripTion DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) R = 0.115 TYP 6 0.675 ±0.05 0.38 ± 0.10 10 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 PIN 1 TOP MARK (SEE NOTE 6) 3.00 ±0.10 (4 SIDES) 1.65 ± 0.10 (2 SIDES) 5 0.50 BSC 2.38 ±0.05 (2 SIDES) 0.200 REF 0.75 ±0.05 2.38 ±0.10 (2 SIDES) 1 (DD) DFN 1103 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 431012f  LTC4310-1/LTC4310-2 package DescripTion (Reference LTC DWG # 05-08-1661 Rev E) MS Package 10-Lead Plastic MSOP 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 10 9 8 7 6 0.497 ± 0.076 (.0196 ± .003) REF 0.254 (.010) GAUGE PLANE DETAIL “A” 0° – 6° TYP 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 12345 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.86 (.034) REF 0.50 (.0197) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) TYP 0.1016 ± 0.0508 (.004 ± .002) MSOP (MS) 0307 REV E 431012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LTC4310-1/LTC4310-2 Typical applicaTion Breaking Ground Loops Using Capacitors 3.3V 5V C6 0.01µF R1 5.1k R2 5.1k R3 10k C1 C7 0.01µF R4 10k R5 10k R6 10k TXP LTC4310-1 CBUS = 100pF SDA SCL READY EN GND TXN C3 RXP RXN C5 VCC C2 RXP LTC4310-1 RXN TXP TXN GND SDA SCL READY EN CBUS = 20pF VCC C4 431012 TA02 C1 TO C5 = 47pF 100V , relaTeD parTs PART NUMBER LTC4300A-3 LTC4301 LTC4302-1/LTC4302-2 LTC4303/LTC4304 LTC4305/LTC4306 LTC4307 LTC4307-1 LTC4308 Supply Independent Hot-Swappable 2-Wire Bus Buffer Addressable 2-Wire Bus Buffer Hot-Swappable 2-Wire Bus Buffer with Stuck Bus Recovery 2- or 4-Channel, 2-Wire Bus Multiplexers with Capacitance Buffering Low Offset Hot-Swappable 2-Wire Bus Buffer with Stuck Bus Recovery High Definition Multimedia Interface (HDMI) Level Shifting Low Voltage Level Shifting Hot-Swappable 2-Wire Bus Buffer with Stuck Bus Recovery Level Shifting Low Offset Hot-Swappable 2-Wire Bus Buffer with Stuck Bus Recovery I2C/SMBus Rise Time Accelerator DESCRIPTION COMMENTS LTC4300A–1: Bus Buffer with READY and ENABLE, LTC4300A–2: Dual Supply Bus Buffer with VCC2 and ACC, LTC4300A–3: Dual Supply Bus Buffer with VCC2 and ENABLE Supply Independent Address Expansion, GPIO, Software Controlled Provides Automatic Clocking to Free Stuck I2C Busses Two or Four Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance 60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators, ±5kV HBM ESD Tolerance 2-Wire Bus Buffer, 60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM ESD Tolerance –200mV Offset In-Out/+300mV Offset Out-In, 0.9V to 5.5V Level Shifting, 30ms Stuck Bus Disconnect and Recovery, Output Side Rise Time Accelerators, ±6kV HBM ESD Tolerance 60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators, 1.8V to 5V Level Shifting, ±5kV HBM ESD Tolerance Strong Slew Limited Current Source, Wide 1.6V to 5.5V Supply Range, Auto Detect Low Power Standby, Low