LTC4355IDE-TRPBF

SPELL CHECK COMPLETED FeaTures ■ ■ ■ ■ ■ ■ ■ ■ LTC4355 Positive High Voltage Ideal Diode-OR with Input Supply and Fuse Monitors DescripTion The LTC®4355 is a positive voltage ideal diode-OR controller that drives two external N-channel MOSFETs. Forming the diode-OR with N-channel MOSFETs instead of Schottky diodes reduces power consumption, heat dissipation and PC board area. With the LTC4355, power sources can easily be ORed together to increase total system reliability. The LTC4355 can diode-OR two positive supplies or the return paths of two negative supplies, such as in a –48V system. In the forward direction the LTC4355 controls the voltage drop across the MOSFET to ensure smooth current transfer from one path to the other without oscillation. If a power source fails or is shorted, fast turnoff minimizes reverse current transients. Power fault detection indicates if the input supplies are not in regulation, the inline fuses are blown, or the voltages across the MOSFETs are greater than the fault threshold. Replaces Power Schottky Diodes Controls N-Channel MOSFETs 0.5µs Turn-Off Time Limits Peak Fault Current Wide Operating Voltage Range: 9V to 80V Smooth Switchover without Oscillation No Reverse DC Current Monitors VIN, Fuse, and MOSFET Diode Available in 14-Lead (4mm × 3mm) DFN and 16-Lead SO Packages applicaTions ■ ■ ■ ■ High Availability Systems AdvancedTCA® (ATCA) Systems +48V and –48V Distributed Power Systems Telecom Infrastructure , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion +48V Diode-OR VIN1 = +48V VIN2 = +48V 340k 7A 7A FDB3632 TO LOAD FDB3632 POWER DISSIPATION (W) 22k 340k IN1 MON1 SET MON2 12.7k GND 12.7k LTC4355 GND GATE1 IN2 GATE2 OUT VDSFLT FUSEFLT1 FUSEFLT2 PWRFLT1 PWRFLT2 22k 22k 22k 22k 6 5 DIODE (MBR10100) 4 3 2 1 FET (FDB3632) GREEN LEDs PANASONIC LN1351C 4355 TA01 Power Dissipation vs Load Current POWER SAVED 0 0 2 4 6 CURRENT (A) 8 10 4355 TA02 4355fa  LTC4355 absoluTe MaxiMuM raTings (Notes 1, 2) Supply Voltages IN1, IN2 ............................................... –0.3V to 100V OUT ..................................................... –0.3V to 100V Input Voltages MON1, MON2, SET .................................. –0.3V to 7V Output Voltages GATE1 (Note 3) ................... VIN1 – 0.2V to VIN1 + 13V GATE2 (Note 3) ................... VIN2 – 0.2V to VIN2 + 13V PWRFLT1, PWRFLT2, VDSFLT, FUSEFLT1, FUSEFLT2 ............................... –0.3V to 8V Operating Temperature Range LTC4355C ................................................ 0°C to 70°C LTC4355I ............................................. –40°C to 85°C Storage Temperature Range DFN Package...................................... –65°C to 125°C SO Package........................................ –65°C to 150°C Lead Temperature (Soldering, 10 sec) SO Package....................................................... 300°C pin conFiguraTion TOP VIEW IN1 GATE1 OUT GATE2 IN2 VDSFLT GND 1 2 3 4 5 6 7 15 14 MON1 13 PWRFLT1 12 FUSEFLT1 11 FUSEFLT2 10 PWRFLT2 9 MON2 8 SET IN1 1 GATE1 2 NC 3 OUT 4 NC 5 GATE2 6 IN2 7 NC 8 TOP VIEW 16 MON1 15 PWRFLT1 14 FUSEFLT1 13 FUSEFLT2 12 PWRFLT2 11 MON2 10 SET 9 GND DE14 PACKAGE 14-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 15) PCB GND CONNECTION OPTIONAL S PACKAGE 16-LEAD PLASTIC SO TJMAX = 125°C, θJA = 75°C/W orDer inForMaTion LEAD FREE FINISH LTC4355CDE#PBF LTC4355IDE#PBF LTC4355CS#PBF LTC4355IS#PBF TAPE AND REEL LTC4355CDE#TRPBF LTC4355IDE#TRPBF LTC4355CS#TRPBF LTC4355IS#TRPBF PART MARKING* 4355 4355 LTC4355CS LTC4355IS PACKAGE DESCRIPTION 14-Lead (4mm × 3mm) Plastic DFN 14-Lead (4mm × 3mm) Plastic DFN 16-Lead Plastic SO 16-Lead Plastic SO TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4355fa  LTC4355 elecTrical characTerisTics SYMBOL VOUT IOUT IINx DVGATEx IGATEx(UP) IGATEx(DN) tOFF VMONx(TH) VMONx(HYST) IMONx(IN) VINx(TH) VINx(HYST) DVSD DVSD(FLT) PARAMETER Operating Supply Range Supply Current INx Pin Input Current External N-Channel Gate Drive (VGATEx – VINx) External N-Channel Gate Pull-Up Current External N-Channel Gate Pulldown in Fault Condition Gate Turn-Off Time MONx Pin Threshold Voltage MONx Pin Hysteresis Voltage MONx Pin Input Current INx Pin Threshold Voltage INx Pin Hysteresis Voltage Source-Drain Regulation Voltage (VINx – VOUT ) Short-Circuit Fault Voltage (VINx – VOUT) Rising VGATEx – VINx = 2.5V SET = 0V SET = 100kW SET = Hi-Z IPWRFLTx, IFUSEFLTx, IVDSFLT = 5mA VPWRFLTx, VFUSEFLTx, VVDSFLT = 5V VMONx = 1.23V VINx Rising GATE High VOUT = 20V to 80V VOUT = 9V to 20V VGATE = VINx , VINx – VOUT = 100mV Gate Drive Off, VGATEx = VINx +5V – VINx – VOUT = 55mV |––1V VGATEx – VINx < 1V The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 9V < VOUT < 80V, unless otherwise noted. CONDITIONS ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN 9 TYP 2 MAX 80 3 1.2 18 18 –26 UNITS V mA mA V V µA A 0.5 10 4.5 –14 1 0.6 14 6 –20 2 0.3 0.4 1.245 45 ±1 4 150 55 0.3 0.6 1.6 200 ±1 5 150 µs V mV µA V mV mV V V V mV mV µA kW kW MW VMONx Rising 1.209 10 3 25 10 0.2 0.4 1.3 1.227 30 0 3.5 75 25 0.25 0.5 1.5 30 100 0 DVSD(FLT)(HYST) Short-Circuit Fault Hysteresis Voltage V`F`L`T I`F`L`T RSET(L) RSET(M) RSET(H) PWRFLTx, FUSEFLTx, VDSFLT Pins Output Low PWRFLTx, FUSEFLTx, VDSFLT Pins Leakage Current SET Resistance Range for DVSD(FLT) = 0.25V SET Resistance Range for DVSD(FLT) = 0.5V SET Resistance Range for DVSD(FLT) = 1.5V ● ● ● ● ● 0 50 1 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: The GATEx pins are internally limited to a minimum of 13V above INx. Driving these pins beyond the clamp may damage the part. 4355fa  LTC4355 Typical perForMance characTerisTics IOUT vs VOUT 2.0 VOUT = VIN 1.0 IIN vs VIN VIN = VOUT 20 IGATE vs DVSD VGATE = 2.5V 1.5 IOUT (mA) IIN (mA) 0.75 IGATE (µA) 0 40 VIN (V) 4355 G01 4355 G02 0 1.0 0.5 –20 0.5 0.25 –40 0 0 20 40 VOUT (V) 60 80 0 20 60 80 –60 –50 0 50 VSD (mV) 100 150 4355 G03 DVGATE vs IGATE 15 VIN > 18V 0.3 Fault Output Low vs Load Current 150 Fault Output Low vs Temperature IFLT = 5mA 125 10 DVGATE (V) VFLT (V) VFLT (V) 0.1 75 0 0 10 IFLT (mA) 4355 G04 4355 G05 VIN = 12V VIN = 9V 0.2 100 5 0 0 5 10 15 IGATE (µA) 20 25 5 15 50 –50 50 0 TEMPERATURE (°C) 100 4355 G06 FET Turn-Off Time vs GATE Capacitance 500 VGATE < VIN + 1V DVSD = 50mV –1V 500 FET Turn-Off Time vs Initial Overdrive VIN = 48V DVSD = VINITIAL –1V 2000 FET Turn-Off Time vs Final Overdrive VIN = 48V DVSD = 50mV VFINAL 400 400 1500 t PD (ns) t OFF (ns) t PD (ns) 300 300 1000 200 200 100 100 500 0 0 10 20 20 CGATE (nF) 40 50 4355 G07 0 0 0.2 0.6 0.4 VINITIAL (V) 0.8 1.0 4355 G08 0 –1.0 – 0.8 – 0.4 – 0.6 VFINAL (V) – 0.2 0 4355 G09 4355fa  LTC4355 pin FuncTions (DE/S Packages) EXPOSED PAD (Pin 15, DE Package Only): Exposed pad may be left open or connected to GND. FUSEFLTx (Pins 11,12/13,14): Fuse Fault Outputs. Open-drain output that pulls to GND when VINx < 3.5V, indicating that the fuse has blown open. Otherwise, this output is high-impedance. Connect to GND if unused. GATEx (Pins 2,4/2,6): Gate Drive Outputs. The GATE pins pull high, enhancing the N-channel MOSFET when the load current creates more than 25mV of voltage drop across the MOSFET. When the load current is small, the gates are actively driven to maintain 25mV across the MOSFET. If the reverse current develops more than –25mV of voltage drop across a MOSFET, a fast pulldown circuit quickly connects the GATE pin to the IN pin, turning off the MOSFET. Limit the capacitance between the GATE and IN pins to less than 0.1µF. GND (7/9): Device Ground. INx (Pins 1,5/1,7): Input Voltages and GATE Fast Pulldown Returns. The IN pins are the anodes of the ideal diodes and connect to the sources of the N-channel MOSFETs. The voltages sensed at these pins are used to control the source-drain voltages across the MOSFETs and are used by the fault detection circuits that drive the PWRFLT, FUSEFLT, and VDSFLT pins. The GATE fast pulldown current is returned through the IN pins. Connect these pins as close to the MOSFET sources as possible. Connect to OUT if unused. MONx (Pins 9,14/11,16): Input Supply Monitors. These pins are used to sense the input supply voltages. Connect these pins to external resistive dividers between the input supplies and GND. If VMONx falls below 1.23V, the PWRFLTx pin pulls to GND. Connect to GND if unused. OUT (Pin 3/4): Drain Voltage Sense and Positive Supply Input. OUT is the diode-OR output of IN1 and IN2. It connects to the common drain connection of the N-channel MOSFETs. The voltage sensed at this pin is used to control the source-drain voltages across the MOSFETs and is used by the fault detection circuits that drive the PWRFLT and VDSFLT pins. The LTC4355 is powered from the OUT pin. PWRFLTx (Pins 10,13/12,15): Power Fault Outputs. Open-drain output that pulls to GND when VMONx falls below 1.23V or the forward voltage across the MOSFET exceeds DVSD(FLT). When VMONx is above 1.23V and the forward voltage across the MOSFET is less than DVSD(FLT), PWRFLTx is high-impedance. Connect to GND if unused. SET (Pin 8/10): DVSD(FLT) Threshold Configuration Input. Tying SET to GND, to a 100kW resistor connected to GND, or leaving SET open configures the DVSD(FLT) forward voltage fault threshold to 250mV, 500mV, or 1.5V respectively. When the voltage across a MOSFET exceeds DVSD(FLT), the VSDFLT pin and at least one of the PWRFLT pins pull to GND. VDSFLT (Pin 6, DE Package Only): MOSFET Fault Output. Open-drain output that pulls to GND when the forward voltage across either MOSFET exceeds DVSD(FLT). PWRFLT1 or PWRFLT2 also pulls low to indicate which MOSFET’s forward voltage drop exceeds DVSD(FLT). Otherwise, this pin is high-impedance. Connect to GND if unused. 4355fa  LTC4355 block DiagraM IN1 GATE1 OUT GATE2 IN2 GATE1 AMP GATE2 AMP + – – + – + DVSD1(FLT) FAULT 25mV DVSD(FLT) 25mV DVSD(FLT) – + – – + – DVSD(FLT) = 0.25V, 0.5V OR 1.5V + DVSD2(FLT) FAULT VDSFLT FUSEFLT1 – FUSE1 FAULT – + – + – + FUSE2 FAULT + + + – 3.5V 3.5V FUSEFLT2 PWRFLT1 PWRFLT2 MON1 MON2 + + – + + – SET – MON1 – 1.23V 1.23V MON2 4355 BD GND 4355fa  LTC4355 operaTion High availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. ORing diodes have been a popular means of connecting these supplies at the point of load. The disadvantage of this approach is the forward voltage drop and resulting efficiency loss. This drop reduces the available supply voltage and dissipates significant power. Using N-channel MOSFETs to replace Schottky diodes reduces the power dissipation and eliminates the need for costly heat sinks or large thermal layouts in high power applications. The LTC4355 is a positive voltage diode-OR controller that drives two external N-channel MOSFETs as pass transistors to replace ORing diodes. The IN and OUT pins form the anodes and cathodes of the ideal diodes. The source pins of the external MOSFETs are connected to the IN pins. The drains of the MOSFETs are connected together at the OUT pin, which is the positive supply of the device. The gates of the external MOSFETs are driven by the LTC4355 to regulate the voltage drop across the pass transistors. At power-up, the initial load current flows through the body diode of the MOSFET with the higher INx voltage. The associated GATEx pin immediately ramps up and turns on the MOSFET. The amplifier tries to regulate the voltage drop across the source and drain connections to 25mV. If the load current causes more than 25mV of drop, the MOSFET gate is driven fully on and the voltage drop is equal to RDS(ON) • ILOAD. When the power supply voltages are nearly equal, this regulation technique ensures that the load current is smoothly shared between the MOSFETs without oscillation. The current flowing through each pass transistor depends on the RDS(ON) of each MOSFET and the output impedances of the supplies. In the event of a supply failure, such as if the supply that is conducting most or all of the current is shorted to GND, reverse current flows temporarily through the MOSFET that is on. This current is sourced from any load capacitance and from the second supply through the body diode of the other MOSFET. The LTC4355 quickly responds to this condition, turning off the MOSFET in about 500ns. This fast turn-off prevents the reverse current from ramping up to a damaging level. In the case where the forward voltage drop exceeds the configurable fault threshold, DVSD(FLT), the VDSFLT pin pulls low. Using this pin to shunt current away from an LED or optocoupler provides an indication that a pass transistor has either failed or has excessive forward current. Additionally, in this condition the PWRFLT1 or PWRFLT2 pin pulls low to identify the faulting channel. The PWRFLT pins also indicate if an input supply is within regulation. When VMON1 < 1.23V or VMON2 < 1.23V, the corresponding PWRFLT pin pulls low to indicate that the input supply is low, turning off an optional LED or optocoupler. The FUSEFLT pins indicate the status of input fuses. If the voltage at one of the IN pins is less than 3.5V, the corresponding FUSEFLT pin pulls low. The IN pins sink a minimum of 0.5mA to guarantee that the IN pin will pull low when the input fuse is blown open. Note that the FUSEFLT pin will activate if the input supply is less than 3.5V even if the fuse is intact. 4355fa  LTC4355 applicaTions inForMaTion MOSFET Selection The LTC4355 drives N-channel MOSFETs to conduct the load current. The important features of the MOSFETs are on-resistance RDS(ON), the maximum drain-source voltage VDSS, and the threshold voltage. The gate drive for the MOSFET is guaranteed to be greater than 4.5V when the supply voltage at VOUT is between 9V and 20V. When the supply voltage at VOUT is greater than 20V, the gate drive is guaranteed to be greater than 10V. The gate drive is limited to less than 18V. This allows the use of logic level threshold N-channel MOSFETs and standard N-channel MOSFETs above 20V. An external zener diode can be used to clamp the potential from the MOSFET’s gate to source if the rated breakdown voltage is less than 18V. See the circuit in Figure 4 for an example. The maximum allowable drain-source voltage, BVDSS, must be higher than the supply voltages. If an input is connected to GND, the full supply voltage will appear across the MOSFET. If the voltage drop across either MOSFET exceeds the configurable DVSD(FLT) fault threshold, the VDSFLT pin and the PWRFLT pin corresponding to the f aulting channel pull low. The RDS(ON) s hould be small enough to conduct the maximum load current while not triggering a fault, and to stay within the MOSFET’s power rating at the maximum load current (I2 • RDS(ON)). Fault Conditions The LTC4355 monitors fault conditions and shunts current away from LEDs or optocouplers, turning each one off to indicate a specific fault condition (see Table 1). When the voltage drop across the pass transistor is higher than the configurable DVSD(FLT) fault threshold, the internal pulldown at the VDSFLT pin and the PWRFLT1 or PWRFLT2 pin corresponding to the faulting channel turns on. The DVSD(FLT) threshold is configured by the SET pin. Tying SET to GND, tying SET to a 100kW resistor connected to GND, or floating SET configures DVSD(FLT) to 250mV, 500mV, or 1.5V respectively. Fault conditions that may cause a high voltage across the pass transistor include: a MOSFET open on the higher supply, excessive MOSFET current due to overcurrent on the load or a shorted MOSFET on the lower supply. During startup or when a switchover between supplies occurs, the VDSFLT pin and PWRFLT1 or PWRFLT2 pin may momentarily indicate that the forward voltage has exceeded the programmed threshold during the short interval when the MOSFET gate ramps up and the body diode conducts. The PWRFLT pins are additionally used to indicate if either input supply is below its normal regulation range. If the voltage at the MON1 or MON2 pin is less than VMON(TH), typically 1.23V, the corresponding PWRFLT1 or PWRFLT2 pin will pull low. A resistive divider connected to the input supply drives the MON pin for the corresponding supply, configuring the PWRFLT threshold for that supply. Be sure to account for the tolerance of the MON pin threshold, the resistor tolerances, and the regulation range of the supply being monitored. Also, ensure that the voltage on the MON pin will not exceed 7V. The FUSEFLT pins are used to indicate the status of the input fuses. If one of the IN pins falls below VINx(TH), typically 3.5V, the FUSEFLT pin corresponding to that supply will pull low. The IN pins each sink a minimum of 0.5mA, Table 1. Fault Table DVSD1 < DVSD(FLT) True True True True False False False False VIN1 > 3.5V True True False False True True False False VMON1 > 1.23V True False True False True False True False VDSFLT* Hi-Z Hi-Z Hi-Z Hi-Z Pulldown Pulldown Pulldown Pulldown FUSEFLT1 PWRFLT1 Hi-Z Hi-Z Pulldown Pulldown Hi-Z Hi-Z Pulldown Pulldown Hi-Z Pulldown Hi-Z Pulldown Pulldown Pulldown Pulldown Pulldown *DVSD2 < DVSD(FLT) enough to pull the pin low after an input fuse blows open. If there is a possibility that the MOSFET leakage current can be greater than 0.5mA, a resistor can be connected between the IN pin and GND to sink more current. Note that if the input supply voltage is less than VINx(TH) the FUSEFLT pin will pull low. 4355fa  LTC4355 applicaTions inForMaTion System Power Supply Failure The LTC4355 automatically supplies load current from the system input supply with the higher voltage. If this supply shorts to ground, reverse current begins to flow through the pass transistor temporarily and the transistor begins to turn off. When this reverse current creates –25mV of voltage drop across the drain and source pins of the pass transistor, a fast pulldown circuit engages to drive the gate low faster. The remaining system power supply delivers the load current through the body diode of its pass transistor until the channel turns on. The LTC4355 ramps the gate up with 20µA, turning on the N-channel MOSFET to reduce the voltage drop across it. When the capacitances at the inputs and output are very small, large changes in current can cause inductive transients that exceed the 100V Absolute Maximum Ratings of the pins. A surge suppressor (TransZorb) at the output will minimize this ringing. Loop Stability The servo loop is compensated by the parasitic capacitance of the power N-channel MOSFET. No further compensation components are normally required. In the case when a MOSFET with less than 1000pF gate capacitance is chosen, a 1000pF compensation capacitor connected across the gate and source pins might be required. Design Example The following design example demonstrates the calculations involved for selecting components in a 36V to 72V system with 5A maximum load current (see Figure 1). First, choose the N-channel MOSFET. The 100V, FDS3672 in the SO-8 package with RDS(ON) = 22mW(max) offers a good solution. The maximum voltage drop across it is: DV = 5A • 22mW = 110mV The maximum power dissipation in the MOSFET is a mere: P = 5A • 110mV = 0.55W Next, select the resistive dividers that guarantee the PWRFLT pins willl not assert when the input supplies are above 36V. The maximum VMONx(TH) is 1.245V and the maximum IMONx(IN) is 1µA. Choose a 1% tolerance resistor R1 = 12.7kW. Then, IR2 = + IMONx (TH)(MAX ) R1(MIN) 1 . 245V = + 1µ A = 100µ A 1 2 . 7kW (− 1 %) VMONx(TH) Use IR2 to choose R2. R2 = 36 V − 1 . 245V = 348kW 100µ A VIN1 = +48V VIN2 = +48V R2 340k F1 7A F2 7A R4 340k M1 FDS3672 M2 FDS3672 R5 33k IN1 MON1 SET MON2 LTC4355 GND GATE1 IN2 GATE2 OUT VDSFLT FUSEFLT1 FUSEFLT2 PWRFLT1 PWRFLT2 GREEN LEDs PANASONIC LN1351C D1 D2 R6 33k R7 33k R8 33k R9 33k TO LOAD R1 12.7k GND R3 12.7k D3 D4 4355 F01 D5 Figure 1. 36V to 72V/5A Design Example 4355fa  LTC4355 applicaTions inForMaTion Adjust R2 down by 1% to 344kW to account for its tolerance. The next lower standard resistor value is R2 = 340kW. The LED D1, a Panasonic Green LN1351C, requires at least 1mA of current to fully turn on. Therefore, R5 is set to 33kW to accommodate the lowest input supply voltage of 36V. Layout Considerations The following advice should be considered when laying out a printed circuit board for the LTC4355. The inputs to the servo amplifiers, IN1, IN2, and OUT should be connected as closely as possible to the MOSFETs’ terminals for good accuracy. Keep the traces to the MOSFETs wide and short. The PCB traces associated with the power path through the MOSFETs should have low resistance (see Figure 2). For the DFN package, pin spacing may be a concern at voltages greater then 30V. Check creepage and clearance guidelines to determine if this is an issue. Use no-clean solder to minimize PCB contamination. S S S G FET D D D D D D D D FET G S S S Figure 2. Layout Considerations 4355 F02 IN2 GATE2 LTC4355 OUT GATE1 IN1 4355fa 0 LTC4355 applicaTions inForMaTion RTNA RTNB 340k 10A 10A IRF3710 IRF3710 33k 33k 33k 33k 33k 340k IN1 MON1 SET MON2 GATE1 IN2 GATE2 OUT VDSFLT FUSEFLT1 FUSEFLT2 PWRFLT1 PWRFLT2 LTC4355 GND 12.7k 12.7k GREEN LEDs PANASONIC LN1351C LOAD 12k 33k VCC LTC4354 DA 2k DB 2k IRF3710 IRF3710 4355 F03 FAULT GB VSS 1µF RED LED PANASONIC LN1251CLA GA VA = –48V VB = –48V 15A 15A Figure 3. –36V to –72V/10A with Positive Supply and Negative Supply Diode-ORing 4355fa  LTC4355 applicaTions inForMaTion VA = 48V 10A IRLR3110ZPbF 12V ZENER CM4Z669-LTC VB = 48V 10A IRLR3110ZPbF 33k 12V ZENER CM4Z669-LTC 340k 340k IN1 MON1 SET MON2 GATE1 IN2 LTC4355 GND GATE2 OUT VDSFLT FUSEFLT1 FUSEFLT2 PWRFLT1 PWRFLT2 12.7k 12.7k GREEN LEDs PANASONIC LN1351C LOAD 12k VCC LTC4354 FAULT GB VSS 1µF DA 2k DB 2k GA GNDA GNDB 15A 15A IRLR3110ZPbF IRLR3110ZPbF 4355 F04 Figure 4. 36V to 72V/10A with Positive Supply and Negative Supply Diode-ORing, Combined Fault Outputs, and Zener Clamps on MOSFET Gates 4355fa  LTC4355 Typical applicaTions Single 12V/15A Ideal Diode with Parallel Drivers F1 15A M1 HAT2165H VIN = 12V TO LOAD R3 10k R4 10k R5 10k R1 86.6k IN1 MON1 SET R2 12.7k MON2 LTC4355 GND IN2 GATE1 GATE2 OUT VDSFLT FUSEFLT1 PWRFLT1 FUSEFLT2 PWRFLT2 D1 D2 GREEN LEDs D3 PANASONIC LN1351C GND 4355 TA03 Single 36V to 72V/30A Ideal Diode Using Parallel MOSFETs F1 30A VIN = +48V M1 IRFS4710 M2 IRFS4710 TO LOAD R3 33k R5 33k R4 33k R1 340k IN1 MON1 SET R2 12.7k MON2 LTC4355 GND IN2 GATE1 GATE2 OUT VDSFLT FUSEFLT1 PWRFLT1 FUSEFLT2 PWRFLT2 D1 D2 GND 4355 TA04 D3 GREEN LEDs PANASONIC LN1351C 4355fa  LTC4355 Typical applicaTions AdvancedTCA with High-Side and Low-Side Ideal Diode-OR and Hot Swap Controller with I2C Current and Voltage Monitor LONG VRTN_A LONG VRTN_B 10A VDA– 10A VDA – FDS3672 91Ω 22nF 100V –48VRTN(OUT) FDS3672 SMBT70A IN1 GATE1 IN2 GATE2 OUT MON1 SET MON2 D ENABLE_B SHORT 100k D FMMT5401 D 100k FMMT5401 D 100k LTC4355CS GND 1.1k 1.1k 1.1k 1.1k ENABLE_A SHORT 1M 100k 1M 1 µF 10k 137k 107k VCC LTC4354CS8 DA DB GA 2k 2k MEDIUM LONG –48V_A 7A FDS3672 GB VSS VSS 100nF HZS5C1 100nF 100k 100nF 10.2k 2.49k 1µF UVH UVL ADIN2 OV ON INTVCC FLTIN EN ADR1 ADR0 SS 100nF 330nF VIN LTC4261CGN PG SCL SDAI SDAO ALERT PGIO PGI ADIN GATE DRAIN RAMP 33nF TMR VEE SENSE 330nF 47nF 10Ω 1M 1k 10nF 100V MEDIUM SHORT –48V_B 7A FDS3672 D: 1N4148WS 8mΩ IRF1310NS –48VOUT 4355 TA05 4355fa  LTC4355 package DescripTion DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev A) R = 0.115 TYP 0.40 ± 0.10 14 4.00 ± 0.10 (2 SIDES) 0.70 ± 0.05 3.60 ± 0.05 2.20 ± 0.05 3.30 ± 0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.00 – 0.05 PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF R = 0.05 TYP 3.00 ± 0.10 (2 SIDES) 8 3.30 ± 0.10 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 1 0.25 ± 0.05 0.50 BSC 3.00 REF BOTTOM VIEW—EXPOSED PAD (DE14) DFN 0806 REV B 7 0.75 ± 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .045 ±.005 16 15 14 .386 – .394 (9.804 – 10.008) NOTE 3 13 12 11 10 9 .050 BSC N .245 MIN N .160 ±.005 .228 – .244 (5.791 – 6.197) 1 2 3 N/2 N/2 .150 – .157 (3.810 – 3.988) NOTE 3 .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) 1 .053 – .069 (1.346 – 1.752) 2 3 4 5 6 7 8 .008 – .010 (0.203 – 0.254) 0° – 8° TYP .004 – .010 (0.101 – 0.254) .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC S16 0502 INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4355fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.  LTC4355 Typical applicaTion 200W AdvancedTCA Ideal Diode-OR RTNA 10A 10A FDS3672 RTNB FDS3672 IN1 GATE1 IN2 GATE2 OUT LTC4355 GND LOAD 12k VCC LTC4354 DA 2k DB 2k FDS3672 FDS3672 4355 TA06 1µF GB VSS GA VA = –48V VB = –48V 7A 7A relaTeD parTs PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1921 LT4250 LTC4251/LTC4251-1/ LTC4251-2 LTC4252-1/LTC4252-2/ LTC4252-1A/LTC4252-2A LTC4253 LT4256 LTC4260 LTC4261 LTC4350 LT4351 LTC4354 DESCRIPTION Negative High Voltage Hot Swap™ Controllers in SO-8 Positive High Voltage Hot Swap Controllers Dual –48V Supply and Fuse Monitor –48V Hot Swap Controller –48V Hot Swap Controllers in SOT-23 –48V Hot Swap Controllers in MS8/MS10 –48V Hot Swap Controller with Sequencer Positive 48V Hot Swap Controller with Open-Circuit Detect Positive High Voltage Hot Swap Controller Negative High Voltage Hot Swap Controller Hot Swappable Load Share Controller MOSFET Diode-OR Controller Negative Voltage Diode-OR Controller and Monitor COMMENTS Negative High Voltage Supplies From –10V to –80V Active Current Limiting, Supplies From 9V to 80V UV/OV Monitor, –10V to –80V Operation, MSOP Package Active Current Limiting, Supplies From –20V to –80V Fast Active Current Limiting, Supplies From –15V Fast Active Current Limiting, Supplies From –15V, Drain Accelerated Response Fast Active Current Limiting, Supplies From –15V, Drain Accelerated Response, Sequenced Power Good Outputs Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to 80V Supply With I2C and ADC, Supplies from 8.5V to 80V With I2C and 10-Bit ADC, Adjustable Inrush and Overcurrent Limits Output Voltage: 1.2V to 20V, Equal Load Sharing External N-Channel MOSFETs Replace ORing Diodes, 1.2V to 20V Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation Hot Swap is a trademark of Linear Technology Corporation. 4355fa  Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0907 REV A • PRINTED IN USA www.linear.com  LINEAR TECHNOLOGY CORPORATION 2007