LTC4357IMS8-TRPBF

LTC4357 Positive High Voltage Ideal Diode Controller FEATURES n n n n n n DESCRIPTION The LTC®4357 is a positive high voltage ideal diode controller that drives an external N-channel MOSFET to replace a Schottky diode. When used in diode-OR and high current diode applications, the LTC4357 reduces power consumption, heat dissipation, voltage loss and PC board area. The LTC4357 easily ORs power sources to increase total system reliability. In diode-OR applications, the LTC4357 controls the forward voltage drop across the MOSFET to ensure smooth current transfer from one path to the other without oscillation. If the power source fails or is shorted, a fast turn-off minimizes reverse current transients. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Reduces Power Dissipation by Replacing a Power Schottky Diode with an N-Channel MOSFET 0.5μs Turn-Off Time Limits Peak Fault Current Wide Operating Voltage Range: 9V to 80V Smooth Switchover without Oscillation No Reverse DC Current Available in 6-Lead (2mm × 3mm) DFN and 8-Lead MSOP Packages APPLICATIONS n n n n n N + 1 Redundant Power Supplies High Availability Systems AdvancedTCA Systems Telecom Infrastructure Automotive Systems TYPICAL APPLICATION 48V, 10A Diode-OR VINA 48V FDB3632 Power Dissipation vs Load Current 6 5 POWER DISSIPATION (W) DIODE (MBR10100) 4 3 2 1 FET (FDB3632) 0 0 2 4 6 CURRENT (A) 8 10 4357 TA01b IN GATE LTC4357 GND OUT VDD VOUT TO LOAD POWER SAVED VINB 48V FDB3632 IN GATE LTC4357 GND OUT VDD 4357 TA01 4357fb 1 LTC4357 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages IN, OUT, VDD ........................................ –0.3V to 100V Output Voltage GATE (Note 3) ........................ VIN – 0.2V to VIN + 10V Operating Ambient Temperature Range LTC4357C ................................................ 0°C to 70°C LTC4357I.............................................. –40°C to 85°C Storage Temperature Range DCB Package ..................................... –65°C to 150°C MS Package ....................................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package ...................................................... 300°C PIN CONFIGURATION TOP VIEW OUT 1 IN 2 GATE 3 7 6 VDD 5 NC 4 GND TOP VIEW IN NC NC GATE 1 2 3 4 8 7 6 5 OUT VDD NC GND DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 90°C/W EXPOSED PAD (PIN 7) PCB GND CONNECTION OPTIONAL MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/W ORDER INFORMATION LEAD FREE FINISH LTC4357CDCB#TRMPBF LTC4357IDCB#TRMPBF LTC4357CMS8#PBF LTC4357IMS8#PBF TAPE AND REEL LTC4357CDCB#TRPBF LTC4357IDCB#TRPBF LTC4357CMS8#TRPBF LTC4357IMS8#TRPBF PART MARKING* LCXF LCXF LTCXD LTCXD PACKAGE DESCRIPTION 6-Lead (2mm × 3mm) Plastic DFN 6-Lead (2mm × 3mm) Plastic DFN 8-Lead Plastic MSOP 8-Lead Plastic MSOP TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = VDD, VDD = 9V to 80V unless otherwise noted. SYMBOL VDD IDD IIN IOUT ΔVGATE PARAMETER Operating Supply Range Supply Current IN Pin Current OUT Pin Current External N-Channel Gate Drive (VGATE – VIN) VIN = VOUT ±1V VIN = VOUT ±1V VDD, VOUT = 20V to 80V VDD, VOUT = 9V to 20V CONDITIONS l l l l l ELECTRICAL CHARACTERISTICS MIN 9 TYP 0.5 MAX 80 1 450 170 15 15 UNITS V mA μA μA V V 150 10 4.5 350 80 12 6 4357fb 2 LTC4357 ELECTRICAL CHARACTERISTICS SYMBOL IGATE(UP) IGATE(DOWN) tOFF ΔVSD PARAMETER External N-Channel Gate Pull Down Current in Fault Condition Gate Turn-Off Time Source-Drain Regulation Voltage (VIN – VOUT) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = VDD, VDD = 9V to 80V unless otherwise noted. CONDITIONS l l l l MIN –14 1 TYP –20 2 300 MAX –26 UNITS μA A External N-Channel Gate Pull Up Current VGATE = VIN, VIN – VOUT = 0.1V VGATE = VIN + 5V – VIN – VOUT = 55mV |––1V, VGATE – VIN < 1V 500 55 ns mV VGATE – VIN = 2.5V 10 25 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 10V above IN or 100V above GND. Driving this pin to voltages beyond this clamp may damage the device. 4357fb 3 LTC4357 TYPICAL PERFORMANCE CHARACTERISTICS VDD Current (IDD vs VDD) 800 VDD = VIN = VOUT 400 IN Current (IIN vs VIN) VDD = VIN = VOUT 120 OUT Current (IOUT vs VOUT) VDD = VIN = VOUT 600 IDD (μA) 300 IOUT (μA) 40 VIN (V) 4357 G01 4357 G02 90 400 IIN (μA) 200 60 200 100 30 0 0 20 40 VDD (V) 60 80 0 0 20 60 80 0 0 20 40 VOUT (V) 60 80 4357 G03 GATE Current vs Forward Drop (IGATE(UP) vs ΔVSD) 25 VGATE = 2.5V 15 GATE Voltage vs GATE Current (ΔVGATE vs IGATE) 500 VIN > 18V FET Turn-Off Time vs GATE Capacitance VGATE < VIN + 1V ΔVSD = 50mV –1V 400 300 tOFF (ns) 0 VGATE (V) IGATE (μA) 10 VIN = 12V VIN = 9V 5 200 –25 100 –50 –50 0 50 VSD (mV) 100 150 4357 G04 0 0 5 10 15 IGATE (μA) 20 25 4357 G06 0 0 10 20 30 40 50 CGATE (nF) 60 70 80 4357 G07 FET Turn-Off Time vs Initial Overdrive 400 2000 VIN = 48V ΔVSD = VINITIAL –1V 1500 FET Turn-Off Time vs Final Overdrive VIN = 48V ΔVSD = 55mV VFINAL 300 tPD (ns) 200 tPD (ns) 1000 100 500 0 0 0 0.2 0.6 0.4 VINITIAL (V) 0.8 1.0 4357 G08 –1 –0.8 –0.4 –0.6 VFINAL (V) –0.2 0 4357 G09 4357fb 4 LTC4357 PIN FUNCTIONS Exposed Pad: Exposed Pad may be left open or connected to GND. GATE: Gate Drive Output. The GATE pin pulls high, enhancing the N-channel MOSFET when the load current creates more than 25mV of voltage drop across the MOSFET. When the load current is small, the gate is actively driven to maintain 25mV across the MOSFET. If reverse current develops more than –25mV of voltage drop across the MOSFET, a fast pulldown circuit quickly connects the GATE pin to the IN pin, turning off the MOSFET. GND: Device Ground. IN: Input Voltage and GATE Fast Pull-Down Return. IN is the anode of the ideal diode and connects to the source of the N-channel MOSFET. The voltage sensed at this pin is used to control the source-drain voltage across the MOSFET. The GATE fast pulldown current is returned through the IN pin. Connect this pin as close as possible to the MOSFET source. NC: No Connection. Not internally connected. OUT: Drain Voltage Sense. OUT is the cathode of the ideal diode and the common output when multiple LTC4357s are configured as an ideal diode-OR. It connects to the drain of the N-channel MOSFET. The voltage sensed at this pin is used to control the source-drain voltage across the MOSFET. VDD: Positive Supply Input. The LTC4357 is powered from the VDD pin. Connect this pin to OUT either directly or through an RC hold-up circuit. BLOCK DIAGRAM IN GATE OUT CHARGE PUMP VDD FPD COMP GATE AMP 25mV + – + GND – + – + – 25mV IN 4357 BD 4357fb 5 LTC4357 OPERATION High availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. ORing diodes have been a popular means of connecting these supplies at the point of load. The disadvantage of this approach is the forward voltage drop and resulting efficiency loss. This drop reduces the available supply voltage and dissipates significant power. Using an N-channel MOSFET to replace a Schottky diode reduces the power dissipation and eliminates the need for costly heat sinks or large thermal layouts in high power applications. The LTC4357 controls an external N-channel MOSFET to form an ideal diode. The voltage across the source and drain is monitored by the IN and OUT pins, and the GATE pin drives the MOSFET to control its operation. In effect the MOSFET source and drain serve as the anode and cathode of an ideal diode. At power-up, the load current initially flows through the body diode of the MOSFET. The resulting high forward voltage is detected at the IN and OUT pins, and the LTC4357 drives the GATE pin to servo the forward drop to 25mV. If the load current causes more than 25mV of voltage drop when the MOSFET gate is driven fully on, the forward voltage is equal to RDS(ON) • ILOAD. If the load current is reduced causing the forward drop to fall below 25mV, the MOSFET gate is driven lower by a weak pull-down in an attempt to maintain the drop at 25mV. If the load current reverses and the voltage across IN to OUT is more negative than –25mV the LTC4357 responds by pulling the MOSFET gate low with a strong pull-down. In the event of a power supply failure, such as if the output of a fully loaded supply is suddenly shorted to ground, reverse current temporarily flows through the MOSFET that is on. This current is sourced from any load capacitance and from the other supplies. The LTC4357 quickly responds to this condition turning off the MOSFET in about 500ns, thus minimizing the disturbance to the output bus. 4357fb 6 LTC4357 APPLICATIONS INFORMATION MOSFET Selection The LTC4357 drives an N-channel MOSFET to conduct the load current. The important features of the MOSFET are on-resistance, RDS(ON), the maximum drain-source voltage, VDSS, and the gate threshold voltage. Gate drive is compatible with 4.5V logic-level MOSFETs in low voltage applications (VDD = 9V to 20V). At higher voltages (VDD = 20V to 80V) standard 10V threshold MOSFETs may be used. An internal clamp limits the gate drive to 15V between the GATE and IN pins. An external zener clamp may be added between GATE and IN for MOSFETs with a VGS(MAX) of less than 15V. The maximum allowable drain-source voltage, BVDSS, must be higher than the power supply voltage. If an input is connected to GND, the full supply voltage will appear across the MOSFET. ORing Two Supply Outputs Where LTC4357s are used to combine the outputs of two power supplies, the supply with the highest output voltage sources most or all of the load current. If this supply’s output is quickly shorted to ground while delivering load current, the flow of current temporarily reverses and flows backwards through the LTC4357’s MOSFET. When the reverse current produces a voltage drop across the MOSFET of more than –25mV, the LTC4357’s fast pull-down activates and quickly turns off the MOSFET. If the other, initially lower, supply was not delivering load current at the time of the fault, the output falls until the body diode of its ORing MOSFET conducts. Meanwhile, the LTC4357 charges its MOSFET gate with 20μA until the forward drop is reduced to 25mV. If instead this supply was delivering load current at the time of the fault, its associated ORing MOSFET was already driven at least partially on, and the LTC4357 will simply drive the MOSFET gate harder in an effort to maintain a drop of 25mV. When the capacitances at the input and output are very small, rapid changes in current can cause transients that exceed the 100V Absolute Maximum Rating of the IN, OUT, and VDD pins. A surge suppressor (TransZorb or TVS) connected from OUT to ground clamps the output and prevents VINA 48V PS1 IN RTNA LTC4357 GND VDD GATE OUT FDB3632 48V BUS damage by limiting the magnitude of the peak voltage. In the absence of a surge suppressor, an output capacitance of 10μF is sufficient in most applications to prevent the transient from exceeding 100V. In lower voltage applications, the MOSFET’s drain-source breakdown voltage may be sufficient to protect the LTC4357 provided BVDSS + VIN < 100V, making a surge suppressor unnecessary. Load Sharing The application in Figure 1 combines the outputs of multiple, redundant supplies using a simple technique known as droop sharing. Load current is first taken from the highest output, with the low outputs contributing as the output voltage falls under increased loading. The 25mV regulation technique ensures smooth load sharing between outputs without oscillation. The degree of sharing is a function of RDS(ON), the output impedance of the supplies and their initial output voltages. VINB 48V PS2 IN RTNA FDB3632 GATE LTC4357 GND OUT VDD VINC 48V PS3 RTNA IN FDB3632 GATE LTC4357 GND OUT VDD 4357 F01 Figure 1. Droop Sharing Redundant Supplies 4357fb 7 LTC4357 APPLICATIONS INFORMATION VDD Hold-Up Circuit In the event of an input short, parasitic inductance between the input supply of the LTC4357 and the load bypass capacitor may cause VDD to glitch below its minimum operating voltage. This causes the turn-off time (tOFF) to increase. To preserve the fast turn-off time, local output bypassing of 39μF is sufficient at voltages less than 30V. At higher voltages, 100μF is adequate. As an alternative to local bypassing, a 100Ω, 0.1μF RC hold-up circuit on the VDD pin can be used, shown in Figure 2. In applications with unusually large inductance or load current greater than 10A, use 100Ω and 1μF . Design Example The following design example demonstrates the calculations involved for selecting components in a 12V system with 10A maximum load current (see Figure 3). VIN 12V Si4874DY First, calculate the RDS(ON) of the MOSFET to achieve the desired forward drop at full load. Assuming VDROP = 0.1V, RDS(ON) VDROP I LOAD = 0.1V 10 A RDS(ON) 10m The Si4874DY offers a good solution, in an S8 package with RDS(ON) = 10mΩ(max) and BVDSS of 30V. The maximum power dissipation in the MOSFET is: P = ILOAD2 • RDS(ON) = (10A)2 • 10mΩ = 1W With less than 39μF of local bypass, the recommended RC values of 100Ω and 0.1μF were used in Figure 3. Since BVDSS + VIN is much less than 100V, output clamping is unnecessary. VIN1 12V Si4874DY VOUT TO LOAD 100Ω IN GATE LTC4357 GND OUT VDD IN CBYPASS 39μF GATE LTC4357 GND OUT VDD 0.1μF VIN 12V Si4874DY VIN2 12V R1 100Ω Si4874DY 100Ω IN GATE LTC4357 OUT VDD 0.1μF 4357 F03 IN GATE LTC4357 GND OUT VDD C1 0.1μF 4357 F02 GND Figure 2. Two Methods of Protecting Against Collapse of VDD From Input Short and Stray Inductance Figure 3. 12V, 10A Diode-OR 4357fb 8 LTC4357 APPLICATIONS INFORMATION Layout Considerations Connect the IN and OUT pins as close as possible to the MOSFET’s source and drain pins. Keep the traces to the MOSFET wide and short to minimize resistive losses. See Figure 4. For the DFN package, pin spacing may be a concern at voltages greater than 30V. Check creepage and clearance guidelines to determine if this is an issue. To increase the pin spacing between high voltage and ground pins, leave the exposed pad connection open. Use no-clean solder to minimize PCB contamination. 1S VIN 2S 3S 4G MOSFET D8 D7 D6 D5 VOUT VIN 1S 2S 3S 4G IN GATE D8 D7 D6 D5 VOUT IN LTC4357 GATE OUT OUT 2 7 5 1 3 4 6 4357 F04 Figure 4. Layout Considerations TYPICAL APPLICATIONS Solar Panel Charging a Battery FDB3632 100Ω 100W SOLAR PANEL 14V SHUNT REGULATOR 0.1μF IN VDD GATE LTC4357 GND 4357 TA02 OUT + 12V BATTERY LOAD 4357fb 9 LTC4357 TYPICAL APPLICATIONS –12V Reverse Input Protection Si4874DY CLOAD IN GATE LTC4357 GND MMBD1205 OUT VDD 4357 F03 VIN2 12V VOUT 12V 10A –48V Reverse Input Protection VOUT 48V 10A VIN2 48V FDB3672 CLOAD IN GATE LTC4357 GND OUT VDD SMAT70A 4357 F05 MMBD1205 4357fb 10 LTC4357 PACKAGE DESCRIPTION DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 2.00 0.10 (2 SIDES) 0.70 0.05 R = 0.115 TYP R = 0.05 TYP 0.40 4 6 0.10 3.55 0.05 1.65 0.05 (2 SIDES) PACKAGE OUTLINE PIN 1 BAR TOP MARK (SEE NOTE 6) 3.00 0.10 (2 SIDES) 1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 45 CHAMFER 3 1 0.25 0.50 BSC 1.35 0.10 (2 SIDES) (DCB6) DFN 0405 2.15 0.05 0.25 0.50 BSC 1.35 0.05 (2 SIDES) 0.05 0.200 REF 0.75 0.05 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 0.102 (.118 .004) (NOTE 3) 8 7 65 0.52 (.0205) REF 0.889 (.035 0.127 .005) 0.254 (.010) GAUGE PLANE DETAIL “A” 0 – 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) DETAIL “A” 1 0.53 0.152 (.021 .006) 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 1.10 (.043) MAX 23 4 0.86 (.034) REF 0.42 0.038 (.0165 .0015) TYP 0.65 (.0256) BSC RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.65 (.0256) BSC 0.1016 (.004 0.0508 .002) MSOP (MS8) 0307 REV F 4357fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC4357 TYPICAL APPLICATION Plug-In Card Input Diode for Supply Hold-Up BACKPLANE CONNECTORS 48V PLUG-IN CARD CONNECTOR 1 FDB3632 Hot Swap CONTROLLER VOUT1 IN GATE LTC4357 GND OUT VDD + CHOLDUP GND FDB3632 Hot Swap CONTROLLER VOUT2 IN GATE LTC4357 GND OUT VDD + CHOLDUP GND 4357 TA05 GND PLUG-IN CARD CONNECTOR 2 RELATED PARTS PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1921 LT4250 LTC4251/LTC4251-1/ LTC4251-2 LTC4252-1/LTC4252-2/ LTC4252-1A/LTC4252-2A LTC4253 LT4256 LTC4260 LTC4261 LTC4350 LT4351 LTC4354 LTC4355 DESCRIPTION Negative High Voltage Hot Swap™ Controllers in SO-8 Positive High Voltage Hot Swap Controllers Dual –48V Supply and Fuse Monitor –48V Hot Swap Controller –48V Hot Swap Controllers in SOT-23 –48V Hot Swap Controllers in MS8/MS10 –48V Hot Swap Controller with Sequencer Positive 48V Hot Swap Controller with Open-Circuit Detect Positive High Voltage Hot Swap Controller Negative High Voltage Hot Swap Controller Hot Swappable Load Share Controller MOSFET Diode-OR Controller Negative Voltage Diode-OR Controller and Monitor Positive Voltage Diode-OR Controller and Monitor COMMENTS Negative High Voltage Supplies From –10V to –80V Active Current Limiting, Supplies From 9V to 80V UV/OV Monitor, –10V to –80V Operation, MSOP Package Active Current Limiting, Supplies From –20V to –80V Fast Active Current Limiting, Supplies From –15V Fast Active Current Limiting, Supplies From –15V, Drain Accelerated Response Fast Active Current Limiting, Supplies From –15V, Drain Accelerated Response, Sequenced Power Good Outputs Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to 80V Supply With I2C and ADC, Supplies from 8.5V to 80V With I2C and 10-Bit ADC, Adjustable Inrush and Overcurrent Limits Output Voltage: 1.2V to 20V, Equal Load Sharing External N-Channel MOSFETs Replace ORing Diodes, 1.2V to 20V Controls Two N-Channel MOSFETs, 1μs Turn-Off, 80V Operation Controls Two N-Channel MOSFETs, 0.5μs Turn-Off, 80V Operation Hot Swap is a trademark of Linear Technology Corporation. 4357fb 12 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0108 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007