LTC4360CSC8-1TRMPBF

LTC4360-1/LTC4360-2 Overvoltage Protection Controller FEATURES n n n n n n n n n n n DESCRIPTION The LTC®4360 overvoltage protection controller safeguards 2.5V to 5.5V systems from power supply overvoltage. It is designed for portable devices with multiple power supply options including wall adaptors, car battery adaptors and USB ports. The LTC4360 controls an external N-channel MOSFET in series with the input power supply. During overvoltage transients, the LTC4360 turns off the MOSFET within 1μs, isolating downstream components from the input supply. Inductive cable transients are absorbed by the MOSFET and load capacitance. In most applications, the LTC4360 provides protection from transients up to 80V without requiring transient voltage suppressors or other external components. The LTC4360 has a delayed start-up and an adjustable dV/dt ramp-up for inrush current limiting. A PWRGD pin provides power good monitoring for VIN. Following an overvoltage condition, the LTC4360 automatically restarts with a start-up delay. The LTC4360-1 features a soft shutdown controlled by the ON pin, while the LTC4360-2 controls an optional external P-channel MOSFET for negative voltage protection. 2.5V to 5.5V Operation Overvoltage Protection Up to 80V No Input Capacitor or TVS Required for Most Applications 2% Accurate 5.8V Overvoltage Threshold Controls N-Channel MOSFET VGATE(TH) to PWRGD Low VON = Step 0V to 2.5V (LTC4360-1) l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VON = 0V (LTC4360-1) unless otherwise noted. PARAMETER Input Voltage Range Input Undervoltage Lockout Input Supply Current VIN Rising LTC4360-1 VON = 0V, LTC4360-2 LTC4360-1 VON = 2.5V IN Pin Overvoltage Threshold Overvoltage Hysteresis External N-Channel MOSFET Gate Drive (VGATE – VOUT) 2.5V ≤ VIN < 3V, IGATE = –1μA 3V ≤ VIN < 5.5V, IGATE = –1μA VIN Rising CONDITIONS l l l l l l l l l l l l l l l l l l l l l l MIN 2.5 1.8 TYP MAX 80 UNITS V V μA μA V mV V V V V μA V/ms mA μA μA μA V μA V MΩ V kΩ ms μs μs ms μs 2.1 220 1.5 2.45 400 10 5.916 200 6 7.9 6.8 7.8 –15 4.5 60 80 20 ±3 1.5 10 7.5 3.2 0.4 800 200 1 1 100 5 5.684 25 3.5 4.5 5.7 6.7 –5 1.5 15 10 5 0.4 2.5 5 0.8 250 50 5.8 100 4.5 6 6.3 7.2 –10 3 30 40 10 0 5 5.8 2 0.23 500 130 0.25 0.25 65 2 External Gate Drive GATE High Threshold for PWRGD Status VIN = 3.3V VIN = 5V GATE Pull-Up Current GATE Ramp-Up GATE Fast Pull-Down Current GATE Pull-Down Current OUT Input Current ON Input Threshold ON Pull-Down Current IN to GATEP Clamp Voltage GATEP Resistive Pull-down PWRGD Output Low Voltage PWRGD Pull-Up Resistance to OUT VGATE = 1V VGATE = 1V to 7V Fast Turn-Off, VIN = 6V, VGATE = 9V VON = 2.5V, VGATE = 9V (LTC4360-1) VOUT = 5V, VON = 0V VOUT = 5V, VON = 2.5V (LTC4360-1) VON = 2.5V (LTC4360-1) (LTC4360-2) VGATEP = 3V (LTC4360-2) VIN = 5V, IPWRGD = 3mA VIN = 6.5V, VPWRGD = 1V 25 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits VGATE to a minimum of 4.5V above VOUT. Driving this pin to voltages beyond this clamp may damage the device. 436012f 3 LTC4360-1/LTC4360-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 5V, VON = 0V (LTC4360-1) unless otherwise noted. Input Supply Current vs Input Voltage 1000 LTC4360-1 VON = 0V, LTC4360-2) 100 VGATE (V) VON = 2.5V (LTC4360-1) 10 8 7 6 5 VIN = 3V 4 3 1 2 1 0.1 1 10 VIN (V) 100 436012 G01 GATE Drive vs GATE Current 40 GATE Fast Pull-Down Current vs Temperature VIN = 6V VGATE = 9V IGATE(FST) (mA) VIN = 5V 35 IIN (μA) 30 VIN = 2.5V 25 0 0 2 4 6 8 IGATE (μA) 10 12 20 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 436012 G02 436012 G03 PWRGD Voltage vs PWRGD Current 500 8 7 400 VPWRGD(OL) (mV) GATE Off Propagation Delay vs Overdrive (VOVDRV) VIN = STEP 5V TO (VIN(OV) + VOVDRV) 12 11 VGATE /VGATE(TH) (V) 10 9 8 7 6 5 0 0.5 1 1.5 VOVDRV (V) 2 2.5 436012 G05 GATE Voltage and GATE High Threshold (for PWRGD Status) vs Input Voltage VIN = VOUT VGATE 6 tOFF (μs) 5 4 3 2 300 VGATE(TH) 200 100 1 0 0 1 3 IPWRGD (mA) 2 4 5 436012 G04 0 4 2.5 3 3.5 4 4.5 VIN (V) 5 5.5 6 436012 G06 Normal Start-Up Sequence VIN 5V/DIV VOUT 5V/DIV GATE Slow Ramp-Up VON 5V/DIV Entering Sleep Mode (LTC4360-1) VIN 5V/DIV VOUT 5V/DIV VOUT 5V/DIV VGATE 10V/DIV VGATE 10V/DIV VGATE 10V/DIV ICABLE 0.5A/DIV ICABLE 0.5A/DIV 436012 G07 ICABLE 0.5A/DIV 20ms/DIV FIGURE 5 CIRCUIT RIN = 150mΩ, LIN = 0.7μH LOAD = 10Ω, COUT = 10μF 1ms/DIV FIGURE 5 CIRCUIT RIN = 150mΩ, LIN = 0.7μH LOAD = 10Ω, COUT = 10μF 436012 G08 50μs/DIV FIGURE 5 CIRCUIT RIN = 150mΩ, LIN = 0.7μH LOAD = 10Ω, COUT = 10μF 436012 G09 436012f 4 LTC4360-1/LTC4360-2 PIN FUNCTIONS GATE: Gate Drive for External N-Channel MOSFET. An internal charge pump provides a 10μA pull-up current to charge the gate of the external N-channel MOSFET. An additional ramp circuit limits the GATE ramp rate when turning on to 3V/ms. For slower ramp rates, connect an external capacitor from GATE to GND. An internal clamp limits GATE to 6V above the OUT pin voltage. An internal GATE high comparator controls the PWRGD pin. GATEP (LTC4360-2): Gate Drive for External P-Channel MOSFET. GATEP connects to the gate of an optional external P-channel MOSFET to protect against negative voltages at IN. This pin is internally clamped to 5.8V below VIN. An internal 2M resistor connects this pin to ground. Connect to IN if not used. GND: Device Ground. IN: Supply Voltage Input. Connect this pin to the input power supply. This pin has an overvoltage threshold of 5.8V. After an overvoltage event, this pin must fall below VIN(OV) – ΔVOV to release the overvoltage lockout. During lockout, GATE is held low and the PWRGD pull-down releases. ON (LTC4360-1): On Control Input. A logic low at ON enables the LTC4360-1. A logic high at ON activates a low current pull-down at the GATE pin and causes the LTC4360-1 to enter a low current sleep mode. An internal 5μA current pulls ON down to ground. Connect to ground or leave open if unused. OUT: Output Voltage Sense Input for Gate Clamp. Connect to the source of the external N-channel MOSFET to sense the output voltage for GATE to OUT clamp. PWRGD: Power Good Status. Open-drain output with internal 500k resistive pull-up to OUT. Pulls low 65ms after GATE ramps above VGATE(TH). BLOCK DIAGRAM GATEP (LTC4360-2) 200k 5.8V IN 1.8M CHARGE PUMP 10μA GATE GATE HIGH COMPARATOR ON (LTC4360-1) 1V 5μA 5.8V OUT VGATE(TH) + – + – OVERVOLTAGE COMPARATOR CONTROL + 5.8V 500k – 5.7V PWRGD GND 436012 BD 436012f 5 LTC4360-1/LTC4360-2 OPERATION Mobile devices like cell phones and MP3/MP4 players have highly integrated subsystems fabricated from deep submicron CMOS processes. The small form factor is accompanied by low absolute maximum voltage ratings. The sensitive electronics are susceptible to damage from transient or DC overvoltage conditions from the power supply. Failures or faults in the power adaptor can cause an overvoltage event. So can hot-plugging an AC adaptor into the power input of the mobile device (see LTC Application Note 88). Today’s mobile devices derive their power supply or recharge their internal batteries from multiple alternative inputs like AC wall adaptors, car battery adaptors and USB ports. A user may unknowingly plug in the wrong adaptor, damaging the device with a high or even a negative power supply voltage. The LTC4360 protects low voltage electronics from these overvoltage conditions by controlling a low cost external N-channel MOSFET configured as a pass transistor. At power-up (VIN > 2.1V), a start-up delay cycle begins. Any overvoltage condition causes the delay cycle to continue until a safe voltage is present. When the delay cycle completes, an internal high side switch driver slowly ramps up the MOSFET gate, powering up the output at a controlled rate and limiting the inrush current to the output capacitor. If the voltage at the IN pin exceeds 5.8V (VIN(OV)), GATE is pulled low quickly to protect the load. The incoming power supply must remain below 5.7V (VIN(OV) – ΔVOV) for the duration of the start-up delay to restart the GATE ramp-up. The LTC4360-1 has a CMOS compatible ON input. When driven low, the part is enabled. When driven high, the external N-channel MOSFET is turned off and the supply current of the LTC4360-1 drops to 1.5μA. The PWRGD pull-down releases during this low current sleep mode, UVLO or overvoltage and the subsequent 130ms start-up delay. After the start-up delay, GATE starts its slow rampup and ramps higher than VGATE(TH) to trigger a 65ms delay cycle. When that completes, PWRGD pulls low. The LTC4360-2 has a GATEP pin that drives an optional external P-channel MOSFET to provide protection against negative voltages at IN. APPLICATIONS INFORMATION The typical LTC4360 application protects 2.5V to 5.5V systems in portable devices from power supply overvoltage. The basic application circuit is shown in Figure 1. Device operation and external component selection is discussed in detail in the following sections. VIN 5V M1 Si1470DH COUT 10μF GATE IN OUT LTC4360-1 VOUT 5V 1.5A Start-Up When VIN is less than the undervoltage lockout level of 2.1V, the GATE driver is held low and the PWRGD pulldown is high impedance. When VIN rises above 2.1V and ON (LTC4360-1) is held low, a 130ms delay cycle starts. Any undervoltage or overvoltage event at IN (VIN < 2.1V or VIN > 5.7V) restarts the delay cycle. This delay allows the N-channel MOSFET to isolate the output from any input transients that occur at start-up. When the delay cycle completes, GATE starts its slow ramp-up. GATE Control ON PWRGD GND 436012 F01 Figure 1. Protection from Input Overvoltage An internal charge pump enhances the external MOSFET with 6V from GATE to OUT. This allows the use of logiclevel N-channel MOSFETs. An internal 6V clamp between GATE and OUT protects the MOSFET gate. 436012f 6 LTC4360-1/LTC4360-2 APPLICATIONS INFORMATION The GATE ramp rate is limited to 3V/ms. VOUT follows at a similar rate which results in an inrush current into the load capacitor COUT of: IINRUSH = COUT • dVGATE = COUT • 3 [mA/µF ] dt resistor from PWRGD to the I/O rail with a resistance low enough to override the internal 500k pull-up to OUT. Figure 2 details PWRGD behavior for a LTC4360-1 with 1k pull-up to 5V at PWRGD. START-UP FROM UVLO VIN(OV) VIN(UVL) IN OV RESTART FROM OV ON RESTART FROM ON The servo loop is compensated by the parasitic capacitance of the external MOSFET. No further compensation components are normally required. In the case where the parasitic capacitance is less than 100pF a 100pF , compensation capacitor between GATE and ground may be required. An even slower GATE ramp and lower inrush current can be achieved by connecting an external capacitor, CG, from GATE to ground. The voltage at GATE then ramps up with a slope equal to 10μA/CG [V/s]. Choose CG using the formula: CG = 10µA IINRUSH • COUT VIN(OV)– VOV OUT VGATE(TH) GATE VGATE(TH) VGATE(TH) VGATE(TH) ON PWRGD 130ms 65ms 130ms 65ms 130ms 65ms Overvoltage When power is first applied, VIN must remain below 5.7V (VIN(OV) – ΔVOV) for more than 130ms before GATE is ramped up to turn on the MOSFET. If VIN then rises above 5.8V (VIN(OV)), the overvoltage comparator activates the 30mA fast pull-down on GATE within 1μs. After an overvoltage condition, the MOSFET is held off until VIN once again remains below 5.7V for 130ms. PWRGD Output PWRGD is an active low output with a MOSFET pulldown to ground and a 500k resistive pull-up to OUT. The PWRGD pin pull-down releases during the low current sleep mode (invoked by ON high), UVLO or overvoltage and the subsequent 130ms start-up delay. After the start-up delay, GATE starts its slow ramp-up and control of the PWRGD pull-down passes on to the GATE high comparator. VGATE > VGATE(TH) for more than 65ms asserts the PWRGD pull-down and VGATE < VGATE(TH) releases the pull-down. The PWRGD pull-down is capable of sinking up to 3mA of current allowing it to drive an optional LED. To interface PWRGD to another I/O rail, connect a Figure 2. PWRGD Behavior ON Input (LTC4360-1) ON is a CMOS compatible, active low enable input. It has a default 5μA pull-down to ground. Connect this pin to ground or leave open to enable normal device operation. If it is driven high while the external MOSFET is turned on, GATE is pulled low with a weak pull-down current (40μA) to turn off the external MOSFET gradually, minimizing input voltage transients. The LTC4360-1 then goes into a low current sleep mode, drawing only 1.5μA at IN. When ON goes back low, the part restarts with a 130ms delay cycle. GATEP Control (LTC4360-2) GATEP has a 2M resistive pull-down to ground and a 5.8V Zener clamp in series with a 200k resistor to IN. It controls the gate of an optional external P-channel MOSFET to provide negative voltage protection. The 2M resistive pull-down turns on the MOSFET once VIN – VGATEP is more than the MOSFET gate threshold voltage. The IN to GATEP Zener protects the MOSFET from gate overvoltage by clamping its VGS to 5.8V when VIN goes high. 436012f 7 LTC4360-1/LTC4360-2 APPLICATIONS INFORMATION MOSFET Configurations and Selection The LTC4360 can be used with various external MOSFET configurations (see Figure 3). The simplest configuration is a single N-channel MOSFET. It has the lowest RDS(ON) and voltage drop and is thus the most power efficient solution. When GATE is pulled to ground, the MOSFET can isolate OUT from a positive voltage at IN up to the BVDSS of the MOSFET. However, reverse current can still flow from OUT to IN via the parasitic body diode of the MOSFET. For near zero reverse leakage current protection when GATE is pulled to ground, back-to-back N-channel MOSFETs can be used. Adding an additional P-channel MOSFET controlled by GATEP (LTC4360-2) provides negative input voltage protection down to the BVDSS of the P-channel MOSFET. Another configuration consists of a P-channel MOSFET controlled by GATEP and a N-channel MOSFET controlled by GATE. This provides protection against overvoltage and negative voltage but not reverse current. Input Transients GATEP SUPPLY IN GATE OVERVOLTAGE, REVERSE CURRENT PROTECTION M1 M3 OVERVOLTAGE PROTECTION M1 OUT SUPPLY IN OUT GATE SUPPLY NEGATIVE VOLTAGE PROTECTION M2 IN GATEP NEGATIVE VOLTAGE PROTECTION M2 IN OVERVOLTAGE, REVERSE CURRENT PROTECTION M1 M3 OUT GATE SUPPLY OVERVOLTAGE PROTECTION M1 OUT GATE 436012 F03 Figure 4 shows a typical setup when an AC wall adaptor charges a mobile device. The inductor LIN represents the lumped equivalent inductance of the cable and the EMI filter found in some wall adaptors. RIN is the lumped equivalent resistance of the cable, adaptor output capacitor ESR and the connector contact resistance. LIN and RIN form an LC tank circuit with any capacitance at IN. If the wall adaptor is powered up first, plugging the wall adaptor output to IN does the equivalent of applying WALL ADAPTOR AC/DC MOBILE DEVICE Figure 3. MOSFET Configurations a voltage step to this LC circuit. The resultant voltage overshoot at IN can rise to twice the DC output voltage of the wall adaptor as shown in Figure 4. Figure 5 shows the 20V adaptor output applied to the LTC4360. Due to the low capacitance at the IN pin, the plug-in transient has been brought down to a manageable level. RIN LIN ICABLE IN + COUT CABLE LOAD VIN 10V/DIV ICABLE 20A/DIV 436012 F04a 5μs/DIV RIN = 150mΩ, LIN = 0.7μH LOAD = 10Ω, COUT = 10μF 436012 F04b Figure 4. 20V Hot-Plug into a 10μF Capacitor 436012f 8 LTC4360-1/LTC4360-2 APPLICATIONS INFORMATION WALL ADAPTOR AC/DC RIN LIN ICABLE IN M1 Si1470DH OUT MOBILE DEVICE + COUT CABLE GATE IN OUT LTC4360 GND LOAD VIN 10V/DIV VOUT 1V/DIV ICABLE 20A/DIV 436012 F04a 5μs/DIV RIN = 150mΩ, LIN = 0.7μH LOAD = 10Ω, COUT = 10μF 436012 F04b Figure 5. 20V Hot-Plug into the LTC4360 VIN 20V/DIV VIN 20V/DIV VOUT 1V/DIV ICABLE 5A/DIV 5μs/DIV FDC5612 RIN = 150mΩ, LIN = 0.7μH LOAD = 10Ω, COUT = 10μF 436012 F05 VADAPTOR VADAPTOR/VOUT 5V/DIV ICABLE 5A/DIV VOUT 2μs/DIV FIGURE 5 CIRCUIT RIN = 150μΩ, LIN = 2μH LOAD = 10Ω, COUT = 10μF 436012 F06 Figure 6. 50V Hot-Plug into the LTC4360 Figure 7. Input Transient After Overvoltage As the IN pin can withstand up to 80V, a high voltage Nchannel MOSFET can be used to protect the system against rugged abuse from high transient or DC voltages up to the BVDSS of the MOSFET. Figure 6 shows a 50V input plugged into the LTC4360 controlling a 60V rated MOSFET. Input transients also occur when the current through the cable inductance changes abruptly. This can happen when the LTC4360 turns off the N-channel MOSFET rapidly in an overvoltage event. Figure 7 shows the effects of a voltage transient at the wall adaptor output VADAPTOR. The current in LIN will cause VIN to overshoot and avalanche the N-channel MOSFET to COUT . Typically, IN will be clamped to a voltage of VOUT + 1.3•(BVDSS of Si1470DH) = 45V. This is well below the 85V absolute maximum voltage rating of the LTC4360. The single, nonrepetitive, pulse of energy (EAS) absorbed by the MOSFET during this avalanche breakdown with a peak current IAS is approximated by the formula: EAS = 0.5 • LIN • IAS2 For LIN = 2μH and IAS = 4A, then EAS = 16μJ. This is within the IAS and EAS capabilities of most MOSFET’s including the Si1470DH. So in most instances, the LTC4360 can ride through such transients without a bypass capacitor, transient voltage suppressor or other external components at IN. 436012f 9 LTC4360-1/LTC4360-2 APPLICATIONS INFORMATION Figure 8 shows a particularly severe situation which can occur in a mobile device with dual power inputs. A 20V wall adaptor is mistakenly hot-plugged into the 5V device with the USB input already live. As shown in Figure 9, a large current can build up in LIN to charge up COUT . When the N-channel MOSFET shuts off, the energy stored in LIN is dumped into COUT, causing a large 40V input transient. The LTC4360 limits this to a 1V rise in the output voltage. RIN 20V WALL ADAPTER LIN ICABLE IN M1 Si1470DH + – OUT If the voltage rise at VOUT due to the discharge of the energy in LIN into COUT is not acceptable or the avalanche capability of the MOSFET is exceeded, an additional external clamp such as the SMAJ24A can be placed between IN and GND. COUT is the decoupling capacitor of the protected circuits and its value will largely be determined by their requirements. Using a larger COUT will work with LIN to slow down the dV/dt at OUT, allowing time for the LTC4360 to shut off the MOSFET before VOUT overshoots to a dangerous voltage. A larger COUT also helps to lower the ΔVOUT due to the discharge of the energy in LIN if the MOSFET BVDSS is used as an input clamp. Layout Considerations Figure 10 shows example PCB layouts for the single N-channel MOSFET (SC70 package) configuration and the P-channel MOSFET/N-channel MOSFET (Complementary P N MOSFET in TSOP-6 package) configuration. Keep the , traces to the MOSFETs wide and short. The PCB traces associated with the power path through the MOSFETs should have low resistance. D1 B160 GATE IN OUT R1 100k LTC4360 GND COUT LOAD 5V USB + – 436012 F07 Figure 8. Setup for Testing 20V Plugged into 5V System SUPPLY VIN 20V/DIV VOUT 5V/DIV VGATE 10V/DIV ICABLE 10A/DIV 1μs/DIV 436012 F08 IN 6 5 4 6 5 SUPPLY/IN 4 Si3590DV OUT OUT Si1470DH GND 1 2 GND 1 2 3 4 8 7 6 5 LTC4360-2 436012 F09 1 2 FIGURE 8 CIRCUIT RIN = 150mΩ, LIN = 2μH LOAD = 10Ω, COUT = 10μF (16V, SIZE 1210) 1 2 3 4 8 7 6 5 LTC4360-1 Figure 9. Overvoltage Protection Waveforms When 20V Plugged into 5V System Figure 10. Recommended Layout for N-Channel MOSFET and P-/N-Channel MOSFET Configurations 3 3 436012f 10 LTC4360-1/LTC4360-2 PACKAGE DESCRIPTION SC8 Package 8-Lead Plastic SC70 (Reference LTC DWG # 05-08-1639 Rev Ø) 0.30 MAX 0.50 REF PIN 8 1.00 REF 1.80 – 2.20 (NOTE 4) 2.8 BSC 1.8 REF 1.80 – 2.40 1.15 – 1.35 (NOTE 4) INDEX AREA (NOTE 6) PIN 1 RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.10 – 0.40 0.50 BSC 0.15 – 0.27 8 PLCS (NOTE 3) 0.80 – 1.00 0.00 – 0.10 REF 1.00 MAX GAUGE PLANE 0.15 BSC 0.26 – 0.46 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE INDEX AREA 7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70 AND JEDEC MO-203 VARIATION BA 0.10 – 0.18 (NOTE 3) SC8 SC70 0905 REV Ø 436012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC4360-1/LTC4360-2 TYPICAL APPLICATION 5V System Protected from ±24V Power Supplies 5V System Protected from ±24V Power Supplies and Reverse Current M2 Si1471DH FDC6561AN M1 M3 COUT 10μF GATE VIO 5V R1 1k IN LTC4360-2 OUT VIO 5V R1 1k VOUT 5V 0.5A Si3590DV VIN 5V M2 M1 COUT 10μF GATE IN LTC4360-2 OUT VOUT 5V 0.5A VIN 5V GATEP GND PWRGD 436012 TA02 D1 LN1351CTR GATEP GND PWRGD 436012 TA03 D1 LN1351CTR RELATED PARTS PART NUMBER LTC2935 LT3008 LT3009 LTC3576/ LTC3576-1 LTC4090/ LTC4090-5 LTC4098 LTC4210 LTC4213 LT4356 LTC4411 LTC4412 LTC4413-1/ LTC4413-2 DESCRIPTION Ultralow Power Supervisor with Eight Pin-Selectable Thresholds 20mA, 45V, 3μA IQ Micropower LDO 20mA, 3μA IQ Micropower LDO COMMENTS 500nA Quiescent Current, 2mm × 2mm 8-Lead DFN and TSOT-23 Packages 280mV Dropout Voltage, Low IQ: 3μA, VIN = 2.0V to 45V, VOUT = 0.6V to 39.5V; ThinSOT™ and 2mm × 2mm DFN-6 Packages 280mV Dropout Voltage, Low IQ: 3μA, VIN = 1.6V to 20V, VOUT = 0.6V to 19.5V; ThinSOT and SC-70 Packages Switching USB Power Manager with USB OTG + Triple Complete Multifunction PMIC: Bi-Directional Switching Power Manager + 3 Step-Down DC/DCs Bucks + LDO High Voltage USB Power Manager with Ideal Diode Controller and High Efficiency Li-Ion Battery Charger USB-Compatible Switchmode Power Manager with OVP Single Channel, Low Voltage Hot Swap™ Controller No RSENSE™ Electronic Circuit Breaker Surge Stopper Overvoltage/Overcurrent Protection Regulator SOT-23 Ideal Diode 2.5V to 28V, Low Loss PowerPath™ Controller in ThinSOT Dual 2.6A, 2.5V to 5.5V Fast Ideal Diodes in 3mm × 3mm DFN High Efficiency 1.2A Charger from 6V to 38V (60V Max) Input Charges Single Cell Li-Ion Batteries Directly from a USB Port High VIN: 38V operating, 60V transient; 66V OVP 1.5A Max Charge Current . from Wall, 600mA Charge Current from USB Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 Controls Load Voltages from 0V to 6V. 3 Selectable Circuit Breaker Thresholds. Dual Level Overcurrent Fault Protection Wide Operation Range: 4V to 80V. Reverse Input Protection to –60V. Adjustable Output Clamp Voltage 2.6A Forward Current, 28mV Regulated Forward Voltage More Efficient than Diode-ORing, Automatic Switching Between DC Sources, Simplified Load Sharing 130mΩ On Resistance, Low Reverse Leakage Current, 18mV Regulated Forward Voltage (LTC4413-2 with Overvoltage Protection Sensor) 436012f 12 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0410 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010