LTC4403-2

LTC4403-1/LTC4403-2 Multiband RF Power Controllers for EDGE/TDMA FEATURES s s DESCRIPTIO s s s s s s s s s s s s s Supports AM Modulation in EDGE/TDMA (ANSI-136) Applications Single Output RF Power Amplifier Control (LTC4403-1) Dual Output RF Power Amplifier Control (LTC4403-2) Internal Schottky Diode Detector with >40dB Range Wide Input Frequency Range: 300MHz to 2.4GHz Autozero Loop Cancels Offset Errors and Temperature Dependent Offsets Wide VIN Range: 2.7V to 6V Allows Direct Connection to Battery RF Output Power Set by External DAC Internal Frequency Compensation Rail-to-Rail Power Control Outputs Low Operating Current: 1mA Low Shutdown Current: < 10µA PCTL Input Filter Available in a 8-Pin MSOP Package (LTC4403-1) and 10-Pin MSOP (LTC4403-2) The LTC®4403-2 is a multiband RF power controller for RF power amplifiers operating in the 300MHz to 2.4GHz range. The LTC4403-2 has two outputs to control dual TX PA modules with two control inputs. An internal sample and hold circuit enables the LTC4403-2 to be used with AM modulation via the carrier or PA supply. The input voltage range is optimized for operation from a single lithium-ion cell or 3 × NiMH. RF power is controlled by driving the RF amplifier power control pins and sensing the resultant RF output power. The RF sense voltage is peak detected using an on-chip Schottky diode. This detected voltage is compared to the DAC voltage at the PCTL pin to control the output power. The LTC4403-1 is a single output RF power controller with identical performance to the LTC4403-2. The LTC4403-1 has one output to control a single TX PA or dual TX PA module with a single control input and is available in an 8-pin MSOP package. Internal and external offsets are cancelled over temperature by an autozero control loop. The shutdown feature disables the part and reduces the supply current to < 10µA. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s Multiband GSM/GPRS/EDGE Cellular Telephones PCS Devices Wireless Data Modems U.S. TDMA Cellular Phones TYPICAL APPLICATIO LTC4403-2 Multiband EDGE Cellular Telephone Transmitter LTC4403-2 1 Li-Ion 0.1µF BSEL VHOLD SHDN DAC 9 8 7 6 VIN BSEL VHOLD SHDN PCTL RF VPCA VPCB GND GND 10 2 3 4 5 850MHz/ 900MHz RF PA 50Ω 0.4pF ± 0.05pF 1.8GHz / 1.9GHz RF PA U DIPLEXER 4403 TA01 U U 4403f 1 LTC4403-1/LTC4403-2 ABSOLUTE AXI U RATI GS VIN to GND ............................................... – 0.3V to 6.5V VPCA, VPCB Voltage .................................. – 0.3V to 4.6V PCTL Voltage ............................... – 0.3V to (VIN + 0.3V) RF Voltage ........................................ (VIN ± 2.6V) to 7V SHDN, VHOLD, BSEL Voltage to GND ......................................... – 0.3V to (VIN + 0.3V) PACKAGE/ORDER I FOR ATIO TOP VIEW VIN VPCA GND GND 1 2 3 4 8 7 6 5 RF VHOLD SHDN PCTL ORDER PART NUMBER LTC4403-1EMS8 MS8 PART MARKING LTXG MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS PARAMETER VIN Operating Voltage IVIN Shutdown Current IVIN Operating Current VPCA/B VOL VPCA/B Dropout Voltage VPCA/B Output Current VPCA/B Enable Time VPCA/B Bandwidth VPCA/B Load Capacitance VPCA/B Slew Rate VPCA/B VHOLD Droop VHOLD Time VPCA/B Start Voltage VPCA/B Voltage Clamp SHDN, VHOLD, BSEL Input Threshold Low SHDN = 0V IVPCA = IVPCB = 0mA CONDITIONS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, SHDN = VIN unless otherwise noted. MIN q q q q q q q RLOAD = 400Ω, Enabled ILOAD = 6mA, VIN = 2.7V VPCA/B = 2.4V, VIN = 2.7V, ∆VOUT = 10mV SHDN = High (Note 5) CLOAD = 33pF, RLOAD = 400 (Note 7) (Note 6) VPCTL = 2V Step, CLOAD = 100pF, RLOAD = 400 (Note 3) Unity Gain, VPCTL = 2V, VHOLD = High Time from VHOLD High to Hold Switch Opening Open Loop PCTL = 1V, VIN = 5V VIN = 2.7V to 6V PCTL < 80mV PCTL > 160mV SHDN, VHOLD, BSEL Input Threshold High VIN = 2.7V to 6V SHDN, BSEL, VHOLD Input Current SHDN, BSEL, VHOLD = VIN = 3.6V PCTL Input Voltage Range PCTL Input Resistance (Note 4) 2 U U W WW U W (Note 1) IVPCA/B .................................................................................. 10mA Operating Temperature Range (Note 2) .. – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Maximum Junction Temperature ........................ 125°C Lead Temperature (Soldering, 10 sec)................ 300°C TOP VIEW VIN VPCA VPCB GND GND 1 2 3 4 5 10 RF 9 BSEL 8 VHOLD 7 SHDN 6 PCTL ORDER PART NUMBER LTC4403-2EMS MS PART MARKING LTXJ MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 160°C/W TYP 10 1.5 MAX 6 20 2 0.1 VIN – 0.25 UNITS V µA mA V V mA µs kHz kHz 2.7 0 6 9 250 130 11 q 100 1.4 1 100 pF V/µs µV/ms ns q q q q q q q 250 3.6 1.4 16 0 60 450 4 550 4.4 0.35 mV V V V µA V kΩ 4403f 24 90 36 2.4 120 LTC4403-1/LTC4403-2 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, SHDN = VIN, unless otherwise noted. PARAMETER PCTL Input Filter Autozero Range RF Input Frequency Range RF Input Power Range Maximum DAC Zero-Scale Offset Voltage that can be applied to PCTL (Note 6) F = 900MHz (Note 6) F = 1800MHz (Note 6) F = 2400MHz (Note 6) Referenced to VIN q q q ELECTRICAL CHARACTERISTICS CONDITIONS MIN TYP 270 MAX 400 UNITS kHz mV MHz dBm dBm dBm 300 –27 to 18 –25 to 18 –23 to 16 150 250 2400 RF Input Resistance 350 Ω Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications are assured over the –40°C to 85°C temperature range by design characterization and correlation with statistical process controls. Note 3: Slew rate is measured open loop. The rise time at VPCA or VPCB is measured between 1V and 2V. Note 4: Includes maximum DAC offset voltage and maximum control voltage. Note 5: This is the time from SHDN rising edge 50% switch point to VPCA/B = 250mV. Note 6: Guaranteed by design. This parameter is not production tested. Note 7: Bandwidth is calculated using the 10% to 90% rise time: BW = 0.35/rise time TYPICAL PERFOR A CE CHARACTERISTICS PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV) PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV) 10000 10000 PCTL REFERENCED DETECTOR OUTPUT VOLTAGE (mV) Detector Characteristics at 900MHz 1000 100 0.9GHz AT 25°C 0.9GHz AT –30°C 0.9GHz AT 75°C 10 1 –26 –20 –14 –8 –2 4 10 RF INPUT POWER (dBm) 16 4403 G01 PI FU CTIO S (LTC4403-1/LTC4403-2) VIN (Pin 1): Input Supply Voltage, 2.7V to 6V. VIN should be bypassed with 0.1µF and 100pF ceramic capacitors. VPCA (Pin 2): Power Control Voltage Output. This pin drives an external RF power amplifier power control pin. The maximum load capacitance is 100pF. The output is capable of rail-to-rail swings at low load currents. Selected when BSEL is low. UW Detector Characteristics at 1800MHz Detector Characteristics at 2400MHz 10000 1000 1.8GHz AT –30°C 100 1.8GHz AT 25°C 1000 100 2.4GHz AT –30°C 2.4GHz AT 25°C 10 1.8GHz AT 75°C 1 –26 –20 10 2.4GHz AT 75°C 1 –20 –14 –8 –2 4 RF INPUT POWER (dBm) 10 16 –14 –8 –2 4 10 RF INPUT POWER (dBm) 16 4403 G02 4403 G03 U U U VPCB (Pin 3): (LTC4403-2 Only) Power Control Voltage Output. This pin drives an external RF power amplifier power control pin. The maximum load capacitance is 100pF. The output is capable of rail-to-rail swings at low load currents. Selected when BSEL is high. GND (Pin 3/4): System Ground. 4403f 3 LTC4403-1/LTC4403-2 PI FU CTIO S GND (Pin 4/5): System Ground. PCTL (Pin 5/6): Analog Input. The external power control DAC drives this input. The amplifier servos the RF power until the RF detected signal equals the DAC signal applied at this pin. SHDN (Pin 6/7): Shutdown Input. A logic low on the SHDN pin places the part in shutdown mode. A logic high enables the part after 10µs. SHDN has an internal 150k pull-down resistor to ensure that the part is in shutdown when no input is applied. In shutdown, VPCA and VPCB are pulled to ground via a 112Ω resistor. BLOCK DIAGRA 0.4pF ±0.05pF 50Ω VIN 250Ω 10 RF VIN 28pF 30k 60µA 4 5 GND 9µs DELAY 60µA 150k 7 SHDN 4 W U U U (LTC4403-1/LTC4403-2) VHOLD (Pin 7/8): Asserted high prior to AM modulation, opens control loop and holds voltage at VPCA or VPCB during EDGE modulation. BSEL (Pin 9): (LTC4403-2 Only) Selects VPCA when low and VPCB when high. This input has an internal 150k resistor to ground. RF (Pin 8/10): Coupled RF Feedback Voltage . This input is referenced to VIN. The frequency range is 300MHz to 2400MHz. This pin has an internal 250Ω termination, an internal Schottky diode detector and peak detector capacitor. (LTC4403-2) DIPLEXER 850MHz/900MHz RF PA RF PA 1.8GHz/1.9GHz Li-Ion 1 TXENB AUTOZERO – AZ + + – GAIN COMPRESSION – GM + VHOLD + – 30k 70mV CHOLD 270kHz FILTER 38k + – BUFFER 2 VPCA 3 VPCB + RFDET – 22k VHOLD 12Ω TXENB VREF VHOLD 150k 51k 150k CREF MUX CONTROL PA PB 100Ω 12Ω 100Ω 8 VHOLD 6 PCTL 9 BSEL 4403 BD 4403f LTC4403-1/LTC4403-2 APPLICATIONS INFORMATION Operation The LTC4403-1/-2 single/dual band RF power controller integrates several functions to provide RF power control over frequencies ranging from 300MHz to 2.4GHz. These functions include an internally compensated amplifier to control the RF output power, an autozero section to cancel internal and external voltage offsets, an RF Schottky diode peak detector and amplifier to convert the RF feedback signal to DC, a multiplexer to switch the controller output to either VPCA or VPCB, a VPCA/B overvoltage clamp, compression and a bandgap reference. Band Selection The LTC4403-2 is designed for multiband operation. The BSEL pin will select output VPCA when low and output VPCB when high. For example, VPCA could be used to drive an 850MHz/900MHz channel and VPCB a 1.8GHz/1.9GHz channel. BSEL must be established before the part is enabled. The LTC4403-1 can be used to drive a single RF channel or dual channel with integral multiplexer. Control Amplifier The control amplifier supplies the power control voltage to the RF power amplifier. A portion (typically – 19dB for low frequencies and –14dB for high frequencies) of the RF output voltage is coupled into the RF pin, to close the gain control loop. When a DAC voltage is applied to PCTL, the amplifier quickly servos VPCA or VPCB positive until the detected feedback voltage applied to the RF pin matches the voltage at PCTL. This feedback loop provides accurate RF power control. VPCA or VPCB are capable of driving a 6mA load current and 100pF load capacitor. RF Detector The internal RF Schottky diode peak detector and amplifier convert the coupled RF feedback voltage to a low frequency voltage. This voltage is compared to the DAC voltage at the PCTL pin by the control amplifier to close the RF power control loop. The RF pin input resistance is typically 250Ω and the frequency range of this pin is 300MHz to 2400MHz. The detector demonstrates excellent efficiency and linearity over a wide range of input power. The Schottky detector is biased at about 60µA and drives an on-chip peak detector capacitor of 28pF. Autozero An autozero system is included to improve power programming accuracy over temperature. This section cancels internal offsets associated with the Schottky diode detector and control amplifier. External offsets associated with the DAC driving the PCTL pin are also cancelled. Offset drift due to temperature is cancelled between each burst. The maximum offset allowed at the DAC output is limited to 400mV. Autozeroing is performed after SHDN is asserted high. An internal delay of typically 9 µs enables the VPCA/B output after the autozero has settled. When the part is enabled, the autozero capacitors are held and the VPCA or VPCB pin is connected to the buffer amplifier output. The hold droop voltage of typically < 1µV/ms provides for accurate offset cancellation. Filter There is a 270kHz filter included in the PCTL path. This filter is trimmed at test. Modes of Operation Shutdown: The part is in shutdown mode when SHDN is low. VPCA and VPCB are held at ground and the power supply current is typically 10µA. Enable: When SHDN is asserted high the part will automatically calibrate out all offsets. This takes about 9µs and is controlled by an internal delay circuit. After 9µs VPCA or VPCB will step up to the starting voltage of 450mV. The user can then apply the ramp signal. The user should wait at least 11µs after SHDN has been asserted high before applying the ramp. The DAC should be settled 2µs after asserting SHDN high. Hold: When the VHOLD pin is low, the RF power control feedback loop is closed and the LTC4403-X servos the VPCA/VPCB pins according to the voltages at the PCTL and RF inputs. When the VHOLD pin is asserted high, the RF power control feedback loop is opened and the power control voltage at VPCA or VCPB is held at its present level. Generally, the VHOLD pin is asserted high after the power up ramp has been completed and the desired RF output power has been achieved. The power control voltage is then held at a constant voltage during the EDGE modulation time. After the EDGE modulation is completed and prior to power ramping down, the VHOLD pin is set low. 4403f U W U U 5 LTC4403-1/LTC4403-2 APPLICATIONS INFORMATION This closes the RF power control loop and the RF power is then controlled during ramp down. LTC4403-1 Description The LTC4403-1 is identical in performance to the LTC4403-2 except that only one control output (VPCA) is available. The LTC4403-1 can drive a single band (300MHz to 2400MHz) or a dual RF channel module with an internal multiplexer. Several manufacturers offer dual RF channel modules with an internal multiplexer. General Layout Considerations The LTC4403-X should be placed near the coupling components. The feedback signal line to the RF pin should be a 50Ω transmission line. Capacitive Coupling An alternative to a directional coupler is illustrated on the first page of this data sheet. This method couples RF from the power amplifier to the power controller through a 0.4pF ±0.05pF capacitor and 50Ω series resistor, completely eliminating the directional coupler. LTC4403-X Timing Diagram 11µs SHDN 2µs 28µs 543µs 28µs VPCA/B VSTART PCTL VHOLD T1 T2 T3 T4 T5 AM MODULATION PERIOD 4403 TD T6 T7 T8 T1: PART COMES OUT OF SHUTDOWN 11µs PRIOR TO BURST. T2: INTERNAL TIMER COMPLETES AUTOZERO CORRECTION, TYPICALLY 9µs. T3: BASEBAND CONTROLLER STARTS RF POWER RAMP UP AT LEAST 11µs AFTER SHDN IS ASSERTED HIGH. T4: BASEBAND CONTROLLER COMPLETES RAMP UP. T5: CONTROL LOOP OPENS, VPCA/B VOLTAGE HELD, AM MODULATION STARTS. T6: AM MODULATION STOPS, CONTROL LOOP CLOSES, VPCA/B WILL FOLLOW DAC. T7: BASEBAND CONTROLLER STARTS RF POWER RAMP DOWN AT END OF BURST. T8: RETURNS TO SHUTDOWN MODE BETWEEN BURSTS. 6 U W U U Application Note AN91 describes the capacitive coupling scheme in full detail. Demo boards featuring this coupling method are available upon request. Power Ramp Profiles The external voltage gain associated with the RF channel can vary significantly between RF power amplifier types. Frequency compensation generally defines the loop dynamics that impact the power/time response and possibly (slow loops) the power ramp sidebands. The LTC4403-X operates open loop until an RF voltage appears at the RF pin, at which time the loop closes and the output power follows the DAC profile. The RF power amplifier will require a certain control voltage level (threshold) before an RF output signal is produced. The LTC4403-X VPCA/B outputs must quickly rise to this threshold voltage in order to meet the power/time profile. To reduce this time, the LTC4403-X starts at 450mV. However, at very low power levels the PCTL input signal is small, and the VPCA/B outputs may take several microseconds to reach the RF power amplifier threshold voltage. To reduce this time, it may be necessary to apply a positive pulse at the start of the ramp to quickly bring the VPCA/B outputs to the threshold voltage. This can generally be achieved with DAC programming. The magnitude of the pulse is dependent on the RF amplifier characteristics. Power ramp sidebands and power/time are also a factor when ramping to zero power. For RF amplifiers requiring high control voltages, it may be necessary to further adjust the DAC ramp profile. When the power is ramped down, the loop will eventually open at power levels below the LTC4403-X detector threshold. The LTC4403-X will then go open loop and the output voltage at VPCA or VPCB will stop falling. If this voltage is high enough to produce RF output power, the power/time or power ramp sidebands may not meet specification. This problem can be avoided by starting the DAC ramp from 200mV (Figure 1). At the end of the cycle, the DAC can be ramped down to 0mV. This applies a negative signal to the LTC4403-X thereby ensuring that the VPCA/B outputs will ramp to 0V. The 200mV ramp step must be applied at least 2µs after SHDN is asserted high to allow the autozero to cancel the step. 4403f LTC4403-1/LTC4403-2 APPLICATIO S I FOR ATIO 10 0 –10 RFOUT (dBc) –20 –30 –40 –50 –60 –70 –80 –28 –18 –10 0 TIME (µs) 543 553 561 571 DAC VOLTAGE START PULSE START CODE ZERO CODE 200mV SHDN 11µs MINIMUM, ALLOWS TIME FOR AUTOZERO TO SETTLE Figure 1. LTC4403 Ramp Timing Demo Board The LTC4403-X demo board is available upon request. The demo board has a 900MHz and an 1800MHz RF channel and VHOLD controlled by the LTC4403-X. Timing signals for SHDN are generated on the board using a 13MHz crystal oscillator reference. The PCTL power control pin is driven by a 10-bit DAC and the DAC profile can be loaded via a serial port. The serial port data is stored in a flash memory which is capable of storing eight ramp profiles. The board is supplied preloaded with four GSM power profiles and four DCS power profiles covering the entire power range. External timing signals can be used in place of the internal crystal controlled timing. A power ramp software package is available which allows the user to create power control ramps. LTC4403 Control Loop Stability There are several factors that can improve or degrade loop frequency stability. 1) The additional voltage gain supplied by the RF power amplifier increases the loop gain, raising poles normally U below the 0dB axis. The extra voltage gain can vary significantly over input/output power ranges, frequency, power supply, temperature and manufacturer. RF power amplifier gain control transfer functions are often not available and must be generated by the user. Loop oscillations are most likely to occur in the midpower range where the external voltage gain associated with the RF power amplifier typically peaks. It is useful to measure the oscillation or ringing frequency to determine whether it corresponds to the expected loop bandwidth and thus is due to high gain bandwidth. 2) Loop voltage losses supplied by the coupler network will improve phase margin. The larger the coupler loss the more stable the loop will become. However, larger losses reduce the RF signal to the LTC4403-X and detector performance may be degraded at low power levels. (See RF Detector Characteristics.) 3) Additional poles within the loop due to filtering or the turn-on response of the RF power amplifier can degrade the phase margin if these pole frequencies are near the effective loop bandwidth frequency. Generally loops using RF power amplifiers with fast turn-on times have more phase margin. Extra filtering below 16MHz should never be placed within the control loop, as this will only degrade phase margin. 4) Control loop instability can also be due to open loop issues. RF power amplifiers should first be characterized in an open loop configuration to ensure self oscillation is not present. Self-oscillation is often related to poor power supply decoupling, ground loops, coupling due to poor layout and extreme VSWR conditions. The oscillation frequency is generally in the 100kHz to 10MHz range. Power supply related oscillation suppression requires large value ceramic decoupling capacitors placed close to the RF power amp supply pins. The range of decoupling capacitor values is typically 1nF to 3.3µF. 5) Poor layout techniques associated with the coupler network may result in high frequency signals bypassing the coupler. This could result in stability problems due to the reduction in the coupler loss. 4403 F01 W UU 4403f 7 LTC4403-1/LTC4403-2 APPLICATIO S I FOR ATIO Determining External Loop Gain and Bandwidth The external loop voltage gain contributed by the RF channel and coupler network should be measured in a closed loop configuration. A voltage step is applied to PCTL and the change in VPCA (or VPCB) is measured. The detected RF voltage is 0.6 • PCTL and the external voltage gain contributed by the RF power amplifier and coupler network is 0.6 • ∆VPCTL/∆VVPCA. Measuring voltage gain in the closed loop configuration accounts for the nonlinear detector gain that is dependent on RF input voltage and frequency. The LTC4403-X unity gain bandwidth specified in the data sheet assumes that the net voltage gain contributed by the RF power amplifier and coupler network is unity. The bandwidth is calculated by measuring the rise time between 10% and 90% of the voltage change at VPCA or VPCB for a small step in voltage applied to PCTL. BW1 = 0.35/rise time The LTC4403-X control amplifier unity gain bandwidth (BW1) is typically 250kHz. For PCTL