LTC4425EMSEPBF

Electrical Specifications Subject to Change FEATURES n n n n n n n n n n n LTC4425 Linear SuperCap Charger with Current-Limited Ideal Diode and V/I Monitor DESCRIPTION The LTC®4425 is a constant-current/constant-voltage linear charger designed to charge a 2-cell supercap stack from either a Li-Ion/Polymer battery, a USB port, or a 2.7V to 5.5V current-limited supply. The part operates as an ideal diode with an extremely low 50mΩ on-resistance making it suitable for high peak-power/low average power applications. The LTC4425 charges the output capacitors to an externally programmed output voltage in LDO mode at a constant charge current, or to VIN in normal mode with a smart charge current profile to limit the inrush current until the VIN to VOUT differential is less than 250mV. In addition the LTC4425 can be set to clamp the output voltage to 4.9V or 5.4V. Charge current (VOUT current limit) is programmed by connecting a resistor between PROG and GND. The voltage on the PROG pin represents the current flowing from VIN to VOUT for current monitoring. An internal active balancing circuit maintains equal voltages across each supercapacitor and clamps the peak voltage across each cell to a pin-selectable maximum value. The LTC4425 operates at a very low 20μA quiescent current (shutdown current 750mV RPROG = 5k, VIN – VOUT < 250mV RPROG = 5k, VIN – VOUT > 750mV VIN = VOUT VIN = VOUT EN = 0 3 15 50 l μA mV mΩ Ideal Diode Supercap Charger VFB IFB ICHG 1.18 1.2 100 2 0.2 2 0.2 200 20 1.00 1000 VIN – VOUT < 250mV VIN – VOUT > 750mV PROG Pin Shorted to GND, FB = 0 FB = 0 VOUT = 0, FB = 0, RPROG = 0.5k 2 1.00 0.1 3 1.5 105 4 1.22 V nA A A A A mA mA V mA/mA V V A ms °C VPROG hPROG VPROG ISC tSS TLIM PROG Pin Servo Voltage in LDO Mode Ratio of Charge Current to PROG Pin Current PROG Pin Servo Voltage in Normal Mode (FB = VIN) Charger Short-Circuit Current Limit Charger Soft Start Time Junction Temperature in Constant Temperature Mode (Note 5) Maximum Voltage Across the Top Capacitor Maximum Voltage Across the Bottom Capacitor FB < 1.2V Voltage Clamps VCLAMP VSEL = Lo VSEL = Hi VSEL = Lo VSEL = Hi If Either Capacitor Reaches Clamp Voltage i.e. VOUT < VIN RPROG = 1k, (VOUT – VMID) > VCLAMP RPROG = 1k, VMID > VCLAMP l l l l 2.45 2.7 2.45 2.7 50 160 140 2.5 2.75 2.5 2.75 V V V V mV mA mA VRIP ISH(TOP) ISH(BOT) VOUT Clamp Hysteresis Top Shunt Current Bottom Shunt Current 4425p 3 LTC4425 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Leakage Balancer VMID VMID Output Voltage VMID Maximum Current Sourcing Capability VMID Maximum Current Sinking Capability PFO, PFI_RET, PFI Output Low Voltage (PFO, PFI_RET) Pin Leakage Current (PFO, PFI_RET) FB Threshold Voltage for Power Good (Rising) VPFI IPFI PFI Threshold (Falling) PFI Hysteresis PFI Pin Input Leakage Power Good Timer Delay Logic Inputs (EN, SEL) VIL VIH IIH IIL Logic Low Input Voltage Logic High Input Voltage Input Current High Input Current Low EN, SEL Pins at 5.5V EN, SEL Pins at GND l l l l The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = TJ = 25°C, VIN = 3.8V. (Note 4) CONDITIONS VOUT = 3.6V VMID < VOUT/2 , VMID < VCLAMP VMID > VOUT/2 , VMID < VCLAMP IPIN = 5mA VPIN = 5V, EN = 0 LDO Mode l l MIN 1.76 TYP 1.8 0.7 1.2 65 MAX 1.84 UNITS V mA mA 100 1 1.13 1.22 mV μA V mV V mV nA ms 1.09 1.18 1.11 265 1.2 10 100 200 Input-to-Output Differential for Power Good (Rising) Normal Mode 0.4 1.2 –1 –1 1 1 V V μA μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The current limit features of this part are intended to protect the IC from short term or intermittent fault conditions. Continuous operation above the maximum specified pin current rating may result in device degradation or failure. Note 3: Failure to solder the exposed backside of the package to the PC board ground plane will result in a thermal resistance much greater than 43°C/W on the DD package and greater than 35°C C/W on MSE package. Note 4: The LTC4425E (E grade) is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC4425I (I grade) is guaranteed over the full –40°C to 125°C operating junction temperature range. The junction temperature, TJ, is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: TJ = TA + (PD • θJA °C/W). Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated thermal package thermal resistance and other environmental factors. Note 5: VIN to VOUT charge current is reduced by thermal foldback as junction temperature approaches 105°C. 4425p 4 LTC4425 TYPICAL PERFORMANCE CHARACTERISTICS LDO Regulation Voltage vs Charge Current 3.295 3.290 3.285 VOLTAGE (V) 3.280 3.275 3.270 3.265 VIN = 3.8V, IOUT = 10mA 3.260 RPROG = 1k VOUT SET FOR 3.3V 3.255 200 400 600 800 0 IOUT (mA) 3.286 LDO Regulation Voltage vs Temperature VIN = 3.8V 3.285 VOUT SET FOR 3.3V ON-RESISTANCE (mΩ) 3.284 3.283 VOUT (V) 3.282 3.281 3.280 3.279 3.278 1000 1200 3.277 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 80 70 Charger FET On-Resistance vs Supply 90°C 60 25°C 50 40 30 20 10 0 2.7 3 3.3 3.6 3.9 4.2 INPUT VOLTAGE (V) 4.5 4.8 –45°C 3586 G35 4425 G02 4425 G03 Charge Current vs (VIN–VOUT) Differential 1200 1000 CHARGE CURRENT (mA) PROG VOLTAGE (mV) LDO MODE (FB GROUNDED) 800 600 400 200 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VIN TO VOUT DIFFERENTIAL (V) 4425 G04 PROG Pin Voltage vs (VIN – VOUT) Differential 1200 1000 LDO MODE (FB GROUNDED) CURRENT (μA) 800 NORMAL MODE 600 400 200 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VIN TO VOUT DIFFERENTIAL (V) 4425 G05 VIN Quiescent Current vs Supply and Temperature (VIN ≥ VOUT) 25 VIN = 3.8V VIN = 3.8V RPROG = 1k VIN = 3.8V RPROG = 1k 20 15 VIN = 2.7V 10 NORMAL MODE 5 0 –45 –25 –5 15 35 55 TEMPERATURE (°C) 75 4425 G06 Charge Current vs Temperature in Thermal Regulation 1200 1000 CHARGE CURRENT (mA) CHARGE CURRENT (mA) 800 600 400 200 0 –45 –30 –15 0 15 30 45 60 75 90 105 120 TEMPERATURE (°C) 4425 G07 Charge Current vs VOUT in Thermal Regulation 3000 VIN = 5V PROG PIN SHORTED TO GND 2500 FB PIN SHORTED TO GND AMBIENT TEMP 24°C CURRENT (μA) 2000 1500 1000 500 THERMAL REGULATION ON-CHIP POWER DISSIPATION ~4W CASE TEMP ~100°C 0 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE (V) 20 18 16 14 12 10 8 6 4 2 4 4.5 VOUT Quiescent Current vs VOUT and Temperature (VIN ≥ VOUT) VIN < VOUT VIN = 3.8V VIN = 3.8V, VOUT = 3.5V RPROG = 1k, FB GROUNDED VOUT = 2.7V 0 –45 –25 –5 15 35 55 TEMPERATURE (°C) 75 4425 G09 4425 G08 4425p 5 LTC4425 TYPICAL PERFORMANCE CHARACTERISTICS Logic Inputs (EN and SEL) Threshold Voltage vs Temperature 0.9 0.8 0.7 RESISTANCE (Ω) VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 –45 –25 –5 15 35 55 TEMPERATURE (°C) 75 4425 G10 Open Drain Outputs (PFI_RET and PFO) FET On-Resistance vs Temperature 18 16 2.95 14 CHARGE CURRENT (A) 12 10 8 6 4 2.75 2 0 –45 –25 –5 15 35 55 TEMPERATURE (°C) 75 4425 G11 PROG Pin Short Circuit Charge Current vs Temperature 3.00 VIN = 3.8V VOUT = 3.3V PROG PIN SHORTED TO GND VIN = 3.8V VIN = 3.8V 2.90 2.85 2.80 2.70 –45 –25 –5 15 35 55 TEMPERATURE (°C) 75 4425 G011a Charge Current vs Voltage Across Top Capacitor (VOUT – VMID) 3500 3000 CHARGE CURRENT (mA) CHARGE CURRENT (mA) 2500 2000 1500 1000 500 VIN = 3.8V VOUT = 3.4V SEL = 0 0 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 VOUT TO VMID (V) 4425 G12 Charge Current vs Voltage Across Bottom Capacitor (VMID) 3500 3000 Output Voltage Transient Step Response Waveform (LDO Mode) PROG PIN GROUNDED 2500 2000 1500 1000 500 VIN = 3.8V VOUT = 3.4V SEL = 0 0 1.6 1.7 1.8 1.9 PROG PIN GROUNDED VOUT 20mV/DIV (AC-COUPLED) ILOAD 800mA 100mA 500μs/DIV VIN = 3.8V RPROG = 500Ω SUPERCAP VALUE = 0.55F 2 2.1 2.2 2.3 2.4 2.5 VMID (V) 4425 G13 4425 G14 RPROG = 1k Output Voltage Waveform When VMID is Shorted to GND VIN = 3.8V RPROG = 1k Output Voltage Waveform When VMID is Shorted to VOUT PROG Pin Soft-Start Waveform (Normal Mode) VOUT (1V/DIV) VOUT 20mV/DIV AC-COUPLED VOUT 20mV/DIV AC-COUPLED EN VIN = 3.8V RPROG = 1k 250ms/DIV SUPERCAP VALUE = 0.55F 4425 G16 VIN = 3.8V RPROG = 1k 100ms/DIV SUPERCAP VALUE = 0.55F 4425 G15 VIN = 5V RPROG = 1k 500μs/DIV 4425 G18 4425p 6 LTC4425 PIN FUNCTIONS VOUT (Pin 1, 2): Output Pin of the Charger. Typically connects to the top of the 2-cell supercap stack. PROG (Pin 3): Charge Current Program and Charge Current Monitor Pin. A resistor connected from PROG to ground programs the charge current. In LDO mode, this pin always servos to 1V. However, if the charge current profile is turned on, this pin servos to a voltage between 1V and 0.1V depending on the input-to-output differential. In all cases, the voltage on this pin always represents the actual charge current. SEL (Pin 4): Logic Input to Select One of the Two Possible Clamp Voltages (VCLAMP). If the pin is a logic low, the maximum voltage across any supercap of the stack is 2.45V. If the pin is a logic high, it is 2.7V. Do not float this pin. FB (Pin 5): In LDO mode, output voltage is programmed by a resistor divider from VOUT via the FB pin. In this mode, the voltage on this pin always servos to the internal reference voltage of 1.2V. If the FB pin is pulled up to VIN , the LDO mode is disabled and the charge current profile mode is turned on. Do not float this pin. EN (Pin 6): Digital Input to Enable the Charger. If this pin is a logic high, the part is enabled and it draws only 20μA of quiescent current from the input or output when idle. If this pin is a logic low, the part is in shutdown mode and draws less than 2μA. Do not float this pin. PFI_RET (Pin 7): This pin connects to the bottom of the external resistor divider for the input power-fail comparator. In shutdown mode, an internal switch opens up this path to reduce the current drawn by the resistor divider. PFO (Pin 8): Open Drain Output of the Power-Fail Comparator. This pin is driven to logic low if at least one of the following conditions is true: (1) VIN is less than a value programmed by an external divider via PFI, (2) VOUT has not reached within 7.5% of its final programmed value in LDO mode, or (3) VOUT is not within 250mV of VIN in charge current profile mode. When all these conditions are false for at least 200ms, this pin goes high impedance indicating that power is good. PFI (Pin 9): Input to the Power-Fail Comparator. The input voltage below which PFO pin indicates a power-fail condition can be programmed by connecting this pin to an external resistor divider between VIN and PFI_RET pin. VMID (Pin 10): Connects to the Midpoint of the 2-Cell supercap stack. An internal leakage balancing amplifier drives this pin to a voltage which is exactly half of VOUT. VIN (Pin 11, 12): Input Power Pin. Typically connected to a DC source like a Li-Ion/Polymer battery or a USB port. GND (Exposed Pad Pin 13): GND. The Exposed Pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the part to achieve optimum thermal conduction. 4425p 7 LTC4425 BLOCK DIAGRAM VIN VOUT VIN – 15mV 1.2V BANDGAP 1.11V REFERENCE 0.1V + – MPSNS 1 MPSW 1000 VOUT IDEAL DIODE CONTROLLER PSHUNT CBIG VMID CONSTANT-VOLTAGE/ CONSTANT-CURRENT/ CONSTANT-TEMPERATURE CHARGER CIRCUITRY VOLTAGE CLAMP CIRCUITRY CHARGE CURRENT PROFILE GENERATOR CHARGE CURRENT 10X R NSHUNT CBIG 1X VOUT/2 250mV 150mV VIN – VOUT R VIN – VOUT COMPARATOR VIN RPF1 VOUT + 250mV PFI 1.2V PFI_RET LEAKAGE BALANCER VSEL VIN + – + PFC – OSCILLATOR + – 1.11V 2.7V 2.45V PROG PGOOD COMPARATOR 200ms TIMER + – LBA RPROG RPF2 PFI COMPARATOR RFB1 FB EN RFB2 PFO GND 4425 BD Figure 1. LTC4425 Block Diagram 4425p 8 LTC4425 OPERATION The LTC4425 is a linear charger designed to charge a two-cell supercap stack by employing a constant-current, constant-voltage, and constant-temperature architecture. It has two modes of operation: charge current profile mode (also referred to as normal mode) and LDO mode. In LDO mode, the LTC4425 charges the top of the stack to an externally programmed output voltage with a fixed charge current that is also externally programmable. In charge current profile mode, the LTC4425 charges the top of the stack to the input voltage VIN with a charge current that varies based on the input-to-output differential voltage. LDO Mode In LDO mode, the output voltage VOUT is programmed by an external resistor divider network consisting of RFB1 and RFB2 via the FB pin and the charge current is programmed by an external resistor RPROG via the PROG pin. Please refer to the Block Diagram shown in Figure 1. The charger control circuitry consists of a constantcurrent amplifier and a constant-voltage amplifier. When the part is enabled to charge a discharged supercap stack, initially the constant-current amplifier is in control and servos the PROG pin voltage to 1V. The current through the PROG resistor gets multiplied by approximately 1000, the ratio of the sense MOSFET (MPSNS) and the power MOSFET (MPSW), to charge the supercap stack. As the output voltage VOUT gets close to the programmed value, the constant-voltage amplifier takes over and backs off the charge current as necessary to maintain the FB pin voltage equal to an internal reference voltage of 1.2V. Since the PROG pin current is always about 1/1000 of the charge current, the PROG pin voltage continues to give an indication of the actual charge current even when the constant-voltage amplifier is in control. Charge Current Profile or Normal Mode The LTC4425 is in charge current profile mode when the FB pin is shorted to the input voltage VIN . In this mode of operation, the constant-voltage amplifier is internally disabled but the charge current is still programmed by the external RPROG resistor. The charger provides 1/10 of the programmed charge current if the input-to-output voltage differential (VIN–VOUT) is more than 750mV to limit the power dissipation within the chip. As this differential voltage decreases from 750mV, the charge current increases linearly to its full programmed value when VOUT is within 250mV or closer to VIN . As VOUT rises further, the voltage across the charger FET gets too small to support the full charge current. So the charge current gradually falls off and the charger FET enters into its triode (ohmic) region of operation (see Figure 2). Since the charger FET RDS(ON) is approximately 50mΩ, with a programmed charge current of 2A, the FET will enter the ohmic (triode) region and the charge current will start to fall off when VOUT is within about 100mV of VIN . IDEAL DIODE CONTROL REGION 2A CHARGE CURRENT (A) OHMIC REGION FULL CHARGE CURRENT REGION LINEAR CHARGE CURRENT REGION 1/10 CHARGE CURRENT REGION 0.2A 0.3A 15 100 250 VIN – VOUT (mV) 750 4425 F02 Figure 2. Different Regions of Charge Current Profile The Ideal Diode Controller When the input-to-output differential approaches 15mV, the ideal diode controller takes over the control from the constant-current amplifier and backs off the charge current by pulling up the gate of the charger FET as much as necessary to maintain a 15mV delta across the FET (see Figure 2). As a result, VOUT can only be charged to 15mV below VIN. In the event VIN suddenly drops below VOUT, the controller will quickly turn the FET completely off to prevent any loss of charge due to the reverse flow of charge from the supercap back to the supply. 4425p 9 LTC4425 OPERATION Thermal Regulation In either mode, if the die temperature starts to approach 105°C due to internal power dissipation, a thermal regulator limits the die temperature to approximately 105°C by reducing the charge current. Even in thermal regulation, the PROG pin continues to give an indication of the charge current. The thermal regulation protects the LTC4425 from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without the risk of damaging the LTC4425 or the external components. Another benefit of this feature is that the charge current can be set according to typical, rather than worst-case, ambient temperatures for a given application with the assurance that the charger will automatically reduce the charge current in worst-case conditions. Voltage Clamp Circuitry The LTC4425 is equipped with circuitry to limit the voltage across any supercap of the stack to a maximum allowable voltage VCLAMP. There are two preset voltages, 2.45V or 2.7V, for VCLAMP selectable by the SEL pin. The SEL pin should be set to logic low for lower VCLAMP voltage of 2.45V and to logic high for the higher VCLAMP voltage of 2.7V. If the voltage across the bottom capacitor, i.e., the VMID pin voltage reaches VCLAMP first, an NMOS shunt transistor turns on and starts to bleed charge off of the bottom capacitor to GND. Similarly, if the voltage across the top capacitor, VTOP, reaches the VCLAMP voltage first, a PMOS shunt transistor turns on and starts to bleed charge off of the top capacitor to the bottom one. When the voltage across any of the supercaps reaches within 50mV of VCLAMP, a transconductance amplifier starts to cut back the charge current linearly. By the time any of the shunt devices are on, the charge current gets reduced to 1/10 of the programmed value and stays at this reduced level as long as the shunt device is on. This is to prevent the shunt devices from getting damaged by excessive heat. The comparators that control the shunt devices have a 50mV hysteresis meaning that when the voltage across either capacitor is reduced by 50mV, the shunt devices turn off and normal charging resumes with full charge current unless limited by any of the other amplifiers controlling the gate of the charger FET. In the event Short-Circuit Current Limit In the event the PROG pin gets shorted to GND, the LTC4425 limits the PROG pin current to approximately 3mA which, in turn, limits the maximum charge current to about 3A. While in short-circuit, if one of the supercaps approaches within 50mV of its maximum allowable voltage, VCLAMP, a current-limit foldback circuit cuts back the short-circuit current limit to approximately 1/10 of its full value or to about 300mA. Supply Status Monitor The LTC4425 includes an input power-fail comparator, PFC, which monitors the input voltage VIN via the PFI pin. At anytime, if VIN falls below a certain externally program-mable threshold, it reports the undervoltage situation by pulling down the open-drain output PFO low. This under-voltage threshold is programmed by connecting an external resistor divider network (consisting of RPF1 andRPF2) between VIN and the PFI_RET pins. When the part is enabled, a low RDS(ON) (approx. 13Ω) internal pull-down transistor pulls the bottom end of RPF2 , i.e., the PFI_RET pin to GND to complete the divider network. When the part is disabled, this transistor opens RPF2 from GND, thereby saving the current drawn by the divider network. The power-fail comparator has a built-in filter to reject any transient supply glitch that is less than 10μS long. 4425p both capacitors exceed their maximum allowable voltage, VCLAMP, the main charger FET completely shuts off and both shunt devices turn on. Both shunt devices are actually current mirrors guaranteed to shunt more current away than that coming through the charger FET. Leakage Balancing Circuitry The LTC4425 is equipped with an internal leakage balancing amplifier, LBA, which servos the midpoint, i.e., VMID pin voltage, to exactly half of the output voltage, VOUT . However it has a very limited source and sink capability of approximately 1mA. It is designed to handle slight mismatch of the supercaps due to leakage currents; not to correct any gross mismatch due to defects. The balancer is only active as long as there is an input present. The internal balancer eliminates the need for external balancing resistors. 10 LTC4425 OPERATION Output Status Monitor The LTC4425 has an internal comparator to always monitor the output voltage VOUT . At any time, if VOUT falls below 7.5% of its final programmed value in LDO mode or more than 250mV below the input voltage VIN in charge current profile mode, the comparator reports the power-fail condition by pulling the same open-drain output PFO low. When both input and output voltages are good for at least 200ms, the PFO pin goes high impedance and can be pulled up to any external supply by a resistor to indicate a power good situation. In normal mode, the load should not exceed 1/10th of the programmed charge current until PFO is high. VOUT > VIN Operation If for some reason VIN falls below VOUT or the input is not present and the EN pin is pulled high, most of the circuitry including the voltage clamp circuitry is kept alive and the part draws about 20μA from the output capacitors. However, the internal leakage balancer is turned off under this condition. Shutdown Mode The LTC4425 can be shut down by pulling the EN pin low. In shutdown mode, very minimal circuitry is alive and the part draws less than 2μA from the supply or from the output capacitors if the supply is not present. Charge Current Soft-Start The LTC4425 includes a soft-start circuit to minimize the inrush current at the start of a charge cycle. When a charge cycle is initiated, the charge current ramps from zero to full-scale over a period of approximately 1ms and this soft-start can be monitored by observing the PROG pin voltage. This has the effect of minimizing the transient current load on the power supply during start-up. Thermal Shutdown The LTC4425 includes a thermal shutdown circuit in addition to the thermal regulator. If for any reason, the die temperature exceeds 160°C, the entire part shuts down. It resumes normal operation once the temperature drops by about 14°C, to approximately 146°C. 4425p 11 LTC4425 APPLICATIONS INFORMATION Programming the Output Voltage In LDO mode, the LTC4425 output voltage can be programmed for any voltage between 2.7V and VIN by using a resistor divider from VOUT pin to GND via the FB pin such that: VOUT = VFB • (1 + RFB1/RFB2) where VFB is 1.2V. See Figure 3. Typical values for RFB are in the range of 40k to 1M. Too small a resistor will result in a large quiescent current whereas too large a resistor coupled with FB pin capacitance will create an additional pole and may cause loop instability. VIN RPF1 VIN VOUT VOUT RFB1 PROG pin. The program resistor and the charge current are calculated using the following equations: RPROG = 1000 • (1V/ICHRG), ICHRG = 1000 • (1V/RPROG) where ICHRG is the charge current out of the VOUT pin. The charge current out of the VOUT pin can be determined at any time by monitoring the PROG pin voltage and using the following equation: ICHRG = 1000 • (VPROG /RPROG) Stability Considerations In LDO mode, the LTC4425 supercapacitor charger has two principal control loops: constant-voltage and constant-current. The constant-voltage loop is stable when con-nected to a supercap of at least 0.2F. However, when disconnected from the supercap, the voltage loop requires at least 10μF capacitance in series with 500Ω resistance for stability. In constant-current mode, the PROG pin voltage is in the feedback loop, not the VOUT pin voltage. Because of the additional pole created by the PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capacitance on the PROG pin, the charger is stable with a program resistor as high as 100k. However, any additional capacitance on this node reduces the maximum allowed program resistor. The pole frequency at the PROG pin should be kept above 100kHz. Therefore, if the PROG pin is loaded with a capacitance, CPROG , the following equation should be used to calculate the maximum resistance value for RPROG: RPROG ≤ 1/(2π • 100kHz • CPROG) Board Layout Considerations To be able to deliver maximum charge current under all conditions, it is critical that the exposed metal pad on the backside of the LTC4425’s package has a good thermal contact to the PC board ground. Correctly soldered to a 2500mm2 double-sided 1 oz. copper board, the part has a thermal resistance of approximately 43°C/W. Failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in a thermal resistance far greater than 43°C/W. 4425p LTC4425 PFI FB RPF2 PFI_RET 4425 F03 RFB2 Figure 3. Programming Output Voltage and Input Threshold for Power Fail Comparator. Programming the Input Voltage Threshold for Power Fail Status Indicator The input voltage below which the power fail status pin PFO indicates a power-fail condition is programmed by using a resistor divider from the VIN pin to the PFI_RET pin via the PFI pin such that: VIN , PFO = VPFI • (1 + RPF1/RPF2) where VPFI is 1.2V. See Figure 3. Typical values for RPF are in the range of 40k to 1M. In shutdown mode, this divider network is disconnected from ground via the PFI_RET pin to save the quiescent current drawn by the network. Programming the Charge Current The LTC4425 charge current is programmed using a single resistor from the PROG pin to ground. The charge current out of the VOUT pin is 1000 times the current out of the 12 LTC4425 APPLICATIONS INFORMATION Charge Current Reduction by the Thermal Regulator To protect the part against excessive heat generated by internal power dissipation, the LTC4425 is equipped with a thermal regulator which automatically reduces the charge current to maintain a maximum die temperature of 105°C. Ignoring the quiescent current, the power dissipation can be approximated by the following equation: PD = (VIN – VOUT) • ICHRG If θJA is the thermal resistance and TA is the ambient temperature, then the die temperature can be calculated as: TDIE = TA + PD • θJA When the part is in thermal regulation, the die temperature is 105°C and for a given VIN and VOUT, the charge current can be determined by the following equation: ICHRG = Figure 4 shows the graph of charge current vs output voltage when the charge current profile is turned off by shorting the FB pin to GND and the charge current is limited by thermal regulation. 2.5 VIN = 5V RPROG = 500Ω TA = 25°C 2.0 JA = 43° C/W THERMAL REGULATION = 105°C 1.5 FB PIN GROUNDED THERMAL REGULATION 1.0 CHARGE CURRENT(A) 4.07V 0.5 372mA 0 1 2 3 4 OUTPUT VOLTAGE (V) 5 6 4425 F04 0 (VIN – VOUT ) • θJA 105 – TA Figure 4. Charge Current vs Output Voltage under Thermal Regulation (LDO Mode) Charging a Single Supercapacitor The LTC4425 can also be used to charge a single supercapacitor by connecting two series-connected matched ceramic capacitors with a minimum capacitance of 100μF in parallel with the supercapacitor as shown in Figure 5. Refer to Table 1 for supercapacitor manufacturers. Table 1. Supercapacitor Manufacturers CAP-XX NESS CAP Maxwell Bussmann AVX Illinois Capacitor Tecate Group www.cap-xx.com www.nesscap.com www.maxwell.com www.cooperbussmann.com www.avx.com www.illcap.com www.tecategroup.com For example, if the LTC4425 is used in LDO mode to charge a completely discharged supercap stack (VOUT = 0V) at a room temperature of 25°C from a 5V source, the charge current, at first, will be limited to approximately: ICHRG = (5 – 0) V • 43°C / W 105°C – 25°C = 80°C = 372mA 215°C / A As the output voltage rises, the charge current will gradually rise to the full charge current programmed by the PROG pin resistor as long as the constant-current loop is in control. If the LTC4425 is programmed for a charge current of 2A, the output voltage at which the part will deliver full charge current can be determined by the following equation: VOUT = VIN – 105 – TA ICHRG • θ JA LTC4425 VOUT VMID C2 GND 4425 F05 C1 VOUT CSUP Using the previous example, for full charge current, the output voltage has to rise to at least: VOUT = 5 V – (105 – 25) °C 2 A • 43°C / W = 5V – 80°C = 4.07 V 86°C / V C1 = C2 ≥ 100μF Figure 5. Charging a Single Supercapacitor 4425p 13 LTC4425 TYPICAL APPLICATIONS USB to High Peak Power 3.3V Charging USB 5V, 500mA VIN 1.5M PFI 1.2M LTC4425 PFI_RET SEL μC EN FB 1.2M 470k PFO PROG 2k 4425 TA03 3.3V VOUT 1F VMID 1F TO LOAD 2.1M 3 × AA Alkaline to High Peak Power 3.3V Charging 4.5V TO 3.6V VIN 3 AA 1.5M PFI 1.2M LTC4425 PFI_RET SEL μC EN FB 470k PFO PROG 500Ω 4425 TA04 3.3V, 2A VOUT 1F VMID 1F TO LOAD 2.1M 1.2M CURRENT MONITOR Li-Ion High Peak Power Battery Buffer VIN Li-Ion VMID SEL 1.5M EN 470k FB PFI 1.2M PFI-RET 4425 TA04a + VOUT 0.6F 0.6F TO LOAD LTC4425 PFO PROG CURRENT MONITOR 500Ω 4425p 14 LTC4425 TYPICAL APPLICATIONS High Current USB Charging with Power Path Control L1 3.3μH INSTANT-ON USB VBUS R1 100k C1 10μF 0805 D0 μC D1 D2 CHRG NTC CLPROG R2 100k R5 8.2Ω C2 0.1μF 0603 R3 2.94k R4 2k PROG C/X LTC4088 SW VOUT LDO3V3 GATE M1 C3 10μF 0805 5V VIN R7 1.5M PFI R8 1.2M PFI_RET LTC4425 VOUT LOAD CSC 0.55F HS203F VMID BAT GND + LI-Ion μC VIN FB PFO SEL EN GND PROG R6 2k 4425 TA05 L1: COILCRAFT LPS4018-332MLC M1: SILICONIX Si2333 R2: VISHAY-DALE NTHS0603N011-N1003F C1, C3: MURATA GRM21BR61A106KE19 C2: MURATA GRM188R71C104KA01 CSC: CAP-XX HS203F 3.3V Peak-Power/Back-up Supply 2.2μH 5V VIN 1.5M PFI 1.2M PFI_RET PFO LTC4425 VOUT CSC 0.55F HS203F ≈5V SW1 PVIN VIN SW2 PVOUT VOUT LTC3533 340k 6.49k 47pF FB 107k VC 4.7pF 330pF VOUT 3.3V 1.5A VMID OFF ON RUN/SS RT VIN FB 10μF 100μF BURST PROG 2k GND 33.2k SGND PGND 0.1μF 200k 200k 4425 TA05a μC SEL EN 4425p 15 LTC4425 TYPICAL APPLICATIONS 12V to 5V/3.3V High Peak Power Supply 12V D1 VIN BOOST 0.1μF 10μH SW LT3505 61.1k SHDN FB RT GND VC D2 75k 1μF 69.8k 70pF 11.3k 10μF R8 1.2M PFI_RET PFO μC SEL EN D1: 1N4148 D2: MBRM140 CSP1, CSP2: GND R6 2k 1.2M FB PFI 68pF R7 1.5M VIN LTC4425 VMID CSP2 1F 2.1M VOUT VOUT (5V) 5V 3.3V CSP1 1F HIGH PEAKPOWER LOAD PROG 4425 TA06 12V Input to 5V Outputs with Input Voltage Monitoring 12V VIN 2.2μF ON OFF RUN ILIM 28.7k GND LT3663 ISENSE VOUT 59k FB 11k 1.5M R8 1.2M PFI LTC4425 PFI_RET PFO μC SEL EN GND 4425 TA07 BOOST 0.1μF SW D1 6.8μH D1: DFLS240 CSP1, CSP2: 5V INSTANT-ON 22μF VIN FB VOUT VMID CSP1 1F CSP2 1F 5V HIGH-PEAK POWER, OR BACKUP SUPPLY PROG R6 2k 4425p 16 LTC4425 TYPICAL APPLICATIONS Redundant High Peak Power Battery Supplies USB VIN 1.5M FB PFI 1.2M PFI_RET μC USB POWER OK SEL EN PFO PROG LTC4425 1F VOUT VMID TO LOAD 1F 2k VIN 3 AA 1.5M FB PFI LTC4425 PFI_RET SEL EN VOUT VMID 1.2M 470k PFO PROG BAT POWER OK 500Ω 4425 TA08 4425p 17 LTC4425 PACKAGE DESCRIPTION DD Package 12-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1725 Rev A) 0.70 ±0.05 3.50 ±0.05 2.10 ±0.05 2.38 ±0.05 1.65 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.45 BSC 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.115 TYP 7 0.40 ± 0.10 12 3.00 ±0.10 (4 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 2.38 ±0.10 1.65 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.25 45° CHAMFER 6 0.200 REF 0.75 ±0.05 2.25 REF 0.00 – 0.05 1 0.23 ± 0.05 0.45 BSC (DD12) DFN 0106 REV A BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4425p 18 LTC4425 PACKAGE DESCRIPTION MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev B) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ± 0.102 (.112 ± .004) 2.845 ± 0.102 (.112 ± .004) 1 6 0.35 REF 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 1.651 ± 0.102 3.20 – 3.45 (.065 ± .004) (.126 – .136) 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 12 0.65 0.42 ± 0.038 (.0256) (.0165 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 12 11 10 9 8 7 0.406 ± 0.076 (.016 ± .003) REF 0.254 (.010) GAUGE PLANE DETAIL “A” 0° – 6° TYP 4.90 ± 0.152 (.193 ± .006) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) 123456 1.10 (.043) MAX 0.86 (.034) REF SEATING PLANE 0.650 NOTE: (.0256) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.22 – 0.38 (.009 – .015) TYP 0.1016 ± 0.0508 (.004 ± .002) MSOP (MSE12) 0608 REV B Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4425p 19 LTC4425 TYPICAL APPLICATION Embedded Automotive Backup Controller 6V to 36V CAR BATTERY 2.2μF ON OFF RUN BOOST L1 0.1μF 2.2μH SW VC 20k RT 330pF 28.7k PG GND FB 200k 10μF μC 4 6 BIAS 590k LT3684 D1 R8 1.2M 7 8 PFI_RET PFO SEL EN GND 13 R7 1.5M 9 VIN BD VOUT (5V) 11, 12 VIN 5 FB VMID PFI LTC4425 PROG 3 R6 500Ω 10 CSP2 1F VOUT 1, 2 5V, 2A CSP1 1F 4425 TA09 22μF SVIN PVIN, 1, 2, 3 SW1 L2 2.2μH 3.3V 20pF 750k 240k 10μF EN1 FB1 EN2 EN3 MODE RT LTC3569 (UD PACKAGE) FB2 D1: DIODES INC. DFLS240 L1: SUMIDA CDRH4D22/HP-2R2 L2: WURTH 7440430022 L3, L4 WURTH 744031002 CSP1, CSP2: PGOOD SW3 SGND PGND, 1, 2, 3 FB3 20pF L4 2.5μH 20pF SW2 L3 2.5μH 1.8V 300k 240k 4.7μF 1.2V 150k 240k 4.7μF RELATED PARTS PART NUMBER LTC3625-1 LTC3625 LT3485-0/LT3485-1/ LT3485-2/LT3485-3 LT3750 LT3751 LTC3225-1 LTC3225 DESCRIPTION 1A High Efficiency SuperCap Charger 1.4A/0.7A/1A/2A Photoflash Capacitor Charger with Output Voltage Monitor and IGBT Capacitor Charger Controller Capacitor Controller with Regulation 150mA Supercapacitor Charger COMMENTS Programmable Average Charge Current 1A, 12-Lead 3mm × 4mm DFN Package VIN; 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to 320V, 100μF VIN = 3.6V), ISD < 1μA, 3mm × 3mm 10-Lead DFN , Charges Any Size Capacitor, 10-Lead MS Package Charges Any Size Capacitor, 4mm x 5mm QFN-20 Package Programmable Supercapacitor Charger Designed to Charge Two Supercapacitors in Series to a Fixed Output Voltage (4.8V/5/3V Selectable) 4425p 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0310 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010