LTC4556EUF

LTC4556 Smart Card Interface with Serial Control FEATURES s s DESCRIPTIO s s s s s s s s s s Electrical Specifications Are ISO7816-3 and EMV Compatible Control/Status Serial Port May be Daisy-Chained for Multicard Applications Automatic Shutdown on Electrical Faults Buck Boost Charge Pump Generates 5V, 3V or 1.8V Outputs (Smart Card Classes A, B and C) Automatic Level Translation Dynamic Pull-Ups Deliver Fast Signal Rise Times* Supervisory Functions Prevent Smart Card Faults Low Operating Current: 250µA Typical VIN: 2.7V to 5.5V Ultralow Shutdown Current >10kV ESD on Smart Card Pins Small 24-Pin 4mm × 4mm QFN Package The LTC®4556 provides all necessary power control, level translation and supervisory functions for a smart card or S.A.M. card interface. The part contains a low noise charge pump** plus LDO for generating VCC power, as well as all necessary level shifting circuitry. The card voltage can be set to either 1.8V, 3V or 5V. The LTC4556 includes a card detection channel with automatic debounce circuitry. To reduce wiring costs, the LTC4556 interfaces to a microcontroller via a simple 4-wire serial interface. Multiple devices may be connected in daisychain fashion so that the number of wires to the card socket board is independent of the number of sockets. Status data is returned over the same interface. Extensive security features ensure proper deactivation sequencing in the event of a supply fault or a smart card electrical fault. The smart card pins can withstand greater than 10kV ESD in-situ with no additional components. The LTC4556 is available in a small, low profile (0.75mm), 4mm × 4mm QFN package. , LTC and LT are registered trademarks of Linear Technology Corporation. *U.S. Patent No. 6,356,140 **U.S. Patent No. 6,411,531 APPLICATIO S s s s s s s Handheld Payment Terminals Pay Telephones ATM Machines POS Terminals Computer Keyboards Multiple S.A.M. Sockets TYPICAL APPLICATIO 240k 1 10 INPUT POWER 0.1µF 1µF 8 6 21 4-WIRE COMMAND INTERFACE 22 23 24 DVCC VBATT 180k 20 UNDERV PRES LTC4556 19 GND FAULT DIN DOUT SCLK LD C8 C4 I/O RST CLK VCC 18 17 16 15 14 13 1µF 4556 TA01 SMART CARD 2 4-WIRE CARD INTERFACE 3 4 5 DATA RIN SYNC ASYNC C+ C– 11 1µF 9 CPO 12 1µF U Deactivation Sequence RST 5V/DIV CLK 5V/DIV I/O 5V/DIV VCC 5V/DIV 10µs/DIV 4556 G11.eps U U 4556f 1 LTC4556 ABSOLUTE AXI U RATI GS VBATT, DVCC, CPO, FAULT, UNDERV to GND ....................................... –0.3V to 6.0V PRES, DATA, RIN, SYNC, ASYNC, LD, DIN, SCLK to GND ............... –0.3V to (DVCC + 0.3V) I/O, CLK ....................................... –0.3V to (VCC + 0.3V) PACKAGE/ORDER I FOR ATIO TOP VIEW UNDERV PRES SCLK DOUT DIN LD 24 23 22 21 20 19 DVCC 1 DATA 2 RIN 3 SYNC 4 ASYNC 5 FAULT 6 7 NC 25 8 GND 9 10 11 12 C– VBATT C+ CPO UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS SGND. MUST BE SOLDERED TO PCB Consult LTC Marketing for parts specified with wider operating temperature ranges. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted. PARAMETER Input Power Supply VBATT Operating Voltage IVBATT Operating Current IVBATT Shutdown Current DVCC Operating Voltage IDVCC Operating Current IDVCC Shutdown Current Charge Pump ROLCP 5V Mode Open-Loop Output Resistance CPO Turn On Time VBATT = 3.075V, ICPO = ICC = 60mA, (Note 3) ICC = 0mA, 10% to 90% q q q ELECTRICAL CHARACTERISTICS CONDITIONS VCC = 5V, ICC = 0µA No Card Present, VCPO = 0V 2 U U W WW U W (Note 1) ICC (Note 5) .......................................................... 65mA VCC Short-Circuit Duration ............................... Indefinite Operating Temperature Range (Note 4) .. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 125°C ORDER PART NUMBER LTC4556EUF 18 C8 17 C4 16 I/O 15 RST 14 CLK 13 VCC UF PART MARKING 4556 MIN 2.7 TYP MAX 5.5 UNITS V µA µA V µA µA Ω ms q q q q q 250 0.5 1.7 5 0.2 8.2 0.6 400 1.75 5.5 25 1.5 17 1.5 4556f LTC4556 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted. SYMBOL Smart Card Supply VCC Output Voltage 5V Mode, 0 < ICC < 60mA 3V Mode, 0 < ICC < 50mA 1.8V Mode, 0 < ICC < 30mA ICC = 0mA, 10% to 90% Relative to Nominal Output q q q q q q ELECTRICAL CHARACTERISTICS CONDITIONS MIN 4.65 2.75 1.65 –9 60 15 TYP 5.0 3.0 1.8 0.8 –5 110 32 1 100 MAX 5.35 3.25 1.95 1.5 – 2.5 150 60 2.5 250 0.2 UNITS V V V ms % mA ms µA µs V V ns MHz VCC Turn On-Time Undervoltage Detection Overcurrent Detection Smart Card Detection Debounce Time ( Deactivation Time ( PRES to D7) q PRES Pull-Up Current RST to VCC = 0.4V) CLK (Non-Bidirectional Modes) Low Level Output Voltage (VOL), (Note 2) High Level Output Voltage (VOH), (Note 2) Rise/Fall Time, (Note 2) CLK Frequency, (Note 2) RST, C4, C8 Low Level Output Voltage (VOL), (Note 2) High Level Output Voltage (VOH), (Note 2) Rise/Fall Time, (Note 2) Low Level Output Voltage (VOL), (Note 2) High Level Output Voltage (VOH), (Note 2) Rise/Fall Time, (Note 2) Short Circuit Current, (Note 2) Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Rise/Fall Time Low Input Threshold (VIL) High Input Threshold (VIH) Input Current (IIH/IIL) DOUT Low Level Output Voltage (VOL) High Level Output Voltage (VOH) UNDERV Threshold Leakage Current VPRES = 0 ICC = 0mA, CVCC = 1µF Sink Current = – 200µA Source Current = 200µA Loaded with 50pF, 10% to 90% q q q q q q VCC – 0.2 16 10 0.2 VCC – 0.2 100 0.3 0.85 • VCC 500 5 10 0.3 0.8 • DVCC 500 0.15 • DVCC 0.85 • DVCC –1 1 0.3 DVCC – 0.3 1.17 1.23 1.29 50 Sink Current = – 200µA Source Current = 200µA Loaded with 50pF, 10% to 90% Sink Current = –1mA (VDATA = 0V or VSYNC = 0V) Source Current = 20µA (VDATA = VDVCC or VSYNC = VDVCC) Loaded with 50pF, 10% to 90% VDATA = 0V or VSYNC = 0V Sink Current = – 500µA (VI/O = 0V or VCLK = 0V) Source Current = 20µA (VI/O = VCC or VCLK = VCC) Loaded with 50pF q q q V V ns V V ns mA V V ns V V µA V V V nA I/O, CLK (CLK Specifications in Bidirectional Mode Only) q q q q DATA, SYNC (SYNC Specifications in Bidirectional Mode Only) q q q RIN, DIN, SCLK, LD, SYNC, ASYNC (SYNC Specifications for Non-Bidirectional Mode) q q q Sink Current = – 200µA Source Current = 200µA q q q VUNDERV = 3.3V q 4556f 3 LTC4556 The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBATT = 3.3V, DVCC = 3.3V unless otherwise noted. PARAMETER FAULT Low Level Output Voltage (VOL) Leakage Current Serial Port Timing tDS tDH tDD tL tH tLW tCL tLC DIN Valid to SCLK Setup DIN Valid to SCLK Hold DOUT Output Delay SCLK Low Time SCLK High Time LD Pulse Width SCLK to LD LD to SCLK CLOAD = 15pF 8 8 15 50 50 50 50 0 60 ns ns ns ns ns ns ns ns Sink Current = – 200µA VFAULT = 5.5V q q ELECTRICAL CHARACTERISTICS CONDITIONS MIN TYP 0.005 MAX 0.3 1 UNITS V µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This specification applies to all three smart card voltage classes: 1.8V, 3V and 5V. Note 3: ROLCP ≡ (2VBATT – VCPO)/ICPO; VCPO will depend upon total load (ICC) and minimum supply voltage VBATT. See Figure 6. Note 4: The LTC4556E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 5: Based on long term current density limitation. TYPICAL PERFOR A CE CHARACTERISTICS No Load Supply Current vs VBATT 500 SHORT-CIRCUIT CURRENT (mA) TA = 25°C ICC = 0µA 6.0 DVCC = VBATT = 3.3V VCC = 5V OUTPUT RESISTANCE (Ω) 9 400 SUPPLY CURRENT (µA) 300 VCC = 5V VCC = 3V 200 VCC = 1.8V 100 0 2.7 3.1 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 3.5 4 UW 5.5 4556 G01 I/O and CLK Short-Circuit Current vs Temperature (CLK in Bidirectional Mode) 10 Charge Pump Open-Loop Output Resistance vs Temperature (2VBATT – VCPO) / ICPO VBATT = 2.7V VCPO = 4.9V 5.5 5.0 CLK I/O 8 4.5 7 4.0 3.5 –40 –15 10 35 TEMPERATURE (°C) 60 85 4556 G02 6 –40 –15 10 35 TEMPERATURE (°C) 60 85 4556 G03 4556f LTC4556 TYPICAL PERFOR A CE CHARACTERISTICS VCC Overcurrent Shutdown Threshold vs Temperature 140 VBATT = 3.3V 130 LOAD CURRENT (mA) 120 VCC = 5V, CPO = 5.5V 110 100 90 80 –40 VCC = 3V, CPO = 5.5V VCC = 1.8V, CPO = 4V DEBOUNCE TIME (ms) 45 I/O LOW OUTPUT VOLTAGE (mV) –15 10 35 TEMPERATURE (°C) Extra Input Current vs Load Current (IBATT – 2ICC) 6 5 4 3 2 1 0 0.01 VBATT = 3.3V TA = 25°C EXTRA INPUT CURRENT (mA) SUPPLY CURRENT (µA) 2.0 TA = 25°C 1.5 1.0 0.5 0 2.7 TA = – 40°C SUPPLY CURRENT (µA) 0.1 1 10 LOAD CURRENT (mA) Charge Pump and LDO Activation RST 5V/DIV VCPO 5V/DIV VCC 5V/DIV I/O 5V/DIV 1ms/DIV 4556 G10 UW 60 85 4556 G04 Card Detection Debounce Time vs VBATT Supply Voltage 50 TA = 85°C TA = 25°C TA = – 40°C 200 Bidirectional Channel (I/O) Low Output Level vs Temperature VDATA = VSYNC = 0V IOL = – 1mA VBATT = 3V 175 VCC = 1.8V 40 150 VCC = 3V, 5V 35 125 30 25 2.7 3.1 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 3.5 5.5 100 –40 –15 10 35 TEMPERATURE (°C) 60 85 4556 G06 4556 G05 VBATT Shutdown Current vs Supply Voltage 3.0 VDVCC = VBATT 2.5 DVCC Shutdown Current vs Supply Voltage 1.0 VBATT = VDVCC 0.8 TA = 25°C 0.6 0.4 TA = – 40°C TA = 85°C TA = 85°C 0.2 100 4556 G07 3.1 3.9 4.3 4.7 5.1 VBATT SUPPLY VOLTAGE (V) 3.5 5.5 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VDVCC SUPPLY VOLTAGE (V) 5.5 4556 G08 4556 G09 Deactivation Sequence Data – I/O Channel CLK 5V/DIV I/O 5V/DIV VCC 5V/DIV I/O 2V/DIV DATA 2V/DIV 10µs/DIV 4556 G11.eps 100ns/DIV 4556 G12 4556f 5 LTC4556 PI FU CTIO S DVCC (Pin 1): Power. Reference voltage for the control logic. DATA (Pin 2): Input/Output. Microcontroller side data I/O pin. The DATA pin provides the bidirectional communication path to the smart card. The card may be selected to communicate via the DATA pin. If several LTC4556s are connected in parallel, the DATA pin can be made high impedance by selecting neither card socket. The C4 and C8 synchronous card pins can be selected to connect to the DATA pin via the serial port (see Table 4). RIN (Pin 3): Input. The RIN pin supplies the RST signal to the smart card. It is level shifted and transmitted directly to the RST pin of a selected card. When the card is deselected, the RST pin is latched at its current state. SYNC (Pin 4): Input-Input/Output. The SYNC pin provides the clock input for synchronous smart cards. When a synchronous card is selected, its CLK pin follows SYNC directly. When a synchronous card is deselected, the CLK pin is latched at its current state. In bidirectional mode, the SYNC pin becomes an input/output with the smart card CLK pin. ASYNC (Pin 5): Input. The ASYNC pin provides the clock input for asynchronous cards and should be connected to a free running clock. The clock signal to the smart card can be a ÷1, ÷2, ÷4 or ÷8 version of the signal on ASYNC. Asynchronous cards can also be placed in clock stop mode with the clock stopped either high or low. FAULT (Pin 6): Output. The FAULT pin can be used as an interrupt to a microcontroller to indicate when a fault has occurred. It is an open drain output, which is logically equivalent to D4 . (See Table 1) NC (Pin 7): No Connection to chip. May be grounded. GND (Pin 8): Ground. Power ground for the chip. This pin should be connected directly to a low impedance ground plane. C –, C + (Pins 9, 11): Charge Pump. Charge pump flying capacitor pins. A 1µF X5R or X7R ceramic capacitor should be connected from C + to C –. VBATT (Pin 10): Power. Supply voltage for analog and power sections of the LTC4556. CPO (Pin 12): Charge Pump. CPO is the output of the charge pump. When the smart card requires power, the charge pump will charge CPO to either 3.7V or 5.35V depending on what smart card voltage is required. A low impedance 1µF X5R or X7R ceramic capacitor is required on CPO. VCC (Pin 13): Card Socket. The VCC pin should be connected to the VCC pin of the smart card socket. The activation of the VCC pin is controlled by the serial port (see Tables 1 and 2) and can be set to 0V, 1.8V, 3V or 5V. CLK (Pin 14): Card Socket. The CLK pin should be connected to the CLK pin of the smart card socket. The CLK signal can be derived from either the SYNC input or the ASYNC input depending on which type of card is being accessed. The card type is selected via the serial port (see Tables 1 and 3). In bidirectional mode, the CLK pin becomes an input/output with the microcontroller side SYNC pin. RST (Pin 15): Card Socket. This pin should be connected to the RST pin of the smart card socket. The RST signal is derived from the RIN pin. When the card is selected, its RST pin follows RIN. When the card is deselected, the RST pin holds the current value on RIN. I/O (Pin 16): Card Socket. The I/O pin connects to the I/O pin of the smart card socket. When the smart card is selected, its I/O pin connects to the DATA pin. When the smart card is deselected, its I/O pin returns to the idle state (H). C4, C8 (Pins 17, 18): Card Socket. These pins connect to the C4 and C8 pins of synchronous memory cards on the smart card socket. The signal for these pins is unidirectional and can only be sent to the card. Data for C4 and C8 is transmitted via the DATA pin and may be selected in place of I/O via the serial port (see Table 4). When either C4 or C8 is selected, it will follow the DATA pin. When it is deselected, it will remain latched at its current state. PRES (Pin 19): Card Socket. The PRES pin is used to detect the presence of a smart card. It should be connected to a normally open detection switch on the smart card acceptor’s socket. This pin has a pull-up current source on-chip so no external components are required. 4556f 6 U U U LTC4556 PI FU CTIO S UNDERV (Pin 20): Input. The UNDERV pin provides security by supplying a precision undervoltage threshold for external supply monitoring. An external resistive voltage divider programs the desired undervoltage threshold. Once UNDERV falls below 1.23V, the LTC4556 automatically begins the deactivation sequence. If external supply monitoring is not required, the UNDERV pin should be connected to either VBATT or DVCC. DIN (Pin 21): Input. Input for the serial port. Command data is shifted into DIN synchronously with SCLK. DIN can be connected directly to a microcontroller or the DOUT pin of another LTC4556 or LTC1955 for daisy chained operation. DOUT (Pin 22): Output. Output for the serial port. Smart card status data is shifted out of DOUT synchronously with SCLK. DOUT can be connected directly to a microcontroller or the DIN pin of another LTC4556 or LTC1955 for daisy chained operation. SCLK (Pin 23): Input. The SCLK pin clocks the serial port. Each new data bit is received on the rising edge of SCLK. SCLK should be left high during idle times and should not be clocked when LD is low. LD (Pin 24): Input. The falling edge of this pin loads the current state of the shift register into the command register. Command changes to the smart card will be updated on the falling edge of LD. The rising edge of LD latches status information into the shift register for the next read/ write cycle. SGND (Pin 25): Exposed Pad. Must be soldered to PCB Ground. BLOCK DIAGRA W U U U CHARGE PUMP C+ 11 C– 9 GND 8 VBATT 10 CPO 12 CHARGE PUMP LDO 13 VCC 16 I/O 17 C4 DATA 2 ASYNC 5 SMART CARD COMMUNICATIONS SYNC 4 CLOCK CONTROL LOGIC RESET CONTROL LOGIC τ 18 C8 SMART CARD SOCKET 14 CLK RIN 3 15 RST 19 PRES 6 STATUS DATA FAULT DIN 21 SERIAL PORT COMMAND/STATUS DATA DOUT 22 SCLK 23 LD 24 SHIFT REGISTER 1 DVCC DIGITAL SUPPLY – COMMAND LATCH 20 UNDERV + 1.23V + – 4556 BD 4556f 7 LTC4556 OPERATIO Serial Port The microcontroller compatible serial port provides all of the command and control inputs for the LTC4556 as well as the status of the smart card. Data on the DIN input is loaded on the rising edge of SCLK. D7 is loaded first and D0 last. At the same time the command bits are being shifted into the DIN input, the status bits are being shifted out of the DOUT output. The status bits are presented to DOUT on the rising edge of SCLK. Once all bits have been clocked into the shift register, the command data is loaded into the command latch by bringing LD low. At this time the command latch is updated and the LTC4556 will begin to act on the new command set. When LD is low, the shift register is transparent to the status data of the smart card channel. The status data is latched into the shift register on the rising edge of LD. SCLK should be held in the high state when idle and should only be clocked when LD is high. Likewise LD should only be brought high when SCLK is high. Figure 2 shows the operation of the serial port. Multiple LTC4556s may be daisy chained together by connecting the DOUT pin of one LTC4556 to the DIN pin of another. Figure 7 shows an example of an LTC4556 daisy chained together with LTC1955s. The maximum clock rate for the serial port is 10MHz. The serial port controls the following parameters of the smart card socket: • Selection/deselection of the smart card • VCC voltage level of the card (5V/3V/1.8V/0V) tLC SCLK tDS tDH tDD tH tL tCL tLW 8 U • Clock mode of the card (synchronous, asynchronous or bidirectional) • Operating mode of asynchronous cards (clock stop high, low, ÷1, ÷2, ÷4 or ÷8) • Selection of the I/O, C4 or C8 pins The serial port provides the following status data: • It indicates the presence or absence of the smart card. • It indicates the readiness of the smart card VCC supply. Communication with the smart card is disabled until its power supply voltage has reached the final value. • It indicates fault status. In the event of an electrical or ATR fault, the fault is reported. For electrical faults, the LTC4556 will automatically deactivate the smart card. Table 1 illustrates the command inputs and status outputs associated with each bit of the serial data word. Three voltage options are available from the LTC4556: 5V, 3V and 1.8V. Bits D0, D1 determine which voltage is selected. Setting both control bits to 0 deactivates the card and sets the smart card supply voltage to 0V. Table 2 shows the operation of the supply control bits. The CLK pin to the smart card can be programmed for various modes. Both synchronous and asynchronous cards are supported. There are several options available with asynchronous cards. Table 3 shows how all clock options are obtained using bits D5–D7. DIN X D7 D6 D2 D1 D0 X LD D7 FROM INPUT DOUT D7 D6 D5 D1 D0 D7 4556 F02 Figure 2. Serial Port Timing Diagram 4556f LTC4556 OPERATIO STATUS OUTPUT 0 0 0 0 Card Electrical Fault Card ATR Fault Card VCC Ready Card Present Table 1. Serial Port Commands BIT D0 D1 D2 D3 D4 D5 D6 D7 COMMAND INPUT VCC Options (See Table 2) Card Select/Deselect Card Communications Options (See Table 4) Card Clock Options (See Table 3) Table 2. VCC and Shutdown Options D1 0 0 1 1 D0 0 1 0 1 STATUS VCC = 0V (Shutdown) VCC = 1.8V VCC = 3V VCC = 5V Table 3. Clock Options D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 CLOCK MODE Synchronous Mode Bidirectional Mode Asynchronous Stop Low Asynchronous Stop High Asynchronous ÷1 Asynchronous ÷2 Asynchronous ÷4 Asynchronous ÷8 To receive status data from the serial port, a read/write operation must be performed. When polling for the presence of a smart card, the input word may be set to $00 since this is the shutdown command for the LTC4556. Data Channel The data channel is level shifted to the appropriate VCC voltages at the I/O pin. An NMOS pass transistor performs the level shifting. The gate of the NMOS transistor is biased such that the transistor is completely off when both sides have relinquished the channel. If one side of the channel asserts an L, then the transistor will convey the L to the other side. U Note that current passes from the receiving side of the channel to the transmitting side. The low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the IR drop of the pass transistor. When a card socket is selected, it becomes a candidate to drive data on the DATA pin and likewise receive data from the DATA pin. When a card socket is deselected, the voltage on its I/O pin will return to the idle state (H) and the DATA side of that channel will become high impedance. The LTC4556 includes provision for unidirectional communication with the C4 and C8 pins of the smart card. The C4, C8 and I/O pins are individually multiplexed to the DATA pin using bits D3 and D4 as shown in Table 4. Table 4. Communications Options D4 0 0 1 1 D3 0 1 0 1 COMMUNICATION MODE Nothing Selected C4 Connected to DATA Pin C8 Connected to DATA Pin I/O Connected to DATA Pin Dynamic Pull-Up Current Sources The current sources on the bidirectional pins (DATA, I/O) are dynamically activated to achieve a fast rise time with a relatively small static current. Once a bidirectional pin is relinquished, a small start up current begins to charge the node. An edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. If a valid transition is detected, a large pull-up current enhances the edge rate on the node. The higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. LOCAL SUPPLY + – dv dt VREF ISTART BIDIRECTIONAL PIN 4556 F03 Figure 3. Dynamic Pull-Up Current Sources 4556f 9 LTC4556 OPERATIO Clock Channel As described in the section Serial Port, the LTC4556 supports both synchronous and asynchronous smart cards. When bits D5-D7 are set to 0s, the clock channel is in synchronous mode. In synchronous mode, the CLK pin follows the SYNC pin for a channel that is selected. If the channel is deselected (via the serial port) the CLK line is latched at its current value. When control bits D7, D6 and D5 are set to 0, 0 and 1 respectively, the clock channel is in bidirectional mode. This mode permits clock stretching when communicating with bidirectional cards. The bidirectional level translation circuit is identical to the I/O-DATA circuit. A low can be asserted from either the SYNC pin or the CLK pin and the other pin will follow. The low can be “handed off” to affect clock stretching if both sides assert at the same time. It will not run as fast as the unidirectional synchronous or asynchronous modes but does employ accelerating pullup sources on both sides for maximum clock rate. In asynchronous mode the CLK pin follows either the ASYNC pin (÷1 mode) or a divided version of this pin. The CLK pin can also be stopped high or low. The available divider ratios include ÷2, ÷4 and ÷8. When switching between divider ratios, the internal selection circuitry ensures that no spikes or glitches appear on the CLK pin. Consequently, it may take up to 8 clock pulses for the clock frequency change command to take affect. Synchronization circuitry ensures that no glitches occur when entering or exiting one of the stop modes. For example, when entering Stop Low mode, the selection circuitry waits for the next falling edge of the CLK signal to make the change. Likewise if Stop High is selected it will occur on the next rising edge. Deselection of an asynchronous card does not affect its CLK pin. Its clock can be started, stopped or its divider ratio changed at any time. To clean up the duty cycle of the incoming clock in asynchronous applications, any of the clock divider modes ÷2, ÷4 or ÷8 will yield a very nearly 50% duty cycle. 10 U Additional synchronization circuitry prevents glitches from occurring when switching between synchronous mode and asynchronous mode. Because of this circuitry, two edges (a falling edge followed by a rising edge) are necessary at the CLK pin to switch modes from asynchronous to synchronous. For example, if clock stop mode is engaged, the clock channel will not change modes until clock stop mode is disengaged. Both SYNC and ASYNC inputs are independently level shifted to the appropriate voltage for the CLK pin (5V, 3V, 1.8V). Reset Channel When the card is selected, the reset channel provides a level shifted path from the RIN pin to the RST pin. When the card is deselected its RST pin is latched at the current value of RIN. Smart Card Detection Circuit The PRES pin is used to detect the presence of a smart card. An automatic debounce circuit waits until a smart card has been present for a continuous period of typically 32ms. Once a valid card indication exists, the status bit is updated and may be polled by cycling data through the serial port. The DOUT pin (equivalent to D7) of the serial port can be used to indicate the presence of a card in real time if LD is held low. The PRES pin has a built-in pull-up current source so no external components are required for switch detection. The pull-up current source is designed to have a small current when the pin voltage is below approximately 1V but somewhat higher current when the pin voltage reaches 1V. This helps maintain low power dissipation when a card is present and yet fast response time to a card removal. Activation/Deactivation For maximum flexibility, the activation sequencing of the smart card is left to the application programmer. However, deactivation can be achieved either manually or automatically. An electrical fault condition will trigger the automatic deactivation. 4556f LTC4556 OPERATIO The built-in deactivation sequence can be executed via the serial port simply by setting the control bits D0 and D1 to 0. The deactivation sequence is outlined below. 1. The RST pin is immediately brought low. 2. The deactivation of the CLK pin depends upon which type of card is used: If the smart card was set to asynchronous mode then the CLK pin will be latched low on its next falling edge. If no falling edges occur within 5µs (min) then the CLK line is forced low. If the smart card was set to synchronous mode then the CLK pin is immediately latched at its current value (either high or low) and then forced low after a duration of 5µs (min). During the 5µs timeout period, changes on SYNC will be ignored. 3. The I/O, C4 and C8 pins are brought low. 4. The VCC pin is brought low. Upon activation, to comply with relevant smart card standards, none of the smart card signal pins will be allowed to go high before the smart card supply voltage (VCC) has reached its final value. Electrical Fault Detection Several types of faults are detected by the LTC4556. They include VCC undervoltage, VCC overcurrent, CLK, RST, C8, C4 short circuit, card removal during a transaction, failed answer to reset (ATR), supply undervoltage or UNDERV and chip overtemperature. To prevent false errors from plaguing the microcontroller, the electrical faults are acted upon only after a 5µs (min) timeout period. Card removal during transaction faults initiate the deactivation sequence immediately. VCC undervoltage faults are determined by comparing the actual output voltage with the internal reference voltage. If the output is more than ~5% below its set point for the entire timeout period, the fault is reported and the deactivation sequence is initiated. U VCC overcurrent faults are detected by comparing the output current of the LDOs with an internal reference level. If the current of the LDO is more than 110mA (typ) for the entire timeout period, the fault is reported and the deactivation sequence is initiated. CLK and RST faults are detected by comparing the outputs of these pins with their expected signals. If the signal on a pin is incorrect for the entire timeout period, the fault is reported and the deactivation sequence is initiated. The clock channel is a special case. Since it can have a free running clock, the error indication is accumulated over a longer period of time without being cleared. Even though the clock may be running, an error will still be detected. An overtemperature fault is detected by sensing the junction temperature of the IC. If the junction temperature exceeds approximately 150°C for the entire timeout period, the fault is reported by setting the fault bit (D4) and the deactivation sequence is initiated. A card removal fault is determined as soon as the PRES pin is high. Once this occurs the fault is reported and the deactivation sequence is initiated. If no card is present, and the application software attempts to power up a card socket, an automatic fault will result. Short circuits on the I/O line will not be detected by the fault detection hardware; however, a short circuit from I/O to VCC will be compliant with the maximum current limits set by applicable standards (