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LTC485IN8

LTC485IN8

  • 厂商:

    LINER

  • 封装:

  • 描述:

    LTC485IN8 - Low Power RS485 Interface Transceiver - Linear Technology

  • 数据手册
  • 价格&库存
LTC485IN8 数据手册
LTC485 Low Power RS485 Interface Transceiver FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Power: ICC = 300µA Typ Designed for RS485 Interface Applications Single 5V supply – 7V to 12V Bus Common Mode Range Permits ± 7V Ground Difference Between Devices on the Bus Thermal Shutdown Protection Power-Up/Down Glitch-Free Driver Outputs Permit Live Insertion or Removal of Transceiver Driver Maintains High Impedance in Three-State or with the Power Off Combined Impedance of a Driver Output and Receiver Allows Up to 32 Transceivers on the Bus 70mV Typical Input Hysteresis 30ns Typical Driver Propagation Delays with 5ns Skew Pin Compatible with ±60V Protected LT1785 and 52Mbps LTC1685 The LTC®485 is a low power differential bus/line transceiver designed for multipoint data transmission standard RS485 applications with extended common mode range (12V to – 7V). It also meets the requirements of RS422. The CMOS design offers significant power savings over its bipolar counterpart without sacrificing ruggedness against overload of ESD damage. The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common mode range. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. The receiver has a fail-safe feature which guarantees a high output state when the inputs are left open. The LTC485 is fully specified over the commercial and extended industrial temperature range. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S ■ ■ Low Power RS485/RS422 Transceiver Level Translator TYPICAL APPLICATIO RO1 RE1 DE1 DI1 D VCC1 R Rt GND1 A Rt RO2 RE2 DE2 DI2 D GND2 LTC485 • TA01 LTC485 • TA02 R VCC2 B U Driver Outputs sn 485LTC485ffs U U 1 LTC485 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW RO 1 RE 2 DE 3 DI 4 N8 PACKAGE 8-LEAD PLASTIC DIP D R 8 7 6 5 VCC B A GND Supply Voltage ....................................................... 12V Control Input Voltages ................... – 0.5V to VCC + 0.5V Driver Input Voltage ....................... – 0.5V to VCC + 0.5V Driver Output Voltage ........................................... ± 14V Receiver Input Voltage .......................................... ± 14V Receiver Output Voltages .............. – 0.5V to VCC + 0.5V Operating Temperature Range LTC485I ...................................... – 40°C ≤ TA ≤ 85°C LTC485C ......................................... 0°C ≤ TA ≤ 70°C LTC485M (OBSOLETE) .......... – 55°C ≤ TA ≤ 125°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC485CN8 LTC485CS8 LTC485IN8 LTC485IS8 S8 PART MARKING 485 485I ORDER PART NUMBER LTC485CJ8 LTC485MJ8 S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 125°C, θJA = 100°C/ W (N) TJMAX = 150°C, θJA = 150°C/ W (S) J8 PACKAGE 8-LEAD CERAMIC DIP TJMAX = 155°C, θJA = 100°C/ W (J) OBSOLETE PACKAGE Consider the N8 Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V ± 5%, unless otherwise noted. (Notes 2 and 3) SYMBOL VOD1 VOD2 ∆VOD VOC ∆⏐VOC⏐ VIH VIL IIN1 IIN2 VTH ∆VTH VOH VOL IOZR RIN PARAMETER Differential Driver Output Voltage (Unloaded) Differential Driver Output Voltage (with Load) Change in Magnitude of Driver Differential Output Voltage for Complementary States Driver Common Mode Output Voltage Change in Magnitude of Driver Common-Mode Output Voltage for Complementary States Input High Voltage Input Low Voltage Input Current Input Current (A, B) Differential Input Threshold Voltage for Receiver Receiver Input Hysteresis Receiver Output High Voltage Receiver Output Low Voltage Three-State (High Impedance) Output Current at Receiver Receiver Input Resistance CONDITIONS IO = 0 R = 50Ω (RS422) R = 27Ω (RS485), Figure 1 R = 27Ω or R = 50Ω, Figure 1 R = 27Ω or R = 50Ω, Figure 1 R = 27Ω or R = 50Ω, Figure 1 DE, DI, RE DE, DI, RE DE, DI, RE DE = 0, VCC = 0V or 5.25V – 7V ≤ VCM ≤ 12V VCM = 0V IO = – 4mA, VID = 200mV IO = 4mA, VID = – 200mV VCC = Max, 0.4V ≤ VO ≤ 2.4V – 7V ≤ VCM ≤ 12V VIN = 12V VIN = – 7V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN 2 1.5 TYP MAX 5 5 0.2 3 0.2 UNITS V V V V V V V 2 0.8 ±2 ±1 – 0.8 – 0.2 70 3.5 0.4 ±1 12 0.2 sn485 LTC485ffs 2 U V µA mA mA V mV V V µA kΩ W U U WW W LTC485 SWITCHI G CHARACTERISTICS SYMBOL ICC IOSD1 IOSD2 IOSR tPLH tPHL tSKEW tr, tf tZH tZL tLZ tHZ tPLH tPHL tSKD tZL tZH tLZ tHZ ⏐tPLH – tPHL⏐ Differential Receiver Skew The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.VCC = 5V ± 5%, unless otherwise noted. (Notes 2 and 3) PARAMETER Supply Current Driver Short-Circuit Current, VOUT = HIGH Driver Short-Circuit Current, VOUT = LOW Receiver Short-Circuit Current Driver Input to Output Driver Input to Output Driver Output to Output Driver Rise or Fall Time Driver Enable to Output High Driver Enable to Output Low Driver Disable Time from Low Driver Disable Time from High Receiver Input to Output CL = 100pF (Figures 4 and 6) S2 Closed CL = 100pF (Figures 4 and 6) S1 Closed CL = 15pF (Figures 4 and 6) S1 Closed CL = 15pF (Figures 4 and 6) S2 Closed RDIFF = 54Ω, CL1 = CL2 = 100pF, (Figures 3 and 7) CONDITIONS No Load, Pins 2, 3, 4 = 0V or 5V VO = – 7V VO = 10V 0V ≤ VO ≤ VCC RDIFF = 54Ω, CL1 = CL2 = 100pF, (Figures 3 and 5) Outputs Enabled Outputs Disabled ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Receiver Enable to Output Low Receiver Enable to Output High Receiver Disable from Low Receiver Disable from High Note 1: Absolute maximum ratings are those beyond which the safety of the device cannot be guaranteed. Note 2: All currents into device pins are positive; all currents out ot device pins are negative. All voltages are referenced to device ground unless otherwise specified. TYPICAL PERFOR A CE CHARACTERISTICS Receiver Output Low Voltage vs Output Current 36 32 TA = 25°C –18 –16 TA = 25°C OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) 28 24 20 16 12 8 4 0 0 0.5 1.0 1.5 OUTPUT VOLTAGE (V) 2.0 LTC485 • TPC01 –12 –10 –8 –6 –4 –2 0 5 4 3 OUTPUT VOLTAGE (V) 2 LTC485 • TPC02 OUTPUT VOLTAGE (V) UW U MIN TYP 500 300 MAX 900 500 250 250 85 50 50 10 25 70 70 70 70 200 200 50 50 50 50 UNITS µA µA mA mA mA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 35 35 7 10 10 3 100 100 30 30 5 15 40 40 40 40 30 30 90 90 13 20 20 20 20 CRL = 15pF (Figures 2 and 8) S1 Closed CRL = 15pF (Figures 2 and 8) S2 Closed CRL = 15pF (Figures 2 and 8) S1 Closed CRL = 15pF (Figures 2 and 8) S2 Closed Note 3: All typicals are given for VCC = 5V and TA = 25°C. Note 4: The LTC485 is guaranteed by design to be functional over a supply voltage range of 5V ± 10%. Data sheet parameters are guaranteed over the tested supply voltage range of 5V ± 5%. Receiver Output High Voltage vs Output Current 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 Receiver Output High Voltage vs Temperature I = 8mA –14 3.0 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC03 sn 485LTC485ffs 3 LTC485 TYPICAL PERFOR A CE CHARACTERISTICS Receiver Output Low Voltage vs Temperature 0.9 0.8 0.7 I = 8mA 72 64 TA = 25°C DIFFERENTIAL VOLTAGE (V) OUTPUT CURRENT (mA) OUTPUT VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 Driver Output Low Voltage vs Output Current 90 80 TA = 25°C –108 –96 OUTPUT CURRENT (mA) –84 –72 –60 –48 –36 –24 –12 0 0 1 3 2 OUTPUT VOLTAGE (V) 4 LTC485 • TPC07 INPUT THRESHOLD VOLTAGE (V) OUTPUT CURRENT (mA) 70 60 50 40 30 20 10 0 Receiver ⏐tPLH – tPHL⏐ vs Temperature 7.5 7.0 6.5 6.0 TIME (ns) SUPPLY CURRENT (µA) 5.5 5.0 4.5 4.0 3.5 3.0 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 TIME (ns) 4 UW LTC485 • TPC03 Driver Differential Output Voltage vs Output Current 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 0 1 3 2 OUTPUT VOLTAGE (V) 4 LTC485 • TPC05 Driver Differential Output Voltage vs Temperature RI = 54Ω 56 48 40 32 24 16 8 0 1.5 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC06 Driver Output High Voltage vs Output Current 1.64 TA = 25°C 1.63 1.62 1.61 1.60 1.59 1.58 1.57 1.56 0 1 3 2 OUTPUT VOLTAGE (V) 4 LTC485 • TPC08 TTL Input Threshold vs Temperature 1.55 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC09 Driver Skew vs Temperature 5.4 4.8 4.2 3.6 3.0 2.4 1.8 1.2 0.6 0 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 640 580 520 460 400 340 Supply Current vs Temperature DRIVER ENABLED DRIVER DISABLED 280 220 160 100 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC10 LTC485 • TPC11 LTC485 • TPC12 sn485 LTC485ffs LTC485 PI FU CTIO S RO (Pin 1): Receiver Output. If the receiver output is enabled(RE low), then if A > B by 200mV, RO will be high. If A < B by 200mV, then RO will be low. RE (Pin 2): Receiver Output Enable. A low enables the receiver output, RO. A high input forces the receiver output into a high impedance state. DE (Pin 3): Driver Outputs Enable. A high on DE enables the driver output. A and B, and the chip will function as a line driver. A low input will force the driver outputs into a high impedance state and the chip will function as a line receiver. DI (Pin 4): Driver Input. If the driver outputs are enabled (DE high), then a low on DI forces the outputs A low and B high. A high on DI with the driver outputs enabled will force A high and B low. GND (Pin 5): Ground Connection. A (Pin 6): Driver Output/Receiver Input. B (Pin 7): Driver Output/Receiver Input. VCC (Pin 8): Positive Supply; 4.75 < VCC < 5.25. TEST CIRCUITS A R VOD R B LTC485 • F01 Figure 1. Driver DC Test Load 3V DE A DI B RDIFF CL2 CL1 A RO B RE 15pF Figure 3. Driver/Receiver Timing Test Circuit SWITCHI G TI E WAVEFOR S 3V DI 0V t PLH B VO A 1/2 VO VO 0V –VO 10% tr tSKEW 80% 90% VDIFF = V(A) – V(B) tf 20% LTC485 • F05 1.5V Figure 5. Driver Propagation Delays sn 485LTC485ffs W W U U U U TEST POINT RECEIVER OUTPUT S1 1k VCC VOC CRL 15pF 1k S2 LTC485 • F02 Figure 2. Receiver Timing Test Load S1 OUTPUT UNDER TEST 500Ω S2 CL LTC485 • F02 LTC485 • F03 VCC Figure 4. Driver Timing Test Load #2 f = 1MHz, t r ≤ 10ns, t f ≤ 10ns t PLH 1.5V 1/2 VO t SKEW 5 LTC485 SWITCHI G TI E WAVEFOR S 3V DI 0V 5V A, B VOL VOH A, B 0V t ZH t HZ LTC485 • F06 1.5V t ZL 2.3V 2.3V Figure 6. Driver Enable and Disable Times VOH R VOL t PHL VOD2 A, B –VOD2 0V 1.5V OUTPUT f = 1MHz, t r ≤ 10ns, t f ≤ 10ns INPUT t PLH 1.5V Figure 7. Receiver Propagation Delays 3V RE 0V 5V R t ZL 1.5V OUTPUT NORMALLY LOW t LZ 0.5V 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V R 0V t ZH 1.5V Figure 8. Receiver Enable and Disable Times FU CTIO TABLES LTC485 Transmitting INPUTS RE X X X X DE 1 1 0 1 DI 1 0 X X LINE CONDITION No Fault No Fault X Fault OUTPUTS B 0 1 Z Z A 1 0 Z Z RE 0 0 0 1 6 W W U U f = 1MHz, t r ≤ 10ns, t f ≤ 10ns t LZ OUTPUT NORMALLY LOW 1.5V 0.5V OUTPUT NORMALLY HIGH 0.5V LTC485 • F07 OUTPUT NORMALLY HIGH t HZ 0.5V LTC485 • F08 U LTC485 Receiving INPUTS DE 0 0 0 0 A–B ≥ 0.2V ≤ – 0.2V Inputs Open X OUTPUTS R 1 0 1 Z sn485 LTC485ffs LTC485 APPLICATIO S I FOR ATIO Basic Theory of Operation Previous RS485 transceivers have been designed using bipolar technology because the common-mode range of the device must extend beyond the supplies and the device must be immune to ESD damage and latchup. Unfortunately, the bipolar devices draw a large amount of supply current, which is unacceptable for the numerous applications that require low power consumption. The LTC485 is the first CMOS RS485/RS422 transceiver which features ultra-low power consumption without sacrificing ESD and latchup immunity. The LTC485 uses a proprietary driver output stage, which allows a common-mode range that extends beyond the power supplies while virtually eliminating latchup and providing excellent ESD protection. Figure 9 shows the LTC485 output stage while Figure 10 shows a conventional CMOS output stage. When the conventional CMOS output stage of Figure 10 enters a high impedance state, both the P-channel (P1) and the N-channel (N1) are turned off. If the output is then driven above VCC or below ground, the P + /N-well diode VCC SD3 P1 D1 OUTPUT LOGIC SD4 N1 D2 LTC485 • F09 Figure 9. LTC485 Output Stage U (D1) or the N + /P-substrate diode (D2) respectively will turn on and clamp the output to the supply. Thus, the output stage is no longer in a high impedance state and is not able to meet the RS485 common-mode range requirement. In addition, the large amount of current flowing through either diode will induce the well known CMOS latchup condition, which could destroy the device. The LTC485 output stage of Figure 9 eliminates these problems by adding two Schottky diodes, SD3 and SD4. The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the output stage is operating normally, the Schottky diodes are forward biased and have a small voltage drop across them. When the output is in the high impedance state and is driven above VCC or below ground, the parasitic diodes D1 or D2 still turn on, but SD3 or SD4 will reverse bias and prevent current from flowing into the N-well or the substrate. Thus, the high impedance state is maintained even with the output voltage beyond the supplies. With no minority carrier current flowing into the N-well or substrate, latchup is virtually eliminated under power-up or power-down conditions. VCC P1 D1 LOGIC OUTPUT N1 D2 LTC485 • F10 W UU Figure 10. Conventional CMOS Output Stage sn 485LTC485ffs 7 LTC485 APPLICATIO S I FOR ATIO The LTC485 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively. The output will be clamped to either VCC or ground by a Zener voltage plus a Schottky diode drop, but this voltage is way beyond the RS485 operating range. This clamp protects the MOS gates from ESD voltages well over 2000V. Because the ESD injected current in the N-well or substrate consists of majority carriers, latchup is prevented by careful layout techniques. A DRIVER OUTPUTS B RECEIVER OUTPUT RO RECEIVER OUTPUT DRIVER OUTPUTS LTC485 • F11 Figure 11. Receiver tPHL TTL IN t r, t f < 6ns D Figure 13. Receiver Propagation Delay Test Circuit 8 U Propagation Delay Many digital encoding schemes are dependent upon the difference in the propagation delay times of the driver and the receiver. Using the test circuit of Figure 13, Figures 11 and 12 show the typical LTC485 receiver propagation delay. The receiver delay times are: ⏐tPLH – tPHL⏐ = 9ns Typ, VCC = 5V W UU The driver skew times are: Skew = 5ns Typ, VCC = 5V 10ns Max, VCC = 5V, TA = – 40°C to 85°C A B RO LTC485 • F12 Figure 12. Receiver tPLH 100pF R 100Ω BR R RECEIVER OUT LTC485 • F13 100pF sn485 LTC485ffs LTC485 APPLICATIO S I FOR ATIO LTC485 Line Length vs Data Rate The maximum line length allowable for the RS422/RS485 standard is 4000 feet. 100Ω A LTC485 B TTL IN NOISE GENERATOR C D 4000 FT 26AWG TWISTED PAIR LTC485 TTL OUT Figure 14. Line Length Test Circuit Figure 17. System Common Mode Voltage at 110kHz Using the test circuit in Figure 14, Figures 15 and 16 show that with ~ 20VP-P common mode noise injected on the line, The LTC485 is able to reconstruct the data stream at the end of 4000 feet of twisted pair wire. RO DI COMMON MODE VOLTAGE (A + B)/2 DI LTC485 • F15 Figure 15. System Common Mode Voltage at 19.2kHz CABLE LENGTH (FT) RO DIFFERENTIAL VOLTAGE A – B DI LTC485 • F16 Figure 16. System Differential Voltage at 19.2kHz U Figures 17 and 18 show that the LTC485 is able to comfortably drive 4000 feet of wire at 110kHz. RO COMMON MODE VOLTAGE (A + B)/2 DI LTC485 • F17 W UU RO COMMON MODE VOLTAGE (A – B) LTC485 • F18 Figure 18. System Differential Voltage at 110kHz When specifying line length vs maximum data rate the curve in Figure 19 should be used: 10k 1k 100 10 10k 100k 1M 2.5M MAXIMUM DATA RATE 10M LTC485 • F19 Figure 19. Cable Length vs Maximum Data Rate sn 485LTC485ffs 9 LTC485 TYPICAL APPLICATIO S Typical RS485 Network Rt Rt PACKAGE DESCRIPTIO CORNER LEADS OPTION (4 PLCS) 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.300 BSC (0.762 BSC) 0.008 – 0.018 (0.203 – 0.457) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 10 U U LTC485 • TA03 J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 0.005 (0.127) MIN 0.405 (10.287) MAX 8 7 6 5 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.025 (0.635) RAD TYP 1 2 3 0.220 – 0.310 (5.588 – 7.874) 4 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0° – 15° 0.045 – 0.065 (1.143 – 1.651) 0.014 – 0.026 (0.360 – 0.660) 0.100 (2.54) BSC 0.125 3.175 MIN J8 1298 OBSOLETE PACKAGE sn485 LTC485ffs LTC485 PACKAGE DESCRIPTIO U N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 0.045 – 0.065 (1.143 – 1.651) 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1098 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) SO8 1298 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC sn 485LTC485ffs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC485 RELATED PARTS PART NUMBER LTC486/LTC487 LTC488/LTC489 LTC490/LTC491 LTC1480 LTC1481 LTC1482 LTC1483 LTC1484 LTC1485 LTC1518/LTC1519 LTC1520 LTC1535 LTC1685 LTC1686/LTC1687 LTC1688/LTC1689 LTC1690 LT1785/LTC1785A LT1791/LTC1791A DESCRIPTION Low Power Quad RS485 Drivers Low Power Quad RS485 Receivers Low Power Full-Duplex RS485 Transceivers 3.3V Supply RS485 Transceiver Low Power RS485 Transceiver with Shutdown RS485 Transceiver with Carrier Detect Low Power, Low EMI RS485 Transceiver RS485 Transceiver with Fail-Safe 10Mbps RS485 Transceiver 52Mbps Quad RS485 Receivers LVDS-Compatible Quad Receiver 2500V Isolated RS485 Transceiver 52Mbps RS485 Transceiver 52Mbps Full-Duplex RS485 Transceiver 100Mbps Quad RS485 Drivers Full-Duplex RS485 Transceiver with Fail-Safe ±60V Protected RS485 Transceivers ±60V Protected Full-Duplex RS485 Transceivers COMMENTS 110µA Supply Current 7mA Supply Current 300µA Supply Current Lower Supply Voltage Lowest Power ±15kV ESD, Fail-Safe Slew Rate Limited Driver Outputs, Lowest Power ±15kV ESD, MSOP Package High Speed Higher Speed, LTC488/LTC489 Pin-Compatible 100mV Threshold, Low Channel-to-Channel Skew Full-Duplex, Self-Powered Using External Transformer Industry-Standard Pinout, 500ps Propagation Delay Skew LTC490/LTC491 Pin Compatible Highest Speed, LTC486/LTC487 Pin Compatible ±15kV ESD, LTC490 Pin Compatible ±15kV ESD, Fail-Safe (LT1785A) ±15kV ESD, Fail-Safe (LT1791A) sn485 LTC485ffs 12 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/LCG 1101 1.5K REV F • PRINTED IN THE USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 1994
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