LTC6412IUF

LTC6412 800MHz, 31dB Range Analog-Controlled VGA FEATURES n n n n n n n n n n n n DESCRIPTION The LTC®6412 is a fully differential variable gain amplifier with linear-in-dB analog gain control. It is designed for AC-coupled operation in IF receiver chains from 1MHz to 500MHz. The part has a constant OIP3 across a wide output amplitude range and across the 31dB gain control range. The output noise (NF + Gain) is also flat versus gain to provide a uniform spurious-free dynamic range (SFDR) >120dB over the full gain control range at 240MHz. The LTC6412 is ideal for interfacing with the LT®5527 and LT5557 downconverting mixers, LTC6410-6 IF amplifier and the LTC6400/LTC6401/LTC6416 ADC drivers for use in 12-, 14-, and 16-bit ADC applications. The LTC6412 recovers quickly from an overdrive condition, and the EN pin allows for a fast output signal disable to protect sensitive downstream components. Asserting the SHDN pin reduces the current consumption below 1mA for power-down or sleep modes. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 800MHz –3dB Small-Signal Bandwidth Continuously-Adjustable Gain Control –14dB to +17dB Linear-in-dB Gain Range 35dBm OIP3 at 240MHz Across All Gain Settings 10dB Noise Figure at Maximum Gain (IIP3 – NF) = +8dBm at 240MHz Across All Gains 2.7nV/√Hz Input Referred Noise Differential Inputs and Outputs 50Ω Input Impedance Across all Gains Single Supply Operation from 3V to 3.6V 110mA Supply Current 4mm × 4mm × 0.75mm 24-Pin QFN Package APPLICATIONS n n n n IF Signal Chain Automatic Gain Control (AGC) 2.5G and 3G Cellular Basestation Transceivers WiMAX, WiBro, WLAN Receivers Satellite and GPS Receiver IF TYPICAL APPLICATION 3.3V Fully Differential 240MHz IF Receiver Chain with 31dB Gain Control 3.3V 3.3V 1nF VCC SHDN 10nF 0.1μF 180nH EN +OUT 0.1μF 180nH 3.3V BPF +IN V+ +OUT AIN+ LTC2208 AIN– VCM GND 6412 TA01 VGA Gain vs Frequency Over Gain Control Range 20 GMAX 3.3V VDD 10 GND VCM DECL1 DECL2 –VG VREF +VG IF INPUT LTC6412 –IN 10nF –OUT 0.1μF GAIN CONTROL (+ SLOPE MODE) LTC6400-8 VCM –IN V– –OUT GAIN (dB) +IN 0 –10 GMIN –20 2.2μF –30 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G01 10nF 0.1μF 0.1μF 0.1μF 6412f 1 LTC6412 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION TOP VIEW SHDN GND GND VCC 18 GND 17 +OUT 25 16 –OUT 15 GND 14 DECL2 13 VCC 7 DECL1 8 GND 9 10 11 12 VREF GND +VG –VG VCC EN Total Supply Voltage (VCC to GND)...........................3.8V Amplifier Input Current (+IN, –IN)........................±20mA Amplifier Output Current (+OUT, –OUT) ...............±70mA Input Current (+VG, –VG, VREF, EN, SHDN ) .........±10mA Input Current (VCM, DECL1, DECL2) ....................±10mA RF Input Power, Continuous, 50Ω......................+15dBm RF Input Power, 100μs pulse, 50Ω ....................+20dBm Operating Temperature Range (Note 2).... –40°C to 85°C Specified Temperature Range (Note 3) .... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C Junction Temperature ........................................... 150°C 24 23 22 21 20 19 GND 1 +IN 2 –IN 3 VCM 4 VCM 5 VCC 6 UF PACKAGE 24-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC6412CUF#PBF LTC6412IUF#PBF TAPE AND REEL LTC6412CUF#TRPBF LTC6412IUF#TRPBF PART MARKING* 6412 6412 PACKAGE DESCRIPTION 24-Lead (4mm × 4mm) Plastic QFN 24-Lead (4mm × 4mm) Plastic QFN SPECIFIED TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 6412f 2 LTC6412 DC ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DC electrical performance measured using DC test circuit schematic. VIN(DIFF) is defined as (+IN) – (–IN). VOUT(DIFF) is defined as (+OUT) – (–OUT). VIN(CM) is defined as [(+IN) + (–IN)]/2. VOUT(CM) is defined as [(+OUT) + (–OUT)]/2. Unless noted otherwise, default operating conditions are VCC = 3.3V, EN = 0.8V, SHDN = 2.2V, +VG tied to VREF (negative gain slope mode), VOUT(CM) = 3.3V. Differential power gain defined at ZSOURCE = 50Ω differential and ZLOAD = 200Ω differential. SYMBOL GMAX GMIN GRANGE TCGAIN GSLOPE GCONF(AVE) GCONF(MAX) PARAMETER Maximum Differential Power Gain (Note 4) Minimum Differential Power Gain (Note 4) Differential Power Gain Range Temperature Coefficient of Gain at Fixed VG Gain Control Slope Average Conformance Error to Gain Slope Line Maximum Conformance Error to Gain Slope Line Differential Input Resistance at Maximum Gain Differential Input Resistance at Minimum Gain CONDITIONS –VG = 0V, VIN(DIFF) = 100mV –VG = 1.2V, VIN(DIFF) = 200mV GMAX-GMIN –VG = 0V to 1.2V –VG = 0.2V to 1.0V, 85 Points, Slope of the Least-Square Fit Line –VG = 0.2V to 1.0V, 85 Points, Standard Error to the Least-Square Fit Line –VG = 0.2V to 1.0V, 85 points, Maximum Error to the Least-Square Fit Line –VG = 0V, VIN(DIFF) = 100mV –VG = 1.2V, VIN(DIFF) = 200mV 49 47 49 47 l MIN 16.1 15.5 –16.2 –16.8 30.7 30.1 –34.1 –34.7 TYP 17.1 –14.9 31.9 0.007 –32.9 0.12 0.20 MAX 18.1 18.7 –13.6 –13.0 33.1 33.7 –31.7 –31.1 0.20 0.45 UNITS dB dB dB dB dB dB dB/°C dB/V dB/V dB dB Gain Characteristics l l l +IN and –IN Pins RIN(GMAX) RIN(GMIN) VINCM(GMAX) VINCM(GMIN) RIH(+VG) RIH(–VG) IIL(+VG) IIL(–VG) VREF 57 57 640 640 7.8 7.2 7.8 7.2 –9 –10 –9 –10 590 580 9.2 9.2 –5 –5 615 10.6 11.6 10.6 11.6 –1 –1 –1 –1 640 650 l l 65 67 65 67 Ω Ω Ω Ω mV mV kΩ kΩ kΩ kΩ μA μA μA μA mV mV Input Common Mode Voltage at Maximum Gain –VG = 0V, DC Blocking Capacitor to Input Input Common Mode Voltage at Minimum Gain –VG = 1.2V, DC Blocking Capacitor to Input +VG, –VG, and VREF Pins +VG Input High Resistance –VG Input High Resistance +VG Input Low Current –VG Input Low Current Internal Bias Voltage +VG = 1.0V, –VG Tied to VREF , RIN(+VG) = 1V/Δ IIL(+VG) –VG = 1.0V, +VG Tied to VREF , RIN(–VG) = 1V/Δ IIL(–VG) +VG = 0V, –VG Tied to VREF –VG = 0V, +VG Tied to VREF –VG = 0V, +VG Tied to VREF l l l l l 6412f 3 LTC6412 DC ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DC electrical performance measured using DC test circuit schematic. VIN(DIFF) is defined as (+IN) – (–IN). VOUT(DIFF) is defined as (+OUT) – (–OUT). VIN(CM) is defined as [(+IN) + (–IN)]/2. VOUT(CM) is defined as [(+OUT) + (–OUT)]/2. Unless noted otherwise, default operating conditions are VCC = 3.3V, EN = 0.8V, SHDN = 2.2V, +VG tied to VREF (negative gain slope mode), VOUT(CM) = 3.3V. Differential power gain defined at ZSOURCE = 50Ω differential and ZLOAD = 200Ω differential. PARAMETER SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Low Current SHDN Input High Current EN Input Low Voltage EN Input High Voltage EN Input Low Current EN Input High Current Operating Supply Range Total Supply Current Sum of Supply Current to OUT Pins Delta of Supply Current to OUT Pins Supply Current in Shutdown Power Supply Rejection Ratio at Max Gain Power Supply Rejection Ratio at Min Gain All VCC Pins Plus +OUT and –OUT Pins IS(OUT) = I+OUT + I–OUT Current Imbalance to +OUT and –OUT l SYMBOL SHDN Pin VIL(SHDN) VIH(SHDN) IIL(SHDN) IIH(SHDN) EN Pin VIL(EN) VIH(EN) IIL(EN) IIH(EN) Power Supply VS IS(TOT) IS(OUT) IΔ(OUT) IS(SHDN) PSRRMAX PSRRMIN CONDITIONS l l MIN TYP MAX 0.8 UNITS V V μA μA V V μA μA V mA mA mA mA mA mA mA mA dB dB 2.2 –60 –30 –30 –15 –1 –1 0.8 2.2 –60 –30 3.0 –30 –15 3.3 110 –1 –1 3.6 135 140 55 60 1.5 2.0 1.3 2.0 SHDN = 0.8V SHDN = 2.2V l l l l EN = 0.8V EN = 2.2V l l l l 44 l 0.5 0.5 l IS(OUT) at SHDN = 0.8V –VG = 0V, Output Referred –VG = 1.2V, Output Referred 40 40 53 53 6412f 4 LTC6412 AC ELECTRICAL CHARACTERISTICS SYMBOL Small Signal BWGMAX BWGMIN Sdd11 Sdd22 Sdd12 –3dB Bandwidth for Sdd21 at Maximum Gain –VG = 0V, Test Circuit B –3dB Bandwidth for Sdd21 at Minimum Gain –VG = 1.2V, Test Circuit B Input Match at ZSOURCE = 50Ω Differential Output Match at ZLOAD = 200Ω Differential Reverse Isolation –VG = 0V to 1.2V, 10MHz-500MHz, Test Circuit B –VG = 0V to 1.2V, 10MHz-250MHz, Test Circuit B –VG = 0V to 1.2V, 10MHz-500MHz, Test Circuit B Peak POUT = +4dBm, –VG = 0.2V to 0.4V, Time to Settle Within 1dB of Final POUT Peak POUT = +4dBm, –VG = 0.2V to 0.6V, Time to Settle Within 1dB of Final POUT Peak POUT = +4dBm, –VG = 0.2V to 0.8V, Time to Settle Within 1dB of Final POUT –VG = 0V, PIN = +3dBm to –17dBm, Time to Settle Within 1dB of Final POUT POUT = 0dBm at EN = 0V, –VG = 0V, EN = 0V to 3V, Time for POUT ≤ –20dBm POUT = 0dBm at EN = 0V, –VG = 0V, EN = 3V to 0V, Time for POUT ≥ –1dBm –VG = 0V, Test Circuit B –VG = 1.2V, Test Circuit B GMAX-GMIN POUT = 0dBm, –VG = 0V to 1.0V POUT = 0dBm, –VG = 0V to 1.0V f1 = 69.5MHz, f2 = 70.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V f1 = 69.5MHz, f2 = 70.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V –VG = 0V (Note 6) –VG = 0V (Note 5) –VG = 1.2V (Note 5) –VG = 0V, Test Circuit B –VG = 1.2V, Test Circuit B GMAX-GMIN POUT = 0dBm, –VG = 0V to 1.0V POUT = 0dBm, –VG = 0V to 1.0V 800 800 –20 –10 -80 MHz MHz dB dB dB PARAMETER The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Typical AC electrical performance measured in demo board DC1464A (Figure 3, Test Circuit A) unless otherwise noted. Default operating conditions are VCC = 3.3V, EN = 0.8V, SHDN = 2.2V, +VG tied to VREF (negative gain slope mode), and ZSOURCE = ZLOAD = 50Ω unless otherwise noted. CONDITIONS MIN TYP MAX UNITS Transient Response tSTEP(6dB) tSTEP(12dB) tSTEP(20dB) tOVDR tOFF tON 6dB Gain Step Response Time 12dB Gain Step Response Time 20dB Gain Step Response Time Overdrive Recovery Time at 70MHz Output Amplifier Disable Time Output Amplifier Enable Time 0.4 0.4 0.4 25 25 20 μs μs μs ns ns ns 70MHz Signal GMAX GMIN GRANGE HD2 HD3 IM3 OIP3 P1dBGMAX NFGMAX NFGMIN GMAX GMIN GRANGE HD2 HD3 Maximum Gain Minimum Gain Gain Range Second Harmonic Distortion Third Harmonic Distortion Third-Order Intermodulation Output Third-Order Intercept Output 1dB Compression Point at Max Gain Noise Figure at Maximum Gain Noise Figure at Minimum Gain Maximum Gain Minimum Gain Gain Range Second Harmonic Distortion Third Harmonic Distortion 17 –15 32 –80 –80 –90 39 13 10 42 17 –15 32 –80 –75 dB dB dB dBc dBc dBc dBm dBm dB dB dB dB dB dBc dBc 140MHz Signal 6412f 5 LTC6412 AC ELECTRICAL CHARACTERISTICS SYMBOL IM3 OIP3 P1dBGMAX NFGMAX NFGMIN GMAX GMIN GRANGE HD2 HD3 IM3 OIP3 P1dBGMAX NFGMAX NFGMIN GMAX GMID GMIN GRANGE IM3GMAX IM3GMID IM3GMIN OIP3GMAX OIP3GMID OIP3GMIN PARAMETER Third-Order Intermodulation Output Third-Order Intercept Output 1dB Compression Point at Max Gain Noise Figure at Maximum Gain Noise Figure at Minimum Gain Maximum Gain Minimum Gain Gain Range Second Harmonic Distortion Third Harmonic Distortion Third-Order Intermodulation Output Third-Order Intercept Output 1dB Compression Point at Max Gain Noise Figure at Maximum Gain Noise Figure at Minimum Gain Maximum Gain Medium Gain Minimum Gain Gain Range Third-Order Intermodulation at Max Gain Third-Order Intermodulation at Mid Gain Third-Order Intermodulation at Min Gain Output Third-Order Intercept at Max Gain Output Third-Order Intercept at Mid Gain Output Third-Order Intercept at Min Gain The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Typical AC electrical performance measured in demo board DC1464A (Figure 3, Test Circuit A) unless otherwise noted. Default operating conditions are VCC = 3.3V, EN = 0.8V, SHDN = 2.2V, +VG tied to VREF (negative gain slope mode), and ZSOURCE = ZLOAD = 50Ω unless otherwise noted. CONDITIONS f1 = 139.5MHz, f2 = 140.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V f1 = 139.5MHz, f2 = 140.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V –VG = 0V (Note 6) –VG = 0V (Note 5) –VG = 1.2V (Note 5) –VG = 0V, Test Circuit B –VG = 1.2V, Test Circuit B GMAX-GMIN POUT = 0dBm, –VG = 0V to 1.0V POUT = 0dBm, –VG = 0V to 1.0V f1 = 239.5MHz, f2 = 240.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V f1 = 239.5MHz, f2 = 240.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V –VG = 0V (Note 6) –VG = 0V (Note 5) –VG = 1.2V (Note 5) f = 320MHz, POUT = –3dBm, –VG = 0V f = 320MHz, POUT = –5dBm, –VG = 0.6V f = 320MHz, POUT = –5dBm, –VG = 1.2V 320MHz, GMAX-GMIN f1 = 280MHz, f2 = 320MHz, POUT = –3dBm/Tone, –VG = 0V f1 = 280MHz, f2 = 320MHz, POUT = –5dBm/Tone, –VG = 0.6V f1 = 280MHz, f2 = 320MHz, POUT = –5dBm/Tone, –VG = 1.2V f1 = 280MHz, f2 = 320MHz, POUT = –3dBm/Tone, –VG = 0V f1 = 280MHz, f2 = 320MHz, POUT = –5dBm/Tone, –VG = 0.6V f1 = 280MHz, f2 = 320MHz, POUT = –5dBm/Tone, –VG = 1.2V 26.0 29.7 MIN TYP –88 38 13 10 42 17 –14 31 –70 –70 –82 35 12 10 42 16.9 1.5 –14.2 31.1 –72 –71 –56 31.0 30.5 23.0 –65 32.5 MAX UNITS dBc dBm dBm dB dB dB dB dB dBc dBc dBc dBm dBm dB dB dB dB dB dB dBc dBc dBc dBm dBm dBm 240MHz Signal 280MHz/320MHz Signal 6412f 6 LTC6412 AC ELECTRICAL CHARACTERISTICS SYMBOL GMAX GMIN GRANGE IM3 OIP3 P1dBGMAX NFGMAX NFGMIN PARAMETER Maximum Gain Minimum Gain Gain Range Third-Order Intermodulation Output Third-Order Intercept Output 1dB Compression Point at Max Gain Noise Figure at Maximum Gain Noise Figure at Minimum Gain The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Typical AC electrical performance measured in demo board DC1464A (Figure 3, Test Circuit A) unless otherwise noted. Default operating conditions are VCC = 3.3V, EN = 0.8V, SHDN = 2.2V, +VG tied to VREF (negative gain slope mode), and ZSOURCE = ZLOAD = 50Ω unless otherwise noted. CONDITIONS –VG = 0V, Test Circuit B –VG = 1.2V, Test Circuit B GMAX-GMIN f1 = 379.5MHz, f2 = 380.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V f1 = 379.5MHz, f2 = 380.5MHz, POUT = –6dBm/Tone, –VG = 0V to 1.0V –VG = 0V (Note 6) –VG = 0V (Note 5) –VG = 1.2V (Note 5) MIN TYP 17 –14 31 –72 30 11 10.5 42 MAX UNITS dB dB dB dBc dBm dBm dB dB 380MHz Signal Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. RF input power rating is guaranteed by design and engineering characterization, but not production tested. The absolute maximum continuous RF input power shall not exceed +15dBm Note 2: The LTC6412C/LTC6412I are guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: The LTC6412C is guaranteed to meet specified performance from 0°C to 70°C. It is designed, characterized and expected to meet specified performance from –40°C and 85°C but is not tested or QA sampled at these temperatures. The LT6412I is guaranteed to meet specified performance from –40°C to 85°C. Note 4: Power gain is defined at ZSOURCE = 50Ω and ZLOAD = 200Ω. Voltage gain for this test condition is 6dB higher than the stated power gain. Note 5: en can be calculated from 50Ω NF with the formula: en = √{4kT(50)(10NF/10 – 1)} where en = Input referred voltage noise in V/√Hz NF = 50Ω noise figure in dB k = Boltzmann’s constant = 1.38 • 10–23J/°K T = Absolute temperature in °K = °C + 273 Note 6: P1dB compression of the output amplifier cannot be achieved in the minimum gain state while complying with the absolute maximum rating for input RF power. 6412f 7 LTC6412 Electrical Performance in Test Circuits A and B at TA = 25°C and VCC = 3.3V unless otherwise noted. Differential Gain (Sdd21) vs Frequency Over 11 Gain Settings 20 GMAX 10 0 GMAX GAIN (dB) GAIN (dB) GAIN (dB) 0 –20 GMIN GMAX –20 20 TYPICAL PERFORMANCE CHARACTERISTICS Common Mode Gain (Scc21) vs Frequency Over 11 Gain Settings 0 CM-to-DM Gain (Sdc21) vs Frequency Over 11 Gain Settings –40 GMIN –60 –10 GMIN –40 –20 –60 –30 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G01 –80 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G02 –80 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G03 Differential Input Match (Sdd11) vs Frequency Over 11 Gain Settings 0 0 Differential Output Match (Sdd22) vs Frequency Over 11 Gain Settings –40 GMAX Differential Reverse Isolation (Sdd12) vs Frequency Over 6 Gain Settings GMAX –60 ISOLATION (dB) –10 RETURN LOSS (dB) RETURN LOSS (dB) GMAX –20 GMIN –30 –10 GMIN –20 –80 GMIN –30 –100 –40 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G04 –40 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G05 –120 1 10 100 1000 FREQUENCY (MHz) 10000 6412 G06 Differential Input Smith Chart (Sdd11) 10MHz to 500MHz Over 6 Gain Settings Differential Output Smith Chart (Sdd22) 10MHz to 500MHz Over 6 Gain Settings 120 TOTAL SUPPLY CURRENT (mA) 115 110 105 Supply Current vs Supply Voltage Over Temperature ZO = 50Ω GMIN GMAX ZO = 200Ω 10MHz GMAX 120MHz GMIN 240MHz 380MHz 500MHz 85°C 30°C –40°C 100 95 90 0°C 6412 G07 6412 G08 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 6412 G09 6412f 8 LTC6412 TYPICAL PERFORMANCE CHARACTERISTICS Differential Gain (Sdd21) vs Control Voltage Over Temperature 20 15 10 GAIN (dB) 5 –V : NEGATIVE G SLOPE MODE 0 –5 –10 –15 –20 0 0.2 –40°C 25°C 85°C 0.4 0.8 1.0 0.6 +VG OR –VG VOLTAGE (V) 1.2 6412 G10 Electrical Performance in Test Circuits A and B at TA = 25°C and VCC = 3.3V unless otherwise noted. Gain (Sdd21) Conformance Error vs Control Voltage Over Temperature 5 GAIN CONFORMANCE ERROR (dB) 4 3 2 1 0 –1 –2 –3 –4 –5 0 GMAX 0.2 0.6 0.8 0.4 –VG VOLTAGE (V) GMIN 1.0 1.2 6412 G11 Relative Phase (Sdd21) vs Control Voltage Over Frequency 20 sdd21 PHASE RELATIVE TO GMAX (DEG) 15 10 5 0 –5 –10 –15 –20 0 GMAX 0.2 0.4 0.8 0.6 –VG VOLTAGE (V) PHASE DELAY PHASE ADV. 100MHz 400MHz 200MHz FREQ = 140MHz FREQ = 140MHz +VG: POSITIVE SLOPE MODE –40°C 25°C 85°C GMIN 1.0 1.2 6412 G12 Output IP3 at 140MHz vs Control Voltage Over Temperature 45 40 35 30 25 20 15 GMAX 10 0 0.2 0.8 0.6 0.4 –VG VOLTAGE (V) 1.0 1.2 6412 G13 Output IP3 vs Control Voltage Over Frequency 45 40 35 70MHz 140MHz OIP3 (dBm) 240MHz 30 25 20 15 POUT = –6dBm/TONE ΔFREQ = 1MHz 0.8 0.6 0.4 –VG VOLTAGE (V) 380MHz 45 40 35 30 25 20 15 GMIN 10 0 0.2 1.0 1.2 6412 G14 Output IP3 at 140MHz vs Control Voltage Over VCC POUT = –6dBm/TONE ΔFREQ = 1MHz –40°C 25°C 85°C POUT = –6dBm/TONE ΔFREQ = 1MHz 3.6V 3.3V 3V OIP3 (dBm) OIP3 (dBm) GMIN 10 GMAX GMAX 0 0.2 0.8 0.6 0.4 –VG VOLTAGE (V) GMIN 1.0 1.2 6412 G15 Output IP3 vs Control Voltage Over Tone Spacing 45 40 35 30 25 20 15 GMAX 10 0 0.2 0.8 0.6 0.4 –VG VOLTAGE (V) 1.0 1.2 6412 G16 Output IP3 vs Control Voltage Over Output Power per Tone 45 40 –40 35 TEST EQUIPMENT LIMITED 30 25 20 15 FREQ = 140MHz ΔFREQ = 1MHz POUT = –6dBm/TONE –3dBm/TONE –9dBm/TONE GMAX 10 0 0.2 0.8 0.6 0.4 –VG VOLTAGE (V) 1.0 1.2 6412 G17 3rd Harmonic Distortion vs Control Voltage Over VCC –20 FREQ = 140MHz POUT = 0dBm POUT = –6dBm/TONE FREQ = 140MHz SPACING = 0.5MHz 1MHz 2MHz 5MHz GMIN OIP3 (dBm) OIP3 (dBm) HD3 (dBc) –60 VCC = 3V –80 VCC = 3.6V VCC = 3.3V INPUT ATTENUATOR LIMITED –100 GMIN GMAX 0 0.2 0.4 0.6 0.8 –VG VOLTAGE (V) GMIN 1.0 1.2 6412 G18 –120 6412f 9 LTC6412 Electrical Performance in Test Circuits A and B at TA = 25°C and VCC = 3.3V unless otherwise noted. 2nd Harmonic vs Distortion vs Control Voltage Over Frequency –20 POUT = 0dBm –20 TYPICAL PERFORMANCE CHARACTERISTICS 3rd Harmonic Distortion vs Control Voltage Over Frequency POUT = 0dBm 14 12 Noise Figure at GMAX vs Frequency Over Temperature 85°C 25°C NOISE FIGURE (dB) 10 8 6 4 2 –40°C –40 –40 HD2 (dBc) HD3 (dBc) –60 –60 FREQ = 280MHz –80 FREQ = 70MHz FREQ = 140MHz –80 –100 GMAX 0 0.2 FREQ = 280MHz FREQ = 140MHz FREQ = 70MHz 0.4 0.6 0.8 –VG VOLTAGE (V) –100 GMIN 1.0 1.2 6412 G19 –120 –120 GMAX 0 0.2 0.4 0.6 0.8 –VG VOLTAGE (V) GMIN 1.0 1.2 6412 G20 0 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 6412 G21 2nd Harmonic Distortion vs Control Voltage Over POUT –20 FREQ = 140MHz POUT = 3dBm POUT = 0dBm –40 POUT = –3dBm –60 –20 INPUT ATTENUATOR LIMITED HD3 (dBc) 3rd Harmonic Distortion vs Control Voltage Over POUT FREQ = 140MHz INPUT ATTENUATOR LIMITED POUT = 3dBm 45 40 35 NOISE FIGURE (dB) 30 25 140MHz Noise Figure vs Gain Setting Over Temperature –40 HD2 (dBc) –60 85°C –40°C 25°C 20 15 10 –80 –80 POUT = –3dBm POUT = 0dBm –100 GMAX 0 0.2 0.4 0.6 0.8 –VG VOLTAGE (V) GMIN 1.0 1.2 6412 G22 –100 GMAX 0 0.2 0.4 0.6 0.8 –VG VOLTAGE (V) GMIN 1.0 1.2 6412 G23 5 0 –20 –15 –10 0 5 –5 10 GAIN SETTING (dB) 15 20 –120 –120 6412 G24 Output P1dB at GMAX vs Frequency Over Supply Voltage 20 18 16 OUTPUT P1dB (dBm) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 6412 G25 Input and Output P1dB vs Gain Setting at 140MHz 20 INPUT P1dB 0 –20 OUTPUT P1dB POWER DENSITY (dBc/Hz) –40 –60 –80 –100 –120 140MHz Sideband Noise Near GMAX at POUT = +8dBm GAIN = GMAX – 2dB 3.6V P1dB (dBm) 3.3V 3V 15 10 5 0 –5 –20 –15 –10 INPUT ATTENUATOR LIMITED OUTPUT AMPLIFIER LIMITED 15 20 0 –5 5 10 GAIN SETTING (dB) –140 –20000 –10000 0 10000 20000 6412 G27 OFFSET FROM 140MHz (Hz) 6412 G26 6412f 10 LTC6412 TYPICAL PERFORMANCE CHARACTERISTICS 6dB Gain Control Step 70MHz Time Domain Response –VG (0.25V/DIV) VOLTAGE (V) RFOUT 50Ω VOLTAGE (V) RFOUT 50Ω Electrical Performance in Test Circuits A and B at TA = 25°C and VCC = 3.3V unless otherwise noted. 10dB Gain Control Step 70MHz Time Domain Response –VG (0.5V/DIV) 20dB Gain Control Step 70MHz Time Domain Response –VG (0.5V/DIV) RFOUT 50Ω PEAK RFOUT = 4dBm 0 1 2 3 TIME (μs) 4 5 6412 G30 PEAK RFOUT = 4dBm 0 1 2 3 TIME (μs) 4 5 6412 G28 PEAK RFOUT = 4dBm 0 1 2 3 TIME (μs) 4 5 6412 G29 SHDN Step at GMAX with EN = 0V 70MHz Time Domain Response SHDN (1V/DIV) VOLTAGE (V) RFOUT 50Ω VOLTAGE (V) SHDN Step at G = 3dB with EN = 0V 70MHz Time Domain Response SHDN (1V/DIV) RFOUT 50Ω VOLTAGE (V) VOLTAGE (V) 10dB 0dB Overdrive Compression at GMAX 70MHz Time Domain Response PEAK GAIN RF OUT 50Ω COMPRESSION 20dB PEAK RFOUT = 4dBm 0 100 200 300 TIME (μs) 400 500 6412 G31 PEAK RFOUT = 4dBm 0 100 200 300 TIME (μs) 400 500 6412 G32 PEAK RFOUT = 14dBm 0 20 40 60 TIME (μs) 80 100 6412 G33 Overdrive Recovery at GMAX 70MHz Time Domain Response 1.2 1.0 0.8 VOLTAGE (V) 0.6 0.4 0.2 0 –0.2 –0.4 15dB COMPRESSED –0.6 0 50 SMALL SIGNAL PEAK RFOUT = 14dBm RFOUT INTO 50Ω, 10dB ATTENUATED EXTERNAL RF SWITCH PULSE VOLTAGE (V) 2.5 2.0 Output EN Step at GMAX 140MHz Time Domain Response SHDN Supply Current Time Domain Response 3.0 SHDN PIN VOLTAGE (V) EN 1.5 1.0 0.5 0 –0.5 –1.0 PEAK RFOUT = 10dBm –1.5 0 20 40 60 80 100 120 140 160 180 200 TIME (ns) 6412 G35 2.0 120 SUPPLY CURRENT (mA) RFOUT 50Ω 100 80 60 40 20 0 0 1.0 0 100 150 200 250 300 350 400 TIME (ns) 6412 G34 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME (ms) 6412 G36 6412f 11 LTC6412 PIN FUNCTIONS GND (Pins 1, 8, 12, 15, 18, 20, 23): Ground. Pins are connected to each other internally. For best RF performance, all ground pins should be connected to the printed circuit board ground plane. +IN (Pin 2): Positive Signal Input Pin. Has an internally generated DC Bias. A 10nF DC blocking capacitor is recommended. –IN (Pin 3): Negative Signal Input Pin. Has an internally generated DC Bias. A 10nF DC blocking capacitor is recommended. VCM (Pins 4, 5): Input Common Mode Voltage Pins. Two pins are tied together internally and serve as a virtual ground for the differential inputs, +IN and –IN. Capacitive decoupling to ground with 10nF close to the pins is recommended to help terminate any residual common mode input signal. VCC (Pins 6, 13, 19, 24): Positive Power Supply. All four pins must be tied to the same voltage, usually 3.3V. Bypass each pin with 1000pF and 0.1μF capacitors close to the pins. DECL1 (Pin 7): Decoupling Pin. Serves to reduce internal noise. Bypass to ground with a 0.1μF capacitor close to the pin. +VG (Pin 9): Positive Gain Control Pin. Input signal pin used for positive mode gain control. Otherwise, pin is typically connected to VREF for negative mode gain control. Pin is internally pulled to ground with a 10k resistor. In positive gain slope mode, the gain control slope is approximately +32dB/V at 140MHz with a gain control range of 0.1V to 1.1V. VREF (Pin 10): Internal Bias Voltage Pin. Typically tied to –VG pin for positive gain control or tied to +VG for negative gain control. Determines the midpoint voltage of the gain-vs-VG characteristic. Bypass to ground with 0.1μF capacitor close to the pin. Not intended for use as an external reference voltage. –VG (Pin 11): Negative Gain Control Pin. Input signal pin used for negative mode gain control. Otherwise, pin is typically connected to VREF for positive mode gain control. Pin is internally pulled to ground with a 10k resistor. In negative gain slope mode, the gain control slope is approximately –32dB/V at 140MHz with a gain control range of 0.1V to 1.1V. DECL2 (Pin 14): Decoupling Pin. Serves to reduce internal noise. Bypass to ground with a 1000pF capacitor close to the pin. –OUT (Pin 16): Negative Amplifier Output Pin. A transformer with a center tap tied to VCC or a choke inductor is recommended to conduct DC quiescent current to the open-collector output device. For best performance, DC bias voltage to –OUT must be within 100mV of VCC. +OUT (Pin 17): Positive Amplifier Output Pin. A transformer with a center tap tied to VCC or a choke inductor is recommended to conduct DC quiescent current to the open-collector output device. For best performance, DC bias voltage to +OUT must be within 100mV of VCC. EN (Pin 21): Output Signal Enable Pin. Pin is internally pulled high with 100kΩ to VCC. Assert pin to a low voltage to enable the output amplifier signal. Output amplifier impedance and DC current are not affected by the EN state. Connect pin to ground if enable function is not used. SHDN (Pin 22): Shutdown Pin. Pin is internally pulled high with 100 kΩ to VCC. Assert pin to a low voltage to shut down the circuit and greatly reduce the supply current. Proper sequencing of the EN and SHDN pins is required to avoid non-monotonic output signal behavior. See Applications Information section for details. Connect pin to VCC if shutdown function is not used. Exposed Pad (Pin 25): Ground. The Exposed Pad should have multiple via holes to an underlying ground plane for low inductance and good thermal dissipation. 6412f 12 LTC6412 BLOCK DIAGRAM 6 VCC 13 VCC 19 VCC 24 VCC 22 SHDN 21 EN 15 GND 23 GND REFERENCE AND BIAS CONTROL 2 +IN ••• ••• 3 4 5 –IN VCM VCM ATTENUATOR CONTROL –VG GND 11 1 GND 8 REFERENCE AND BIAS CONTROL GND 12 GND 15 GND 18 ••• BUFFER/ OUTPUT AMPLIFIER –OUT DECL1 DECL2 EXPOSED PAD 25 6412 BD +OUT 17 16 7 14 +VG 9 VREF 10 DC TEST CIRCUIT VCC 2.2V 0.8V 0.1μF VCC 0.1μF VCM SHDN VSUPPLY ≈ VCC + 2.3V EN 100Ω +IN VIN(DIFF) = (+IN) – (–IN) VIN(CM) = [(+IN) + (–IN)]/2 –IN +IN LTC6412 –IN –VG DECL2 +VG VREF +OUT +OUT VOUT(DIFF) = (+OUT) – (–OUT) VOUT(CM) = [(+OUT) + (–OUT)]/2 6412 TC –OUT 100Ω –OUT DECL1 VSUPPLY ≈ VCC + 2.3V GND 0.1μF 0.1μF GAIN CONTROL (NEGATIVE SLOPE) 0.1μF 6412f 13 LTC6412 OPERATION The LTC6412 employs an interpolated, tapped attenuator circuit architecture to generate the variable-gain characteristic of the amplifier. The tapped attenuator is fed to a buffer and output amplifier to complete the differential signal path shown in the Block Diagram. This circuit architecture provides good RF input power handling capability along with a constant output noise and output IP3 characteristic that are desirable for most IF signal chain applications. The internal control circuitry takes the gain control signal from the ±VG terminals and converts this to an appropriate set of control signals to the attenuator ladder. The attenuator control circuit ensures that the linear-in-dB gain response is continuous and monotonic over the gain range for both slow and fast moving input control signals while exhibiting very little input impedance variation over gain. These design considerations result in a gain-vs-VG characteristic with a ±0.1dB ripple and a 0.5μs gain response time that is slower than a similar digital step attenuator design. An often overlooked characteristic of an analog-controlled VGA is upconverted amplitude modulation (AM) noise from the gain control terminals. The VGA behaves as a 2-quadrant multiplier, so some minimal care is required to avoid excessive AM sideband noise generation. The table below demonstrates the effect of the baseline 20nV/√Hz equivalent input control noise from the LTC6412 circuit along with the effect of a higher combined input noise due to a noisy external control circuit. CONTROL INPUT TOTAL NOISE VOLTAGE (nV/√Hz) 20 40 70 100 200 PEAK AM NOISE AT 10kHz OFFSET NEAR MAXIMUM GAIN (dBc/Hz) –142 –136 –131 –128 –122 The baseline equivalent 20nV/√Hz input noise is seen to produce worst-case AM sidebands of –142dBc/Hz which is near the –147dBm/Hz output noise floor at maximum gain for a nominal 0dBm output signal. An input control noise voltage less than 80nV/√Hz is generally recommended to avoid measurable AM sideband noise. While op amp control circuit output noise voltage is usually below 80nV/√Hz, some low power DAC outputs exceed 150nV/√Hz. DACs with output noise in the range of 100nV/√Hz to 150nV/√Hz can usually be accommodated with a suitable 2:1 or 3:1 resistor divider network on the DAC output to suppress the noise amplitude by the same ratio. Noisy DACs in excess of 150nV/√Hz should be avoided if minimal AM noise is important in the application. 6412f 14 LTC6412 APPLICATIONS INFORMATION Introduction The LTC6412 is a high linearity, fully-differential analogcontrolled variable-gain amplifier (VGA) optimized for application frequencies in the range of 1MHz to 500MHz. The VGA architecture provides a constant OIP3 and constant output noise level (NF + Gain) over the 31dB gain-control range and thus exhibits a uniform spurious-free dynamic range (SFDR) over gain. This constant SFDR characteristic is ideal for use in receiver IF chains that are upstream from a signal sink such as a demodulator or ADC. The low supply voltage requirements and fully differential design are compatible with many other LTC mixer, amplifier and ADC products for use in compact, low voltage, fully differential receiver chains. For non-differential systems, the 50Ω input impedance and 200Ω output impedance are easily converted to single-ended 50Ω ports with inexpensive 1:1 and 4:1 baluns. Gain Characteristics The LTC6412 provides a continuously adjustable gain range of –14dB to 17dB that is linear-in-dB with respect to the control voltages applied to +VG and –VG. These control pins can be operated with a differential signal, but it is more common to operate one of the VG pins with a single-ended control signal while connecting the other VG pin to the provided VREF pin. In this way, either a positive gain-control slope or negative gain-control slope is easily achieved: Negative Gain-Control Slope. Tie +VG to VREF and apply gain control voltage to the –VG pin. Gain decreases with increasing –VG voltage. Positive Gain-Control Slope. Tie –VG to VREF and apply gain control voltage to the +VG pin. Gain increases with increasing +VG voltage. When connected in this typical single-ended configuration, the active control input range extends from 0.1V to 1.1V. This control input range can be extended using a resistor divider with a suitably low output resistance. For example, two series resistors of 1k each would extend the control input range from 0.2V to 2.2V while providing an effective 500Ω Thevinin equivalent source resistance, a relatively small loading effect compared to the 10k input resistance of the +VG/–VG terminals. Port Characteristics The LTC6412 provides a nominal 50Ω differential input impedance and 200Ω differential output impedance over the operating frequency range. The input impedance characteristic derives from the differential attenuator ladder shown in the Block Diagram. The internal circuit controls the RF connections to this attenuator ladder and generates the appropriate common mode DC voltage to this port. The differential attenuator ladder creates a virtual ground node that needs a capacitor bypass to ground at the VCM pin to effectively attenuate any common mode signal presented to the input port. The +VIN and –VIN pins are connected to the input signal through DC blocking capacitors as shown in Test Circuit A and Test Circuit B, Figures 1-4. The output impedance characteristic derives from the open-collector equivalent circuit shown in Figure 7. The action of the differential shunt, lowpass filter, and internal feedback presents an effective differential output impedance of 200Ω to 300Ω between the +OUT and –OUT pins over the operating band. The +VOUT and –VOUT pins are connected to the output port using shunt inductors or a transformer to provide a DC path to the supply voltage. The DC block to the circuit output is usually accomplished using series capacitors. These blocking capacitors can be avoided if a flux transformer is used at the output. Figure 9 illustrates a few common inductor and balun transformer methods for coupling the AC signal and DC supply to the output pins. This is discussed further in the Typical Application Circuits section. Power Supplies Inductance to the supply path can degrade the performance of the LTC6412. It is recommended that low inductance bypass capacitors are installed very close to each of the VCC pins. 1000pF and 0.1μF parallel capacitors are recommended with the smaller capacitor placed closer to the VCC pin. Do not leave any supply pins disconnected. For best performance, DC bias voltage to the +OUT and –OUT pins 6412f 15 LTC6412 APPLICATIONS INFORMATION must be within 100mV of VCC. The Exposed Pad on the underside of the package must be connected to ground with low inductance and low thermal resistance. Refer to details of DC1464A (Test Circuit A) for an example of proper grounding and supply decoupling. Failure to provide low impedance supply and ground at high frequencies can cause oscillations and increased distortion. Enable/Shutdown Both the EN pin and SHDN pin are self-biased to VCC through their respective 100k pull-up resistors, so the default open-pin state is powered on with the output amplifier signal path disabled. Pulling the EN pin low completes the signal path from the attenuator ladder through the output amplifier. The EN pin essentially provides a fast muting function while the SHDN pin provides slower power on/off function. For applications requiring the SHDN function, it is recommended that the output amplifier signal path be disabled with a high EN voltage before transitioning the SHDN signal. When enabling the amplifier, allow at least 5ms dwell time between the rising SHDN transition and the falling EN transition to avoid non-monotonic output signal behavior though the VGA. The opposite delay sequence is recommended for the falling SHDN transition, but this is less critical as the output signal amplitude will drop abruptly regardless of the EN pin. SHDN tDWELL EN tDWELL 6412 AI01 Layout/Grounding The high frequency performance of the LTC6412 requires special attention to proper RF grounding, bias decoupling and termination. The recommended PCB stack-up for a 4-layer board is shown below for 1oz copper clad FR-4 laminate with a relative dielectric constant, εr = 4.2-4.5 at 1GHz. METAL 1 FR4 12-18 MILS METAL 2 FR4 20-30 MILS METAL 3 FR4 NOT CRITICAL METAL 4 6412 AI02 RF SIGNAL GROUND PLANE POWER PLANE GND AND LF SIGNAL The topside metal and silkscreen drawings for Test Circuit A illustrate the recommended decoupling capacitor placement, signal routing and grounding. Ground vias directly beneath the Exposed Pad are critical; use as many as possible. Ground vias to the other ground pins are less critical. ESD The LTC6412 is protected with reverse-biased ESD diodes on all I/O pins. If any I/O pin is forced one diode drop above the positive supply or one diode drop below the negative supply, then large currents may flow through the diodes. No damage to the devices will occur if the current is kept below 10 mA. The +OUT/–OUT pins have additional series diodes to the positive supply and can sustain approximately 2V overshoot above the positive supply before conducting appreciable currents. 6412f 16 LTC6412 APPLICATIONS INFORMATION Signal Compression Characteristics The graph entitled, Input and Output P1dB, illustrates an important characteristic of the LTC6412 VGA. At gain settings above –5dB, the output amplifier limits the linear power handling capability, but at gain settings below –5dB, the input attenuator ladder limits the linear power handling capability. The linear input power limitations at minimum gain do not affect the overall performance of a signal chain if the preceding mixer or amplifier stage exhibits an OP1dB < 19dBm and an OIP3 < 50dBm. Test Circuits The fully-differential nature of the LTC6412 design requires two test circuits to generate the performance information presented in this data sheet. Test Circuit A is DC1464A, a 2-port demonstration circuit with input/output balun transformers to allow for direct connection to a 2-port network analyzer or other singleended 50Ω test system. The balun transformers limit the high and low frequency performance of the LTC6412 but allow for simple and reasonably accurate measurements from 70MHz to 380MHz. The gain control signal is supplied to either of the VG turrets for DC control measurements or through the VGAIN SMA connector for transient control signal measurements. Clip leads to the gain control turrets are susceptible to noise pickup and should be lowpass filtered to avoid AM upconversion artifacts. While using the ±VG turrets, a 4.7μF capacitor from the VGAIN SMA input to ground provides an effective lowpass filter. Typical data curves quoted for Test Circuit A are measured at the plane of the SMA connectors and are NOT corrected for any losses introduced by the input and output baluns, estimated at approximately 0.5dB and 1.2dB, respectively. All typical AC data reported in this data sheet correspond to Test Circuit A, except for mixed-mode S-parameters of the form Sdd21, Scc21, etc. Test Circuit B uses a 4-port network analyzer to measure differential mode and common mode S-parameters beyond the frequency limitations imposed by the balun transformers and associated circuitry. A matching calibration set establishes the measurement reference planes shown in Test Circuit B. The output plane is defined at the edge of the package while the input plane is defined at the edge of the input pair of 0402 capacitors. The IC land and ground via pattern are identical to that shown for Test Circuit A. The ground via pattern directly beneath the package is critical to provide the proper RF ground to produce the RF characteristics quoted in this data sheet. All mixed-mode S-parameter typical data curves of the form SxyAB correspond to Test Circuit B following the definitions described in Figures 5 and 6. Typical Application Circuits Grounding and supply decoupling should closely follow the suggested layout shown for Test Circuit A, but the input and output networks can be customized to suit various application requirements. On the input side, the differential port impedance is very close to 50Ω over all gain settings and application frequencies. In a differential signal chain, the differential input signal is easily supplied from a preceding differential output stage with a suitable DC blocking capacitor of approximately 10nF If the system employs a single-ended input signal . to the VGA, then a suitable balun is required to convert to a differential input signal. The passive conversion from 50Ω single-ended to 50Ω differential is most effectively accomplished with a 1:1 transmission-line balun such as the ETC1-1-13 or MABA-007159. These 1:1 balun devices are relatively inexpensive and offer excellent electrical characteristics such as low loss, broad band response and good phase matching. 6412f 17 LTC6412 APPLICATIONS INFORMATION 6412 F01 6412 F02 Figure 2. Top Metal for DC1464A. Test Circuit A Figure 1. Top Silkscreen for DC1464A. Test Circuit A On the output side, the differential port admittance is very close to 300Ω||1.5pF across all gain settings and application frequencies. This output port circuit must provide a path for DC output supply current as well as any balun, matching, or filtering functions required by the application. Thus, the design options for the output circuitry are more varied. A brief list of the more common output circuits is shown in Figure 9 along with a few design guidelines to estimate component values. Final design simulations should use the small-signal equivalent circuit model in Figure 8 to properly account for loading effects of the output terminals. Figure 9a shows the simplest differential output configuration employing two suitable inductors, L1 = L2, to pass the DC supply current without loading the output nodes at the application frequency. The PCB trace widths from the output pins should be narrow in keeping with the high impedance of these terminals; 8 to 10mil trace width on 1oz copper is a good choice. The 0.1μF capacitors serve to DC block and decouple as needed. These capacitor values are adequate down to a few MHz and can be scaled down for higher application frequencies. If bandpass filtering is needed at the VGA output of Figure 9a, then L1 and L2 can be designed to resonate with a shunt capacitor, CO, at the frequency of interest, ω =1/√CO(L1 + L2). Alternately, L1 = L2 can be designed to resonate with two separate capacitors, C1 = C2, so any common mode noise is filtered as well. Figure 9b shows a further variation of the tuned differential output where the DC blocking capacitors are brought inside the tank resonator to participate in the bandpass filter and transform the VGA output impedance to a lower value. Here too, the CO capacitor can be split into two separate shunt capacitors to ground, so any common mode noise is filtered as well. 6412f 18 LTC6412 APPLICATIONS INFORMATION SHDN EN VCC R1 1k VCC C3 0.1μF R3 [1] R5 1k R6 1k R4 1k VCC R2 [1] VCC C4 0.1μF C2 1000pF 24 1 C8 10nF 2 3 4 5 C11 10nF VCC C14 0.1μF 6 C13 1000pF C2 1000pF 20 19 18 17 16 15 14 13 VCC C16 1000pF C15 0.1μF C12 1000pF C7 0.1μF VCC 3 2 1 T2 4:1 4 C20 [1] R7 [1] +IN 0dB R9 0Ω 5 • 4 T1 1:1 C5 10nF 1 23 22 21 VCC GND SHDN EN GND VCC GND +IN –IN VCM VCM VCC 7 8 9 10 11 LTC6412 GND +OUT –OUT GND DECL2 VCC 12 C6 0.1μF C9 [1] +OUT • 2 3 –IN • 5 C21 0.1μF –OUT DECL1 GND +VG VREF –VG GND C17 0.1μF VCC VCC 3.00V TO 3.60V GND CB1 4.7μF CA1 1μF R17 100Ω +VG R15 0Ω R14 [1] C22 0.1μF R20 100Ω –VG BALUN PART NUMBER T1, T3, T4 TYCO MABA-007159 T2 MINI-CIRCUITS TCM4-19+ R18 [1] R19 0Ω VGAIN NOTE: [1] DO NOT PLACE TEST IN 5 • 4 R21 0Ω T3 1:1 C18 0.1μF 1 3 C19 0.1μF 2 1 • 2 3 • T4 1:1 4 • 5 TEST OUT R22 0Ω 6412 F03 Figure 3. Demo Board DC1464A Circuit Schematic. Test Circuit A Figure 9c shows a flux transformer used to achieve a 50Ω single-ended output. The flux transformer does not provide the large bandwidth typical of the output transmission-line transformer shown in Figure 3, but it usually performs well over smaller bandwidths, especially when tuned with shunt capacitors (not shown). The flux transformer design eliminates DC blocking capacitors and is attractive in rugged applications where the amplifier output is subjected to ESD events and other forms of transient electrical overstress that do not pass through a typical RF flux transformer such as the MABAES0061. Figure 9d shows a discrete LC balun suitable for bandwidths of approximately 15% to 30%. Larger bandwidths are difficult to achieve with the number of components shown, and smaller bandwidths are often limited by component tolerance effects. Despite these limitations, the discrete LC balun can be a cost effective output circuit solution. At resonance, the tuned circuit produces an impedance transformation along with the differential-to-single-ended conversion. DC Coupled Operation The LTC6412 is intended for AC-coupled operation. The translation between the fixed input DC common mode voltage and higher open-collector output DC bias point makes it impractical to use in DC-coupled applications. 6412f 19 LTC6412 APPLICATIONS INFORMATION INPUT REF PLANE 3.3V OUTPUT REF PLANE 1nF SHDN 1/2 AGILENT E5071C PORT 1 50Ω 10nF PORT 2 50Ω VCC 0.1μF 1/2 AGILENT E5071C PORT 3 50Ω IDC PORT 4 50Ω 6412 F04 10nF +IN –IN GND VCM DECL1 DECL2 +VG VREF –VG LTC6412 EN +OUT IDC –OUT GAIN CONTROL (– SLOPE MODE) 0.1μF 10nF 0.1μF 0.1μF Figure 4. 4-Port Analysis Schematic. Test Circuit B DIFFERENTIAL MODE PORT 1 50Ω COMMON MODE PORT 1 +IN +OUT COMMON MODE PORT 2 DIFFERENTIAL MODE PORT 2 200Ω 12.5Ω DUT 50Ω –IN 1:1 IDEAL TRANSFORMER WITH CENTER TAP –OUT 6412 F05 1:1 IDEAL TRANSFORMER WITH CENTER TAP Figure 5. Schematic of Mixed-Mode S-Parameters Reported for Test Circuit B S xyAB STIMULUS PORT NUMBER RESPONSE PORT NUMBER STIMULUS PORT MODE RESPONSE PORT MODE MODE d: DIFFERENTIAL MODE (BALANCED) c: COMMON MODE (BALANCED) x MODE SIGNAL OUTPUT ON PORT A y MODE SIGNAL INPUT ON PORT B 6412 F06 S xyAB = Figure 6. Definition of Mixed-Mode S-Parameters Reported for Test Circuit B 6412f 20 LTC6412 APPLICATIONS INFORMATION 5Ω 5Ω +OUT 0.3pF 8pF TO BUFFER AMP 0.3pF 5Ω 5Ω 6412 F06 150Ω 150Ω –OUT LOWPASS FILTER Figure 7. Large-Signal Output Equivalent Circuit Schematic IDEAL 1:1 TRANSFORMER WITH CENTER TAP 1nH +OUT gm 300Ω 1.5pF 1nH ZOUT –OUT DIFFERENTIAL MODE ADMITTANCE COMMON MODE ADMITTANCE 190Ω 5pF 6412 F08 175Ω 4pF Figure 8. Small-Signal Output Equivalent Circuit Model 6412f 21 LTC6412 APPLICATIONS INFORMATION 10mil LINE WIDTH C1 0.1μF L1 = L2 C1 = C2 CO 0.1μF L2 0.1μF NOTE: DASHED LINE COMPONENTS ARE FOR BANDPASS FILTERING (SEE TEXT) ZOUT = 200Ω DIFFERENTIAL +OUT (a) LTC6412 –OUT VCC L1 C2 C1 L1 = L2 C1 = C2 +OUT (b) LTC6412 –OUT 0.1μF L2 C2 VCC L1 AT RESONANCE, CO 1 CO 200Ω ZOUT = 1+1+1 C1 C2 CO DIFFERENTIAL T2 4:1 VCC 0.1μF 2 +OUT (c) LTC6412 –OUT T2 = MABAES0061 ZOUT = 50Ω SINGLE ENDED VCC 0.1μF L1 LCHOKE +OUT (d) LTC6412 –OUT L2 C1 0.1μF L1 = L2 = L C1 = C2 = C XC = fO = 1 2π√LC 1 2πfOC AT RESONANCE, XC2 200Ω SINGLE ENDED ZOUT = C2 LC BALUN 6412 F09 Figure 9. Output AC/DC Coupling, Filter and Balun Circuit Design Options 6412f 22 LTC6412 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 0.05 4.50 0.05 3.10 2.45 0.05 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD 0.75 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 45 CHAMFER 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 23 24 0.40 1 2 0.10 2.45 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 6412f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC6412 RELATED PARTS PART NUMBER LT1993-2, LT1993-4, LT1993-10 DESCRIPTION 800MHz Differential Amplifier/ADC Drivers COMMENTS –72dBc IM3 at 70MHz 2VP-P Composite, AV = 2V/V, 4V/V, 10V/V –71dBc IM3 at 240MHz 2VP-P Composite, IS = 90mA, AV = 8dB, 14dB, 20dB, 26dB –74dBc IM3 at 140MHz 2VP-P Composite, IS = 50mA, AV = 8dB, 14dB, 20dB, 26dB –71dBc IM3 at 20MHz 2VP-P Composite, AV = 6dB, 12dB, 20dB OIP3 = 36dBm at 70MHz, Flexible Interface to Mixer IF Port –72dBc IM2 at 300MHz 2VP-P Composite, IS = 42mA, eN = 2.8nV/√Hz, AV = 0dB, 300MHz ±0.1dB Bandwidth Dual Version of the LTC6400-20, AV = 20dB Dual Version of the LTC6401-20, AV = 20dB Fixed Gain IF Amplifiers/ADC Drivers LTC6400-8, LTC6400-14, 1.8GHz Low Noise, Low Distortion Differential LTC6400-20, LTC6400-26 ADC Drivers LTC6401-8, LTC6401-14, 1.3GHz Low Noise, Low Distortion Differential LTC6401-20, LTC6401-26 ADC Drivers LT6402-6, LT6402-12, LT6402-20 LTC6410-6 LTC6416 LTC6420-20 LTC6421-20 300MHz Differential Amplifier/ADC Drivers 1.4GHz Differential IF Amplifier with Configurable Input Impedance 2GHz, 16-Bit Differential ADC Buffer Dual 1.8GHz Low Noise, Low Distortion Differential ADC Drivers Dual 1.3GHz Low Noise, Low Distortion Differential ADC Drivers Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain High Dynamic Range 7-Bit Digitally Controlled IF VGA/ADC Driver Low Noise, Low Distortion Differential Amplifier/ADC Driver Low Noise Rail-to-Rail Output Differential Amplifier/ADC Driver Low Noise Rail-to-Rail Output Differential Amplifier/ADC Driver IF Amplifiers/ADC Drivers with Digitally Controlled Gain LT5514 LT5524 LT5554 OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB by 1.5dB OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB by 1.5dB OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB by 0.125dB Baseband Differential Amplifiers LT1994 LTC6403-1 LTC6404-1, LTC6404-2 LTC6406 LT6411 16-Bit SNR, SFDR at 1MHz, Rail-to-Rail Outputs 16-Bit SNR, SFDR at 3MHz, Rail-to-Rail Outputs, eN = 2.8nV/√Hz 16-Bit SNR, SFDR at 10MHz, Rail-to-Rail Outputs, eN = 1.5nV/√Hz, LTC6404-1 is Unity-Gain Stable, LTC6404-2 is Gain-of-2 Stable 3GHz Rail-to-Rail Input Differential Amplifier/ADC –65dBc IM3 at 50MHz 2VP-P Composite, Rail-to-Rail Inputs, Driver eN = 1.6nV/√Hz, 18mA Low Power Differential ADC Driver/Dual Selectable Gain Amplifier Low Power, Internal Reference, Single Supply 10-Bit DAC Low Power, Internal Reference, Single Supply 10-Bit DAC –83dBc IM3 at 70MHz 2VP-P Composite, AV = 1, –1 or 2, 16mA, Excellent for Single-Ended to Differential Conversion SPI Input, 2.5V Output Range, Resistor Divide Output by ~2:1 SPI Input, 2.5V Output Range, Resistor Divide Output by ~2:1 Low Noise DAC for Gain Control LTC2630-10 LTC2640-10 LTC2641-12 LTC2642-12 Low Noise, Low Power, Single Supply 12-Bit DAC SPI Input, Low Glitch Impulse, Power-On to Zero Scale Low Noise, Low Power, Single Supply 12-Bit DAC SPI Input, Low Glitch Impulse, Power-On to Midscale 6412f 24 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0509 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009